| 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Keith Packard <keithp@keithp.com> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include <linux/i2c.h> |
| 29 | #include <linux/slab.h> |
| 30 | #include <linux/export.h> |
| 31 | #include <linux/notifier.h> |
| 32 | #include <linux/reboot.h> |
| 33 | #include <drm/drmP.h> |
| 34 | #include <drm/drm_atomic_helper.h> |
| 35 | #include <drm/drm_crtc.h> |
| 36 | #include <drm/drm_crtc_helper.h> |
| 37 | #include <drm/drm_edid.h> |
| 38 | #include "intel_drv.h" |
| 39 | #include <drm/i915_drm.h> |
| 40 | #include "i915_drv.h" |
| 41 | |
| 42 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
| 43 | |
| 44 | /* Compliance test status bits */ |
| 45 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 |
| 46 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
| 47 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
| 48 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
| 49 | |
| 50 | struct dp_link_dpll { |
| 51 | int clock; |
| 52 | struct dpll dpll; |
| 53 | }; |
| 54 | |
| 55 | static const struct dp_link_dpll gen4_dpll[] = { |
| 56 | { 162000, |
| 57 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
| 58 | { 270000, |
| 59 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
| 60 | }; |
| 61 | |
| 62 | static const struct dp_link_dpll pch_dpll[] = { |
| 63 | { 162000, |
| 64 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
| 65 | { 270000, |
| 66 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
| 67 | }; |
| 68 | |
| 69 | static const struct dp_link_dpll vlv_dpll[] = { |
| 70 | { 162000, |
| 71 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
| 72 | { 270000, |
| 73 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
| 74 | }; |
| 75 | |
| 76 | /* |
| 77 | * CHV supports eDP 1.4 that have more link rates. |
| 78 | * Below only provides the fixed rate but exclude variable rate. |
| 79 | */ |
| 80 | static const struct dp_link_dpll chv_dpll[] = { |
| 81 | /* |
| 82 | * CHV requires to program fractional division for m2. |
| 83 | * m2 is stored in fixed point format using formula below |
| 84 | * (m2_int << 22) | m2_fraction |
| 85 | */ |
| 86 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
| 87 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
| 88 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
| 89 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
| 90 | { 540000, /* m2_int = 27, m2_fraction = 0 */ |
| 91 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
| 92 | }; |
| 93 | |
| 94 | static const int bxt_rates[] = { 162000, 216000, 243000, 270000, |
| 95 | 324000, 432000, 540000 }; |
| 96 | static const int skl_rates[] = { 162000, 216000, 270000, |
| 97 | 324000, 432000, 540000 }; |
| 98 | static const int default_rates[] = { 162000, 270000, 540000 }; |
| 99 | |
| 100 | /** |
| 101 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
| 102 | * @intel_dp: DP struct |
| 103 | * |
| 104 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
| 105 | * will return true, and false otherwise. |
| 106 | */ |
| 107 | static bool is_edp(struct intel_dp *intel_dp) |
| 108 | { |
| 109 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 110 | |
| 111 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
| 112 | } |
| 113 | |
| 114 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
| 115 | { |
| 116 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 117 | |
| 118 | return intel_dig_port->base.base.dev; |
| 119 | } |
| 120 | |
| 121 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
| 122 | { |
| 123 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
| 124 | } |
| 125 | |
| 126 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
| 127 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
| 128 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
| 129 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
| 130 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
| 131 | enum pipe pipe); |
| 132 | |
| 133 | static unsigned int intel_dp_unused_lane_mask(int lane_count) |
| 134 | { |
| 135 | return ~((1 << lane_count) - 1) & 0xf; |
| 136 | } |
| 137 | |
| 138 | static int |
| 139 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
| 140 | { |
| 141 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
| 142 | |
| 143 | switch (max_link_bw) { |
| 144 | case DP_LINK_BW_1_62: |
| 145 | case DP_LINK_BW_2_7: |
| 146 | case DP_LINK_BW_5_4: |
| 147 | break; |
| 148 | default: |
| 149 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
| 150 | max_link_bw); |
| 151 | max_link_bw = DP_LINK_BW_1_62; |
| 152 | break; |
| 153 | } |
| 154 | return max_link_bw; |
| 155 | } |
| 156 | |
| 157 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
| 158 | { |
| 159 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 160 | u8 source_max, sink_max; |
| 161 | |
| 162 | source_max = intel_dig_port->max_lanes; |
| 163 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
| 164 | |
| 165 | return min(source_max, sink_max); |
| 166 | } |
| 167 | |
| 168 | /* |
| 169 | * The units on the numbers in the next two are... bizarre. Examples will |
| 170 | * make it clearer; this one parallels an example in the eDP spec. |
| 171 | * |
| 172 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: |
| 173 | * |
| 174 | * 270000 * 1 * 8 / 10 == 216000 |
| 175 | * |
| 176 | * The actual data capacity of that configuration is 2.16Gbit/s, so the |
| 177 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - |
| 178 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be |
| 179 | * 119000. At 18bpp that's 2142000 kilobits per second. |
| 180 | * |
| 181 | * Thus the strange-looking division by 10 in intel_dp_link_required, to |
| 182 | * get the result in decakilobits instead of kilobits. |
| 183 | */ |
| 184 | |
| 185 | static int |
| 186 | intel_dp_link_required(int pixel_clock, int bpp) |
| 187 | { |
| 188 | return (pixel_clock * bpp + 9) / 10; |
| 189 | } |
| 190 | |
| 191 | static int |
| 192 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
| 193 | { |
| 194 | return (max_link_clock * max_lanes * 8) / 10; |
| 195 | } |
| 196 | |
| 197 | static enum drm_mode_status |
| 198 | intel_dp_mode_valid(struct drm_connector *connector, |
| 199 | struct drm_display_mode *mode) |
| 200 | { |
| 201 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 202 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 203 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
| 204 | int target_clock = mode->clock; |
| 205 | int max_rate, mode_rate, max_lanes, max_link_clock; |
| 206 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
| 207 | |
| 208 | if (is_edp(intel_dp) && fixed_mode) { |
| 209 | if (mode->hdisplay > fixed_mode->hdisplay) |
| 210 | return MODE_PANEL; |
| 211 | |
| 212 | if (mode->vdisplay > fixed_mode->vdisplay) |
| 213 | return MODE_PANEL; |
| 214 | |
| 215 | target_clock = fixed_mode->clock; |
| 216 | } |
| 217 | |
| 218 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
| 219 | max_lanes = intel_dp_max_lane_count(intel_dp); |
| 220 | |
| 221 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
| 222 | mode_rate = intel_dp_link_required(target_clock, 18); |
| 223 | |
| 224 | if (mode_rate > max_rate || target_clock > max_dotclk) |
| 225 | return MODE_CLOCK_HIGH; |
| 226 | |
| 227 | if (mode->clock < 10000) |
| 228 | return MODE_CLOCK_LOW; |
| 229 | |
| 230 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
| 231 | return MODE_H_ILLEGAL; |
| 232 | |
| 233 | return MODE_OK; |
| 234 | } |
| 235 | |
| 236 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
| 237 | { |
| 238 | int i; |
| 239 | uint32_t v = 0; |
| 240 | |
| 241 | if (src_bytes > 4) |
| 242 | src_bytes = 4; |
| 243 | for (i = 0; i < src_bytes; i++) |
| 244 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
| 245 | return v; |
| 246 | } |
| 247 | |
| 248 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
| 249 | { |
| 250 | int i; |
| 251 | if (dst_bytes > 4) |
| 252 | dst_bytes = 4; |
| 253 | for (i = 0; i < dst_bytes; i++) |
| 254 | dst[i] = src >> ((3-i) * 8); |
| 255 | } |
| 256 | |
| 257 | static void |
| 258 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
| 259 | struct intel_dp *intel_dp); |
| 260 | static void |
| 261 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
| 262 | struct intel_dp *intel_dp); |
| 263 | |
| 264 | static void pps_lock(struct intel_dp *intel_dp) |
| 265 | { |
| 266 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 267 | struct intel_encoder *encoder = &intel_dig_port->base; |
| 268 | struct drm_device *dev = encoder->base.dev; |
| 269 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 270 | enum intel_display_power_domain power_domain; |
| 271 | |
| 272 | /* |
| 273 | * See vlv_power_sequencer_reset() why we need |
| 274 | * a power domain reference here. |
| 275 | */ |
| 276 | power_domain = intel_display_port_aux_power_domain(encoder); |
| 277 | intel_display_power_get(dev_priv, power_domain); |
| 278 | |
| 279 | mutex_lock(&dev_priv->pps_mutex); |
| 280 | } |
| 281 | |
| 282 | static void pps_unlock(struct intel_dp *intel_dp) |
| 283 | { |
| 284 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 285 | struct intel_encoder *encoder = &intel_dig_port->base; |
| 286 | struct drm_device *dev = encoder->base.dev; |
| 287 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 288 | enum intel_display_power_domain power_domain; |
| 289 | |
| 290 | mutex_unlock(&dev_priv->pps_mutex); |
| 291 | |
| 292 | power_domain = intel_display_port_aux_power_domain(encoder); |
| 293 | intel_display_power_put(dev_priv, power_domain); |
| 294 | } |
| 295 | |
| 296 | static void |
| 297 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) |
| 298 | { |
| 299 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 300 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 301 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 302 | enum pipe pipe = intel_dp->pps_pipe; |
| 303 | bool pll_enabled, release_cl_override = false; |
| 304 | enum dpio_phy phy = DPIO_PHY(pipe); |
| 305 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); |
| 306 | uint32_t DP; |
| 307 | |
| 308 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, |
| 309 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", |
| 310 | pipe_name(pipe), port_name(intel_dig_port->port))) |
| 311 | return; |
| 312 | |
| 313 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", |
| 314 | pipe_name(pipe), port_name(intel_dig_port->port)); |
| 315 | |
| 316 | /* Preserve the BIOS-computed detected bit. This is |
| 317 | * supposed to be read-only. |
| 318 | */ |
| 319 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
| 320 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
| 321 | DP |= DP_PORT_WIDTH(1); |
| 322 | DP |= DP_LINK_TRAIN_PAT_1; |
| 323 | |
| 324 | if (IS_CHERRYVIEW(dev)) |
| 325 | DP |= DP_PIPE_SELECT_CHV(pipe); |
| 326 | else if (pipe == PIPE_B) |
| 327 | DP |= DP_PIPEB_SELECT; |
| 328 | |
| 329 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
| 330 | |
| 331 | /* |
| 332 | * The DPLL for the pipe must be enabled for this to work. |
| 333 | * So enable temporarily it if it's not already enabled. |
| 334 | */ |
| 335 | if (!pll_enabled) { |
| 336 | release_cl_override = IS_CHERRYVIEW(dev) && |
| 337 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); |
| 338 | |
| 339 | if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ? |
| 340 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { |
| 341 | DRM_ERROR("Failed to force on pll for pipe %c!\n", |
| 342 | pipe_name(pipe)); |
| 343 | return; |
| 344 | } |
| 345 | } |
| 346 | |
| 347 | /* |
| 348 | * Similar magic as in intel_dp_enable_port(). |
| 349 | * We _must_ do this port enable + disable trick |
| 350 | * to make this power seqeuencer lock onto the port. |
| 351 | * Otherwise even VDD force bit won't work. |
| 352 | */ |
| 353 | I915_WRITE(intel_dp->output_reg, DP); |
| 354 | POSTING_READ(intel_dp->output_reg); |
| 355 | |
| 356 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); |
| 357 | POSTING_READ(intel_dp->output_reg); |
| 358 | |
| 359 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
| 360 | POSTING_READ(intel_dp->output_reg); |
| 361 | |
| 362 | if (!pll_enabled) { |
| 363 | vlv_force_pll_off(dev, pipe); |
| 364 | |
| 365 | if (release_cl_override) |
| 366 | chv_phy_powergate_ch(dev_priv, phy, ch, false); |
| 367 | } |
| 368 | } |
| 369 | |
| 370 | static enum pipe |
| 371 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) |
| 372 | { |
| 373 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 374 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 375 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 376 | struct intel_encoder *encoder; |
| 377 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); |
| 378 | enum pipe pipe; |
| 379 | |
| 380 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 381 | |
| 382 | /* We should never land here with regular DP ports */ |
| 383 | WARN_ON(!is_edp(intel_dp)); |
| 384 | |
| 385 | if (intel_dp->pps_pipe != INVALID_PIPE) |
| 386 | return intel_dp->pps_pipe; |
| 387 | |
| 388 | /* |
| 389 | * We don't have power sequencer currently. |
| 390 | * Pick one that's not used by other ports. |
| 391 | */ |
| 392 | for_each_intel_encoder(dev, encoder) { |
| 393 | struct intel_dp *tmp; |
| 394 | |
| 395 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 396 | continue; |
| 397 | |
| 398 | tmp = enc_to_intel_dp(&encoder->base); |
| 399 | |
| 400 | if (tmp->pps_pipe != INVALID_PIPE) |
| 401 | pipes &= ~(1 << tmp->pps_pipe); |
| 402 | } |
| 403 | |
| 404 | /* |
| 405 | * Didn't find one. This should not happen since there |
| 406 | * are two power sequencers and up to two eDP ports. |
| 407 | */ |
| 408 | if (WARN_ON(pipes == 0)) |
| 409 | pipe = PIPE_A; |
| 410 | else |
| 411 | pipe = ffs(pipes) - 1; |
| 412 | |
| 413 | vlv_steal_power_sequencer(dev, pipe); |
| 414 | intel_dp->pps_pipe = pipe; |
| 415 | |
| 416 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", |
| 417 | pipe_name(intel_dp->pps_pipe), |
| 418 | port_name(intel_dig_port->port)); |
| 419 | |
| 420 | /* init power sequencer on this pipe and port */ |
| 421 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
| 422 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
| 423 | |
| 424 | /* |
| 425 | * Even vdd force doesn't work until we've made |
| 426 | * the power sequencer lock in on the port. |
| 427 | */ |
| 428 | vlv_power_sequencer_kick(intel_dp); |
| 429 | |
| 430 | return intel_dp->pps_pipe; |
| 431 | } |
| 432 | |
| 433 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
| 434 | enum pipe pipe); |
| 435 | |
| 436 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, |
| 437 | enum pipe pipe) |
| 438 | { |
| 439 | return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON; |
| 440 | } |
| 441 | |
| 442 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, |
| 443 | enum pipe pipe) |
| 444 | { |
| 445 | return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
| 446 | } |
| 447 | |
| 448 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, |
| 449 | enum pipe pipe) |
| 450 | { |
| 451 | return true; |
| 452 | } |
| 453 | |
| 454 | static enum pipe |
| 455 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
| 456 | enum port port, |
| 457 | vlv_pipe_check pipe_check) |
| 458 | { |
| 459 | enum pipe pipe; |
| 460 | |
| 461 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
| 462 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & |
| 463 | PANEL_PORT_SELECT_MASK; |
| 464 | |
| 465 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) |
| 466 | continue; |
| 467 | |
| 468 | if (!pipe_check(dev_priv, pipe)) |
| 469 | continue; |
| 470 | |
| 471 | return pipe; |
| 472 | } |
| 473 | |
| 474 | return INVALID_PIPE; |
| 475 | } |
| 476 | |
| 477 | static void |
| 478 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) |
| 479 | { |
| 480 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 481 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 482 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 483 | enum port port = intel_dig_port->port; |
| 484 | |
| 485 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 486 | |
| 487 | /* try to find a pipe with this port selected */ |
| 488 | /* first pick one where the panel is on */ |
| 489 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| 490 | vlv_pipe_has_pp_on); |
| 491 | /* didn't find one? pick one where vdd is on */ |
| 492 | if (intel_dp->pps_pipe == INVALID_PIPE) |
| 493 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| 494 | vlv_pipe_has_vdd_on); |
| 495 | /* didn't find one? pick one with just the correct port */ |
| 496 | if (intel_dp->pps_pipe == INVALID_PIPE) |
| 497 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| 498 | vlv_pipe_any); |
| 499 | |
| 500 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ |
| 501 | if (intel_dp->pps_pipe == INVALID_PIPE) { |
| 502 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", |
| 503 | port_name(port)); |
| 504 | return; |
| 505 | } |
| 506 | |
| 507 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
| 508 | port_name(port), pipe_name(intel_dp->pps_pipe)); |
| 509 | |
| 510 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
| 511 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
| 512 | } |
| 513 | |
| 514 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv) |
| 515 | { |
| 516 | struct drm_device *dev = dev_priv->dev; |
| 517 | struct intel_encoder *encoder; |
| 518 | |
| 519 | if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))) |
| 520 | return; |
| 521 | |
| 522 | /* |
| 523 | * We can't grab pps_mutex here due to deadlock with power_domain |
| 524 | * mutex when power_domain functions are called while holding pps_mutex. |
| 525 | * That also means that in order to use pps_pipe the code needs to |
| 526 | * hold both a power domain reference and pps_mutex, and the power domain |
| 527 | * reference get/put must be done while _not_ holding pps_mutex. |
| 528 | * pps_{lock,unlock}() do these steps in the correct order, so one |
| 529 | * should use them always. |
| 530 | */ |
| 531 | |
| 532 | for_each_intel_encoder(dev, encoder) { |
| 533 | struct intel_dp *intel_dp; |
| 534 | |
| 535 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 536 | continue; |
| 537 | |
| 538 | intel_dp = enc_to_intel_dp(&encoder->base); |
| 539 | intel_dp->pps_pipe = INVALID_PIPE; |
| 540 | } |
| 541 | } |
| 542 | |
| 543 | static i915_reg_t |
| 544 | _pp_ctrl_reg(struct intel_dp *intel_dp) |
| 545 | { |
| 546 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 547 | |
| 548 | if (IS_BROXTON(dev)) |
| 549 | return BXT_PP_CONTROL(0); |
| 550 | else if (HAS_PCH_SPLIT(dev)) |
| 551 | return PCH_PP_CONTROL; |
| 552 | else |
| 553 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); |
| 554 | } |
| 555 | |
| 556 | static i915_reg_t |
| 557 | _pp_stat_reg(struct intel_dp *intel_dp) |
| 558 | { |
| 559 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 560 | |
| 561 | if (IS_BROXTON(dev)) |
| 562 | return BXT_PP_STATUS(0); |
| 563 | else if (HAS_PCH_SPLIT(dev)) |
| 564 | return PCH_PP_STATUS; |
| 565 | else |
| 566 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); |
| 567 | } |
| 568 | |
| 569 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
| 570 | This function only applicable when panel PM state is not to be tracked */ |
| 571 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, |
| 572 | void *unused) |
| 573 | { |
| 574 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), |
| 575 | edp_notifier); |
| 576 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 577 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 578 | |
| 579 | if (!is_edp(intel_dp) || code != SYS_RESTART) |
| 580 | return 0; |
| 581 | |
| 582 | pps_lock(intel_dp); |
| 583 | |
| 584 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
| 585 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
| 586 | i915_reg_t pp_ctrl_reg, pp_div_reg; |
| 587 | u32 pp_div; |
| 588 | |
| 589 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
| 590 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
| 591 | pp_div = I915_READ(pp_div_reg); |
| 592 | pp_div &= PP_REFERENCE_DIVIDER_MASK; |
| 593 | |
| 594 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ |
| 595 | I915_WRITE(pp_div_reg, pp_div | 0x1F); |
| 596 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); |
| 597 | msleep(intel_dp->panel_power_cycle_delay); |
| 598 | } |
| 599 | |
| 600 | pps_unlock(intel_dp); |
| 601 | |
| 602 | return 0; |
| 603 | } |
| 604 | |
| 605 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
| 606 | { |
| 607 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 608 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 609 | |
| 610 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 611 | |
| 612 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
| 613 | intel_dp->pps_pipe == INVALID_PIPE) |
| 614 | return false; |
| 615 | |
| 616 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
| 617 | } |
| 618 | |
| 619 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
| 620 | { |
| 621 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 622 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 623 | |
| 624 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 625 | |
| 626 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
| 627 | intel_dp->pps_pipe == INVALID_PIPE) |
| 628 | return false; |
| 629 | |
| 630 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
| 631 | } |
| 632 | |
| 633 | static void |
| 634 | intel_dp_check_edp(struct intel_dp *intel_dp) |
| 635 | { |
| 636 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 637 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 638 | |
| 639 | if (!is_edp(intel_dp)) |
| 640 | return; |
| 641 | |
| 642 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
| 643 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
| 644 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
| 645 | I915_READ(_pp_stat_reg(intel_dp)), |
| 646 | I915_READ(_pp_ctrl_reg(intel_dp))); |
| 647 | } |
| 648 | } |
| 649 | |
| 650 | static uint32_t |
| 651 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) |
| 652 | { |
| 653 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 654 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 655 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 656 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
| 657 | uint32_t status; |
| 658 | bool done; |
| 659 | |
| 660 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
| 661 | if (has_aux_irq) |
| 662 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
| 663 | msecs_to_jiffies_timeout(10)); |
| 664 | else |
| 665 | done = wait_for_atomic(C, 10) == 0; |
| 666 | if (!done) |
| 667 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", |
| 668 | has_aux_irq); |
| 669 | #undef C |
| 670 | |
| 671 | return status; |
| 672 | } |
| 673 | |
| 674 | static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 675 | { |
| 676 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 677 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
| 678 | |
| 679 | if (index) |
| 680 | return 0; |
| 681 | |
| 682 | /* |
| 683 | * The clock divider is based off the hrawclk, and would like to run at |
| 684 | * 2MHz. So, take the hrawclk value and divide by 2000 and use that |
| 685 | */ |
| 686 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); |
| 687 | } |
| 688 | |
| 689 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 690 | { |
| 691 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 692 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
| 693 | |
| 694 | if (index) |
| 695 | return 0; |
| 696 | |
| 697 | /* |
| 698 | * The clock divider is based off the cdclk or PCH rawclk, and would |
| 699 | * like to run at 2MHz. So, take the cdclk or PCH rawclk value and |
| 700 | * divide by 2000 and use that |
| 701 | */ |
| 702 | if (intel_dig_port->port == PORT_A) |
| 703 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
| 704 | else |
| 705 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); |
| 706 | } |
| 707 | |
| 708 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 709 | { |
| 710 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 711 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
| 712 | |
| 713 | if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) { |
| 714 | /* Workaround for non-ULT HSW */ |
| 715 | switch (index) { |
| 716 | case 0: return 63; |
| 717 | case 1: return 72; |
| 718 | default: return 0; |
| 719 | } |
| 720 | } |
| 721 | |
| 722 | return ilk_get_aux_clock_divider(intel_dp, index); |
| 723 | } |
| 724 | |
| 725 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 726 | { |
| 727 | /* |
| 728 | * SKL doesn't need us to program the AUX clock divider (Hardware will |
| 729 | * derive the clock from CDCLK automatically). We still implement the |
| 730 | * get_aux_clock_divider vfunc to plug-in into the existing code. |
| 731 | */ |
| 732 | return index ? 0 : 1; |
| 733 | } |
| 734 | |
| 735 | static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, |
| 736 | bool has_aux_irq, |
| 737 | int send_bytes, |
| 738 | uint32_t aux_clock_divider) |
| 739 | { |
| 740 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 741 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 742 | uint32_t precharge, timeout; |
| 743 | |
| 744 | if (IS_GEN6(dev)) |
| 745 | precharge = 3; |
| 746 | else |
| 747 | precharge = 5; |
| 748 | |
| 749 | if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A) |
| 750 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
| 751 | else |
| 752 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; |
| 753 | |
| 754 | return DP_AUX_CH_CTL_SEND_BUSY | |
| 755 | DP_AUX_CH_CTL_DONE | |
| 756 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
| 757 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 758 | timeout | |
| 759 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
| 760 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| 761 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
| 762 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
| 763 | } |
| 764 | |
| 765 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
| 766 | bool has_aux_irq, |
| 767 | int send_bytes, |
| 768 | uint32_t unused) |
| 769 | { |
| 770 | return DP_AUX_CH_CTL_SEND_BUSY | |
| 771 | DP_AUX_CH_CTL_DONE | |
| 772 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
| 773 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 774 | DP_AUX_CH_CTL_TIME_OUT_1600us | |
| 775 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
| 776 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| 777 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
| 778 | } |
| 779 | |
| 780 | static int |
| 781 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
| 782 | const uint8_t *send, int send_bytes, |
| 783 | uint8_t *recv, int recv_size) |
| 784 | { |
| 785 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 786 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 787 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 788 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
| 789 | uint32_t aux_clock_divider; |
| 790 | int i, ret, recv_bytes; |
| 791 | uint32_t status; |
| 792 | int try, clock = 0; |
| 793 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
| 794 | bool vdd; |
| 795 | |
| 796 | pps_lock(intel_dp); |
| 797 | |
| 798 | /* |
| 799 | * We will be called with VDD already enabled for dpcd/edid/oui reads. |
| 800 | * In such cases we want to leave VDD enabled and it's up to upper layers |
| 801 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off |
| 802 | * ourselves. |
| 803 | */ |
| 804 | vdd = edp_panel_vdd_on(intel_dp); |
| 805 | |
| 806 | /* dp aux is extremely sensitive to irq latency, hence request the |
| 807 | * lowest possible wakeup latency and so prevent the cpu from going into |
| 808 | * deep sleep states. |
| 809 | */ |
| 810 | pm_qos_update_request(&dev_priv->pm_qos, 0); |
| 811 | |
| 812 | intel_dp_check_edp(intel_dp); |
| 813 | |
| 814 | /* Try to wait for any previous AUX channel activity */ |
| 815 | for (try = 0; try < 3; try++) { |
| 816 | status = I915_READ_NOTRACE(ch_ctl); |
| 817 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
| 818 | break; |
| 819 | msleep(1); |
| 820 | } |
| 821 | |
| 822 | if (try == 3) { |
| 823 | static u32 last_status = -1; |
| 824 | const u32 status = I915_READ(ch_ctl); |
| 825 | |
| 826 | if (status != last_status) { |
| 827 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
| 828 | status); |
| 829 | last_status = status; |
| 830 | } |
| 831 | |
| 832 | ret = -EBUSY; |
| 833 | goto out; |
| 834 | } |
| 835 | |
| 836 | /* Only 5 data registers! */ |
| 837 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { |
| 838 | ret = -E2BIG; |
| 839 | goto out; |
| 840 | } |
| 841 | |
| 842 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
| 843 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
| 844 | has_aux_irq, |
| 845 | send_bytes, |
| 846 | aux_clock_divider); |
| 847 | |
| 848 | /* Must try at least 3 times according to DP spec */ |
| 849 | for (try = 0; try < 5; try++) { |
| 850 | /* Load the send data into the aux channel data registers */ |
| 851 | for (i = 0; i < send_bytes; i += 4) |
| 852 | I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], |
| 853 | intel_dp_pack_aux(send + i, |
| 854 | send_bytes - i)); |
| 855 | |
| 856 | /* Send the command and wait for it to complete */ |
| 857 | I915_WRITE(ch_ctl, send_ctl); |
| 858 | |
| 859 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); |
| 860 | |
| 861 | /* Clear done status and any errors */ |
| 862 | I915_WRITE(ch_ctl, |
| 863 | status | |
| 864 | DP_AUX_CH_CTL_DONE | |
| 865 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 866 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
| 867 | |
| 868 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
| 869 | continue; |
| 870 | |
| 871 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 |
| 872 | * 400us delay required for errors and timeouts |
| 873 | * Timeout errors from the HW already meet this |
| 874 | * requirement so skip to next iteration |
| 875 | */ |
| 876 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
| 877 | usleep_range(400, 500); |
| 878 | continue; |
| 879 | } |
| 880 | if (status & DP_AUX_CH_CTL_DONE) |
| 881 | goto done; |
| 882 | } |
| 883 | } |
| 884 | |
| 885 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
| 886 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
| 887 | ret = -EBUSY; |
| 888 | goto out; |
| 889 | } |
| 890 | |
| 891 | done: |
| 892 | /* Check for timeout or receive error. |
| 893 | * Timeouts occur when the sink is not connected |
| 894 | */ |
| 895 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
| 896 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
| 897 | ret = -EIO; |
| 898 | goto out; |
| 899 | } |
| 900 | |
| 901 | /* Timeouts occur when the device isn't connected, so they're |
| 902 | * "normal" -- don't fill the kernel log with these */ |
| 903 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
| 904 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
| 905 | ret = -ETIMEDOUT; |
| 906 | goto out; |
| 907 | } |
| 908 | |
| 909 | /* Unload any bytes sent back from the other side */ |
| 910 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
| 911 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
| 912 | |
| 913 | /* |
| 914 | * By BSpec: "Message sizes of 0 or >20 are not allowed." |
| 915 | * We have no idea of what happened so we return -EBUSY so |
| 916 | * drm layer takes care for the necessary retries. |
| 917 | */ |
| 918 | if (recv_bytes == 0 || recv_bytes > 20) { |
| 919 | DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", |
| 920 | recv_bytes); |
| 921 | /* |
| 922 | * FIXME: This patch was created on top of a series that |
| 923 | * organize the retries at drm level. There EBUSY should |
| 924 | * also take care for 1ms wait before retrying. |
| 925 | * That aux retries re-org is still needed and after that is |
| 926 | * merged we remove this sleep from here. |
| 927 | */ |
| 928 | usleep_range(1000, 1500); |
| 929 | ret = -EBUSY; |
| 930 | goto out; |
| 931 | } |
| 932 | |
| 933 | if (recv_bytes > recv_size) |
| 934 | recv_bytes = recv_size; |
| 935 | |
| 936 | for (i = 0; i < recv_bytes; i += 4) |
| 937 | intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]), |
| 938 | recv + i, recv_bytes - i); |
| 939 | |
| 940 | ret = recv_bytes; |
| 941 | out: |
| 942 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); |
| 943 | |
| 944 | if (vdd) |
| 945 | edp_panel_vdd_off(intel_dp, false); |
| 946 | |
| 947 | pps_unlock(intel_dp); |
| 948 | |
| 949 | return ret; |
| 950 | } |
| 951 | |
| 952 | #define BARE_ADDRESS_SIZE 3 |
| 953 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) |
| 954 | static ssize_t |
| 955 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
| 956 | { |
| 957 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
| 958 | uint8_t txbuf[20], rxbuf[20]; |
| 959 | size_t txsize, rxsize; |
| 960 | int ret; |
| 961 | |
| 962 | txbuf[0] = (msg->request << 4) | |
| 963 | ((msg->address >> 16) & 0xf); |
| 964 | txbuf[1] = (msg->address >> 8) & 0xff; |
| 965 | txbuf[2] = msg->address & 0xff; |
| 966 | txbuf[3] = msg->size - 1; |
| 967 | |
| 968 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
| 969 | case DP_AUX_NATIVE_WRITE: |
| 970 | case DP_AUX_I2C_WRITE: |
| 971 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
| 972 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
| 973 | rxsize = 2; /* 0 or 1 data bytes */ |
| 974 | |
| 975 | if (WARN_ON(txsize > 20)) |
| 976 | return -E2BIG; |
| 977 | |
| 978 | if (msg->buffer) |
| 979 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); |
| 980 | else |
| 981 | WARN_ON(msg->size); |
| 982 | |
| 983 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
| 984 | if (ret > 0) { |
| 985 | msg->reply = rxbuf[0] >> 4; |
| 986 | |
| 987 | if (ret > 1) { |
| 988 | /* Number of bytes written in a short write. */ |
| 989 | ret = clamp_t(int, rxbuf[1], 0, msg->size); |
| 990 | } else { |
| 991 | /* Return payload size. */ |
| 992 | ret = msg->size; |
| 993 | } |
| 994 | } |
| 995 | break; |
| 996 | |
| 997 | case DP_AUX_NATIVE_READ: |
| 998 | case DP_AUX_I2C_READ: |
| 999 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
| 1000 | rxsize = msg->size + 1; |
| 1001 | |
| 1002 | if (WARN_ON(rxsize > 20)) |
| 1003 | return -E2BIG; |
| 1004 | |
| 1005 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
| 1006 | if (ret > 0) { |
| 1007 | msg->reply = rxbuf[0] >> 4; |
| 1008 | /* |
| 1009 | * Assume happy day, and copy the data. The caller is |
| 1010 | * expected to check msg->reply before touching it. |
| 1011 | * |
| 1012 | * Return payload size. |
| 1013 | */ |
| 1014 | ret--; |
| 1015 | memcpy(msg->buffer, rxbuf + 1, ret); |
| 1016 | } |
| 1017 | break; |
| 1018 | |
| 1019 | default: |
| 1020 | ret = -EINVAL; |
| 1021 | break; |
| 1022 | } |
| 1023 | |
| 1024 | return ret; |
| 1025 | } |
| 1026 | |
| 1027 | static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, |
| 1028 | enum port port) |
| 1029 | { |
| 1030 | switch (port) { |
| 1031 | case PORT_B: |
| 1032 | case PORT_C: |
| 1033 | case PORT_D: |
| 1034 | return DP_AUX_CH_CTL(port); |
| 1035 | default: |
| 1036 | MISSING_CASE(port); |
| 1037 | return DP_AUX_CH_CTL(PORT_B); |
| 1038 | } |
| 1039 | } |
| 1040 | |
| 1041 | static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv, |
| 1042 | enum port port, int index) |
| 1043 | { |
| 1044 | switch (port) { |
| 1045 | case PORT_B: |
| 1046 | case PORT_C: |
| 1047 | case PORT_D: |
| 1048 | return DP_AUX_CH_DATA(port, index); |
| 1049 | default: |
| 1050 | MISSING_CASE(port); |
| 1051 | return DP_AUX_CH_DATA(PORT_B, index); |
| 1052 | } |
| 1053 | } |
| 1054 | |
| 1055 | static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv, |
| 1056 | enum port port) |
| 1057 | { |
| 1058 | switch (port) { |
| 1059 | case PORT_A: |
| 1060 | return DP_AUX_CH_CTL(port); |
| 1061 | case PORT_B: |
| 1062 | case PORT_C: |
| 1063 | case PORT_D: |
| 1064 | return PCH_DP_AUX_CH_CTL(port); |
| 1065 | default: |
| 1066 | MISSING_CASE(port); |
| 1067 | return DP_AUX_CH_CTL(PORT_A); |
| 1068 | } |
| 1069 | } |
| 1070 | |
| 1071 | static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv, |
| 1072 | enum port port, int index) |
| 1073 | { |
| 1074 | switch (port) { |
| 1075 | case PORT_A: |
| 1076 | return DP_AUX_CH_DATA(port, index); |
| 1077 | case PORT_B: |
| 1078 | case PORT_C: |
| 1079 | case PORT_D: |
| 1080 | return PCH_DP_AUX_CH_DATA(port, index); |
| 1081 | default: |
| 1082 | MISSING_CASE(port); |
| 1083 | return DP_AUX_CH_DATA(PORT_A, index); |
| 1084 | } |
| 1085 | } |
| 1086 | |
| 1087 | /* |
| 1088 | * On SKL we don't have Aux for port E so we rely |
| 1089 | * on VBT to set a proper alternate aux channel. |
| 1090 | */ |
| 1091 | static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv) |
| 1092 | { |
| 1093 | const struct ddi_vbt_port_info *info = |
| 1094 | &dev_priv->vbt.ddi_port_info[PORT_E]; |
| 1095 | |
| 1096 | switch (info->alternate_aux_channel) { |
| 1097 | case DP_AUX_A: |
| 1098 | return PORT_A; |
| 1099 | case DP_AUX_B: |
| 1100 | return PORT_B; |
| 1101 | case DP_AUX_C: |
| 1102 | return PORT_C; |
| 1103 | case DP_AUX_D: |
| 1104 | return PORT_D; |
| 1105 | default: |
| 1106 | MISSING_CASE(info->alternate_aux_channel); |
| 1107 | return PORT_A; |
| 1108 | } |
| 1109 | } |
| 1110 | |
| 1111 | static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, |
| 1112 | enum port port) |
| 1113 | { |
| 1114 | if (port == PORT_E) |
| 1115 | port = skl_porte_aux_port(dev_priv); |
| 1116 | |
| 1117 | switch (port) { |
| 1118 | case PORT_A: |
| 1119 | case PORT_B: |
| 1120 | case PORT_C: |
| 1121 | case PORT_D: |
| 1122 | return DP_AUX_CH_CTL(port); |
| 1123 | default: |
| 1124 | MISSING_CASE(port); |
| 1125 | return DP_AUX_CH_CTL(PORT_A); |
| 1126 | } |
| 1127 | } |
| 1128 | |
| 1129 | static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, |
| 1130 | enum port port, int index) |
| 1131 | { |
| 1132 | if (port == PORT_E) |
| 1133 | port = skl_porte_aux_port(dev_priv); |
| 1134 | |
| 1135 | switch (port) { |
| 1136 | case PORT_A: |
| 1137 | case PORT_B: |
| 1138 | case PORT_C: |
| 1139 | case PORT_D: |
| 1140 | return DP_AUX_CH_DATA(port, index); |
| 1141 | default: |
| 1142 | MISSING_CASE(port); |
| 1143 | return DP_AUX_CH_DATA(PORT_A, index); |
| 1144 | } |
| 1145 | } |
| 1146 | |
| 1147 | static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv, |
| 1148 | enum port port) |
| 1149 | { |
| 1150 | if (INTEL_INFO(dev_priv)->gen >= 9) |
| 1151 | return skl_aux_ctl_reg(dev_priv, port); |
| 1152 | else if (HAS_PCH_SPLIT(dev_priv)) |
| 1153 | return ilk_aux_ctl_reg(dev_priv, port); |
| 1154 | else |
| 1155 | return g4x_aux_ctl_reg(dev_priv, port); |
| 1156 | } |
| 1157 | |
| 1158 | static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv, |
| 1159 | enum port port, int index) |
| 1160 | { |
| 1161 | if (INTEL_INFO(dev_priv)->gen >= 9) |
| 1162 | return skl_aux_data_reg(dev_priv, port, index); |
| 1163 | else if (HAS_PCH_SPLIT(dev_priv)) |
| 1164 | return ilk_aux_data_reg(dev_priv, port, index); |
| 1165 | else |
| 1166 | return g4x_aux_data_reg(dev_priv, port, index); |
| 1167 | } |
| 1168 | |
| 1169 | static void intel_aux_reg_init(struct intel_dp *intel_dp) |
| 1170 | { |
| 1171 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
| 1172 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 1173 | int i; |
| 1174 | |
| 1175 | intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); |
| 1176 | for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++) |
| 1177 | intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i); |
| 1178 | } |
| 1179 | |
| 1180 | static void |
| 1181 | intel_dp_aux_fini(struct intel_dp *intel_dp) |
| 1182 | { |
| 1183 | drm_dp_aux_unregister(&intel_dp->aux); |
| 1184 | kfree(intel_dp->aux.name); |
| 1185 | } |
| 1186 | |
| 1187 | static int |
| 1188 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) |
| 1189 | { |
| 1190 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1191 | enum port port = intel_dig_port->port; |
| 1192 | int ret; |
| 1193 | |
| 1194 | intel_aux_reg_init(intel_dp); |
| 1195 | |
| 1196 | intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port)); |
| 1197 | if (!intel_dp->aux.name) |
| 1198 | return -ENOMEM; |
| 1199 | |
| 1200 | intel_dp->aux.dev = connector->base.kdev; |
| 1201 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
| 1202 | |
| 1203 | DRM_DEBUG_KMS("registering %s bus for %s\n", |
| 1204 | intel_dp->aux.name, |
| 1205 | connector->base.kdev->kobj.name); |
| 1206 | |
| 1207 | ret = drm_dp_aux_register(&intel_dp->aux); |
| 1208 | if (ret < 0) { |
| 1209 | DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n", |
| 1210 | intel_dp->aux.name, ret); |
| 1211 | kfree(intel_dp->aux.name); |
| 1212 | return ret; |
| 1213 | } |
| 1214 | |
| 1215 | return 0; |
| 1216 | } |
| 1217 | |
| 1218 | static void |
| 1219 | intel_dp_connector_unregister(struct intel_connector *intel_connector) |
| 1220 | { |
| 1221 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); |
| 1222 | |
| 1223 | intel_dp_aux_fini(intel_dp); |
| 1224 | intel_connector_unregister(intel_connector); |
| 1225 | } |
| 1226 | |
| 1227 | static int |
| 1228 | intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) |
| 1229 | { |
| 1230 | if (intel_dp->num_sink_rates) { |
| 1231 | *sink_rates = intel_dp->sink_rates; |
| 1232 | return intel_dp->num_sink_rates; |
| 1233 | } |
| 1234 | |
| 1235 | *sink_rates = default_rates; |
| 1236 | |
| 1237 | return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; |
| 1238 | } |
| 1239 | |
| 1240 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
| 1241 | { |
| 1242 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1243 | struct drm_device *dev = dig_port->base.base.dev; |
| 1244 | |
| 1245 | /* WaDisableHBR2:skl */ |
| 1246 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0)) |
| 1247 | return false; |
| 1248 | |
| 1249 | if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || |
| 1250 | (INTEL_INFO(dev)->gen >= 9)) |
| 1251 | return true; |
| 1252 | else |
| 1253 | return false; |
| 1254 | } |
| 1255 | |
| 1256 | static int |
| 1257 | intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates) |
| 1258 | { |
| 1259 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1260 | struct drm_device *dev = dig_port->base.base.dev; |
| 1261 | int size; |
| 1262 | |
| 1263 | if (IS_BROXTON(dev)) { |
| 1264 | *source_rates = bxt_rates; |
| 1265 | size = ARRAY_SIZE(bxt_rates); |
| 1266 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
| 1267 | *source_rates = skl_rates; |
| 1268 | size = ARRAY_SIZE(skl_rates); |
| 1269 | } else { |
| 1270 | *source_rates = default_rates; |
| 1271 | size = ARRAY_SIZE(default_rates); |
| 1272 | } |
| 1273 | |
| 1274 | /* This depends on the fact that 5.4 is last value in the array */ |
| 1275 | if (!intel_dp_source_supports_hbr2(intel_dp)) |
| 1276 | size--; |
| 1277 | |
| 1278 | return size; |
| 1279 | } |
| 1280 | |
| 1281 | static void |
| 1282 | intel_dp_set_clock(struct intel_encoder *encoder, |
| 1283 | struct intel_crtc_state *pipe_config) |
| 1284 | { |
| 1285 | struct drm_device *dev = encoder->base.dev; |
| 1286 | const struct dp_link_dpll *divisor = NULL; |
| 1287 | int i, count = 0; |
| 1288 | |
| 1289 | if (IS_G4X(dev)) { |
| 1290 | divisor = gen4_dpll; |
| 1291 | count = ARRAY_SIZE(gen4_dpll); |
| 1292 | } else if (HAS_PCH_SPLIT(dev)) { |
| 1293 | divisor = pch_dpll; |
| 1294 | count = ARRAY_SIZE(pch_dpll); |
| 1295 | } else if (IS_CHERRYVIEW(dev)) { |
| 1296 | divisor = chv_dpll; |
| 1297 | count = ARRAY_SIZE(chv_dpll); |
| 1298 | } else if (IS_VALLEYVIEW(dev)) { |
| 1299 | divisor = vlv_dpll; |
| 1300 | count = ARRAY_SIZE(vlv_dpll); |
| 1301 | } |
| 1302 | |
| 1303 | if (divisor && count) { |
| 1304 | for (i = 0; i < count; i++) { |
| 1305 | if (pipe_config->port_clock == divisor[i].clock) { |
| 1306 | pipe_config->dpll = divisor[i].dpll; |
| 1307 | pipe_config->clock_set = true; |
| 1308 | break; |
| 1309 | } |
| 1310 | } |
| 1311 | } |
| 1312 | } |
| 1313 | |
| 1314 | static int intersect_rates(const int *source_rates, int source_len, |
| 1315 | const int *sink_rates, int sink_len, |
| 1316 | int *common_rates) |
| 1317 | { |
| 1318 | int i = 0, j = 0, k = 0; |
| 1319 | |
| 1320 | while (i < source_len && j < sink_len) { |
| 1321 | if (source_rates[i] == sink_rates[j]) { |
| 1322 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) |
| 1323 | return k; |
| 1324 | common_rates[k] = source_rates[i]; |
| 1325 | ++k; |
| 1326 | ++i; |
| 1327 | ++j; |
| 1328 | } else if (source_rates[i] < sink_rates[j]) { |
| 1329 | ++i; |
| 1330 | } else { |
| 1331 | ++j; |
| 1332 | } |
| 1333 | } |
| 1334 | return k; |
| 1335 | } |
| 1336 | |
| 1337 | static int intel_dp_common_rates(struct intel_dp *intel_dp, |
| 1338 | int *common_rates) |
| 1339 | { |
| 1340 | const int *source_rates, *sink_rates; |
| 1341 | int source_len, sink_len; |
| 1342 | |
| 1343 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); |
| 1344 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
| 1345 | |
| 1346 | return intersect_rates(source_rates, source_len, |
| 1347 | sink_rates, sink_len, |
| 1348 | common_rates); |
| 1349 | } |
| 1350 | |
| 1351 | static void snprintf_int_array(char *str, size_t len, |
| 1352 | const int *array, int nelem) |
| 1353 | { |
| 1354 | int i; |
| 1355 | |
| 1356 | str[0] = '\0'; |
| 1357 | |
| 1358 | for (i = 0; i < nelem; i++) { |
| 1359 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
| 1360 | if (r >= len) |
| 1361 | return; |
| 1362 | str += r; |
| 1363 | len -= r; |
| 1364 | } |
| 1365 | } |
| 1366 | |
| 1367 | static void intel_dp_print_rates(struct intel_dp *intel_dp) |
| 1368 | { |
| 1369 | const int *source_rates, *sink_rates; |
| 1370 | int source_len, sink_len, common_len; |
| 1371 | int common_rates[DP_MAX_SUPPORTED_RATES]; |
| 1372 | char str[128]; /* FIXME: too big for stack? */ |
| 1373 | |
| 1374 | if ((drm_debug & DRM_UT_KMS) == 0) |
| 1375 | return; |
| 1376 | |
| 1377 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
| 1378 | snprintf_int_array(str, sizeof(str), source_rates, source_len); |
| 1379 | DRM_DEBUG_KMS("source rates: %s\n", str); |
| 1380 | |
| 1381 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); |
| 1382 | snprintf_int_array(str, sizeof(str), sink_rates, sink_len); |
| 1383 | DRM_DEBUG_KMS("sink rates: %s\n", str); |
| 1384 | |
| 1385 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
| 1386 | snprintf_int_array(str, sizeof(str), common_rates, common_len); |
| 1387 | DRM_DEBUG_KMS("common rates: %s\n", str); |
| 1388 | } |
| 1389 | |
| 1390 | static int rate_to_index(int find, const int *rates) |
| 1391 | { |
| 1392 | int i = 0; |
| 1393 | |
| 1394 | for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) |
| 1395 | if (find == rates[i]) |
| 1396 | break; |
| 1397 | |
| 1398 | return i; |
| 1399 | } |
| 1400 | |
| 1401 | int |
| 1402 | intel_dp_max_link_rate(struct intel_dp *intel_dp) |
| 1403 | { |
| 1404 | int rates[DP_MAX_SUPPORTED_RATES] = {}; |
| 1405 | int len; |
| 1406 | |
| 1407 | len = intel_dp_common_rates(intel_dp, rates); |
| 1408 | if (WARN_ON(len <= 0)) |
| 1409 | return 162000; |
| 1410 | |
| 1411 | return rates[rate_to_index(0, rates) - 1]; |
| 1412 | } |
| 1413 | |
| 1414 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
| 1415 | { |
| 1416 | return rate_to_index(rate, intel_dp->sink_rates); |
| 1417 | } |
| 1418 | |
| 1419 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
| 1420 | uint8_t *link_bw, uint8_t *rate_select) |
| 1421 | { |
| 1422 | if (intel_dp->num_sink_rates) { |
| 1423 | *link_bw = 0; |
| 1424 | *rate_select = |
| 1425 | intel_dp_rate_select(intel_dp, port_clock); |
| 1426 | } else { |
| 1427 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); |
| 1428 | *rate_select = 0; |
| 1429 | } |
| 1430 | } |
| 1431 | |
| 1432 | bool |
| 1433 | intel_dp_compute_config(struct intel_encoder *encoder, |
| 1434 | struct intel_crtc_state *pipe_config) |
| 1435 | { |
| 1436 | struct drm_device *dev = encoder->base.dev; |
| 1437 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1438 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
| 1439 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1440 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 1441 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
| 1442 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 1443 | int lane_count, clock; |
| 1444 | int min_lane_count = 1; |
| 1445 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
| 1446 | /* Conveniently, the link BW constants become indices with a shift...*/ |
| 1447 | int min_clock = 0; |
| 1448 | int max_clock; |
| 1449 | int bpp, mode_rate; |
| 1450 | int link_avail, link_clock; |
| 1451 | int common_rates[DP_MAX_SUPPORTED_RATES] = {}; |
| 1452 | int common_len; |
| 1453 | uint8_t link_bw, rate_select; |
| 1454 | |
| 1455 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
| 1456 | |
| 1457 | /* No common link rates between source and sink */ |
| 1458 | WARN_ON(common_len <= 0); |
| 1459 | |
| 1460 | max_clock = common_len - 1; |
| 1461 | |
| 1462 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
| 1463 | pipe_config->has_pch_encoder = true; |
| 1464 | |
| 1465 | pipe_config->has_dp_encoder = true; |
| 1466 | pipe_config->has_drrs = false; |
| 1467 | pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; |
| 1468 | |
| 1469 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
| 1470 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
| 1471 | adjusted_mode); |
| 1472 | |
| 1473 | if (INTEL_INFO(dev)->gen >= 9) { |
| 1474 | int ret; |
| 1475 | ret = skl_update_scaler_crtc(pipe_config); |
| 1476 | if (ret) |
| 1477 | return ret; |
| 1478 | } |
| 1479 | |
| 1480 | if (HAS_GMCH_DISPLAY(dev)) |
| 1481 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
| 1482 | intel_connector->panel.fitting_mode); |
| 1483 | else |
| 1484 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
| 1485 | intel_connector->panel.fitting_mode); |
| 1486 | } |
| 1487 | |
| 1488 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
| 1489 | return false; |
| 1490 | |
| 1491 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
| 1492 | "max bw %d pixel clock %iKHz\n", |
| 1493 | max_lane_count, common_rates[max_clock], |
| 1494 | adjusted_mode->crtc_clock); |
| 1495 | |
| 1496 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
| 1497 | * bpc in between. */ |
| 1498 | bpp = pipe_config->pipe_bpp; |
| 1499 | if (is_edp(intel_dp)) { |
| 1500 | |
| 1501 | /* Get bpp from vbt only for panels that dont have bpp in edid */ |
| 1502 | if (intel_connector->base.display_info.bpc == 0 && |
| 1503 | (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) { |
| 1504 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
| 1505 | dev_priv->vbt.edp.bpp); |
| 1506 | bpp = dev_priv->vbt.edp.bpp; |
| 1507 | } |
| 1508 | |
| 1509 | /* |
| 1510 | * Use the maximum clock and number of lanes the eDP panel |
| 1511 | * advertizes being capable of. The panels are generally |
| 1512 | * designed to support only a single clock and lane |
| 1513 | * configuration, and typically these values correspond to the |
| 1514 | * native resolution of the panel. |
| 1515 | */ |
| 1516 | min_lane_count = max_lane_count; |
| 1517 | min_clock = max_clock; |
| 1518 | } |
| 1519 | |
| 1520 | for (; bpp >= 6*3; bpp -= 2*3) { |
| 1521 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
| 1522 | bpp); |
| 1523 | |
| 1524 | for (clock = min_clock; clock <= max_clock; clock++) { |
| 1525 | for (lane_count = min_lane_count; |
| 1526 | lane_count <= max_lane_count; |
| 1527 | lane_count <<= 1) { |
| 1528 | |
| 1529 | link_clock = common_rates[clock]; |
| 1530 | link_avail = intel_dp_max_data_rate(link_clock, |
| 1531 | lane_count); |
| 1532 | |
| 1533 | if (mode_rate <= link_avail) { |
| 1534 | goto found; |
| 1535 | } |
| 1536 | } |
| 1537 | } |
| 1538 | } |
| 1539 | |
| 1540 | return false; |
| 1541 | |
| 1542 | found: |
| 1543 | if (intel_dp->color_range_auto) { |
| 1544 | /* |
| 1545 | * See: |
| 1546 | * CEA-861-E - 5.1 Default Encoding Parameters |
| 1547 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry |
| 1548 | */ |
| 1549 | pipe_config->limited_color_range = |
| 1550 | bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1; |
| 1551 | } else { |
| 1552 | pipe_config->limited_color_range = |
| 1553 | intel_dp->limited_color_range; |
| 1554 | } |
| 1555 | |
| 1556 | pipe_config->lane_count = lane_count; |
| 1557 | |
| 1558 | pipe_config->pipe_bpp = bpp; |
| 1559 | pipe_config->port_clock = common_rates[clock]; |
| 1560 | |
| 1561 | intel_dp_compute_rate(intel_dp, pipe_config->port_clock, |
| 1562 | &link_bw, &rate_select); |
| 1563 | |
| 1564 | DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", |
| 1565 | link_bw, rate_select, pipe_config->lane_count, |
| 1566 | pipe_config->port_clock, bpp); |
| 1567 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
| 1568 | mode_rate, link_avail); |
| 1569 | |
| 1570 | intel_link_compute_m_n(bpp, lane_count, |
| 1571 | adjusted_mode->crtc_clock, |
| 1572 | pipe_config->port_clock, |
| 1573 | &pipe_config->dp_m_n); |
| 1574 | |
| 1575 | if (intel_connector->panel.downclock_mode != NULL && |
| 1576 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
| 1577 | pipe_config->has_drrs = true; |
| 1578 | intel_link_compute_m_n(bpp, lane_count, |
| 1579 | intel_connector->panel.downclock_mode->clock, |
| 1580 | pipe_config->port_clock, |
| 1581 | &pipe_config->dp_m2_n2); |
| 1582 | } |
| 1583 | |
| 1584 | if (!HAS_DDI(dev)) |
| 1585 | intel_dp_set_clock(encoder, pipe_config); |
| 1586 | |
| 1587 | return true; |
| 1588 | } |
| 1589 | |
| 1590 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
| 1591 | const struct intel_crtc_state *pipe_config) |
| 1592 | { |
| 1593 | intel_dp->link_rate = pipe_config->port_clock; |
| 1594 | intel_dp->lane_count = pipe_config->lane_count; |
| 1595 | } |
| 1596 | |
| 1597 | static void intel_dp_prepare(struct intel_encoder *encoder) |
| 1598 | { |
| 1599 | struct drm_device *dev = encoder->base.dev; |
| 1600 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1601 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1602 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 1603 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
| 1604 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
| 1605 | |
| 1606 | intel_dp_set_link_params(intel_dp, crtc->config); |
| 1607 | |
| 1608 | /* |
| 1609 | * There are four kinds of DP registers: |
| 1610 | * |
| 1611 | * IBX PCH |
| 1612 | * SNB CPU |
| 1613 | * IVB CPU |
| 1614 | * CPT PCH |
| 1615 | * |
| 1616 | * IBX PCH and CPU are the same for almost everything, |
| 1617 | * except that the CPU DP PLL is configured in this |
| 1618 | * register |
| 1619 | * |
| 1620 | * CPT PCH is quite different, having many bits moved |
| 1621 | * to the TRANS_DP_CTL register instead. That |
| 1622 | * configuration happens (oddly) in ironlake_pch_enable |
| 1623 | */ |
| 1624 | |
| 1625 | /* Preserve the BIOS-computed detected bit. This is |
| 1626 | * supposed to be read-only. |
| 1627 | */ |
| 1628 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
| 1629 | |
| 1630 | /* Handle DP bits in common between all three register formats */ |
| 1631 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
| 1632 | intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count); |
| 1633 | |
| 1634 | /* Split out the IBX/CPU vs CPT settings */ |
| 1635 | |
| 1636 | if (IS_GEN7(dev) && port == PORT_A) { |
| 1637 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 1638 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
| 1639 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 1640 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
| 1641 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
| 1642 | |
| 1643 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
| 1644 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
| 1645 | |
| 1646 | intel_dp->DP |= crtc->pipe << 29; |
| 1647 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
| 1648 | u32 trans_dp; |
| 1649 | |
| 1650 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
| 1651 | |
| 1652 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
| 1653 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
| 1654 | trans_dp |= TRANS_DP_ENH_FRAMING; |
| 1655 | else |
| 1656 | trans_dp &= ~TRANS_DP_ENH_FRAMING; |
| 1657 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); |
| 1658 | } else { |
| 1659 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
| 1660 | !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range) |
| 1661 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
| 1662 | |
| 1663 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 1664 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
| 1665 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 1666 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
| 1667 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
| 1668 | |
| 1669 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
| 1670 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
| 1671 | |
| 1672 | if (IS_CHERRYVIEW(dev)) |
| 1673 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
| 1674 | else if (crtc->pipe == PIPE_B) |
| 1675 | intel_dp->DP |= DP_PIPEB_SELECT; |
| 1676 | } |
| 1677 | } |
| 1678 | |
| 1679 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
| 1680 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
| 1681 | |
| 1682 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
| 1683 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) |
| 1684 | |
| 1685 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
| 1686 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
| 1687 | |
| 1688 | static void wait_panel_status(struct intel_dp *intel_dp, |
| 1689 | u32 mask, |
| 1690 | u32 value) |
| 1691 | { |
| 1692 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1693 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1694 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
| 1695 | |
| 1696 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1697 | |
| 1698 | pp_stat_reg = _pp_stat_reg(intel_dp); |
| 1699 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 1700 | |
| 1701 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
| 1702 | mask, value, |
| 1703 | I915_READ(pp_stat_reg), |
| 1704 | I915_READ(pp_ctrl_reg)); |
| 1705 | |
| 1706 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, |
| 1707 | 5 * USEC_PER_SEC, 10 * USEC_PER_MSEC)) |
| 1708 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
| 1709 | I915_READ(pp_stat_reg), |
| 1710 | I915_READ(pp_ctrl_reg)); |
| 1711 | |
| 1712 | DRM_DEBUG_KMS("Wait complete\n"); |
| 1713 | } |
| 1714 | |
| 1715 | static void wait_panel_on(struct intel_dp *intel_dp) |
| 1716 | { |
| 1717 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
| 1718 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
| 1719 | } |
| 1720 | |
| 1721 | static void wait_panel_off(struct intel_dp *intel_dp) |
| 1722 | { |
| 1723 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
| 1724 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
| 1725 | } |
| 1726 | |
| 1727 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
| 1728 | { |
| 1729 | ktime_t panel_power_on_time; |
| 1730 | s64 panel_power_off_duration; |
| 1731 | |
| 1732 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
| 1733 | |
| 1734 | /* take the difference of currrent time and panel power off time |
| 1735 | * and then make panel wait for t11_t12 if needed. */ |
| 1736 | panel_power_on_time = ktime_get_boottime(); |
| 1737 | panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); |
| 1738 | |
| 1739 | /* When we disable the VDD override bit last we have to do the manual |
| 1740 | * wait. */ |
| 1741 | if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) |
| 1742 | wait_remaining_ms_from_jiffies(jiffies, |
| 1743 | intel_dp->panel_power_cycle_delay - panel_power_off_duration); |
| 1744 | |
| 1745 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
| 1746 | } |
| 1747 | |
| 1748 | static void wait_backlight_on(struct intel_dp *intel_dp) |
| 1749 | { |
| 1750 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, |
| 1751 | intel_dp->backlight_on_delay); |
| 1752 | } |
| 1753 | |
| 1754 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
| 1755 | { |
| 1756 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, |
| 1757 | intel_dp->backlight_off_delay); |
| 1758 | } |
| 1759 | |
| 1760 | /* Read the current pp_control value, unlocking the register if it |
| 1761 | * is locked |
| 1762 | */ |
| 1763 | |
| 1764 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
| 1765 | { |
| 1766 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1767 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1768 | u32 control; |
| 1769 | |
| 1770 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1771 | |
| 1772 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
| 1773 | if (!IS_BROXTON(dev)) { |
| 1774 | control &= ~PANEL_UNLOCK_MASK; |
| 1775 | control |= PANEL_UNLOCK_REGS; |
| 1776 | } |
| 1777 | return control; |
| 1778 | } |
| 1779 | |
| 1780 | /* |
| 1781 | * Must be paired with edp_panel_vdd_off(). |
| 1782 | * Must hold pps_mutex around the whole on/off sequence. |
| 1783 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
| 1784 | */ |
| 1785 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
| 1786 | { |
| 1787 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1788 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1789 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 1790 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1791 | enum intel_display_power_domain power_domain; |
| 1792 | u32 pp; |
| 1793 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
| 1794 | bool need_to_disable = !intel_dp->want_panel_vdd; |
| 1795 | |
| 1796 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1797 | |
| 1798 | if (!is_edp(intel_dp)) |
| 1799 | return false; |
| 1800 | |
| 1801 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
| 1802 | intel_dp->want_panel_vdd = true; |
| 1803 | |
| 1804 | if (edp_have_panel_vdd(intel_dp)) |
| 1805 | return need_to_disable; |
| 1806 | |
| 1807 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
| 1808 | intel_display_power_get(dev_priv, power_domain); |
| 1809 | |
| 1810 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
| 1811 | port_name(intel_dig_port->port)); |
| 1812 | |
| 1813 | if (!edp_have_panel_power(intel_dp)) |
| 1814 | wait_panel_power_cycle(intel_dp); |
| 1815 | |
| 1816 | pp = ironlake_get_pp_control(intel_dp); |
| 1817 | pp |= EDP_FORCE_VDD; |
| 1818 | |
| 1819 | pp_stat_reg = _pp_stat_reg(intel_dp); |
| 1820 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 1821 | |
| 1822 | I915_WRITE(pp_ctrl_reg, pp); |
| 1823 | POSTING_READ(pp_ctrl_reg); |
| 1824 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
| 1825 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
| 1826 | /* |
| 1827 | * If the panel wasn't on, delay before accessing aux channel |
| 1828 | */ |
| 1829 | if (!edp_have_panel_power(intel_dp)) { |
| 1830 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
| 1831 | port_name(intel_dig_port->port)); |
| 1832 | msleep(intel_dp->panel_power_up_delay); |
| 1833 | } |
| 1834 | |
| 1835 | return need_to_disable; |
| 1836 | } |
| 1837 | |
| 1838 | /* |
| 1839 | * Must be paired with intel_edp_panel_vdd_off() or |
| 1840 | * intel_edp_panel_off(). |
| 1841 | * Nested calls to these functions are not allowed since |
| 1842 | * we drop the lock. Caller must use some higher level |
| 1843 | * locking to prevent nested calls from other threads. |
| 1844 | */ |
| 1845 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
| 1846 | { |
| 1847 | bool vdd; |
| 1848 | |
| 1849 | if (!is_edp(intel_dp)) |
| 1850 | return; |
| 1851 | |
| 1852 | pps_lock(intel_dp); |
| 1853 | vdd = edp_panel_vdd_on(intel_dp); |
| 1854 | pps_unlock(intel_dp); |
| 1855 | |
| 1856 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
| 1857 | port_name(dp_to_dig_port(intel_dp)->port)); |
| 1858 | } |
| 1859 | |
| 1860 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
| 1861 | { |
| 1862 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1863 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1864 | struct intel_digital_port *intel_dig_port = |
| 1865 | dp_to_dig_port(intel_dp); |
| 1866 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 1867 | enum intel_display_power_domain power_domain; |
| 1868 | u32 pp; |
| 1869 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
| 1870 | |
| 1871 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1872 | |
| 1873 | WARN_ON(intel_dp->want_panel_vdd); |
| 1874 | |
| 1875 | if (!edp_have_panel_vdd(intel_dp)) |
| 1876 | return; |
| 1877 | |
| 1878 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
| 1879 | port_name(intel_dig_port->port)); |
| 1880 | |
| 1881 | pp = ironlake_get_pp_control(intel_dp); |
| 1882 | pp &= ~EDP_FORCE_VDD; |
| 1883 | |
| 1884 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 1885 | pp_stat_reg = _pp_stat_reg(intel_dp); |
| 1886 | |
| 1887 | I915_WRITE(pp_ctrl_reg, pp); |
| 1888 | POSTING_READ(pp_ctrl_reg); |
| 1889 | |
| 1890 | /* Make sure sequencer is idle before allowing subsequent activity */ |
| 1891 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
| 1892 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
| 1893 | |
| 1894 | if ((pp & POWER_TARGET_ON) == 0) |
| 1895 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
| 1896 | |
| 1897 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
| 1898 | intel_display_power_put(dev_priv, power_domain); |
| 1899 | } |
| 1900 | |
| 1901 | static void edp_panel_vdd_work(struct work_struct *__work) |
| 1902 | { |
| 1903 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
| 1904 | struct intel_dp, panel_vdd_work); |
| 1905 | |
| 1906 | pps_lock(intel_dp); |
| 1907 | if (!intel_dp->want_panel_vdd) |
| 1908 | edp_panel_vdd_off_sync(intel_dp); |
| 1909 | pps_unlock(intel_dp); |
| 1910 | } |
| 1911 | |
| 1912 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
| 1913 | { |
| 1914 | unsigned long delay; |
| 1915 | |
| 1916 | /* |
| 1917 | * Queue the timer to fire a long time from now (relative to the power |
| 1918 | * down delay) to keep the panel power up across a sequence of |
| 1919 | * operations. |
| 1920 | */ |
| 1921 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); |
| 1922 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); |
| 1923 | } |
| 1924 | |
| 1925 | /* |
| 1926 | * Must be paired with edp_panel_vdd_on(). |
| 1927 | * Must hold pps_mutex around the whole on/off sequence. |
| 1928 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
| 1929 | */ |
| 1930 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
| 1931 | { |
| 1932 | struct drm_i915_private *dev_priv = |
| 1933 | intel_dp_to_dev(intel_dp)->dev_private; |
| 1934 | |
| 1935 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1936 | |
| 1937 | if (!is_edp(intel_dp)) |
| 1938 | return; |
| 1939 | |
| 1940 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
| 1941 | port_name(dp_to_dig_port(intel_dp)->port)); |
| 1942 | |
| 1943 | intel_dp->want_panel_vdd = false; |
| 1944 | |
| 1945 | if (sync) |
| 1946 | edp_panel_vdd_off_sync(intel_dp); |
| 1947 | else |
| 1948 | edp_panel_vdd_schedule_off(intel_dp); |
| 1949 | } |
| 1950 | |
| 1951 | static void edp_panel_on(struct intel_dp *intel_dp) |
| 1952 | { |
| 1953 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1954 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1955 | u32 pp; |
| 1956 | i915_reg_t pp_ctrl_reg; |
| 1957 | |
| 1958 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1959 | |
| 1960 | if (!is_edp(intel_dp)) |
| 1961 | return; |
| 1962 | |
| 1963 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
| 1964 | port_name(dp_to_dig_port(intel_dp)->port)); |
| 1965 | |
| 1966 | if (WARN(edp_have_panel_power(intel_dp), |
| 1967 | "eDP port %c panel power already on\n", |
| 1968 | port_name(dp_to_dig_port(intel_dp)->port))) |
| 1969 | return; |
| 1970 | |
| 1971 | wait_panel_power_cycle(intel_dp); |
| 1972 | |
| 1973 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 1974 | pp = ironlake_get_pp_control(intel_dp); |
| 1975 | if (IS_GEN5(dev)) { |
| 1976 | /* ILK workaround: disable reset around power sequence */ |
| 1977 | pp &= ~PANEL_POWER_RESET; |
| 1978 | I915_WRITE(pp_ctrl_reg, pp); |
| 1979 | POSTING_READ(pp_ctrl_reg); |
| 1980 | } |
| 1981 | |
| 1982 | pp |= POWER_TARGET_ON; |
| 1983 | if (!IS_GEN5(dev)) |
| 1984 | pp |= PANEL_POWER_RESET; |
| 1985 | |
| 1986 | I915_WRITE(pp_ctrl_reg, pp); |
| 1987 | POSTING_READ(pp_ctrl_reg); |
| 1988 | |
| 1989 | wait_panel_on(intel_dp); |
| 1990 | intel_dp->last_power_on = jiffies; |
| 1991 | |
| 1992 | if (IS_GEN5(dev)) { |
| 1993 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
| 1994 | I915_WRITE(pp_ctrl_reg, pp); |
| 1995 | POSTING_READ(pp_ctrl_reg); |
| 1996 | } |
| 1997 | } |
| 1998 | |
| 1999 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
| 2000 | { |
| 2001 | if (!is_edp(intel_dp)) |
| 2002 | return; |
| 2003 | |
| 2004 | pps_lock(intel_dp); |
| 2005 | edp_panel_on(intel_dp); |
| 2006 | pps_unlock(intel_dp); |
| 2007 | } |
| 2008 | |
| 2009 | |
| 2010 | static void edp_panel_off(struct intel_dp *intel_dp) |
| 2011 | { |
| 2012 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2013 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 2014 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 2015 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2016 | enum intel_display_power_domain power_domain; |
| 2017 | u32 pp; |
| 2018 | i915_reg_t pp_ctrl_reg; |
| 2019 | |
| 2020 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 2021 | |
| 2022 | if (!is_edp(intel_dp)) |
| 2023 | return; |
| 2024 | |
| 2025 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
| 2026 | port_name(dp_to_dig_port(intel_dp)->port)); |
| 2027 | |
| 2028 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
| 2029 | port_name(dp_to_dig_port(intel_dp)->port)); |
| 2030 | |
| 2031 | pp = ironlake_get_pp_control(intel_dp); |
| 2032 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
| 2033 | * panels get very unhappy and cease to work. */ |
| 2034 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
| 2035 | EDP_BLC_ENABLE); |
| 2036 | |
| 2037 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 2038 | |
| 2039 | intel_dp->want_panel_vdd = false; |
| 2040 | |
| 2041 | I915_WRITE(pp_ctrl_reg, pp); |
| 2042 | POSTING_READ(pp_ctrl_reg); |
| 2043 | |
| 2044 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
| 2045 | wait_panel_off(intel_dp); |
| 2046 | |
| 2047 | /* We got a reference when we enabled the VDD. */ |
| 2048 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
| 2049 | intel_display_power_put(dev_priv, power_domain); |
| 2050 | } |
| 2051 | |
| 2052 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
| 2053 | { |
| 2054 | if (!is_edp(intel_dp)) |
| 2055 | return; |
| 2056 | |
| 2057 | pps_lock(intel_dp); |
| 2058 | edp_panel_off(intel_dp); |
| 2059 | pps_unlock(intel_dp); |
| 2060 | } |
| 2061 | |
| 2062 | /* Enable backlight in the panel power control. */ |
| 2063 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) |
| 2064 | { |
| 2065 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2066 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 2067 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2068 | u32 pp; |
| 2069 | i915_reg_t pp_ctrl_reg; |
| 2070 | |
| 2071 | /* |
| 2072 | * If we enable the backlight right away following a panel power |
| 2073 | * on, we may see slight flicker as the panel syncs with the eDP |
| 2074 | * link. So delay a bit to make sure the image is solid before |
| 2075 | * allowing it to appear. |
| 2076 | */ |
| 2077 | wait_backlight_on(intel_dp); |
| 2078 | |
| 2079 | pps_lock(intel_dp); |
| 2080 | |
| 2081 | pp = ironlake_get_pp_control(intel_dp); |
| 2082 | pp |= EDP_BLC_ENABLE; |
| 2083 | |
| 2084 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 2085 | |
| 2086 | I915_WRITE(pp_ctrl_reg, pp); |
| 2087 | POSTING_READ(pp_ctrl_reg); |
| 2088 | |
| 2089 | pps_unlock(intel_dp); |
| 2090 | } |
| 2091 | |
| 2092 | /* Enable backlight PWM and backlight PP control. */ |
| 2093 | void intel_edp_backlight_on(struct intel_dp *intel_dp) |
| 2094 | { |
| 2095 | if (!is_edp(intel_dp)) |
| 2096 | return; |
| 2097 | |
| 2098 | DRM_DEBUG_KMS("\n"); |
| 2099 | |
| 2100 | intel_panel_enable_backlight(intel_dp->attached_connector); |
| 2101 | _intel_edp_backlight_on(intel_dp); |
| 2102 | } |
| 2103 | |
| 2104 | /* Disable backlight in the panel power control. */ |
| 2105 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) |
| 2106 | { |
| 2107 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 2108 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2109 | u32 pp; |
| 2110 | i915_reg_t pp_ctrl_reg; |
| 2111 | |
| 2112 | if (!is_edp(intel_dp)) |
| 2113 | return; |
| 2114 | |
| 2115 | pps_lock(intel_dp); |
| 2116 | |
| 2117 | pp = ironlake_get_pp_control(intel_dp); |
| 2118 | pp &= ~EDP_BLC_ENABLE; |
| 2119 | |
| 2120 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 2121 | |
| 2122 | I915_WRITE(pp_ctrl_reg, pp); |
| 2123 | POSTING_READ(pp_ctrl_reg); |
| 2124 | |
| 2125 | pps_unlock(intel_dp); |
| 2126 | |
| 2127 | intel_dp->last_backlight_off = jiffies; |
| 2128 | edp_wait_backlight_off(intel_dp); |
| 2129 | } |
| 2130 | |
| 2131 | /* Disable backlight PP control and backlight PWM. */ |
| 2132 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
| 2133 | { |
| 2134 | if (!is_edp(intel_dp)) |
| 2135 | return; |
| 2136 | |
| 2137 | DRM_DEBUG_KMS("\n"); |
| 2138 | |
| 2139 | _intel_edp_backlight_off(intel_dp); |
| 2140 | intel_panel_disable_backlight(intel_dp->attached_connector); |
| 2141 | } |
| 2142 | |
| 2143 | /* |
| 2144 | * Hook for controlling the panel power control backlight through the bl_power |
| 2145 | * sysfs attribute. Take care to handle multiple calls. |
| 2146 | */ |
| 2147 | static void intel_edp_backlight_power(struct intel_connector *connector, |
| 2148 | bool enable) |
| 2149 | { |
| 2150 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); |
| 2151 | bool is_enabled; |
| 2152 | |
| 2153 | pps_lock(intel_dp); |
| 2154 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
| 2155 | pps_unlock(intel_dp); |
| 2156 | |
| 2157 | if (is_enabled == enable) |
| 2158 | return; |
| 2159 | |
| 2160 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
| 2161 | enable ? "enable" : "disable"); |
| 2162 | |
| 2163 | if (enable) |
| 2164 | _intel_edp_backlight_on(intel_dp); |
| 2165 | else |
| 2166 | _intel_edp_backlight_off(intel_dp); |
| 2167 | } |
| 2168 | |
| 2169 | static void assert_dp_port(struct intel_dp *intel_dp, bool state) |
| 2170 | { |
| 2171 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 2172 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
| 2173 | bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; |
| 2174 | |
| 2175 | I915_STATE_WARN(cur_state != state, |
| 2176 | "DP port %c state assertion failure (expected %s, current %s)\n", |
| 2177 | port_name(dig_port->port), |
| 2178 | onoff(state), onoff(cur_state)); |
| 2179 | } |
| 2180 | #define assert_dp_port_disabled(d) assert_dp_port((d), false) |
| 2181 | |
| 2182 | static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) |
| 2183 | { |
| 2184 | bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; |
| 2185 | |
| 2186 | I915_STATE_WARN(cur_state != state, |
| 2187 | "eDP PLL state assertion failure (expected %s, current %s)\n", |
| 2188 | onoff(state), onoff(cur_state)); |
| 2189 | } |
| 2190 | #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) |
| 2191 | #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) |
| 2192 | |
| 2193 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
| 2194 | { |
| 2195 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2196 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
| 2197 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
| 2198 | |
| 2199 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 2200 | assert_dp_port_disabled(intel_dp); |
| 2201 | assert_edp_pll_disabled(dev_priv); |
| 2202 | |
| 2203 | DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", |
| 2204 | crtc->config->port_clock); |
| 2205 | |
| 2206 | intel_dp->DP &= ~DP_PLL_FREQ_MASK; |
| 2207 | |
| 2208 | if (crtc->config->port_clock == 162000) |
| 2209 | intel_dp->DP |= DP_PLL_FREQ_162MHZ; |
| 2210 | else |
| 2211 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
| 2212 | |
| 2213 | I915_WRITE(DP_A, intel_dp->DP); |
| 2214 | POSTING_READ(DP_A); |
| 2215 | udelay(500); |
| 2216 | |
| 2217 | intel_dp->DP |= DP_PLL_ENABLE; |
| 2218 | |
| 2219 | I915_WRITE(DP_A, intel_dp->DP); |
| 2220 | POSTING_READ(DP_A); |
| 2221 | udelay(200); |
| 2222 | } |
| 2223 | |
| 2224 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
| 2225 | { |
| 2226 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2227 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
| 2228 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
| 2229 | |
| 2230 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 2231 | assert_dp_port_disabled(intel_dp); |
| 2232 | assert_edp_pll_enabled(dev_priv); |
| 2233 | |
| 2234 | DRM_DEBUG_KMS("disabling eDP PLL\n"); |
| 2235 | |
| 2236 | intel_dp->DP &= ~DP_PLL_ENABLE; |
| 2237 | |
| 2238 | I915_WRITE(DP_A, intel_dp->DP); |
| 2239 | POSTING_READ(DP_A); |
| 2240 | udelay(200); |
| 2241 | } |
| 2242 | |
| 2243 | /* If the sink supports it, try to set the power state appropriately */ |
| 2244 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
| 2245 | { |
| 2246 | int ret, i; |
| 2247 | |
| 2248 | /* Should have a valid DPCD by this point */ |
| 2249 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
| 2250 | return; |
| 2251 | |
| 2252 | if (mode != DRM_MODE_DPMS_ON) { |
| 2253 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
| 2254 | DP_SET_POWER_D3); |
| 2255 | } else { |
| 2256 | /* |
| 2257 | * When turning on, we need to retry for 1ms to give the sink |
| 2258 | * time to wake up. |
| 2259 | */ |
| 2260 | for (i = 0; i < 3; i++) { |
| 2261 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
| 2262 | DP_SET_POWER_D0); |
| 2263 | if (ret == 1) |
| 2264 | break; |
| 2265 | msleep(1); |
| 2266 | } |
| 2267 | } |
| 2268 | |
| 2269 | if (ret != 1) |
| 2270 | DRM_DEBUG_KMS("failed to %s sink power state\n", |
| 2271 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); |
| 2272 | } |
| 2273 | |
| 2274 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
| 2275 | enum pipe *pipe) |
| 2276 | { |
| 2277 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2278 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 2279 | struct drm_device *dev = encoder->base.dev; |
| 2280 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2281 | enum intel_display_power_domain power_domain; |
| 2282 | u32 tmp; |
| 2283 | bool ret; |
| 2284 | |
| 2285 | power_domain = intel_display_port_power_domain(encoder); |
| 2286 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
| 2287 | return false; |
| 2288 | |
| 2289 | ret = false; |
| 2290 | |
| 2291 | tmp = I915_READ(intel_dp->output_reg); |
| 2292 | |
| 2293 | if (!(tmp & DP_PORT_EN)) |
| 2294 | goto out; |
| 2295 | |
| 2296 | if (IS_GEN7(dev) && port == PORT_A) { |
| 2297 | *pipe = PORT_TO_PIPE_CPT(tmp); |
| 2298 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
| 2299 | enum pipe p; |
| 2300 | |
| 2301 | for_each_pipe(dev_priv, p) { |
| 2302 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); |
| 2303 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { |
| 2304 | *pipe = p; |
| 2305 | ret = true; |
| 2306 | |
| 2307 | goto out; |
| 2308 | } |
| 2309 | } |
| 2310 | |
| 2311 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
| 2312 | i915_mmio_reg_offset(intel_dp->output_reg)); |
| 2313 | } else if (IS_CHERRYVIEW(dev)) { |
| 2314 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
| 2315 | } else { |
| 2316 | *pipe = PORT_TO_PIPE(tmp); |
| 2317 | } |
| 2318 | |
| 2319 | ret = true; |
| 2320 | |
| 2321 | out: |
| 2322 | intel_display_power_put(dev_priv, power_domain); |
| 2323 | |
| 2324 | return ret; |
| 2325 | } |
| 2326 | |
| 2327 | static void intel_dp_get_config(struct intel_encoder *encoder, |
| 2328 | struct intel_crtc_state *pipe_config) |
| 2329 | { |
| 2330 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2331 | u32 tmp, flags = 0; |
| 2332 | struct drm_device *dev = encoder->base.dev; |
| 2333 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2334 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 2335 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
| 2336 | |
| 2337 | tmp = I915_READ(intel_dp->output_reg); |
| 2338 | |
| 2339 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; |
| 2340 | |
| 2341 | if (HAS_PCH_CPT(dev) && port != PORT_A) { |
| 2342 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
| 2343 | |
| 2344 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) |
| 2345 | flags |= DRM_MODE_FLAG_PHSYNC; |
| 2346 | else |
| 2347 | flags |= DRM_MODE_FLAG_NHSYNC; |
| 2348 | |
| 2349 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
| 2350 | flags |= DRM_MODE_FLAG_PVSYNC; |
| 2351 | else |
| 2352 | flags |= DRM_MODE_FLAG_NVSYNC; |
| 2353 | } else { |
| 2354 | if (tmp & DP_SYNC_HS_HIGH) |
| 2355 | flags |= DRM_MODE_FLAG_PHSYNC; |
| 2356 | else |
| 2357 | flags |= DRM_MODE_FLAG_NHSYNC; |
| 2358 | |
| 2359 | if (tmp & DP_SYNC_VS_HIGH) |
| 2360 | flags |= DRM_MODE_FLAG_PVSYNC; |
| 2361 | else |
| 2362 | flags |= DRM_MODE_FLAG_NVSYNC; |
| 2363 | } |
| 2364 | |
| 2365 | pipe_config->base.adjusted_mode.flags |= flags; |
| 2366 | |
| 2367 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
| 2368 | !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235) |
| 2369 | pipe_config->limited_color_range = true; |
| 2370 | |
| 2371 | pipe_config->has_dp_encoder = true; |
| 2372 | |
| 2373 | pipe_config->lane_count = |
| 2374 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; |
| 2375 | |
| 2376 | intel_dp_get_m_n(crtc, pipe_config); |
| 2377 | |
| 2378 | if (port == PORT_A) { |
| 2379 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) |
| 2380 | pipe_config->port_clock = 162000; |
| 2381 | else |
| 2382 | pipe_config->port_clock = 270000; |
| 2383 | } |
| 2384 | |
| 2385 | pipe_config->base.adjusted_mode.crtc_clock = |
| 2386 | intel_dotclock_calculate(pipe_config->port_clock, |
| 2387 | &pipe_config->dp_m_n); |
| 2388 | |
| 2389 | if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp && |
| 2390 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { |
| 2391 | /* |
| 2392 | * This is a big fat ugly hack. |
| 2393 | * |
| 2394 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
| 2395 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
| 2396 | * unknown we fail to light up. Yet the same BIOS boots up with |
| 2397 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
| 2398 | * max, not what it tells us to use. |
| 2399 | * |
| 2400 | * Note: This will still be broken if the eDP panel is not lit |
| 2401 | * up by the BIOS, and thus we can't get the mode at module |
| 2402 | * load. |
| 2403 | */ |
| 2404 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", |
| 2405 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
| 2406 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; |
| 2407 | } |
| 2408 | } |
| 2409 | |
| 2410 | static void intel_disable_dp(struct intel_encoder *encoder) |
| 2411 | { |
| 2412 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2413 | struct drm_device *dev = encoder->base.dev; |
| 2414 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
| 2415 | |
| 2416 | if (crtc->config->has_audio) |
| 2417 | intel_audio_codec_disable(encoder); |
| 2418 | |
| 2419 | if (HAS_PSR(dev) && !HAS_DDI(dev)) |
| 2420 | intel_psr_disable(intel_dp); |
| 2421 | |
| 2422 | /* Make sure the panel is off before trying to change the mode. But also |
| 2423 | * ensure that we have vdd while we switch off the panel. */ |
| 2424 | intel_edp_panel_vdd_on(intel_dp); |
| 2425 | intel_edp_backlight_off(intel_dp); |
| 2426 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
| 2427 | intel_edp_panel_off(intel_dp); |
| 2428 | |
| 2429 | /* disable the port before the pipe on g4x */ |
| 2430 | if (INTEL_INFO(dev)->gen < 5) |
| 2431 | intel_dp_link_down(intel_dp); |
| 2432 | } |
| 2433 | |
| 2434 | static void ilk_post_disable_dp(struct intel_encoder *encoder) |
| 2435 | { |
| 2436 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2437 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 2438 | |
| 2439 | intel_dp_link_down(intel_dp); |
| 2440 | |
| 2441 | /* Only ilk+ has port A */ |
| 2442 | if (port == PORT_A) |
| 2443 | ironlake_edp_pll_off(intel_dp); |
| 2444 | } |
| 2445 | |
| 2446 | static void vlv_post_disable_dp(struct intel_encoder *encoder) |
| 2447 | { |
| 2448 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2449 | |
| 2450 | intel_dp_link_down(intel_dp); |
| 2451 | } |
| 2452 | |
| 2453 | static void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
| 2454 | bool reset) |
| 2455 | { |
| 2456 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| 2457 | enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); |
| 2458 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
| 2459 | enum pipe pipe = crtc->pipe; |
| 2460 | uint32_t val; |
| 2461 | |
| 2462 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); |
| 2463 | if (reset) |
| 2464 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
| 2465 | else |
| 2466 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
| 2467 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); |
| 2468 | |
| 2469 | if (crtc->config->lane_count > 2) { |
| 2470 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
| 2471 | if (reset) |
| 2472 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
| 2473 | else |
| 2474 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
| 2475 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
| 2476 | } |
| 2477 | |
| 2478 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
| 2479 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
| 2480 | if (reset) |
| 2481 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
| 2482 | else |
| 2483 | val |= DPIO_PCS_CLK_SOFT_RESET; |
| 2484 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
| 2485 | |
| 2486 | if (crtc->config->lane_count > 2) { |
| 2487 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
| 2488 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
| 2489 | if (reset) |
| 2490 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
| 2491 | else |
| 2492 | val |= DPIO_PCS_CLK_SOFT_RESET; |
| 2493 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); |
| 2494 | } |
| 2495 | } |
| 2496 | |
| 2497 | static void chv_post_disable_dp(struct intel_encoder *encoder) |
| 2498 | { |
| 2499 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2500 | struct drm_device *dev = encoder->base.dev; |
| 2501 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2502 | |
| 2503 | intel_dp_link_down(intel_dp); |
| 2504 | |
| 2505 | mutex_lock(&dev_priv->sb_lock); |
| 2506 | |
| 2507 | /* Assert data lane reset */ |
| 2508 | chv_data_lane_soft_reset(encoder, true); |
| 2509 | |
| 2510 | mutex_unlock(&dev_priv->sb_lock); |
| 2511 | } |
| 2512 | |
| 2513 | static void |
| 2514 | _intel_dp_set_link_train(struct intel_dp *intel_dp, |
| 2515 | uint32_t *DP, |
| 2516 | uint8_t dp_train_pat) |
| 2517 | { |
| 2518 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2519 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 2520 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2521 | enum port port = intel_dig_port->port; |
| 2522 | |
| 2523 | if (HAS_DDI(dev)) { |
| 2524 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
| 2525 | |
| 2526 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
| 2527 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
| 2528 | else |
| 2529 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
| 2530 | |
| 2531 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
| 2532 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2533 | case DP_TRAINING_PATTERN_DISABLE: |
| 2534 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
| 2535 | |
| 2536 | break; |
| 2537 | case DP_TRAINING_PATTERN_1: |
| 2538 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
| 2539 | break; |
| 2540 | case DP_TRAINING_PATTERN_2: |
| 2541 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
| 2542 | break; |
| 2543 | case DP_TRAINING_PATTERN_3: |
| 2544 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
| 2545 | break; |
| 2546 | } |
| 2547 | I915_WRITE(DP_TP_CTL(port), temp); |
| 2548 | |
| 2549 | } else if ((IS_GEN7(dev) && port == PORT_A) || |
| 2550 | (HAS_PCH_CPT(dev) && port != PORT_A)) { |
| 2551 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
| 2552 | |
| 2553 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2554 | case DP_TRAINING_PATTERN_DISABLE: |
| 2555 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
| 2556 | break; |
| 2557 | case DP_TRAINING_PATTERN_1: |
| 2558 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
| 2559 | break; |
| 2560 | case DP_TRAINING_PATTERN_2: |
| 2561 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
| 2562 | break; |
| 2563 | case DP_TRAINING_PATTERN_3: |
| 2564 | DRM_ERROR("DP training pattern 3 not supported\n"); |
| 2565 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
| 2566 | break; |
| 2567 | } |
| 2568 | |
| 2569 | } else { |
| 2570 | if (IS_CHERRYVIEW(dev)) |
| 2571 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; |
| 2572 | else |
| 2573 | *DP &= ~DP_LINK_TRAIN_MASK; |
| 2574 | |
| 2575 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2576 | case DP_TRAINING_PATTERN_DISABLE: |
| 2577 | *DP |= DP_LINK_TRAIN_OFF; |
| 2578 | break; |
| 2579 | case DP_TRAINING_PATTERN_1: |
| 2580 | *DP |= DP_LINK_TRAIN_PAT_1; |
| 2581 | break; |
| 2582 | case DP_TRAINING_PATTERN_2: |
| 2583 | *DP |= DP_LINK_TRAIN_PAT_2; |
| 2584 | break; |
| 2585 | case DP_TRAINING_PATTERN_3: |
| 2586 | if (IS_CHERRYVIEW(dev)) { |
| 2587 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; |
| 2588 | } else { |
| 2589 | DRM_ERROR("DP training pattern 3 not supported\n"); |
| 2590 | *DP |= DP_LINK_TRAIN_PAT_2; |
| 2591 | } |
| 2592 | break; |
| 2593 | } |
| 2594 | } |
| 2595 | } |
| 2596 | |
| 2597 | static void intel_dp_enable_port(struct intel_dp *intel_dp) |
| 2598 | { |
| 2599 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 2600 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2601 | struct intel_crtc *crtc = |
| 2602 | to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc); |
| 2603 | |
| 2604 | /* enable with pattern 1 (as per spec) */ |
| 2605 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
| 2606 | DP_TRAINING_PATTERN_1); |
| 2607 | |
| 2608 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
| 2609 | POSTING_READ(intel_dp->output_reg); |
| 2610 | |
| 2611 | /* |
| 2612 | * Magic for VLV/CHV. We _must_ first set up the register |
| 2613 | * without actually enabling the port, and then do another |
| 2614 | * write to enable the port. Otherwise link training will |
| 2615 | * fail when the power sequencer is freshly used for this port. |
| 2616 | */ |
| 2617 | intel_dp->DP |= DP_PORT_EN; |
| 2618 | if (crtc->config->has_audio) |
| 2619 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
| 2620 | |
| 2621 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
| 2622 | POSTING_READ(intel_dp->output_reg); |
| 2623 | } |
| 2624 | |
| 2625 | static void intel_enable_dp(struct intel_encoder *encoder) |
| 2626 | { |
| 2627 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2628 | struct drm_device *dev = encoder->base.dev; |
| 2629 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2630 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
| 2631 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
| 2632 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 2633 | enum pipe pipe = crtc->pipe; |
| 2634 | |
| 2635 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
| 2636 | return; |
| 2637 | |
| 2638 | pps_lock(intel_dp); |
| 2639 | |
| 2640 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
| 2641 | vlv_init_panel_power_sequencer(intel_dp); |
| 2642 | |
| 2643 | /* |
| 2644 | * We get an occasional spurious underrun between the port |
| 2645 | * enable and vdd enable, when enabling port A eDP. |
| 2646 | * |
| 2647 | * FIXME: Not sure if this applies to (PCH) port D eDP as well |
| 2648 | */ |
| 2649 | if (port == PORT_A) |
| 2650 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
| 2651 | |
| 2652 | intel_dp_enable_port(intel_dp); |
| 2653 | |
| 2654 | if (port == PORT_A && IS_GEN5(dev_priv)) { |
| 2655 | /* |
| 2656 | * Underrun reporting for the other pipe was disabled in |
| 2657 | * g4x_pre_enable_dp(). The eDP PLL and port have now been |
| 2658 | * enabled, so it's now safe to re-enable underrun reporting. |
| 2659 | */ |
| 2660 | intel_wait_for_vblank_if_active(dev_priv->dev, !pipe); |
| 2661 | intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, true); |
| 2662 | intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, true); |
| 2663 | } |
| 2664 | |
| 2665 | edp_panel_vdd_on(intel_dp); |
| 2666 | edp_panel_on(intel_dp); |
| 2667 | edp_panel_vdd_off(intel_dp, true); |
| 2668 | |
| 2669 | if (port == PORT_A) |
| 2670 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
| 2671 | |
| 2672 | pps_unlock(intel_dp); |
| 2673 | |
| 2674 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
| 2675 | unsigned int lane_mask = 0x0; |
| 2676 | |
| 2677 | if (IS_CHERRYVIEW(dev)) |
| 2678 | lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count); |
| 2679 | |
| 2680 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
| 2681 | lane_mask); |
| 2682 | } |
| 2683 | |
| 2684 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
| 2685 | intel_dp_start_link_train(intel_dp); |
| 2686 | intel_dp_stop_link_train(intel_dp); |
| 2687 | |
| 2688 | if (crtc->config->has_audio) { |
| 2689 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
| 2690 | pipe_name(pipe)); |
| 2691 | intel_audio_codec_enable(encoder); |
| 2692 | } |
| 2693 | } |
| 2694 | |
| 2695 | static void g4x_enable_dp(struct intel_encoder *encoder) |
| 2696 | { |
| 2697 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2698 | |
| 2699 | intel_enable_dp(encoder); |
| 2700 | intel_edp_backlight_on(intel_dp); |
| 2701 | } |
| 2702 | |
| 2703 | static void vlv_enable_dp(struct intel_encoder *encoder) |
| 2704 | { |
| 2705 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2706 | |
| 2707 | intel_edp_backlight_on(intel_dp); |
| 2708 | intel_psr_enable(intel_dp); |
| 2709 | } |
| 2710 | |
| 2711 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
| 2712 | { |
| 2713 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| 2714 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2715 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 2716 | enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
| 2717 | |
| 2718 | intel_dp_prepare(encoder); |
| 2719 | |
| 2720 | if (port == PORT_A && IS_GEN5(dev_priv)) { |
| 2721 | /* |
| 2722 | * We get FIFO underruns on the other pipe when |
| 2723 | * enabling the CPU eDP PLL, and when enabling CPU |
| 2724 | * eDP port. We could potentially avoid the PLL |
| 2725 | * underrun with a vblank wait just prior to enabling |
| 2726 | * the PLL, but that doesn't appear to help the port |
| 2727 | * enable case. Just sweep it all under the rug. |
| 2728 | */ |
| 2729 | intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, false); |
| 2730 | intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, false); |
| 2731 | } |
| 2732 | |
| 2733 | /* Only ilk+ has port A */ |
| 2734 | if (port == PORT_A) |
| 2735 | ironlake_edp_pll_on(intel_dp); |
| 2736 | } |
| 2737 | |
| 2738 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
| 2739 | { |
| 2740 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2741 | struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private; |
| 2742 | enum pipe pipe = intel_dp->pps_pipe; |
| 2743 | i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
| 2744 | |
| 2745 | edp_panel_vdd_off_sync(intel_dp); |
| 2746 | |
| 2747 | /* |
| 2748 | * VLV seems to get confused when multiple power seqeuencers |
| 2749 | * have the same port selected (even if only one has power/vdd |
| 2750 | * enabled). The failure manifests as vlv_wait_port_ready() failing |
| 2751 | * CHV on the other hand doesn't seem to mind having the same port |
| 2752 | * selected in multiple power seqeuencers, but let's clear the |
| 2753 | * port select always when logically disconnecting a power sequencer |
| 2754 | * from a port. |
| 2755 | */ |
| 2756 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", |
| 2757 | pipe_name(pipe), port_name(intel_dig_port->port)); |
| 2758 | I915_WRITE(pp_on_reg, 0); |
| 2759 | POSTING_READ(pp_on_reg); |
| 2760 | |
| 2761 | intel_dp->pps_pipe = INVALID_PIPE; |
| 2762 | } |
| 2763 | |
| 2764 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
| 2765 | enum pipe pipe) |
| 2766 | { |
| 2767 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2768 | struct intel_encoder *encoder; |
| 2769 | |
| 2770 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 2771 | |
| 2772 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
| 2773 | return; |
| 2774 | |
| 2775 | for_each_intel_encoder(dev, encoder) { |
| 2776 | struct intel_dp *intel_dp; |
| 2777 | enum port port; |
| 2778 | |
| 2779 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 2780 | continue; |
| 2781 | |
| 2782 | intel_dp = enc_to_intel_dp(&encoder->base); |
| 2783 | port = dp_to_dig_port(intel_dp)->port; |
| 2784 | |
| 2785 | if (intel_dp->pps_pipe != pipe) |
| 2786 | continue; |
| 2787 | |
| 2788 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", |
| 2789 | pipe_name(pipe), port_name(port)); |
| 2790 | |
| 2791 | WARN(encoder->base.crtc, |
| 2792 | "stealing pipe %c power sequencer from active eDP port %c\n", |
| 2793 | pipe_name(pipe), port_name(port)); |
| 2794 | |
| 2795 | /* make sure vdd is off before we steal it */ |
| 2796 | vlv_detach_power_sequencer(intel_dp); |
| 2797 | } |
| 2798 | } |
| 2799 | |
| 2800 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) |
| 2801 | { |
| 2802 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2803 | struct intel_encoder *encoder = &intel_dig_port->base; |
| 2804 | struct drm_device *dev = encoder->base.dev; |
| 2805 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2806 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
| 2807 | |
| 2808 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 2809 | |
| 2810 | if (!is_edp(intel_dp)) |
| 2811 | return; |
| 2812 | |
| 2813 | if (intel_dp->pps_pipe == crtc->pipe) |
| 2814 | return; |
| 2815 | |
| 2816 | /* |
| 2817 | * If another power sequencer was being used on this |
| 2818 | * port previously make sure to turn off vdd there while |
| 2819 | * we still have control of it. |
| 2820 | */ |
| 2821 | if (intel_dp->pps_pipe != INVALID_PIPE) |
| 2822 | vlv_detach_power_sequencer(intel_dp); |
| 2823 | |
| 2824 | /* |
| 2825 | * We may be stealing the power |
| 2826 | * sequencer from another port. |
| 2827 | */ |
| 2828 | vlv_steal_power_sequencer(dev, crtc->pipe); |
| 2829 | |
| 2830 | /* now it's all ours */ |
| 2831 | intel_dp->pps_pipe = crtc->pipe; |
| 2832 | |
| 2833 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", |
| 2834 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); |
| 2835 | |
| 2836 | /* init power sequencer on this pipe and port */ |
| 2837 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
| 2838 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
| 2839 | } |
| 2840 | |
| 2841 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
| 2842 | { |
| 2843 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2844 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
| 2845 | struct drm_device *dev = encoder->base.dev; |
| 2846 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2847 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
| 2848 | enum dpio_channel port = vlv_dport_to_channel(dport); |
| 2849 | int pipe = intel_crtc->pipe; |
| 2850 | u32 val; |
| 2851 | |
| 2852 | mutex_lock(&dev_priv->sb_lock); |
| 2853 | |
| 2854 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
| 2855 | val = 0; |
| 2856 | if (pipe) |
| 2857 | val |= (1<<21); |
| 2858 | else |
| 2859 | val &= ~(1<<21); |
| 2860 | val |= 0x001000c4; |
| 2861 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
| 2862 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
| 2863 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
| 2864 | |
| 2865 | mutex_unlock(&dev_priv->sb_lock); |
| 2866 | |
| 2867 | intel_enable_dp(encoder); |
| 2868 | } |
| 2869 | |
| 2870 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
| 2871 | { |
| 2872 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
| 2873 | struct drm_device *dev = encoder->base.dev; |
| 2874 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2875 | struct intel_crtc *intel_crtc = |
| 2876 | to_intel_crtc(encoder->base.crtc); |
| 2877 | enum dpio_channel port = vlv_dport_to_channel(dport); |
| 2878 | int pipe = intel_crtc->pipe; |
| 2879 | |
| 2880 | intel_dp_prepare(encoder); |
| 2881 | |
| 2882 | /* Program Tx lane resets to default */ |
| 2883 | mutex_lock(&dev_priv->sb_lock); |
| 2884 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
| 2885 | DPIO_PCS_TX_LANE2_RESET | |
| 2886 | DPIO_PCS_TX_LANE1_RESET); |
| 2887 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
| 2888 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
| 2889 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | |
| 2890 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | |
| 2891 | DPIO_PCS_CLK_SOFT_RESET); |
| 2892 | |
| 2893 | /* Fix up inter-pair skew failure */ |
| 2894 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
| 2895 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); |
| 2896 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); |
| 2897 | mutex_unlock(&dev_priv->sb_lock); |
| 2898 | } |
| 2899 | |
| 2900 | static void chv_pre_enable_dp(struct intel_encoder *encoder) |
| 2901 | { |
| 2902 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2903 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
| 2904 | struct drm_device *dev = encoder->base.dev; |
| 2905 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2906 | struct intel_crtc *intel_crtc = |
| 2907 | to_intel_crtc(encoder->base.crtc); |
| 2908 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
| 2909 | int pipe = intel_crtc->pipe; |
| 2910 | int data, i, stagger; |
| 2911 | u32 val; |
| 2912 | |
| 2913 | mutex_lock(&dev_priv->sb_lock); |
| 2914 | |
| 2915 | /* allow hardware to manage TX FIFO reset source */ |
| 2916 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
| 2917 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
| 2918 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
| 2919 | |
| 2920 | if (intel_crtc->config->lane_count > 2) { |
| 2921 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
| 2922 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
| 2923 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
| 2924 | } |
| 2925 | |
| 2926 | /* Program Tx lane latency optimal setting*/ |
| 2927 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
| 2928 | /* Set the upar bit */ |
| 2929 | if (intel_crtc->config->lane_count == 1) |
| 2930 | data = 0x0; |
| 2931 | else |
| 2932 | data = (i == 1) ? 0x0 : 0x1; |
| 2933 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), |
| 2934 | data << DPIO_UPAR_SHIFT); |
| 2935 | } |
| 2936 | |
| 2937 | /* Data lane stagger programming */ |
| 2938 | if (intel_crtc->config->port_clock > 270000) |
| 2939 | stagger = 0x18; |
| 2940 | else if (intel_crtc->config->port_clock > 135000) |
| 2941 | stagger = 0xd; |
| 2942 | else if (intel_crtc->config->port_clock > 67500) |
| 2943 | stagger = 0x7; |
| 2944 | else if (intel_crtc->config->port_clock > 33750) |
| 2945 | stagger = 0x4; |
| 2946 | else |
| 2947 | stagger = 0x2; |
| 2948 | |
| 2949 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
| 2950 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
| 2951 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
| 2952 | |
| 2953 | if (intel_crtc->config->lane_count > 2) { |
| 2954 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
| 2955 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
| 2956 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
| 2957 | } |
| 2958 | |
| 2959 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), |
| 2960 | DPIO_LANESTAGGER_STRAP(stagger) | |
| 2961 | DPIO_LANESTAGGER_STRAP_OVRD | |
| 2962 | DPIO_TX1_STAGGER_MASK(0x1f) | |
| 2963 | DPIO_TX1_STAGGER_MULT(6) | |
| 2964 | DPIO_TX2_STAGGER_MULT(0)); |
| 2965 | |
| 2966 | if (intel_crtc->config->lane_count > 2) { |
| 2967 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), |
| 2968 | DPIO_LANESTAGGER_STRAP(stagger) | |
| 2969 | DPIO_LANESTAGGER_STRAP_OVRD | |
| 2970 | DPIO_TX1_STAGGER_MASK(0x1f) | |
| 2971 | DPIO_TX1_STAGGER_MULT(7) | |
| 2972 | DPIO_TX2_STAGGER_MULT(5)); |
| 2973 | } |
| 2974 | |
| 2975 | /* Deassert data lane reset */ |
| 2976 | chv_data_lane_soft_reset(encoder, false); |
| 2977 | |
| 2978 | mutex_unlock(&dev_priv->sb_lock); |
| 2979 | |
| 2980 | intel_enable_dp(encoder); |
| 2981 | |
| 2982 | /* Second common lane will stay alive on its own now */ |
| 2983 | if (dport->release_cl2_override) { |
| 2984 | chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); |
| 2985 | dport->release_cl2_override = false; |
| 2986 | } |
| 2987 | } |
| 2988 | |
| 2989 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) |
| 2990 | { |
| 2991 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
| 2992 | struct drm_device *dev = encoder->base.dev; |
| 2993 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2994 | struct intel_crtc *intel_crtc = |
| 2995 | to_intel_crtc(encoder->base.crtc); |
| 2996 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
| 2997 | enum pipe pipe = intel_crtc->pipe; |
| 2998 | unsigned int lane_mask = |
| 2999 | intel_dp_unused_lane_mask(intel_crtc->config->lane_count); |
| 3000 | u32 val; |
| 3001 | |
| 3002 | intel_dp_prepare(encoder); |
| 3003 | |
| 3004 | /* |
| 3005 | * Must trick the second common lane into life. |
| 3006 | * Otherwise we can't even access the PLL. |
| 3007 | */ |
| 3008 | if (ch == DPIO_CH0 && pipe == PIPE_B) |
| 3009 | dport->release_cl2_override = |
| 3010 | !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); |
| 3011 | |
| 3012 | chv_phy_powergate_lanes(encoder, true, lane_mask); |
| 3013 | |
| 3014 | mutex_lock(&dev_priv->sb_lock); |
| 3015 | |
| 3016 | /* Assert data lane reset */ |
| 3017 | chv_data_lane_soft_reset(encoder, true); |
| 3018 | |
| 3019 | /* program left/right clock distribution */ |
| 3020 | if (pipe != PIPE_B) { |
| 3021 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
| 3022 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
| 3023 | if (ch == DPIO_CH0) |
| 3024 | val |= CHV_BUFLEFTENA1_FORCE; |
| 3025 | if (ch == DPIO_CH1) |
| 3026 | val |= CHV_BUFRIGHTENA1_FORCE; |
| 3027 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
| 3028 | } else { |
| 3029 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
| 3030 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
| 3031 | if (ch == DPIO_CH0) |
| 3032 | val |= CHV_BUFLEFTENA2_FORCE; |
| 3033 | if (ch == DPIO_CH1) |
| 3034 | val |= CHV_BUFRIGHTENA2_FORCE; |
| 3035 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
| 3036 | } |
| 3037 | |
| 3038 | /* program clock channel usage */ |
| 3039 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); |
| 3040 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
| 3041 | if (pipe != PIPE_B) |
| 3042 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
| 3043 | else |
| 3044 | val |= CHV_PCS_USEDCLKCHANNEL; |
| 3045 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); |
| 3046 | |
| 3047 | if (intel_crtc->config->lane_count > 2) { |
| 3048 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); |
| 3049 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
| 3050 | if (pipe != PIPE_B) |
| 3051 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
| 3052 | else |
| 3053 | val |= CHV_PCS_USEDCLKCHANNEL; |
| 3054 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); |
| 3055 | } |
| 3056 | |
| 3057 | /* |
| 3058 | * This a a bit weird since generally CL |
| 3059 | * matches the pipe, but here we need to |
| 3060 | * pick the CL based on the port. |
| 3061 | */ |
| 3062 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); |
| 3063 | if (pipe != PIPE_B) |
| 3064 | val &= ~CHV_CMN_USEDCLKCHANNEL; |
| 3065 | else |
| 3066 | val |= CHV_CMN_USEDCLKCHANNEL; |
| 3067 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); |
| 3068 | |
| 3069 | mutex_unlock(&dev_priv->sb_lock); |
| 3070 | } |
| 3071 | |
| 3072 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder) |
| 3073 | { |
| 3074 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| 3075 | enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
| 3076 | u32 val; |
| 3077 | |
| 3078 | mutex_lock(&dev_priv->sb_lock); |
| 3079 | |
| 3080 | /* disable left/right clock distribution */ |
| 3081 | if (pipe != PIPE_B) { |
| 3082 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
| 3083 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
| 3084 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
| 3085 | } else { |
| 3086 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
| 3087 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
| 3088 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
| 3089 | } |
| 3090 | |
| 3091 | mutex_unlock(&dev_priv->sb_lock); |
| 3092 | |
| 3093 | /* |
| 3094 | * Leave the power down bit cleared for at least one |
| 3095 | * lane so that chv_powergate_phy_ch() will power |
| 3096 | * on something when the channel is otherwise unused. |
| 3097 | * When the port is off and the override is removed |
| 3098 | * the lanes power down anyway, so otherwise it doesn't |
| 3099 | * really matter what the state of power down bits is |
| 3100 | * after this. |
| 3101 | */ |
| 3102 | chv_phy_powergate_lanes(encoder, false, 0x0); |
| 3103 | } |
| 3104 | |
| 3105 | /* |
| 3106 | * Native read with retry for link status and receiver capability reads for |
| 3107 | * cases where the sink may still be asleep. |
| 3108 | * |
| 3109 | * Sinks are *supposed* to come up within 1ms from an off state, but we're also |
| 3110 | * supposed to retry 3 times per the spec. |
| 3111 | */ |
| 3112 | static ssize_t |
| 3113 | intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, |
| 3114 | void *buffer, size_t size) |
| 3115 | { |
| 3116 | ssize_t ret; |
| 3117 | int i; |
| 3118 | |
| 3119 | /* |
| 3120 | * Sometime we just get the same incorrect byte repeated |
| 3121 | * over the entire buffer. Doing just one throw away read |
| 3122 | * initially seems to "solve" it. |
| 3123 | */ |
| 3124 | drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1); |
| 3125 | |
| 3126 | for (i = 0; i < 3; i++) { |
| 3127 | ret = drm_dp_dpcd_read(aux, offset, buffer, size); |
| 3128 | if (ret == size) |
| 3129 | return ret; |
| 3130 | msleep(1); |
| 3131 | } |
| 3132 | |
| 3133 | return ret; |
| 3134 | } |
| 3135 | |
| 3136 | /* |
| 3137 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
| 3138 | * link status information |
| 3139 | */ |
| 3140 | bool |
| 3141 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
| 3142 | { |
| 3143 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
| 3144 | DP_LANE0_1_STATUS, |
| 3145 | link_status, |
| 3146 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; |
| 3147 | } |
| 3148 | |
| 3149 | /* These are source-specific values. */ |
| 3150 | uint8_t |
| 3151 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
| 3152 | { |
| 3153 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 3154 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3155 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 3156 | |
| 3157 | if (IS_BROXTON(dev)) |
| 3158 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
| 3159 | else if (INTEL_INFO(dev)->gen >= 9) { |
| 3160 | if (dev_priv->edp_low_vswing && port == PORT_A) |
| 3161 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
| 3162 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
| 3163 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
| 3164 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
| 3165 | else if (IS_GEN7(dev) && port == PORT_A) |
| 3166 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
| 3167 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
| 3168 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
| 3169 | else |
| 3170 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
| 3171 | } |
| 3172 | |
| 3173 | uint8_t |
| 3174 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
| 3175 | { |
| 3176 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 3177 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 3178 | |
| 3179 | if (INTEL_INFO(dev)->gen >= 9) { |
| 3180 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3181 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3182 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
| 3183 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3184 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3185 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3186 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
| 3187 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
| 3188 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
| 3189 | default: |
| 3190 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
| 3191 | } |
| 3192 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
| 3193 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3194 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3195 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
| 3196 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3197 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3198 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3199 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
| 3200 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
| 3201 | default: |
| 3202 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
| 3203 | } |
| 3204 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
| 3205 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3206 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3207 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
| 3208 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3209 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3210 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3211 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
| 3212 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
| 3213 | default: |
| 3214 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
| 3215 | } |
| 3216 | } else if (IS_GEN7(dev) && port == PORT_A) { |
| 3217 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3218 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3219 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3220 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3221 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3222 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
| 3223 | default: |
| 3224 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
| 3225 | } |
| 3226 | } else { |
| 3227 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3228 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3229 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3230 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3231 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3232 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3233 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
| 3234 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
| 3235 | default: |
| 3236 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
| 3237 | } |
| 3238 | } |
| 3239 | } |
| 3240 | |
| 3241 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
| 3242 | { |
| 3243 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 3244 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3245 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
| 3246 | struct intel_crtc *intel_crtc = |
| 3247 | to_intel_crtc(dport->base.base.crtc); |
| 3248 | unsigned long demph_reg_value, preemph_reg_value, |
| 3249 | uniqtranscale_reg_value; |
| 3250 | uint8_t train_set = intel_dp->train_set[0]; |
| 3251 | enum dpio_channel port = vlv_dport_to_channel(dport); |
| 3252 | int pipe = intel_crtc->pipe; |
| 3253 | |
| 3254 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
| 3255 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3256 | preemph_reg_value = 0x0004000; |
| 3257 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3258 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3259 | demph_reg_value = 0x2B405555; |
| 3260 | uniqtranscale_reg_value = 0x552AB83A; |
| 3261 | break; |
| 3262 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3263 | demph_reg_value = 0x2B404040; |
| 3264 | uniqtranscale_reg_value = 0x5548B83A; |
| 3265 | break; |
| 3266 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3267 | demph_reg_value = 0x2B245555; |
| 3268 | uniqtranscale_reg_value = 0x5560B83A; |
| 3269 | break; |
| 3270 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
| 3271 | demph_reg_value = 0x2B405555; |
| 3272 | uniqtranscale_reg_value = 0x5598DA3A; |
| 3273 | break; |
| 3274 | default: |
| 3275 | return 0; |
| 3276 | } |
| 3277 | break; |
| 3278 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3279 | preemph_reg_value = 0x0002000; |
| 3280 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3281 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3282 | demph_reg_value = 0x2B404040; |
| 3283 | uniqtranscale_reg_value = 0x5552B83A; |
| 3284 | break; |
| 3285 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3286 | demph_reg_value = 0x2B404848; |
| 3287 | uniqtranscale_reg_value = 0x5580B83A; |
| 3288 | break; |
| 3289 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3290 | demph_reg_value = 0x2B404040; |
| 3291 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 3292 | break; |
| 3293 | default: |
| 3294 | return 0; |
| 3295 | } |
| 3296 | break; |
| 3297 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
| 3298 | preemph_reg_value = 0x0000000; |
| 3299 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3300 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3301 | demph_reg_value = 0x2B305555; |
| 3302 | uniqtranscale_reg_value = 0x5570B83A; |
| 3303 | break; |
| 3304 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3305 | demph_reg_value = 0x2B2B4040; |
| 3306 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 3307 | break; |
| 3308 | default: |
| 3309 | return 0; |
| 3310 | } |
| 3311 | break; |
| 3312 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
| 3313 | preemph_reg_value = 0x0006000; |
| 3314 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3315 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3316 | demph_reg_value = 0x1B405555; |
| 3317 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 3318 | break; |
| 3319 | default: |
| 3320 | return 0; |
| 3321 | } |
| 3322 | break; |
| 3323 | default: |
| 3324 | return 0; |
| 3325 | } |
| 3326 | |
| 3327 | mutex_lock(&dev_priv->sb_lock); |
| 3328 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); |
| 3329 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); |
| 3330 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), |
| 3331 | uniqtranscale_reg_value); |
| 3332 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); |
| 3333 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); |
| 3334 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); |
| 3335 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); |
| 3336 | mutex_unlock(&dev_priv->sb_lock); |
| 3337 | |
| 3338 | return 0; |
| 3339 | } |
| 3340 | |
| 3341 | static bool chv_need_uniq_trans_scale(uint8_t train_set) |
| 3342 | { |
| 3343 | return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 && |
| 3344 | (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
| 3345 | } |
| 3346 | |
| 3347 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
| 3348 | { |
| 3349 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 3350 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3351 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
| 3352 | struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); |
| 3353 | u32 deemph_reg_value, margin_reg_value, val; |
| 3354 | uint8_t train_set = intel_dp->train_set[0]; |
| 3355 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
| 3356 | enum pipe pipe = intel_crtc->pipe; |
| 3357 | int i; |
| 3358 | |
| 3359 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
| 3360 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3361 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3362 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3363 | deemph_reg_value = 128; |
| 3364 | margin_reg_value = 52; |
| 3365 | break; |
| 3366 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3367 | deemph_reg_value = 128; |
| 3368 | margin_reg_value = 77; |
| 3369 | break; |
| 3370 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3371 | deemph_reg_value = 128; |
| 3372 | margin_reg_value = 102; |
| 3373 | break; |
| 3374 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
| 3375 | deemph_reg_value = 128; |
| 3376 | margin_reg_value = 154; |
| 3377 | /* FIXME extra to set for 1200 */ |
| 3378 | break; |
| 3379 | default: |
| 3380 | return 0; |
| 3381 | } |
| 3382 | break; |
| 3383 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3384 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3385 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3386 | deemph_reg_value = 85; |
| 3387 | margin_reg_value = 78; |
| 3388 | break; |
| 3389 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3390 | deemph_reg_value = 85; |
| 3391 | margin_reg_value = 116; |
| 3392 | break; |
| 3393 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3394 | deemph_reg_value = 85; |
| 3395 | margin_reg_value = 154; |
| 3396 | break; |
| 3397 | default: |
| 3398 | return 0; |
| 3399 | } |
| 3400 | break; |
| 3401 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
| 3402 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3403 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3404 | deemph_reg_value = 64; |
| 3405 | margin_reg_value = 104; |
| 3406 | break; |
| 3407 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3408 | deemph_reg_value = 64; |
| 3409 | margin_reg_value = 154; |
| 3410 | break; |
| 3411 | default: |
| 3412 | return 0; |
| 3413 | } |
| 3414 | break; |
| 3415 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
| 3416 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3417 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3418 | deemph_reg_value = 43; |
| 3419 | margin_reg_value = 154; |
| 3420 | break; |
| 3421 | default: |
| 3422 | return 0; |
| 3423 | } |
| 3424 | break; |
| 3425 | default: |
| 3426 | return 0; |
| 3427 | } |
| 3428 | |
| 3429 | mutex_lock(&dev_priv->sb_lock); |
| 3430 | |
| 3431 | /* Clear calc init */ |
| 3432 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
| 3433 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
| 3434 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
| 3435 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
| 3436 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
| 3437 | |
| 3438 | if (intel_crtc->config->lane_count > 2) { |
| 3439 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
| 3440 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
| 3441 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
| 3442 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
| 3443 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
| 3444 | } |
| 3445 | |
| 3446 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
| 3447 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
| 3448 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
| 3449 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); |
| 3450 | |
| 3451 | if (intel_crtc->config->lane_count > 2) { |
| 3452 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); |
| 3453 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
| 3454 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
| 3455 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); |
| 3456 | } |
| 3457 | |
| 3458 | /* Program swing deemph */ |
| 3459 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
| 3460 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); |
| 3461 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; |
| 3462 | val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; |
| 3463 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); |
| 3464 | } |
| 3465 | |
| 3466 | /* Program swing margin */ |
| 3467 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
| 3468 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
| 3469 | |
| 3470 | val &= ~DPIO_SWING_MARGIN000_MASK; |
| 3471 | val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; |
| 3472 | |
| 3473 | /* |
| 3474 | * Supposedly this value shouldn't matter when unique transition |
| 3475 | * scale is disabled, but in fact it does matter. Let's just |
| 3476 | * always program the same value and hope it's OK. |
| 3477 | */ |
| 3478 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); |
| 3479 | val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; |
| 3480 | |
| 3481 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
| 3482 | } |
| 3483 | |
| 3484 | /* |
| 3485 | * The document said it needs to set bit 27 for ch0 and bit 26 |
| 3486 | * for ch1. Might be a typo in the doc. |
| 3487 | * For now, for this unique transition scale selection, set bit |
| 3488 | * 27 for ch0 and ch1. |
| 3489 | */ |
| 3490 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
| 3491 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); |
| 3492 | if (chv_need_uniq_trans_scale(train_set)) |
| 3493 | val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; |
| 3494 | else |
| 3495 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; |
| 3496 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); |
| 3497 | } |
| 3498 | |
| 3499 | /* Start swing calculation */ |
| 3500 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
| 3501 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
| 3502 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
| 3503 | |
| 3504 | if (intel_crtc->config->lane_count > 2) { |
| 3505 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
| 3506 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
| 3507 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
| 3508 | } |
| 3509 | |
| 3510 | mutex_unlock(&dev_priv->sb_lock); |
| 3511 | |
| 3512 | return 0; |
| 3513 | } |
| 3514 | |
| 3515 | static uint32_t |
| 3516 | gen4_signal_levels(uint8_t train_set) |
| 3517 | { |
| 3518 | uint32_t signal_levels = 0; |
| 3519 | |
| 3520 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3521 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3522 | default: |
| 3523 | signal_levels |= DP_VOLTAGE_0_4; |
| 3524 | break; |
| 3525 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3526 | signal_levels |= DP_VOLTAGE_0_6; |
| 3527 | break; |
| 3528 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3529 | signal_levels |= DP_VOLTAGE_0_8; |
| 3530 | break; |
| 3531 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
| 3532 | signal_levels |= DP_VOLTAGE_1_2; |
| 3533 | break; |
| 3534 | } |
| 3535 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
| 3536 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3537 | default: |
| 3538 | signal_levels |= DP_PRE_EMPHASIS_0; |
| 3539 | break; |
| 3540 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3541 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
| 3542 | break; |
| 3543 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
| 3544 | signal_levels |= DP_PRE_EMPHASIS_6; |
| 3545 | break; |
| 3546 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
| 3547 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
| 3548 | break; |
| 3549 | } |
| 3550 | return signal_levels; |
| 3551 | } |
| 3552 | |
| 3553 | /* Gen6's DP voltage swing and pre-emphasis control */ |
| 3554 | static uint32_t |
| 3555 | gen6_edp_signal_levels(uint8_t train_set) |
| 3556 | { |
| 3557 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 3558 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 3559 | switch (signal_levels) { |
| 3560 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3561 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3562 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
| 3563 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3564 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
| 3565 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
| 3566 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
| 3567 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
| 3568 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3569 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3570 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
| 3571 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3572 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3573 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
| 3574 | default: |
| 3575 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 3576 | "0x%x\n", signal_levels); |
| 3577 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
| 3578 | } |
| 3579 | } |
| 3580 | |
| 3581 | /* Gen7's DP voltage swing and pre-emphasis control */ |
| 3582 | static uint32_t |
| 3583 | gen7_edp_signal_levels(uint8_t train_set) |
| 3584 | { |
| 3585 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 3586 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 3587 | switch (signal_levels) { |
| 3588 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3589 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
| 3590 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3591 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
| 3592 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
| 3593 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
| 3594 | |
| 3595 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3596 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
| 3597 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3598 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
| 3599 | |
| 3600 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3601 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
| 3602 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3603 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
| 3604 | |
| 3605 | default: |
| 3606 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 3607 | "0x%x\n", signal_levels); |
| 3608 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
| 3609 | } |
| 3610 | } |
| 3611 | |
| 3612 | void |
| 3613 | intel_dp_set_signal_levels(struct intel_dp *intel_dp) |
| 3614 | { |
| 3615 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3616 | enum port port = intel_dig_port->port; |
| 3617 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 3618 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 3619 | uint32_t signal_levels, mask = 0; |
| 3620 | uint8_t train_set = intel_dp->train_set[0]; |
| 3621 | |
| 3622 | if (HAS_DDI(dev)) { |
| 3623 | signal_levels = ddi_signal_levels(intel_dp); |
| 3624 | |
| 3625 | if (IS_BROXTON(dev)) |
| 3626 | signal_levels = 0; |
| 3627 | else |
| 3628 | mask = DDI_BUF_EMP_MASK; |
| 3629 | } else if (IS_CHERRYVIEW(dev)) { |
| 3630 | signal_levels = chv_signal_levels(intel_dp); |
| 3631 | } else if (IS_VALLEYVIEW(dev)) { |
| 3632 | signal_levels = vlv_signal_levels(intel_dp); |
| 3633 | } else if (IS_GEN7(dev) && port == PORT_A) { |
| 3634 | signal_levels = gen7_edp_signal_levels(train_set); |
| 3635 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
| 3636 | } else if (IS_GEN6(dev) && port == PORT_A) { |
| 3637 | signal_levels = gen6_edp_signal_levels(train_set); |
| 3638 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
| 3639 | } else { |
| 3640 | signal_levels = gen4_signal_levels(train_set); |
| 3641 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
| 3642 | } |
| 3643 | |
| 3644 | if (mask) |
| 3645 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); |
| 3646 | |
| 3647 | DRM_DEBUG_KMS("Using vswing level %d\n", |
| 3648 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); |
| 3649 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", |
| 3650 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> |
| 3651 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
| 3652 | |
| 3653 | intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; |
| 3654 | |
| 3655 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
| 3656 | POSTING_READ(intel_dp->output_reg); |
| 3657 | } |
| 3658 | |
| 3659 | void |
| 3660 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
| 3661 | uint8_t dp_train_pat) |
| 3662 | { |
| 3663 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3664 | struct drm_i915_private *dev_priv = |
| 3665 | to_i915(intel_dig_port->base.base.dev); |
| 3666 | |
| 3667 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); |
| 3668 | |
| 3669 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
| 3670 | POSTING_READ(intel_dp->output_reg); |
| 3671 | } |
| 3672 | |
| 3673 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
| 3674 | { |
| 3675 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3676 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 3677 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3678 | enum port port = intel_dig_port->port; |
| 3679 | uint32_t val; |
| 3680 | |
| 3681 | if (!HAS_DDI(dev)) |
| 3682 | return; |
| 3683 | |
| 3684 | val = I915_READ(DP_TP_CTL(port)); |
| 3685 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
| 3686 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; |
| 3687 | I915_WRITE(DP_TP_CTL(port), val); |
| 3688 | |
| 3689 | /* |
| 3690 | * On PORT_A we can have only eDP in SST mode. There the only reason |
| 3691 | * we need to set idle transmission mode is to work around a HW issue |
| 3692 | * where we enable the pipe while not in idle link-training mode. |
| 3693 | * In this case there is requirement to wait for a minimum number of |
| 3694 | * idle patterns to be sent. |
| 3695 | */ |
| 3696 | if (port == PORT_A) |
| 3697 | return; |
| 3698 | |
| 3699 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), |
| 3700 | 1)) |
| 3701 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
| 3702 | } |
| 3703 | |
| 3704 | static void |
| 3705 | intel_dp_link_down(struct intel_dp *intel_dp) |
| 3706 | { |
| 3707 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3708 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
| 3709 | enum port port = intel_dig_port->port; |
| 3710 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 3711 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3712 | uint32_t DP = intel_dp->DP; |
| 3713 | |
| 3714 | if (WARN_ON(HAS_DDI(dev))) |
| 3715 | return; |
| 3716 | |
| 3717 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
| 3718 | return; |
| 3719 | |
| 3720 | DRM_DEBUG_KMS("\n"); |
| 3721 | |
| 3722 | if ((IS_GEN7(dev) && port == PORT_A) || |
| 3723 | (HAS_PCH_CPT(dev) && port != PORT_A)) { |
| 3724 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
| 3725 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
| 3726 | } else { |
| 3727 | if (IS_CHERRYVIEW(dev)) |
| 3728 | DP &= ~DP_LINK_TRAIN_MASK_CHV; |
| 3729 | else |
| 3730 | DP &= ~DP_LINK_TRAIN_MASK; |
| 3731 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
| 3732 | } |
| 3733 | I915_WRITE(intel_dp->output_reg, DP); |
| 3734 | POSTING_READ(intel_dp->output_reg); |
| 3735 | |
| 3736 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
| 3737 | I915_WRITE(intel_dp->output_reg, DP); |
| 3738 | POSTING_READ(intel_dp->output_reg); |
| 3739 | |
| 3740 | /* |
| 3741 | * HW workaround for IBX, we need to move the port |
| 3742 | * to transcoder A after disabling it to allow the |
| 3743 | * matching HDMI port to be enabled on transcoder A. |
| 3744 | */ |
| 3745 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) { |
| 3746 | /* |
| 3747 | * We get CPU/PCH FIFO underruns on the other pipe when |
| 3748 | * doing the workaround. Sweep them under the rug. |
| 3749 | */ |
| 3750 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
| 3751 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
| 3752 | |
| 3753 | /* always enable with pattern 1 (as per spec) */ |
| 3754 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); |
| 3755 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; |
| 3756 | I915_WRITE(intel_dp->output_reg, DP); |
| 3757 | POSTING_READ(intel_dp->output_reg); |
| 3758 | |
| 3759 | DP &= ~DP_PORT_EN; |
| 3760 | I915_WRITE(intel_dp->output_reg, DP); |
| 3761 | POSTING_READ(intel_dp->output_reg); |
| 3762 | |
| 3763 | intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A); |
| 3764 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
| 3765 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
| 3766 | } |
| 3767 | |
| 3768 | msleep(intel_dp->panel_power_down_delay); |
| 3769 | |
| 3770 | intel_dp->DP = DP; |
| 3771 | } |
| 3772 | |
| 3773 | static bool |
| 3774 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
| 3775 | { |
| 3776 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 3777 | struct drm_device *dev = dig_port->base.base.dev; |
| 3778 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3779 | uint8_t rev; |
| 3780 | |
| 3781 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, |
| 3782 | sizeof(intel_dp->dpcd)) < 0) |
| 3783 | return false; /* aux transfer failed */ |
| 3784 | |
| 3785 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
| 3786 | |
| 3787 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
| 3788 | return false; /* DPCD not present */ |
| 3789 | |
| 3790 | /* Check if the panel supports PSR */ |
| 3791 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); |
| 3792 | if (is_edp(intel_dp)) { |
| 3793 | intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, |
| 3794 | intel_dp->psr_dpcd, |
| 3795 | sizeof(intel_dp->psr_dpcd)); |
| 3796 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
| 3797 | dev_priv->psr.sink_support = true; |
| 3798 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
| 3799 | } |
| 3800 | |
| 3801 | if (INTEL_INFO(dev)->gen >= 9 && |
| 3802 | (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { |
| 3803 | uint8_t frame_sync_cap; |
| 3804 | |
| 3805 | dev_priv->psr.sink_support = true; |
| 3806 | intel_dp_dpcd_read_wake(&intel_dp->aux, |
| 3807 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, |
| 3808 | &frame_sync_cap, 1); |
| 3809 | dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; |
| 3810 | /* PSR2 needs frame sync as well */ |
| 3811 | dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; |
| 3812 | DRM_DEBUG_KMS("PSR2 %s on sink", |
| 3813 | dev_priv->psr.psr2_support ? "supported" : "not supported"); |
| 3814 | } |
| 3815 | } |
| 3816 | |
| 3817 | DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", |
| 3818 | yesno(intel_dp_source_supports_hbr2(intel_dp)), |
| 3819 | yesno(drm_dp_tps3_supported(intel_dp->dpcd))); |
| 3820 | |
| 3821 | /* Intermediate frequency support */ |
| 3822 | if (is_edp(intel_dp) && |
| 3823 | (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && |
| 3824 | (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) && |
| 3825 | (rev >= 0x03)) { /* eDp v1.4 or higher */ |
| 3826 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
| 3827 | int i; |
| 3828 | |
| 3829 | intel_dp_dpcd_read_wake(&intel_dp->aux, |
| 3830 | DP_SUPPORTED_LINK_RATES, |
| 3831 | sink_rates, |
| 3832 | sizeof(sink_rates)); |
| 3833 | |
| 3834 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
| 3835 | int val = le16_to_cpu(sink_rates[i]); |
| 3836 | |
| 3837 | if (val == 0) |
| 3838 | break; |
| 3839 | |
| 3840 | /* Value read is in kHz while drm clock is saved in deca-kHz */ |
| 3841 | intel_dp->sink_rates[i] = (val * 200) / 10; |
| 3842 | } |
| 3843 | intel_dp->num_sink_rates = i; |
| 3844 | } |
| 3845 | |
| 3846 | intel_dp_print_rates(intel_dp); |
| 3847 | |
| 3848 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
| 3849 | DP_DWN_STRM_PORT_PRESENT)) |
| 3850 | return true; /* native DP sink */ |
| 3851 | |
| 3852 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
| 3853 | return true; /* no per-port downstream info */ |
| 3854 | |
| 3855 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
| 3856 | intel_dp->downstream_ports, |
| 3857 | DP_MAX_DOWNSTREAM_PORTS) < 0) |
| 3858 | return false; /* downstream port status fetch failed */ |
| 3859 | |
| 3860 | return true; |
| 3861 | } |
| 3862 | |
| 3863 | static void |
| 3864 | intel_dp_probe_oui(struct intel_dp *intel_dp) |
| 3865 | { |
| 3866 | u8 buf[3]; |
| 3867 | |
| 3868 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
| 3869 | return; |
| 3870 | |
| 3871 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
| 3872 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
| 3873 | buf[0], buf[1], buf[2]); |
| 3874 | |
| 3875 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
| 3876 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
| 3877 | buf[0], buf[1], buf[2]); |
| 3878 | } |
| 3879 | |
| 3880 | static bool |
| 3881 | intel_dp_probe_mst(struct intel_dp *intel_dp) |
| 3882 | { |
| 3883 | u8 buf[1]; |
| 3884 | |
| 3885 | if (!i915.enable_dp_mst) |
| 3886 | return false; |
| 3887 | |
| 3888 | if (!intel_dp->can_mst) |
| 3889 | return false; |
| 3890 | |
| 3891 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) |
| 3892 | return false; |
| 3893 | |
| 3894 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { |
| 3895 | if (buf[0] & DP_MST_CAP) { |
| 3896 | DRM_DEBUG_KMS("Sink is MST capable\n"); |
| 3897 | intel_dp->is_mst = true; |
| 3898 | } else { |
| 3899 | DRM_DEBUG_KMS("Sink is not MST capable\n"); |
| 3900 | intel_dp->is_mst = false; |
| 3901 | } |
| 3902 | } |
| 3903 | |
| 3904 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
| 3905 | return intel_dp->is_mst; |
| 3906 | } |
| 3907 | |
| 3908 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) |
| 3909 | { |
| 3910 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 3911 | struct drm_device *dev = dig_port->base.base.dev; |
| 3912 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
| 3913 | u8 buf; |
| 3914 | int ret = 0; |
| 3915 | int count = 0; |
| 3916 | int attempts = 10; |
| 3917 | |
| 3918 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
| 3919 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
| 3920 | ret = -EIO; |
| 3921 | goto out; |
| 3922 | } |
| 3923 | |
| 3924 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
| 3925 | buf & ~DP_TEST_SINK_START) < 0) { |
| 3926 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
| 3927 | ret = -EIO; |
| 3928 | goto out; |
| 3929 | } |
| 3930 | |
| 3931 | do { |
| 3932 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 3933 | |
| 3934 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
| 3935 | DP_TEST_SINK_MISC, &buf) < 0) { |
| 3936 | ret = -EIO; |
| 3937 | goto out; |
| 3938 | } |
| 3939 | count = buf & DP_TEST_COUNT_MASK; |
| 3940 | } while (--attempts && count); |
| 3941 | |
| 3942 | if (attempts == 0) { |
| 3943 | DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n"); |
| 3944 | ret = -ETIMEDOUT; |
| 3945 | } |
| 3946 | |
| 3947 | out: |
| 3948 | hsw_enable_ips(intel_crtc); |
| 3949 | return ret; |
| 3950 | } |
| 3951 | |
| 3952 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) |
| 3953 | { |
| 3954 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 3955 | struct drm_device *dev = dig_port->base.base.dev; |
| 3956 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
| 3957 | u8 buf; |
| 3958 | int ret; |
| 3959 | |
| 3960 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
| 3961 | return -EIO; |
| 3962 | |
| 3963 | if (!(buf & DP_TEST_CRC_SUPPORTED)) |
| 3964 | return -ENOTTY; |
| 3965 | |
| 3966 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) |
| 3967 | return -EIO; |
| 3968 | |
| 3969 | if (buf & DP_TEST_SINK_START) { |
| 3970 | ret = intel_dp_sink_crc_stop(intel_dp); |
| 3971 | if (ret) |
| 3972 | return ret; |
| 3973 | } |
| 3974 | |
| 3975 | hsw_disable_ips(intel_crtc); |
| 3976 | |
| 3977 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
| 3978 | buf | DP_TEST_SINK_START) < 0) { |
| 3979 | hsw_enable_ips(intel_crtc); |
| 3980 | return -EIO; |
| 3981 | } |
| 3982 | |
| 3983 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 3984 | return 0; |
| 3985 | } |
| 3986 | |
| 3987 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) |
| 3988 | { |
| 3989 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 3990 | struct drm_device *dev = dig_port->base.base.dev; |
| 3991 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
| 3992 | u8 buf; |
| 3993 | int count, ret; |
| 3994 | int attempts = 6; |
| 3995 | |
| 3996 | ret = intel_dp_sink_crc_start(intel_dp); |
| 3997 | if (ret) |
| 3998 | return ret; |
| 3999 | |
| 4000 | do { |
| 4001 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 4002 | |
| 4003 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
| 4004 | DP_TEST_SINK_MISC, &buf) < 0) { |
| 4005 | ret = -EIO; |
| 4006 | goto stop; |
| 4007 | } |
| 4008 | count = buf & DP_TEST_COUNT_MASK; |
| 4009 | |
| 4010 | } while (--attempts && count == 0); |
| 4011 | |
| 4012 | if (attempts == 0) { |
| 4013 | DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); |
| 4014 | ret = -ETIMEDOUT; |
| 4015 | goto stop; |
| 4016 | } |
| 4017 | |
| 4018 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { |
| 4019 | ret = -EIO; |
| 4020 | goto stop; |
| 4021 | } |
| 4022 | |
| 4023 | stop: |
| 4024 | intel_dp_sink_crc_stop(intel_dp); |
| 4025 | return ret; |
| 4026 | } |
| 4027 | |
| 4028 | static bool |
| 4029 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
| 4030 | { |
| 4031 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
| 4032 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 4033 | sink_irq_vector, 1) == 1; |
| 4034 | } |
| 4035 | |
| 4036 | static bool |
| 4037 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
| 4038 | { |
| 4039 | int ret; |
| 4040 | |
| 4041 | ret = intel_dp_dpcd_read_wake(&intel_dp->aux, |
| 4042 | DP_SINK_COUNT_ESI, |
| 4043 | sink_irq_vector, 14); |
| 4044 | if (ret != 14) |
| 4045 | return false; |
| 4046 | |
| 4047 | return true; |
| 4048 | } |
| 4049 | |
| 4050 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
| 4051 | { |
| 4052 | uint8_t test_result = DP_TEST_ACK; |
| 4053 | return test_result; |
| 4054 | } |
| 4055 | |
| 4056 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) |
| 4057 | { |
| 4058 | uint8_t test_result = DP_TEST_NAK; |
| 4059 | return test_result; |
| 4060 | } |
| 4061 | |
| 4062 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) |
| 4063 | { |
| 4064 | uint8_t test_result = DP_TEST_NAK; |
| 4065 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 4066 | struct drm_connector *connector = &intel_connector->base; |
| 4067 | |
| 4068 | if (intel_connector->detect_edid == NULL || |
| 4069 | connector->edid_corrupt || |
| 4070 | intel_dp->aux.i2c_defer_count > 6) { |
| 4071 | /* Check EDID read for NACKs, DEFERs and corruption |
| 4072 | * (DP CTS 1.2 Core r1.1) |
| 4073 | * 4.2.2.4 : Failed EDID read, I2C_NAK |
| 4074 | * 4.2.2.5 : Failed EDID read, I2C_DEFER |
| 4075 | * 4.2.2.6 : EDID corruption detected |
| 4076 | * Use failsafe mode for all cases |
| 4077 | */ |
| 4078 | if (intel_dp->aux.i2c_nack_count > 0 || |
| 4079 | intel_dp->aux.i2c_defer_count > 0) |
| 4080 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", |
| 4081 | intel_dp->aux.i2c_nack_count, |
| 4082 | intel_dp->aux.i2c_defer_count); |
| 4083 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; |
| 4084 | } else { |
| 4085 | struct edid *block = intel_connector->detect_edid; |
| 4086 | |
| 4087 | /* We have to write the checksum |
| 4088 | * of the last block read |
| 4089 | */ |
| 4090 | block += intel_connector->detect_edid->extensions; |
| 4091 | |
| 4092 | if (!drm_dp_dpcd_write(&intel_dp->aux, |
| 4093 | DP_TEST_EDID_CHECKSUM, |
| 4094 | &block->checksum, |
| 4095 | 1)) |
| 4096 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
| 4097 | |
| 4098 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; |
| 4099 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; |
| 4100 | } |
| 4101 | |
| 4102 | /* Set test active flag here so userspace doesn't interrupt things */ |
| 4103 | intel_dp->compliance_test_active = 1; |
| 4104 | |
| 4105 | return test_result; |
| 4106 | } |
| 4107 | |
| 4108 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) |
| 4109 | { |
| 4110 | uint8_t test_result = DP_TEST_NAK; |
| 4111 | return test_result; |
| 4112 | } |
| 4113 | |
| 4114 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) |
| 4115 | { |
| 4116 | uint8_t response = DP_TEST_NAK; |
| 4117 | uint8_t rxdata = 0; |
| 4118 | int status = 0; |
| 4119 | |
| 4120 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); |
| 4121 | if (status <= 0) { |
| 4122 | DRM_DEBUG_KMS("Could not read test request from sink\n"); |
| 4123 | goto update_status; |
| 4124 | } |
| 4125 | |
| 4126 | switch (rxdata) { |
| 4127 | case DP_TEST_LINK_TRAINING: |
| 4128 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); |
| 4129 | intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; |
| 4130 | response = intel_dp_autotest_link_training(intel_dp); |
| 4131 | break; |
| 4132 | case DP_TEST_LINK_VIDEO_PATTERN: |
| 4133 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); |
| 4134 | intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; |
| 4135 | response = intel_dp_autotest_video_pattern(intel_dp); |
| 4136 | break; |
| 4137 | case DP_TEST_LINK_EDID_READ: |
| 4138 | DRM_DEBUG_KMS("EDID test requested\n"); |
| 4139 | intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; |
| 4140 | response = intel_dp_autotest_edid(intel_dp); |
| 4141 | break; |
| 4142 | case DP_TEST_LINK_PHY_TEST_PATTERN: |
| 4143 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); |
| 4144 | intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; |
| 4145 | response = intel_dp_autotest_phy_pattern(intel_dp); |
| 4146 | break; |
| 4147 | default: |
| 4148 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); |
| 4149 | break; |
| 4150 | } |
| 4151 | |
| 4152 | update_status: |
| 4153 | status = drm_dp_dpcd_write(&intel_dp->aux, |
| 4154 | DP_TEST_RESPONSE, |
| 4155 | &response, 1); |
| 4156 | if (status <= 0) |
| 4157 | DRM_DEBUG_KMS("Could not write test response to sink\n"); |
| 4158 | } |
| 4159 | |
| 4160 | static int |
| 4161 | intel_dp_check_mst_status(struct intel_dp *intel_dp) |
| 4162 | { |
| 4163 | bool bret; |
| 4164 | |
| 4165 | if (intel_dp->is_mst) { |
| 4166 | u8 esi[16] = { 0 }; |
| 4167 | int ret = 0; |
| 4168 | int retry; |
| 4169 | bool handled; |
| 4170 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
| 4171 | go_again: |
| 4172 | if (bret == true) { |
| 4173 | |
| 4174 | /* check link status - esi[10] = 0x200c */ |
| 4175 | if (intel_dp->active_mst_links && |
| 4176 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
| 4177 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
| 4178 | intel_dp_start_link_train(intel_dp); |
| 4179 | intel_dp_stop_link_train(intel_dp); |
| 4180 | } |
| 4181 | |
| 4182 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
| 4183 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
| 4184 | |
| 4185 | if (handled) { |
| 4186 | for (retry = 0; retry < 3; retry++) { |
| 4187 | int wret; |
| 4188 | wret = drm_dp_dpcd_write(&intel_dp->aux, |
| 4189 | DP_SINK_COUNT_ESI+1, |
| 4190 | &esi[1], 3); |
| 4191 | if (wret == 3) { |
| 4192 | break; |
| 4193 | } |
| 4194 | } |
| 4195 | |
| 4196 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
| 4197 | if (bret == true) { |
| 4198 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
| 4199 | goto go_again; |
| 4200 | } |
| 4201 | } else |
| 4202 | ret = 0; |
| 4203 | |
| 4204 | return ret; |
| 4205 | } else { |
| 4206 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 4207 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); |
| 4208 | intel_dp->is_mst = false; |
| 4209 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
| 4210 | /* send a hotplug event */ |
| 4211 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); |
| 4212 | } |
| 4213 | } |
| 4214 | return -EINVAL; |
| 4215 | } |
| 4216 | |
| 4217 | /* |
| 4218 | * According to DP spec |
| 4219 | * 5.1.2: |
| 4220 | * 1. Read DPCD |
| 4221 | * 2. Configure link according to Receiver Capabilities |
| 4222 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
| 4223 | * 4. Check link status on receipt of hot-plug interrupt |
| 4224 | */ |
| 4225 | static void |
| 4226 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
| 4227 | { |
| 4228 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 4229 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
| 4230 | u8 sink_irq_vector; |
| 4231 | u8 link_status[DP_LINK_STATUS_SIZE]; |
| 4232 | |
| 4233 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
| 4234 | |
| 4235 | /* |
| 4236 | * Clearing compliance test variables to allow capturing |
| 4237 | * of values for next automated test request. |
| 4238 | */ |
| 4239 | intel_dp->compliance_test_active = 0; |
| 4240 | intel_dp->compliance_test_type = 0; |
| 4241 | intel_dp->compliance_test_data = 0; |
| 4242 | |
| 4243 | if (!intel_encoder->base.crtc) |
| 4244 | return; |
| 4245 | |
| 4246 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) |
| 4247 | return; |
| 4248 | |
| 4249 | /* Try to read receiver status if the link appears to be up */ |
| 4250 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
| 4251 | return; |
| 4252 | } |
| 4253 | |
| 4254 | /* Now read the DPCD to see if it's actually running */ |
| 4255 | if (!intel_dp_get_dpcd(intel_dp)) { |
| 4256 | return; |
| 4257 | } |
| 4258 | |
| 4259 | /* Try to read the source of the interrupt */ |
| 4260 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 4261 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
| 4262 | /* Clear interrupt source */ |
| 4263 | drm_dp_dpcd_writeb(&intel_dp->aux, |
| 4264 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 4265 | sink_irq_vector); |
| 4266 | |
| 4267 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
| 4268 | DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); |
| 4269 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
| 4270 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
| 4271 | } |
| 4272 | |
| 4273 | /* if link training is requested we should perform it always */ |
| 4274 | if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) || |
| 4275 | (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) { |
| 4276 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
| 4277 | intel_encoder->base.name); |
| 4278 | intel_dp_start_link_train(intel_dp); |
| 4279 | intel_dp_stop_link_train(intel_dp); |
| 4280 | } |
| 4281 | } |
| 4282 | |
| 4283 | /* XXX this is probably wrong for multiple downstream ports */ |
| 4284 | static enum drm_connector_status |
| 4285 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
| 4286 | { |
| 4287 | uint8_t *dpcd = intel_dp->dpcd; |
| 4288 | uint8_t type; |
| 4289 | |
| 4290 | if (!intel_dp_get_dpcd(intel_dp)) |
| 4291 | return connector_status_disconnected; |
| 4292 | |
| 4293 | /* if there's no downstream port, we're done */ |
| 4294 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) |
| 4295 | return connector_status_connected; |
| 4296 | |
| 4297 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
| 4298 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 4299 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { |
| 4300 | uint8_t reg; |
| 4301 | |
| 4302 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, |
| 4303 | ®, 1) < 0) |
| 4304 | return connector_status_unknown; |
| 4305 | |
| 4306 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
| 4307 | : connector_status_disconnected; |
| 4308 | } |
| 4309 | |
| 4310 | /* If no HPD, poke DDC gently */ |
| 4311 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
| 4312 | return connector_status_connected; |
| 4313 | |
| 4314 | /* Well we tried, say unknown for unreliable port types */ |
| 4315 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
| 4316 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
| 4317 | if (type == DP_DS_PORT_TYPE_VGA || |
| 4318 | type == DP_DS_PORT_TYPE_NON_EDID) |
| 4319 | return connector_status_unknown; |
| 4320 | } else { |
| 4321 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
| 4322 | DP_DWN_STRM_PORT_TYPE_MASK; |
| 4323 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || |
| 4324 | type == DP_DWN_STRM_PORT_TYPE_OTHER) |
| 4325 | return connector_status_unknown; |
| 4326 | } |
| 4327 | |
| 4328 | /* Anything else is out of spec, warn and ignore */ |
| 4329 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
| 4330 | return connector_status_disconnected; |
| 4331 | } |
| 4332 | |
| 4333 | static enum drm_connector_status |
| 4334 | edp_detect(struct intel_dp *intel_dp) |
| 4335 | { |
| 4336 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 4337 | enum drm_connector_status status; |
| 4338 | |
| 4339 | status = intel_panel_detect(dev); |
| 4340 | if (status == connector_status_unknown) |
| 4341 | status = connector_status_connected; |
| 4342 | |
| 4343 | return status; |
| 4344 | } |
| 4345 | |
| 4346 | static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
| 4347 | struct intel_digital_port *port) |
| 4348 | { |
| 4349 | u32 bit; |
| 4350 | |
| 4351 | switch (port->port) { |
| 4352 | case PORT_A: |
| 4353 | return true; |
| 4354 | case PORT_B: |
| 4355 | bit = SDE_PORTB_HOTPLUG; |
| 4356 | break; |
| 4357 | case PORT_C: |
| 4358 | bit = SDE_PORTC_HOTPLUG; |
| 4359 | break; |
| 4360 | case PORT_D: |
| 4361 | bit = SDE_PORTD_HOTPLUG; |
| 4362 | break; |
| 4363 | default: |
| 4364 | MISSING_CASE(port->port); |
| 4365 | return false; |
| 4366 | } |
| 4367 | |
| 4368 | return I915_READ(SDEISR) & bit; |
| 4369 | } |
| 4370 | |
| 4371 | static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, |
| 4372 | struct intel_digital_port *port) |
| 4373 | { |
| 4374 | u32 bit; |
| 4375 | |
| 4376 | switch (port->port) { |
| 4377 | case PORT_A: |
| 4378 | return true; |
| 4379 | case PORT_B: |
| 4380 | bit = SDE_PORTB_HOTPLUG_CPT; |
| 4381 | break; |
| 4382 | case PORT_C: |
| 4383 | bit = SDE_PORTC_HOTPLUG_CPT; |
| 4384 | break; |
| 4385 | case PORT_D: |
| 4386 | bit = SDE_PORTD_HOTPLUG_CPT; |
| 4387 | break; |
| 4388 | case PORT_E: |
| 4389 | bit = SDE_PORTE_HOTPLUG_SPT; |
| 4390 | break; |
| 4391 | default: |
| 4392 | MISSING_CASE(port->port); |
| 4393 | return false; |
| 4394 | } |
| 4395 | |
| 4396 | return I915_READ(SDEISR) & bit; |
| 4397 | } |
| 4398 | |
| 4399 | static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, |
| 4400 | struct intel_digital_port *port) |
| 4401 | { |
| 4402 | u32 bit; |
| 4403 | |
| 4404 | switch (port->port) { |
| 4405 | case PORT_B: |
| 4406 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; |
| 4407 | break; |
| 4408 | case PORT_C: |
| 4409 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; |
| 4410 | break; |
| 4411 | case PORT_D: |
| 4412 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
| 4413 | break; |
| 4414 | default: |
| 4415 | MISSING_CASE(port->port); |
| 4416 | return false; |
| 4417 | } |
| 4418 | |
| 4419 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
| 4420 | } |
| 4421 | |
| 4422 | static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, |
| 4423 | struct intel_digital_port *port) |
| 4424 | { |
| 4425 | u32 bit; |
| 4426 | |
| 4427 | switch (port->port) { |
| 4428 | case PORT_B: |
| 4429 | bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; |
| 4430 | break; |
| 4431 | case PORT_C: |
| 4432 | bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; |
| 4433 | break; |
| 4434 | case PORT_D: |
| 4435 | bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; |
| 4436 | break; |
| 4437 | default: |
| 4438 | MISSING_CASE(port->port); |
| 4439 | return false; |
| 4440 | } |
| 4441 | |
| 4442 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
| 4443 | } |
| 4444 | |
| 4445 | static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, |
| 4446 | struct intel_digital_port *intel_dig_port) |
| 4447 | { |
| 4448 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 4449 | enum port port; |
| 4450 | u32 bit; |
| 4451 | |
| 4452 | intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); |
| 4453 | switch (port) { |
| 4454 | case PORT_A: |
| 4455 | bit = BXT_DE_PORT_HP_DDIA; |
| 4456 | break; |
| 4457 | case PORT_B: |
| 4458 | bit = BXT_DE_PORT_HP_DDIB; |
| 4459 | break; |
| 4460 | case PORT_C: |
| 4461 | bit = BXT_DE_PORT_HP_DDIC; |
| 4462 | break; |
| 4463 | default: |
| 4464 | MISSING_CASE(port); |
| 4465 | return false; |
| 4466 | } |
| 4467 | |
| 4468 | return I915_READ(GEN8_DE_PORT_ISR) & bit; |
| 4469 | } |
| 4470 | |
| 4471 | /* |
| 4472 | * intel_digital_port_connected - is the specified port connected? |
| 4473 | * @dev_priv: i915 private structure |
| 4474 | * @port: the port to test |
| 4475 | * |
| 4476 | * Return %true if @port is connected, %false otherwise. |
| 4477 | */ |
| 4478 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
| 4479 | struct intel_digital_port *port) |
| 4480 | { |
| 4481 | if (HAS_PCH_IBX(dev_priv)) |
| 4482 | return ibx_digital_port_connected(dev_priv, port); |
| 4483 | else if (HAS_PCH_SPLIT(dev_priv)) |
| 4484 | return cpt_digital_port_connected(dev_priv, port); |
| 4485 | else if (IS_BROXTON(dev_priv)) |
| 4486 | return bxt_digital_port_connected(dev_priv, port); |
| 4487 | else if (IS_GM45(dev_priv)) |
| 4488 | return gm45_digital_port_connected(dev_priv, port); |
| 4489 | else |
| 4490 | return g4x_digital_port_connected(dev_priv, port); |
| 4491 | } |
| 4492 | |
| 4493 | static struct edid * |
| 4494 | intel_dp_get_edid(struct intel_dp *intel_dp) |
| 4495 | { |
| 4496 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 4497 | |
| 4498 | /* use cached edid if we have one */ |
| 4499 | if (intel_connector->edid) { |
| 4500 | /* invalid edid */ |
| 4501 | if (IS_ERR(intel_connector->edid)) |
| 4502 | return NULL; |
| 4503 | |
| 4504 | return drm_edid_duplicate(intel_connector->edid); |
| 4505 | } else |
| 4506 | return drm_get_edid(&intel_connector->base, |
| 4507 | &intel_dp->aux.ddc); |
| 4508 | } |
| 4509 | |
| 4510 | static void |
| 4511 | intel_dp_set_edid(struct intel_dp *intel_dp) |
| 4512 | { |
| 4513 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 4514 | struct edid *edid; |
| 4515 | |
| 4516 | edid = intel_dp_get_edid(intel_dp); |
| 4517 | intel_connector->detect_edid = edid; |
| 4518 | |
| 4519 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) |
| 4520 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; |
| 4521 | else |
| 4522 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
| 4523 | } |
| 4524 | |
| 4525 | static void |
| 4526 | intel_dp_unset_edid(struct intel_dp *intel_dp) |
| 4527 | { |
| 4528 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 4529 | |
| 4530 | kfree(intel_connector->detect_edid); |
| 4531 | intel_connector->detect_edid = NULL; |
| 4532 | |
| 4533 | intel_dp->has_audio = false; |
| 4534 | } |
| 4535 | |
| 4536 | static enum drm_connector_status |
| 4537 | intel_dp_detect(struct drm_connector *connector, bool force) |
| 4538 | { |
| 4539 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 4540 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 4541 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 4542 | struct drm_device *dev = connector->dev; |
| 4543 | enum drm_connector_status status; |
| 4544 | enum intel_display_power_domain power_domain; |
| 4545 | bool ret; |
| 4546 | u8 sink_irq_vector; |
| 4547 | |
| 4548 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
| 4549 | connector->base.id, connector->name); |
| 4550 | intel_dp_unset_edid(intel_dp); |
| 4551 | |
| 4552 | if (intel_dp->is_mst) { |
| 4553 | /* MST devices are disconnected from a monitor POV */ |
| 4554 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
| 4555 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
| 4556 | return connector_status_disconnected; |
| 4557 | } |
| 4558 | |
| 4559 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
| 4560 | intel_display_power_get(to_i915(dev), power_domain); |
| 4561 | |
| 4562 | /* Can't disconnect eDP, but you can close the lid... */ |
| 4563 | if (is_edp(intel_dp)) |
| 4564 | status = edp_detect(intel_dp); |
| 4565 | else if (intel_digital_port_connected(to_i915(dev), |
| 4566 | dp_to_dig_port(intel_dp))) |
| 4567 | status = intel_dp_detect_dpcd(intel_dp); |
| 4568 | else |
| 4569 | status = connector_status_disconnected; |
| 4570 | |
| 4571 | if (status != connector_status_connected) { |
| 4572 | intel_dp->compliance_test_active = 0; |
| 4573 | intel_dp->compliance_test_type = 0; |
| 4574 | intel_dp->compliance_test_data = 0; |
| 4575 | |
| 4576 | goto out; |
| 4577 | } |
| 4578 | |
| 4579 | intel_dp_probe_oui(intel_dp); |
| 4580 | |
| 4581 | ret = intel_dp_probe_mst(intel_dp); |
| 4582 | if (ret) { |
| 4583 | /* if we are in MST mode then this connector |
| 4584 | won't appear connected or have anything with EDID on it */ |
| 4585 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
| 4586 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
| 4587 | status = connector_status_disconnected; |
| 4588 | goto out; |
| 4589 | } |
| 4590 | |
| 4591 | /* |
| 4592 | * Clearing NACK and defer counts to get their exact values |
| 4593 | * while reading EDID which are required by Compliance tests |
| 4594 | * 4.2.2.4 and 4.2.2.5 |
| 4595 | */ |
| 4596 | intel_dp->aux.i2c_nack_count = 0; |
| 4597 | intel_dp->aux.i2c_defer_count = 0; |
| 4598 | |
| 4599 | intel_dp_set_edid(intel_dp); |
| 4600 | |
| 4601 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
| 4602 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
| 4603 | status = connector_status_connected; |
| 4604 | |
| 4605 | /* Try to read the source of the interrupt */ |
| 4606 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 4607 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
| 4608 | /* Clear interrupt source */ |
| 4609 | drm_dp_dpcd_writeb(&intel_dp->aux, |
| 4610 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 4611 | sink_irq_vector); |
| 4612 | |
| 4613 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
| 4614 | intel_dp_handle_test_request(intel_dp); |
| 4615 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
| 4616 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
| 4617 | } |
| 4618 | |
| 4619 | out: |
| 4620 | intel_display_power_put(to_i915(dev), power_domain); |
| 4621 | return status; |
| 4622 | } |
| 4623 | |
| 4624 | static void |
| 4625 | intel_dp_force(struct drm_connector *connector) |
| 4626 | { |
| 4627 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 4628 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
| 4629 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
| 4630 | enum intel_display_power_domain power_domain; |
| 4631 | |
| 4632 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
| 4633 | connector->base.id, connector->name); |
| 4634 | intel_dp_unset_edid(intel_dp); |
| 4635 | |
| 4636 | if (connector->status != connector_status_connected) |
| 4637 | return; |
| 4638 | |
| 4639 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
| 4640 | intel_display_power_get(dev_priv, power_domain); |
| 4641 | |
| 4642 | intel_dp_set_edid(intel_dp); |
| 4643 | |
| 4644 | intel_display_power_put(dev_priv, power_domain); |
| 4645 | |
| 4646 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
| 4647 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
| 4648 | } |
| 4649 | |
| 4650 | static int intel_dp_get_modes(struct drm_connector *connector) |
| 4651 | { |
| 4652 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 4653 | struct edid *edid; |
| 4654 | |
| 4655 | edid = intel_connector->detect_edid; |
| 4656 | if (edid) { |
| 4657 | int ret = intel_connector_update_modes(connector, edid); |
| 4658 | if (ret) |
| 4659 | return ret; |
| 4660 | } |
| 4661 | |
| 4662 | /* if eDP has no EDID, fall back to fixed mode */ |
| 4663 | if (is_edp(intel_attached_dp(connector)) && |
| 4664 | intel_connector->panel.fixed_mode) { |
| 4665 | struct drm_display_mode *mode; |
| 4666 | |
| 4667 | mode = drm_mode_duplicate(connector->dev, |
| 4668 | intel_connector->panel.fixed_mode); |
| 4669 | if (mode) { |
| 4670 | drm_mode_probed_add(connector, mode); |
| 4671 | return 1; |
| 4672 | } |
| 4673 | } |
| 4674 | |
| 4675 | return 0; |
| 4676 | } |
| 4677 | |
| 4678 | static bool |
| 4679 | intel_dp_detect_audio(struct drm_connector *connector) |
| 4680 | { |
| 4681 | bool has_audio = false; |
| 4682 | struct edid *edid; |
| 4683 | |
| 4684 | edid = to_intel_connector(connector)->detect_edid; |
| 4685 | if (edid) |
| 4686 | has_audio = drm_detect_monitor_audio(edid); |
| 4687 | |
| 4688 | return has_audio; |
| 4689 | } |
| 4690 | |
| 4691 | static int |
| 4692 | intel_dp_set_property(struct drm_connector *connector, |
| 4693 | struct drm_property *property, |
| 4694 | uint64_t val) |
| 4695 | { |
| 4696 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 4697 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 4698 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
| 4699 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
| 4700 | int ret; |
| 4701 | |
| 4702 | ret = drm_object_property_set_value(&connector->base, property, val); |
| 4703 | if (ret) |
| 4704 | return ret; |
| 4705 | |
| 4706 | if (property == dev_priv->force_audio_property) { |
| 4707 | int i = val; |
| 4708 | bool has_audio; |
| 4709 | |
| 4710 | if (i == intel_dp->force_audio) |
| 4711 | return 0; |
| 4712 | |
| 4713 | intel_dp->force_audio = i; |
| 4714 | |
| 4715 | if (i == HDMI_AUDIO_AUTO) |
| 4716 | has_audio = intel_dp_detect_audio(connector); |
| 4717 | else |
| 4718 | has_audio = (i == HDMI_AUDIO_ON); |
| 4719 | |
| 4720 | if (has_audio == intel_dp->has_audio) |
| 4721 | return 0; |
| 4722 | |
| 4723 | intel_dp->has_audio = has_audio; |
| 4724 | goto done; |
| 4725 | } |
| 4726 | |
| 4727 | if (property == dev_priv->broadcast_rgb_property) { |
| 4728 | bool old_auto = intel_dp->color_range_auto; |
| 4729 | bool old_range = intel_dp->limited_color_range; |
| 4730 | |
| 4731 | switch (val) { |
| 4732 | case INTEL_BROADCAST_RGB_AUTO: |
| 4733 | intel_dp->color_range_auto = true; |
| 4734 | break; |
| 4735 | case INTEL_BROADCAST_RGB_FULL: |
| 4736 | intel_dp->color_range_auto = false; |
| 4737 | intel_dp->limited_color_range = false; |
| 4738 | break; |
| 4739 | case INTEL_BROADCAST_RGB_LIMITED: |
| 4740 | intel_dp->color_range_auto = false; |
| 4741 | intel_dp->limited_color_range = true; |
| 4742 | break; |
| 4743 | default: |
| 4744 | return -EINVAL; |
| 4745 | } |
| 4746 | |
| 4747 | if (old_auto == intel_dp->color_range_auto && |
| 4748 | old_range == intel_dp->limited_color_range) |
| 4749 | return 0; |
| 4750 | |
| 4751 | goto done; |
| 4752 | } |
| 4753 | |
| 4754 | if (is_edp(intel_dp) && |
| 4755 | property == connector->dev->mode_config.scaling_mode_property) { |
| 4756 | if (val == DRM_MODE_SCALE_NONE) { |
| 4757 | DRM_DEBUG_KMS("no scaling not supported\n"); |
| 4758 | return -EINVAL; |
| 4759 | } |
| 4760 | |
| 4761 | if (intel_connector->panel.fitting_mode == val) { |
| 4762 | /* the eDP scaling property is not changed */ |
| 4763 | return 0; |
| 4764 | } |
| 4765 | intel_connector->panel.fitting_mode = val; |
| 4766 | |
| 4767 | goto done; |
| 4768 | } |
| 4769 | |
| 4770 | return -EINVAL; |
| 4771 | |
| 4772 | done: |
| 4773 | if (intel_encoder->base.crtc) |
| 4774 | intel_crtc_restore_mode(intel_encoder->base.crtc); |
| 4775 | |
| 4776 | return 0; |
| 4777 | } |
| 4778 | |
| 4779 | static void |
| 4780 | intel_dp_connector_destroy(struct drm_connector *connector) |
| 4781 | { |
| 4782 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 4783 | |
| 4784 | kfree(intel_connector->detect_edid); |
| 4785 | |
| 4786 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
| 4787 | kfree(intel_connector->edid); |
| 4788 | |
| 4789 | /* Can't call is_edp() since the encoder may have been destroyed |
| 4790 | * already. */ |
| 4791 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
| 4792 | intel_panel_fini(&intel_connector->panel); |
| 4793 | |
| 4794 | drm_connector_cleanup(connector); |
| 4795 | kfree(connector); |
| 4796 | } |
| 4797 | |
| 4798 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
| 4799 | { |
| 4800 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
| 4801 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
| 4802 | |
| 4803 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
| 4804 | if (is_edp(intel_dp)) { |
| 4805 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
| 4806 | /* |
| 4807 | * vdd might still be enabled do to the delayed vdd off. |
| 4808 | * Make sure vdd is actually turned off here. |
| 4809 | */ |
| 4810 | pps_lock(intel_dp); |
| 4811 | edp_panel_vdd_off_sync(intel_dp); |
| 4812 | pps_unlock(intel_dp); |
| 4813 | |
| 4814 | if (intel_dp->edp_notifier.notifier_call) { |
| 4815 | unregister_reboot_notifier(&intel_dp->edp_notifier); |
| 4816 | intel_dp->edp_notifier.notifier_call = NULL; |
| 4817 | } |
| 4818 | } |
| 4819 | drm_encoder_cleanup(encoder); |
| 4820 | kfree(intel_dig_port); |
| 4821 | } |
| 4822 | |
| 4823 | static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
| 4824 | { |
| 4825 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
| 4826 | |
| 4827 | if (!is_edp(intel_dp)) |
| 4828 | return; |
| 4829 | |
| 4830 | /* |
| 4831 | * vdd might still be enabled do to the delayed vdd off. |
| 4832 | * Make sure vdd is actually turned off here. |
| 4833 | */ |
| 4834 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
| 4835 | pps_lock(intel_dp); |
| 4836 | edp_panel_vdd_off_sync(intel_dp); |
| 4837 | pps_unlock(intel_dp); |
| 4838 | } |
| 4839 | |
| 4840 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
| 4841 | { |
| 4842 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 4843 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 4844 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4845 | enum intel_display_power_domain power_domain; |
| 4846 | |
| 4847 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 4848 | |
| 4849 | if (!edp_have_panel_vdd(intel_dp)) |
| 4850 | return; |
| 4851 | |
| 4852 | /* |
| 4853 | * The VDD bit needs a power domain reference, so if the bit is |
| 4854 | * already enabled when we boot or resume, grab this reference and |
| 4855 | * schedule a vdd off, so we don't hold on to the reference |
| 4856 | * indefinitely. |
| 4857 | */ |
| 4858 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); |
| 4859 | power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); |
| 4860 | intel_display_power_get(dev_priv, power_domain); |
| 4861 | |
| 4862 | edp_panel_vdd_schedule_off(intel_dp); |
| 4863 | } |
| 4864 | |
| 4865 | static void intel_dp_encoder_reset(struct drm_encoder *encoder) |
| 4866 | { |
| 4867 | struct intel_dp *intel_dp; |
| 4868 | |
| 4869 | if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) |
| 4870 | return; |
| 4871 | |
| 4872 | intel_dp = enc_to_intel_dp(encoder); |
| 4873 | |
| 4874 | pps_lock(intel_dp); |
| 4875 | |
| 4876 | /* |
| 4877 | * Read out the current power sequencer assignment, |
| 4878 | * in case the BIOS did something with it. |
| 4879 | */ |
| 4880 | if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev)) |
| 4881 | vlv_initial_power_sequencer_setup(intel_dp); |
| 4882 | |
| 4883 | intel_edp_panel_vdd_sanitize(intel_dp); |
| 4884 | |
| 4885 | pps_unlock(intel_dp); |
| 4886 | } |
| 4887 | |
| 4888 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
| 4889 | .dpms = drm_atomic_helper_connector_dpms, |
| 4890 | .detect = intel_dp_detect, |
| 4891 | .force = intel_dp_force, |
| 4892 | .fill_modes = drm_helper_probe_single_connector_modes, |
| 4893 | .set_property = intel_dp_set_property, |
| 4894 | .atomic_get_property = intel_connector_atomic_get_property, |
| 4895 | .destroy = intel_dp_connector_destroy, |
| 4896 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
| 4897 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
| 4898 | }; |
| 4899 | |
| 4900 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
| 4901 | .get_modes = intel_dp_get_modes, |
| 4902 | .mode_valid = intel_dp_mode_valid, |
| 4903 | .best_encoder = intel_best_encoder, |
| 4904 | }; |
| 4905 | |
| 4906 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
| 4907 | .reset = intel_dp_encoder_reset, |
| 4908 | .destroy = intel_dp_encoder_destroy, |
| 4909 | }; |
| 4910 | |
| 4911 | enum irqreturn |
| 4912 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
| 4913 | { |
| 4914 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
| 4915 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 4916 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 4917 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4918 | enum intel_display_power_domain power_domain; |
| 4919 | enum irqreturn ret = IRQ_NONE; |
| 4920 | |
| 4921 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && |
| 4922 | intel_dig_port->base.type != INTEL_OUTPUT_HDMI) |
| 4923 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; |
| 4924 | |
| 4925 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
| 4926 | /* |
| 4927 | * vdd off can generate a long pulse on eDP which |
| 4928 | * would require vdd on to handle it, and thus we |
| 4929 | * would end up in an endless cycle of |
| 4930 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." |
| 4931 | */ |
| 4932 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", |
| 4933 | port_name(intel_dig_port->port)); |
| 4934 | return IRQ_HANDLED; |
| 4935 | } |
| 4936 | |
| 4937 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
| 4938 | port_name(intel_dig_port->port), |
| 4939 | long_hpd ? "long" : "short"); |
| 4940 | |
| 4941 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
| 4942 | intel_display_power_get(dev_priv, power_domain); |
| 4943 | |
| 4944 | if (long_hpd) { |
| 4945 | /* indicate that we need to restart link training */ |
| 4946 | intel_dp->train_set_valid = false; |
| 4947 | |
| 4948 | if (!intel_digital_port_connected(dev_priv, intel_dig_port)) |
| 4949 | goto mst_fail; |
| 4950 | |
| 4951 | if (!intel_dp_get_dpcd(intel_dp)) { |
| 4952 | goto mst_fail; |
| 4953 | } |
| 4954 | |
| 4955 | intel_dp_probe_oui(intel_dp); |
| 4956 | |
| 4957 | if (!intel_dp_probe_mst(intel_dp)) { |
| 4958 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
| 4959 | intel_dp_check_link_status(intel_dp); |
| 4960 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
| 4961 | goto mst_fail; |
| 4962 | } |
| 4963 | } else { |
| 4964 | if (intel_dp->is_mst) { |
| 4965 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) |
| 4966 | goto mst_fail; |
| 4967 | } |
| 4968 | |
| 4969 | if (!intel_dp->is_mst) { |
| 4970 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
| 4971 | intel_dp_check_link_status(intel_dp); |
| 4972 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
| 4973 | } |
| 4974 | } |
| 4975 | |
| 4976 | ret = IRQ_HANDLED; |
| 4977 | |
| 4978 | goto put_power; |
| 4979 | mst_fail: |
| 4980 | /* if we were in MST mode, and device is not there get out of MST mode */ |
| 4981 | if (intel_dp->is_mst) { |
| 4982 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state); |
| 4983 | intel_dp->is_mst = false; |
| 4984 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
| 4985 | } |
| 4986 | put_power: |
| 4987 | intel_display_power_put(dev_priv, power_domain); |
| 4988 | |
| 4989 | return ret; |
| 4990 | } |
| 4991 | |
| 4992 | /* check the VBT to see whether the eDP is on another port */ |
| 4993 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
| 4994 | { |
| 4995 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4996 | |
| 4997 | /* |
| 4998 | * eDP not supported on g4x. so bail out early just |
| 4999 | * for a bit extra safety in case the VBT is bonkers. |
| 5000 | */ |
| 5001 | if (INTEL_INFO(dev)->gen < 5) |
| 5002 | return false; |
| 5003 | |
| 5004 | if (port == PORT_A) |
| 5005 | return true; |
| 5006 | |
| 5007 | return intel_bios_is_port_edp(dev_priv, port); |
| 5008 | } |
| 5009 | |
| 5010 | void |
| 5011 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
| 5012 | { |
| 5013 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 5014 | |
| 5015 | intel_attach_force_audio_property(connector); |
| 5016 | intel_attach_broadcast_rgb_property(connector); |
| 5017 | intel_dp->color_range_auto = true; |
| 5018 | |
| 5019 | if (is_edp(intel_dp)) { |
| 5020 | drm_mode_create_scaling_mode_property(connector->dev); |
| 5021 | drm_object_attach_property( |
| 5022 | &connector->base, |
| 5023 | connector->dev->mode_config.scaling_mode_property, |
| 5024 | DRM_MODE_SCALE_ASPECT); |
| 5025 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
| 5026 | } |
| 5027 | } |
| 5028 | |
| 5029 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
| 5030 | { |
| 5031 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
| 5032 | intel_dp->last_power_on = jiffies; |
| 5033 | intel_dp->last_backlight_off = jiffies; |
| 5034 | } |
| 5035 | |
| 5036 | static void |
| 5037 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
| 5038 | struct intel_dp *intel_dp) |
| 5039 | { |
| 5040 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5041 | struct edp_power_seq cur, vbt, spec, |
| 5042 | *final = &intel_dp->pps_delays; |
| 5043 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
| 5044 | i915_reg_t pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
| 5045 | |
| 5046 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 5047 | |
| 5048 | /* already initialized? */ |
| 5049 | if (final->t11_t12 != 0) |
| 5050 | return; |
| 5051 | |
| 5052 | if (IS_BROXTON(dev)) { |
| 5053 | /* |
| 5054 | * TODO: BXT has 2 sets of PPS registers. |
| 5055 | * Correct Register for Broxton need to be identified |
| 5056 | * using VBT. hardcoding for now |
| 5057 | */ |
| 5058 | pp_ctrl_reg = BXT_PP_CONTROL(0); |
| 5059 | pp_on_reg = BXT_PP_ON_DELAYS(0); |
| 5060 | pp_off_reg = BXT_PP_OFF_DELAYS(0); |
| 5061 | } else if (HAS_PCH_SPLIT(dev)) { |
| 5062 | pp_ctrl_reg = PCH_PP_CONTROL; |
| 5063 | pp_on_reg = PCH_PP_ON_DELAYS; |
| 5064 | pp_off_reg = PCH_PP_OFF_DELAYS; |
| 5065 | pp_div_reg = PCH_PP_DIVISOR; |
| 5066 | } else { |
| 5067 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
| 5068 | |
| 5069 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
| 5070 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
| 5071 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
| 5072 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
| 5073 | } |
| 5074 | |
| 5075 | /* Workaround: Need to write PP_CONTROL with the unlock key as |
| 5076 | * the very first thing. */ |
| 5077 | pp_ctl = ironlake_get_pp_control(intel_dp); |
| 5078 | |
| 5079 | pp_on = I915_READ(pp_on_reg); |
| 5080 | pp_off = I915_READ(pp_off_reg); |
| 5081 | if (!IS_BROXTON(dev)) { |
| 5082 | I915_WRITE(pp_ctrl_reg, pp_ctl); |
| 5083 | pp_div = I915_READ(pp_div_reg); |
| 5084 | } |
| 5085 | |
| 5086 | /* Pull timing values out of registers */ |
| 5087 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
| 5088 | PANEL_POWER_UP_DELAY_SHIFT; |
| 5089 | |
| 5090 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
| 5091 | PANEL_LIGHT_ON_DELAY_SHIFT; |
| 5092 | |
| 5093 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
| 5094 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
| 5095 | |
| 5096 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
| 5097 | PANEL_POWER_DOWN_DELAY_SHIFT; |
| 5098 | |
| 5099 | if (IS_BROXTON(dev)) { |
| 5100 | u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> |
| 5101 | BXT_POWER_CYCLE_DELAY_SHIFT; |
| 5102 | if (tmp > 0) |
| 5103 | cur.t11_t12 = (tmp - 1) * 1000; |
| 5104 | else |
| 5105 | cur.t11_t12 = 0; |
| 5106 | } else { |
| 5107 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
| 5108 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
| 5109 | } |
| 5110 | |
| 5111 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
| 5112 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
| 5113 | |
| 5114 | vbt = dev_priv->vbt.edp.pps; |
| 5115 | |
| 5116 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
| 5117 | * our hw here, which are all in 100usec. */ |
| 5118 | spec.t1_t3 = 210 * 10; |
| 5119 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ |
| 5120 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ |
| 5121 | spec.t10 = 500 * 10; |
| 5122 | /* This one is special and actually in units of 100ms, but zero |
| 5123 | * based in the hw (so we need to add 100 ms). But the sw vbt |
| 5124 | * table multiplies it with 1000 to make it in units of 100usec, |
| 5125 | * too. */ |
| 5126 | spec.t11_t12 = (510 + 100) * 10; |
| 5127 | |
| 5128 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
| 5129 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
| 5130 | |
| 5131 | /* Use the max of the register settings and vbt. If both are |
| 5132 | * unset, fall back to the spec limits. */ |
| 5133 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
| 5134 | spec.field : \ |
| 5135 | max(cur.field, vbt.field)) |
| 5136 | assign_final(t1_t3); |
| 5137 | assign_final(t8); |
| 5138 | assign_final(t9); |
| 5139 | assign_final(t10); |
| 5140 | assign_final(t11_t12); |
| 5141 | #undef assign_final |
| 5142 | |
| 5143 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
| 5144 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
| 5145 | intel_dp->backlight_on_delay = get_delay(t8); |
| 5146 | intel_dp->backlight_off_delay = get_delay(t9); |
| 5147 | intel_dp->panel_power_down_delay = get_delay(t10); |
| 5148 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
| 5149 | #undef get_delay |
| 5150 | |
| 5151 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
| 5152 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
| 5153 | intel_dp->panel_power_cycle_delay); |
| 5154 | |
| 5155 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
| 5156 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
| 5157 | } |
| 5158 | |
| 5159 | static void |
| 5160 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
| 5161 | struct intel_dp *intel_dp) |
| 5162 | { |
| 5163 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5164 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
| 5165 | int div = dev_priv->rawclk_freq / 1000; |
| 5166 | i915_reg_t pp_on_reg, pp_off_reg, pp_div_reg, pp_ctrl_reg; |
| 5167 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 5168 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
| 5169 | |
| 5170 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 5171 | |
| 5172 | if (IS_BROXTON(dev)) { |
| 5173 | /* |
| 5174 | * TODO: BXT has 2 sets of PPS registers. |
| 5175 | * Correct Register for Broxton need to be identified |
| 5176 | * using VBT. hardcoding for now |
| 5177 | */ |
| 5178 | pp_ctrl_reg = BXT_PP_CONTROL(0); |
| 5179 | pp_on_reg = BXT_PP_ON_DELAYS(0); |
| 5180 | pp_off_reg = BXT_PP_OFF_DELAYS(0); |
| 5181 | |
| 5182 | } else if (HAS_PCH_SPLIT(dev)) { |
| 5183 | pp_on_reg = PCH_PP_ON_DELAYS; |
| 5184 | pp_off_reg = PCH_PP_OFF_DELAYS; |
| 5185 | pp_div_reg = PCH_PP_DIVISOR; |
| 5186 | } else { |
| 5187 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
| 5188 | |
| 5189 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
| 5190 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
| 5191 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
| 5192 | } |
| 5193 | |
| 5194 | /* |
| 5195 | * And finally store the new values in the power sequencer. The |
| 5196 | * backlight delays are set to 1 because we do manual waits on them. For |
| 5197 | * T8, even BSpec recommends doing it. For T9, if we don't do this, |
| 5198 | * we'll end up waiting for the backlight off delay twice: once when we |
| 5199 | * do the manual sleep, and once when we disable the panel and wait for |
| 5200 | * the PP_STATUS bit to become zero. |
| 5201 | */ |
| 5202 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
| 5203 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
| 5204 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
| 5205 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
| 5206 | /* Compute the divisor for the pp clock, simply match the Bspec |
| 5207 | * formula. */ |
| 5208 | if (IS_BROXTON(dev)) { |
| 5209 | pp_div = I915_READ(pp_ctrl_reg); |
| 5210 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; |
| 5211 | pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) |
| 5212 | << BXT_POWER_CYCLE_DELAY_SHIFT); |
| 5213 | } else { |
| 5214 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
| 5215 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
| 5216 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
| 5217 | } |
| 5218 | |
| 5219 | /* Haswell doesn't have any port selection bits for the panel |
| 5220 | * power sequencer any more. */ |
| 5221 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
| 5222 | port_sel = PANEL_PORT_SELECT_VLV(port); |
| 5223 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
| 5224 | if (port == PORT_A) |
| 5225 | port_sel = PANEL_PORT_SELECT_DPA; |
| 5226 | else |
| 5227 | port_sel = PANEL_PORT_SELECT_DPD; |
| 5228 | } |
| 5229 | |
| 5230 | pp_on |= port_sel; |
| 5231 | |
| 5232 | I915_WRITE(pp_on_reg, pp_on); |
| 5233 | I915_WRITE(pp_off_reg, pp_off); |
| 5234 | if (IS_BROXTON(dev)) |
| 5235 | I915_WRITE(pp_ctrl_reg, pp_div); |
| 5236 | else |
| 5237 | I915_WRITE(pp_div_reg, pp_div); |
| 5238 | |
| 5239 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
| 5240 | I915_READ(pp_on_reg), |
| 5241 | I915_READ(pp_off_reg), |
| 5242 | IS_BROXTON(dev) ? |
| 5243 | (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) : |
| 5244 | I915_READ(pp_div_reg)); |
| 5245 | } |
| 5246 | |
| 5247 | /** |
| 5248 | * intel_dp_set_drrs_state - program registers for RR switch to take effect |
| 5249 | * @dev: DRM device |
| 5250 | * @refresh_rate: RR to be programmed |
| 5251 | * |
| 5252 | * This function gets called when refresh rate (RR) has to be changed from |
| 5253 | * one frequency to another. Switches can be between high and low RR |
| 5254 | * supported by the panel or to any other RR based on media playback (in |
| 5255 | * this case, RR value needs to be passed from user space). |
| 5256 | * |
| 5257 | * The caller of this function needs to take a lock on dev_priv->drrs. |
| 5258 | */ |
| 5259 | static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) |
| 5260 | { |
| 5261 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5262 | struct intel_encoder *encoder; |
| 5263 | struct intel_digital_port *dig_port = NULL; |
| 5264 | struct intel_dp *intel_dp = dev_priv->drrs.dp; |
| 5265 | struct intel_crtc_state *config = NULL; |
| 5266 | struct intel_crtc *intel_crtc = NULL; |
| 5267 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
| 5268 | |
| 5269 | if (refresh_rate <= 0) { |
| 5270 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); |
| 5271 | return; |
| 5272 | } |
| 5273 | |
| 5274 | if (intel_dp == NULL) { |
| 5275 | DRM_DEBUG_KMS("DRRS not supported.\n"); |
| 5276 | return; |
| 5277 | } |
| 5278 | |
| 5279 | /* |
| 5280 | * FIXME: This needs proper synchronization with psr state for some |
| 5281 | * platforms that cannot have PSR and DRRS enabled at the same time. |
| 5282 | */ |
| 5283 | |
| 5284 | dig_port = dp_to_dig_port(intel_dp); |
| 5285 | encoder = &dig_port->base; |
| 5286 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
| 5287 | |
| 5288 | if (!intel_crtc) { |
| 5289 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); |
| 5290 | return; |
| 5291 | } |
| 5292 | |
| 5293 | config = intel_crtc->config; |
| 5294 | |
| 5295 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
| 5296 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
| 5297 | return; |
| 5298 | } |
| 5299 | |
| 5300 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
| 5301 | refresh_rate) |
| 5302 | index = DRRS_LOW_RR; |
| 5303 | |
| 5304 | if (index == dev_priv->drrs.refresh_rate_type) { |
| 5305 | DRM_DEBUG_KMS( |
| 5306 | "DRRS requested for previously set RR...ignoring\n"); |
| 5307 | return; |
| 5308 | } |
| 5309 | |
| 5310 | if (!intel_crtc->active) { |
| 5311 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
| 5312 | return; |
| 5313 | } |
| 5314 | |
| 5315 | if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) { |
| 5316 | switch (index) { |
| 5317 | case DRRS_HIGH_RR: |
| 5318 | intel_dp_set_m_n(intel_crtc, M1_N1); |
| 5319 | break; |
| 5320 | case DRRS_LOW_RR: |
| 5321 | intel_dp_set_m_n(intel_crtc, M2_N2); |
| 5322 | break; |
| 5323 | case DRRS_MAX_RR: |
| 5324 | default: |
| 5325 | DRM_ERROR("Unsupported refreshrate type\n"); |
| 5326 | } |
| 5327 | } else if (INTEL_INFO(dev)->gen > 6) { |
| 5328 | i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder); |
| 5329 | u32 val; |
| 5330 | |
| 5331 | val = I915_READ(reg); |
| 5332 | if (index > DRRS_HIGH_RR) { |
| 5333 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
| 5334 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
| 5335 | else |
| 5336 | val |= PIPECONF_EDP_RR_MODE_SWITCH; |
| 5337 | } else { |
| 5338 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
| 5339 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
| 5340 | else |
| 5341 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; |
| 5342 | } |
| 5343 | I915_WRITE(reg, val); |
| 5344 | } |
| 5345 | |
| 5346 | dev_priv->drrs.refresh_rate_type = index; |
| 5347 | |
| 5348 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); |
| 5349 | } |
| 5350 | |
| 5351 | /** |
| 5352 | * intel_edp_drrs_enable - init drrs struct if supported |
| 5353 | * @intel_dp: DP struct |
| 5354 | * |
| 5355 | * Initializes frontbuffer_bits and drrs.dp |
| 5356 | */ |
| 5357 | void intel_edp_drrs_enable(struct intel_dp *intel_dp) |
| 5358 | { |
| 5359 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 5360 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5361 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 5362 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
| 5363 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5364 | |
| 5365 | if (!intel_crtc->config->has_drrs) { |
| 5366 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); |
| 5367 | return; |
| 5368 | } |
| 5369 | |
| 5370 | mutex_lock(&dev_priv->drrs.mutex); |
| 5371 | if (WARN_ON(dev_priv->drrs.dp)) { |
| 5372 | DRM_ERROR("DRRS already enabled\n"); |
| 5373 | goto unlock; |
| 5374 | } |
| 5375 | |
| 5376 | dev_priv->drrs.busy_frontbuffer_bits = 0; |
| 5377 | |
| 5378 | dev_priv->drrs.dp = intel_dp; |
| 5379 | |
| 5380 | unlock: |
| 5381 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5382 | } |
| 5383 | |
| 5384 | /** |
| 5385 | * intel_edp_drrs_disable - Disable DRRS |
| 5386 | * @intel_dp: DP struct |
| 5387 | * |
| 5388 | */ |
| 5389 | void intel_edp_drrs_disable(struct intel_dp *intel_dp) |
| 5390 | { |
| 5391 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 5392 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5393 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 5394 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
| 5395 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5396 | |
| 5397 | if (!intel_crtc->config->has_drrs) |
| 5398 | return; |
| 5399 | |
| 5400 | mutex_lock(&dev_priv->drrs.mutex); |
| 5401 | if (!dev_priv->drrs.dp) { |
| 5402 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5403 | return; |
| 5404 | } |
| 5405 | |
| 5406 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
| 5407 | intel_dp_set_drrs_state(dev_priv->dev, |
| 5408 | intel_dp->attached_connector->panel. |
| 5409 | fixed_mode->vrefresh); |
| 5410 | |
| 5411 | dev_priv->drrs.dp = NULL; |
| 5412 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5413 | |
| 5414 | cancel_delayed_work_sync(&dev_priv->drrs.work); |
| 5415 | } |
| 5416 | |
| 5417 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
| 5418 | { |
| 5419 | struct drm_i915_private *dev_priv = |
| 5420 | container_of(work, typeof(*dev_priv), drrs.work.work); |
| 5421 | struct intel_dp *intel_dp; |
| 5422 | |
| 5423 | mutex_lock(&dev_priv->drrs.mutex); |
| 5424 | |
| 5425 | intel_dp = dev_priv->drrs.dp; |
| 5426 | |
| 5427 | if (!intel_dp) |
| 5428 | goto unlock; |
| 5429 | |
| 5430 | /* |
| 5431 | * The delayed work can race with an invalidate hence we need to |
| 5432 | * recheck. |
| 5433 | */ |
| 5434 | |
| 5435 | if (dev_priv->drrs.busy_frontbuffer_bits) |
| 5436 | goto unlock; |
| 5437 | |
| 5438 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) |
| 5439 | intel_dp_set_drrs_state(dev_priv->dev, |
| 5440 | intel_dp->attached_connector->panel. |
| 5441 | downclock_mode->vrefresh); |
| 5442 | |
| 5443 | unlock: |
| 5444 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5445 | } |
| 5446 | |
| 5447 | /** |
| 5448 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
| 5449 | * @dev: DRM device |
| 5450 | * @frontbuffer_bits: frontbuffer plane tracking bits |
| 5451 | * |
| 5452 | * This function gets called everytime rendering on the given planes start. |
| 5453 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). |
| 5454 | * |
| 5455 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. |
| 5456 | */ |
| 5457 | void intel_edp_drrs_invalidate(struct drm_device *dev, |
| 5458 | unsigned frontbuffer_bits) |
| 5459 | { |
| 5460 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5461 | struct drm_crtc *crtc; |
| 5462 | enum pipe pipe; |
| 5463 | |
| 5464 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
| 5465 | return; |
| 5466 | |
| 5467 | cancel_delayed_work(&dev_priv->drrs.work); |
| 5468 | |
| 5469 | mutex_lock(&dev_priv->drrs.mutex); |
| 5470 | if (!dev_priv->drrs.dp) { |
| 5471 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5472 | return; |
| 5473 | } |
| 5474 | |
| 5475 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
| 5476 | pipe = to_intel_crtc(crtc)->pipe; |
| 5477 | |
| 5478 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
| 5479 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; |
| 5480 | |
| 5481 | /* invalidate means busy screen hence upclock */ |
| 5482 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
| 5483 | intel_dp_set_drrs_state(dev_priv->dev, |
| 5484 | dev_priv->drrs.dp->attached_connector->panel. |
| 5485 | fixed_mode->vrefresh); |
| 5486 | |
| 5487 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5488 | } |
| 5489 | |
| 5490 | /** |
| 5491 | * intel_edp_drrs_flush - Restart Idleness DRRS |
| 5492 | * @dev: DRM device |
| 5493 | * @frontbuffer_bits: frontbuffer plane tracking bits |
| 5494 | * |
| 5495 | * This function gets called every time rendering on the given planes has |
| 5496 | * completed or flip on a crtc is completed. So DRRS should be upclocked |
| 5497 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, |
| 5498 | * if no other planes are dirty. |
| 5499 | * |
| 5500 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. |
| 5501 | */ |
| 5502 | void intel_edp_drrs_flush(struct drm_device *dev, |
| 5503 | unsigned frontbuffer_bits) |
| 5504 | { |
| 5505 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5506 | struct drm_crtc *crtc; |
| 5507 | enum pipe pipe; |
| 5508 | |
| 5509 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
| 5510 | return; |
| 5511 | |
| 5512 | cancel_delayed_work(&dev_priv->drrs.work); |
| 5513 | |
| 5514 | mutex_lock(&dev_priv->drrs.mutex); |
| 5515 | if (!dev_priv->drrs.dp) { |
| 5516 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5517 | return; |
| 5518 | } |
| 5519 | |
| 5520 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
| 5521 | pipe = to_intel_crtc(crtc)->pipe; |
| 5522 | |
| 5523 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
| 5524 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
| 5525 | |
| 5526 | /* flush means busy screen hence upclock */ |
| 5527 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
| 5528 | intel_dp_set_drrs_state(dev_priv->dev, |
| 5529 | dev_priv->drrs.dp->attached_connector->panel. |
| 5530 | fixed_mode->vrefresh); |
| 5531 | |
| 5532 | /* |
| 5533 | * flush also means no more activity hence schedule downclock, if all |
| 5534 | * other fbs are quiescent too |
| 5535 | */ |
| 5536 | if (!dev_priv->drrs.busy_frontbuffer_bits) |
| 5537 | schedule_delayed_work(&dev_priv->drrs.work, |
| 5538 | msecs_to_jiffies(1000)); |
| 5539 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5540 | } |
| 5541 | |
| 5542 | /** |
| 5543 | * DOC: Display Refresh Rate Switching (DRRS) |
| 5544 | * |
| 5545 | * Display Refresh Rate Switching (DRRS) is a power conservation feature |
| 5546 | * which enables swtching between low and high refresh rates, |
| 5547 | * dynamically, based on the usage scenario. This feature is applicable |
| 5548 | * for internal panels. |
| 5549 | * |
| 5550 | * Indication that the panel supports DRRS is given by the panel EDID, which |
| 5551 | * would list multiple refresh rates for one resolution. |
| 5552 | * |
| 5553 | * DRRS is of 2 types - static and seamless. |
| 5554 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset |
| 5555 | * (may appear as a blink on screen) and is used in dock-undock scenario. |
| 5556 | * Seamless DRRS involves changing RR without any visual effect to the user |
| 5557 | * and can be used during normal system usage. This is done by programming |
| 5558 | * certain registers. |
| 5559 | * |
| 5560 | * Support for static/seamless DRRS may be indicated in the VBT based on |
| 5561 | * inputs from the panel spec. |
| 5562 | * |
| 5563 | * DRRS saves power by switching to low RR based on usage scenarios. |
| 5564 | * |
| 5565 | * eDP DRRS:- |
| 5566 | * The implementation is based on frontbuffer tracking implementation. |
| 5567 | * When there is a disturbance on the screen triggered by user activity or a |
| 5568 | * periodic system activity, DRRS is disabled (RR is changed to high RR). |
| 5569 | * When there is no movement on screen, after a timeout of 1 second, a switch |
| 5570 | * to low RR is made. |
| 5571 | * For integration with frontbuffer tracking code, |
| 5572 | * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called. |
| 5573 | * |
| 5574 | * DRRS can be further extended to support other internal panels and also |
| 5575 | * the scenario of video playback wherein RR is set based on the rate |
| 5576 | * requested by userspace. |
| 5577 | */ |
| 5578 | |
| 5579 | /** |
| 5580 | * intel_dp_drrs_init - Init basic DRRS work and mutex. |
| 5581 | * @intel_connector: eDP connector |
| 5582 | * @fixed_mode: preferred mode of panel |
| 5583 | * |
| 5584 | * This function is called only once at driver load to initialize basic |
| 5585 | * DRRS stuff. |
| 5586 | * |
| 5587 | * Returns: |
| 5588 | * Downclock mode if panel supports it, else return NULL. |
| 5589 | * DRRS support is determined by the presence of downclock mode (apart |
| 5590 | * from VBT setting). |
| 5591 | */ |
| 5592 | static struct drm_display_mode * |
| 5593 | intel_dp_drrs_init(struct intel_connector *intel_connector, |
| 5594 | struct drm_display_mode *fixed_mode) |
| 5595 | { |
| 5596 | struct drm_connector *connector = &intel_connector->base; |
| 5597 | struct drm_device *dev = connector->dev; |
| 5598 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5599 | struct drm_display_mode *downclock_mode = NULL; |
| 5600 | |
| 5601 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
| 5602 | mutex_init(&dev_priv->drrs.mutex); |
| 5603 | |
| 5604 | if (INTEL_INFO(dev)->gen <= 6) { |
| 5605 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
| 5606 | return NULL; |
| 5607 | } |
| 5608 | |
| 5609 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { |
| 5610 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
| 5611 | return NULL; |
| 5612 | } |
| 5613 | |
| 5614 | downclock_mode = intel_find_panel_downclock |
| 5615 | (dev, fixed_mode, connector); |
| 5616 | |
| 5617 | if (!downclock_mode) { |
| 5618 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
| 5619 | return NULL; |
| 5620 | } |
| 5621 | |
| 5622 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
| 5623 | |
| 5624 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
| 5625 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
| 5626 | return downclock_mode; |
| 5627 | } |
| 5628 | |
| 5629 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
| 5630 | struct intel_connector *intel_connector) |
| 5631 | { |
| 5632 | struct drm_connector *connector = &intel_connector->base; |
| 5633 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 5634 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 5635 | struct drm_device *dev = intel_encoder->base.dev; |
| 5636 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5637 | struct drm_display_mode *fixed_mode = NULL; |
| 5638 | struct drm_display_mode *downclock_mode = NULL; |
| 5639 | bool has_dpcd; |
| 5640 | struct drm_display_mode *scan; |
| 5641 | struct edid *edid; |
| 5642 | enum pipe pipe = INVALID_PIPE; |
| 5643 | |
| 5644 | if (!is_edp(intel_dp)) |
| 5645 | return true; |
| 5646 | |
| 5647 | pps_lock(intel_dp); |
| 5648 | intel_edp_panel_vdd_sanitize(intel_dp); |
| 5649 | pps_unlock(intel_dp); |
| 5650 | |
| 5651 | /* Cache DPCD and EDID for edp. */ |
| 5652 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
| 5653 | |
| 5654 | if (has_dpcd) { |
| 5655 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
| 5656 | dev_priv->no_aux_handshake = |
| 5657 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
| 5658 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
| 5659 | } else { |
| 5660 | /* if this fails, presume the device is a ghost */ |
| 5661 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
| 5662 | return false; |
| 5663 | } |
| 5664 | |
| 5665 | /* We now know it's not a ghost, init power sequence regs. */ |
| 5666 | pps_lock(intel_dp); |
| 5667 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
| 5668 | pps_unlock(intel_dp); |
| 5669 | |
| 5670 | mutex_lock(&dev->mode_config.mutex); |
| 5671 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
| 5672 | if (edid) { |
| 5673 | if (drm_add_edid_modes(connector, edid)) { |
| 5674 | drm_mode_connector_update_edid_property(connector, |
| 5675 | edid); |
| 5676 | drm_edid_to_eld(connector, edid); |
| 5677 | } else { |
| 5678 | kfree(edid); |
| 5679 | edid = ERR_PTR(-EINVAL); |
| 5680 | } |
| 5681 | } else { |
| 5682 | edid = ERR_PTR(-ENOENT); |
| 5683 | } |
| 5684 | intel_connector->edid = edid; |
| 5685 | |
| 5686 | /* prefer fixed mode from EDID if available */ |
| 5687 | list_for_each_entry(scan, &connector->probed_modes, head) { |
| 5688 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
| 5689 | fixed_mode = drm_mode_duplicate(dev, scan); |
| 5690 | downclock_mode = intel_dp_drrs_init( |
| 5691 | intel_connector, fixed_mode); |
| 5692 | break; |
| 5693 | } |
| 5694 | } |
| 5695 | |
| 5696 | /* fallback to VBT if available for eDP */ |
| 5697 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { |
| 5698 | fixed_mode = drm_mode_duplicate(dev, |
| 5699 | dev_priv->vbt.lfp_lvds_vbt_mode); |
| 5700 | if (fixed_mode) |
| 5701 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
| 5702 | } |
| 5703 | mutex_unlock(&dev->mode_config.mutex); |
| 5704 | |
| 5705 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
| 5706 | intel_dp->edp_notifier.notifier_call = edp_notify_handler; |
| 5707 | register_reboot_notifier(&intel_dp->edp_notifier); |
| 5708 | |
| 5709 | /* |
| 5710 | * Figure out the current pipe for the initial backlight setup. |
| 5711 | * If the current pipe isn't valid, try the PPS pipe, and if that |
| 5712 | * fails just assume pipe A. |
| 5713 | */ |
| 5714 | if (IS_CHERRYVIEW(dev)) |
| 5715 | pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); |
| 5716 | else |
| 5717 | pipe = PORT_TO_PIPE(intel_dp->DP); |
| 5718 | |
| 5719 | if (pipe != PIPE_A && pipe != PIPE_B) |
| 5720 | pipe = intel_dp->pps_pipe; |
| 5721 | |
| 5722 | if (pipe != PIPE_A && pipe != PIPE_B) |
| 5723 | pipe = PIPE_A; |
| 5724 | |
| 5725 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", |
| 5726 | pipe_name(pipe)); |
| 5727 | } |
| 5728 | |
| 5729 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
| 5730 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
| 5731 | intel_panel_setup_backlight(connector, pipe); |
| 5732 | |
| 5733 | return true; |
| 5734 | } |
| 5735 | |
| 5736 | bool |
| 5737 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
| 5738 | struct intel_connector *intel_connector) |
| 5739 | { |
| 5740 | struct drm_connector *connector = &intel_connector->base; |
| 5741 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
| 5742 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 5743 | struct drm_device *dev = intel_encoder->base.dev; |
| 5744 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5745 | enum port port = intel_dig_port->port; |
| 5746 | int type, ret; |
| 5747 | |
| 5748 | if (WARN(intel_dig_port->max_lanes < 1, |
| 5749 | "Not enough lanes (%d) for DP on port %c\n", |
| 5750 | intel_dig_port->max_lanes, port_name(port))) |
| 5751 | return false; |
| 5752 | |
| 5753 | intel_dp->pps_pipe = INVALID_PIPE; |
| 5754 | |
| 5755 | /* intel_dp vfuncs */ |
| 5756 | if (INTEL_INFO(dev)->gen >= 9) |
| 5757 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; |
| 5758 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| 5759 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
| 5760 | else if (HAS_PCH_SPLIT(dev)) |
| 5761 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
| 5762 | else |
| 5763 | intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; |
| 5764 | |
| 5765 | if (INTEL_INFO(dev)->gen >= 9) |
| 5766 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; |
| 5767 | else |
| 5768 | intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; |
| 5769 | |
| 5770 | if (HAS_DDI(dev)) |
| 5771 | intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; |
| 5772 | |
| 5773 | /* Preserve the current hw state. */ |
| 5774 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
| 5775 | intel_dp->attached_connector = intel_connector; |
| 5776 | |
| 5777 | if (intel_dp_is_edp(dev, port)) |
| 5778 | type = DRM_MODE_CONNECTOR_eDP; |
| 5779 | else |
| 5780 | type = DRM_MODE_CONNECTOR_DisplayPort; |
| 5781 | |
| 5782 | /* |
| 5783 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but |
| 5784 | * for DP the encoder type can be set by the caller to |
| 5785 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. |
| 5786 | */ |
| 5787 | if (type == DRM_MODE_CONNECTOR_eDP) |
| 5788 | intel_encoder->type = INTEL_OUTPUT_EDP; |
| 5789 | |
| 5790 | /* eDP only on port B and/or C on vlv/chv */ |
| 5791 | if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
| 5792 | is_edp(intel_dp) && port != PORT_B && port != PORT_C)) |
| 5793 | return false; |
| 5794 | |
| 5795 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
| 5796 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", |
| 5797 | port_name(port)); |
| 5798 | |
| 5799 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
| 5800 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
| 5801 | |
| 5802 | connector->interlace_allowed = true; |
| 5803 | connector->doublescan_allowed = 0; |
| 5804 | |
| 5805 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
| 5806 | edp_panel_vdd_work); |
| 5807 | |
| 5808 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
| 5809 | drm_connector_register(connector); |
| 5810 | |
| 5811 | if (HAS_DDI(dev)) |
| 5812 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
| 5813 | else |
| 5814 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
| 5815 | intel_connector->unregister = intel_dp_connector_unregister; |
| 5816 | |
| 5817 | /* Set up the hotplug pin. */ |
| 5818 | switch (port) { |
| 5819 | case PORT_A: |
| 5820 | intel_encoder->hpd_pin = HPD_PORT_A; |
| 5821 | break; |
| 5822 | case PORT_B: |
| 5823 | intel_encoder->hpd_pin = HPD_PORT_B; |
| 5824 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
| 5825 | intel_encoder->hpd_pin = HPD_PORT_A; |
| 5826 | break; |
| 5827 | case PORT_C: |
| 5828 | intel_encoder->hpd_pin = HPD_PORT_C; |
| 5829 | break; |
| 5830 | case PORT_D: |
| 5831 | intel_encoder->hpd_pin = HPD_PORT_D; |
| 5832 | break; |
| 5833 | case PORT_E: |
| 5834 | intel_encoder->hpd_pin = HPD_PORT_E; |
| 5835 | break; |
| 5836 | default: |
| 5837 | BUG(); |
| 5838 | } |
| 5839 | |
| 5840 | if (is_edp(intel_dp)) { |
| 5841 | pps_lock(intel_dp); |
| 5842 | intel_dp_init_panel_power_timestamps(intel_dp); |
| 5843 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
| 5844 | vlv_initial_power_sequencer_setup(intel_dp); |
| 5845 | else |
| 5846 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
| 5847 | pps_unlock(intel_dp); |
| 5848 | } |
| 5849 | |
| 5850 | ret = intel_dp_aux_init(intel_dp, intel_connector); |
| 5851 | if (ret) |
| 5852 | goto fail; |
| 5853 | |
| 5854 | /* init MST on ports that can support it */ |
| 5855 | if (HAS_DP_MST(dev) && |
| 5856 | (port == PORT_B || port == PORT_C || port == PORT_D)) |
| 5857 | intel_dp_mst_encoder_init(intel_dig_port, |
| 5858 | intel_connector->base.base.id); |
| 5859 | |
| 5860 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
| 5861 | intel_dp_aux_fini(intel_dp); |
| 5862 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
| 5863 | goto fail; |
| 5864 | } |
| 5865 | |
| 5866 | intel_dp_add_properties(intel_dp, connector); |
| 5867 | |
| 5868 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
| 5869 | * 0xd. Failure to do so will result in spurious interrupts being |
| 5870 | * generated on the port when a cable is not attached. |
| 5871 | */ |
| 5872 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
| 5873 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
| 5874 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
| 5875 | } |
| 5876 | |
| 5877 | i915_debugfs_connector_add(connector); |
| 5878 | |
| 5879 | return true; |
| 5880 | |
| 5881 | fail: |
| 5882 | if (is_edp(intel_dp)) { |
| 5883 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
| 5884 | /* |
| 5885 | * vdd might still be enabled do to the delayed vdd off. |
| 5886 | * Make sure vdd is actually turned off here. |
| 5887 | */ |
| 5888 | pps_lock(intel_dp); |
| 5889 | edp_panel_vdd_off_sync(intel_dp); |
| 5890 | pps_unlock(intel_dp); |
| 5891 | } |
| 5892 | drm_connector_unregister(connector); |
| 5893 | drm_connector_cleanup(connector); |
| 5894 | |
| 5895 | return false; |
| 5896 | } |
| 5897 | |
| 5898 | void |
| 5899 | intel_dp_init(struct drm_device *dev, |
| 5900 | i915_reg_t output_reg, enum port port) |
| 5901 | { |
| 5902 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5903 | struct intel_digital_port *intel_dig_port; |
| 5904 | struct intel_encoder *intel_encoder; |
| 5905 | struct drm_encoder *encoder; |
| 5906 | struct intel_connector *intel_connector; |
| 5907 | |
| 5908 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
| 5909 | if (!intel_dig_port) |
| 5910 | return; |
| 5911 | |
| 5912 | intel_connector = intel_connector_alloc(); |
| 5913 | if (!intel_connector) |
| 5914 | goto err_connector_alloc; |
| 5915 | |
| 5916 | intel_encoder = &intel_dig_port->base; |
| 5917 | encoder = &intel_encoder->base; |
| 5918 | |
| 5919 | if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
| 5920 | DRM_MODE_ENCODER_TMDS, NULL)) |
| 5921 | goto err_encoder_init; |
| 5922 | |
| 5923 | intel_encoder->compute_config = intel_dp_compute_config; |
| 5924 | intel_encoder->disable = intel_disable_dp; |
| 5925 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
| 5926 | intel_encoder->get_config = intel_dp_get_config; |
| 5927 | intel_encoder->suspend = intel_dp_encoder_suspend; |
| 5928 | if (IS_CHERRYVIEW(dev)) { |
| 5929 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
| 5930 | intel_encoder->pre_enable = chv_pre_enable_dp; |
| 5931 | intel_encoder->enable = vlv_enable_dp; |
| 5932 | intel_encoder->post_disable = chv_post_disable_dp; |
| 5933 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
| 5934 | } else if (IS_VALLEYVIEW(dev)) { |
| 5935 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
| 5936 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
| 5937 | intel_encoder->enable = vlv_enable_dp; |
| 5938 | intel_encoder->post_disable = vlv_post_disable_dp; |
| 5939 | } else { |
| 5940 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
| 5941 | intel_encoder->enable = g4x_enable_dp; |
| 5942 | if (INTEL_INFO(dev)->gen >= 5) |
| 5943 | intel_encoder->post_disable = ilk_post_disable_dp; |
| 5944 | } |
| 5945 | |
| 5946 | intel_dig_port->port = port; |
| 5947 | intel_dig_port->dp.output_reg = output_reg; |
| 5948 | intel_dig_port->max_lanes = 4; |
| 5949 | |
| 5950 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
| 5951 | if (IS_CHERRYVIEW(dev)) { |
| 5952 | if (port == PORT_D) |
| 5953 | intel_encoder->crtc_mask = 1 << 2; |
| 5954 | else |
| 5955 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
| 5956 | } else { |
| 5957 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
| 5958 | } |
| 5959 | intel_encoder->cloneable = 0; |
| 5960 | |
| 5961 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
| 5962 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
| 5963 | |
| 5964 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
| 5965 | goto err_init_connector; |
| 5966 | |
| 5967 | return; |
| 5968 | |
| 5969 | err_init_connector: |
| 5970 | drm_encoder_cleanup(encoder); |
| 5971 | err_encoder_init: |
| 5972 | kfree(intel_connector); |
| 5973 | err_connector_alloc: |
| 5974 | kfree(intel_dig_port); |
| 5975 | |
| 5976 | return; |
| 5977 | } |
| 5978 | |
| 5979 | void intel_dp_mst_suspend(struct drm_device *dev) |
| 5980 | { |
| 5981 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5982 | int i; |
| 5983 | |
| 5984 | /* disable MST */ |
| 5985 | for (i = 0; i < I915_MAX_PORTS; i++) { |
| 5986 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
| 5987 | if (!intel_dig_port) |
| 5988 | continue; |
| 5989 | |
| 5990 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
| 5991 | if (!intel_dig_port->dp.can_mst) |
| 5992 | continue; |
| 5993 | if (intel_dig_port->dp.is_mst) |
| 5994 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); |
| 5995 | } |
| 5996 | } |
| 5997 | } |
| 5998 | |
| 5999 | void intel_dp_mst_resume(struct drm_device *dev) |
| 6000 | { |
| 6001 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6002 | int i; |
| 6003 | |
| 6004 | for (i = 0; i < I915_MAX_PORTS; i++) { |
| 6005 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
| 6006 | if (!intel_dig_port) |
| 6007 | continue; |
| 6008 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
| 6009 | int ret; |
| 6010 | |
| 6011 | if (!intel_dig_port->dp.can_mst) |
| 6012 | continue; |
| 6013 | |
| 6014 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
| 6015 | if (ret != 0) { |
| 6016 | intel_dp_check_mst_status(&intel_dig_port->dp); |
| 6017 | } |
| 6018 | } |
| 6019 | } |
| 6020 | } |