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drm/i915: Refactor ctg+ trickle feed disable
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_drv.h
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1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
29#include <drm/i915_drm.h>
30#include "i915_drv.h"
31#include <drm/drm_crtc.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/drm_fb_helper.h>
34#include <drm/drm_dp_helper.h>
35
36/**
37 * _wait_for - magic (register) wait macro
38 *
39 * Does the right thing for modeset paths when run under kdgb or similar atomic
40 * contexts. Note that it's important that we check the condition again after
41 * having timed out, since the timeout could be due to preemption or similar and
42 * we've never had a chance to check the condition before the timeout.
43 */
44#define _wait_for(COND, MS, W) ({ \
45 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
46 int ret__ = 0; \
47 while (!(COND)) { \
48 if (time_after(jiffies, timeout__)) { \
49 if (!(COND)) \
50 ret__ = -ETIMEDOUT; \
51 break; \
52 } \
53 if (W && drm_can_sleep()) { \
54 msleep(W); \
55 } else { \
56 cpu_relax(); \
57 } \
58 } \
59 ret__; \
60})
61
62#define wait_for(COND, MS) _wait_for(COND, MS, 1)
63#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
64#define wait_for_atomic_us(COND, US) _wait_for((COND), \
65 DIV_ROUND_UP((US), 1000), 0)
66
67#define KHz(x) (1000*x)
68#define MHz(x) KHz(1000*x)
69
70/*
71 * Display related stuff
72 */
73
74/* store information about an Ixxx DVO */
75/* The i830->i865 use multiple DVOs with multiple i2cs */
76/* the i915, i945 have a single sDVO i2c bus - which is different */
77#define MAX_OUTPUTS 6
78/* maximum connectors per crtcs in the mode set */
79#define INTELFB_CONN_LIMIT 4
80
81#define INTEL_I2C_BUS_DVO 1
82#define INTEL_I2C_BUS_SDVO 2
83
84/* these are outputs from the chip - integrated only
85 external chips are via DVO or SDVO output */
86#define INTEL_OUTPUT_UNUSED 0
87#define INTEL_OUTPUT_ANALOG 1
88#define INTEL_OUTPUT_DVO 2
89#define INTEL_OUTPUT_SDVO 3
90#define INTEL_OUTPUT_LVDS 4
91#define INTEL_OUTPUT_TVOUT 5
92#define INTEL_OUTPUT_HDMI 6
93#define INTEL_OUTPUT_DISPLAYPORT 7
94#define INTEL_OUTPUT_EDP 8
95#define INTEL_OUTPUT_UNKNOWN 9
96
97#define INTEL_DVO_CHIP_NONE 0
98#define INTEL_DVO_CHIP_LVDS 1
99#define INTEL_DVO_CHIP_TMDS 2
100#define INTEL_DVO_CHIP_TVOUT 4
101
102struct intel_framebuffer {
103 struct drm_framebuffer base;
104 struct drm_i915_gem_object *obj;
105};
106
107struct intel_fbdev {
108 struct drm_fb_helper helper;
109 struct intel_framebuffer ifb;
110 struct list_head fbdev_list;
111 struct drm_display_mode *our_mode;
112};
113
114struct intel_encoder {
115 struct drm_encoder base;
116 /*
117 * The new crtc this encoder will be driven from. Only differs from
118 * base->crtc while a modeset is in progress.
119 */
120 struct intel_crtc *new_crtc;
121
122 int type;
123 /*
124 * Intel hw has only one MUX where encoders could be clone, hence a
125 * simple flag is enough to compute the possible_clones mask.
126 */
127 bool cloneable;
128 bool connectors_active;
129 void (*hot_plug)(struct intel_encoder *);
130 bool (*compute_config)(struct intel_encoder *,
131 struct intel_crtc_config *);
132 void (*pre_pll_enable)(struct intel_encoder *);
133 void (*pre_enable)(struct intel_encoder *);
134 void (*enable)(struct intel_encoder *);
135 void (*mode_set)(struct intel_encoder *intel_encoder);
136 void (*disable)(struct intel_encoder *);
137 void (*post_disable)(struct intel_encoder *);
138 /* Read out the current hw state of this connector, returning true if
139 * the encoder is active. If the encoder is enabled it also set the pipe
140 * it is connected to in the pipe parameter. */
141 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
142 /* Reconstructs the equivalent mode flags for the current hardware
143 * state. */
144 void (*get_config)(struct intel_encoder *,
145 struct intel_crtc_config *pipe_config);
146 int crtc_mask;
147 enum hpd_pin hpd_pin;
148};
149
150struct intel_panel {
151 struct drm_display_mode *fixed_mode;
152 int fitting_mode;
153};
154
155struct intel_connector {
156 struct drm_connector base;
157 /*
158 * The fixed encoder this connector is connected to.
159 */
160 struct intel_encoder *encoder;
161
162 /*
163 * The new encoder this connector will be driven. Only differs from
164 * encoder while a modeset is in progress.
165 */
166 struct intel_encoder *new_encoder;
167
168 /* Reads out the current hw, returning true if the connector is enabled
169 * and active (i.e. dpms ON state). */
170 bool (*get_hw_state)(struct intel_connector *);
171
172 /* Panel info for eDP and LVDS */
173 struct intel_panel panel;
174
175 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
176 struct edid *edid;
177
178 /* since POLL and HPD connectors may use the same HPD line keep the native
179 state of connector->polled in case hotplug storm detection changes it */
180 u8 polled;
181};
182
183typedef struct dpll {
184 /* given values */
185 int n;
186 int m1, m2;
187 int p1, p2;
188 /* derived values */
189 int dot;
190 int vco;
191 int m;
192 int p;
193} intel_clock_t;
194
195struct intel_crtc_config {
196 /**
197 * quirks - bitfield with hw state readout quirks
198 *
199 * For various reasons the hw state readout code might not be able to
200 * completely faithfully read out the current state. These cases are
201 * tracked with quirk flags so that fastboot and state checker can act
202 * accordingly.
203 */
204#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
205 unsigned long quirks;
206
207 struct drm_display_mode requested_mode;
208 struct drm_display_mode adjusted_mode;
209 /* This flag must be set by the encoder's compute_config callback if it
210 * changes the crtc timings in the mode to prevent the crtc fixup from
211 * overwriting them. Currently only lvds needs that. */
212 bool timings_set;
213 /* Whether to set up the PCH/FDI. Note that we never allow sharing
214 * between pch encoders and cpu encoders. */
215 bool has_pch_encoder;
216
217 /* CPU Transcoder for the pipe. Currently this can only differ from the
218 * pipe on Haswell (where we have a special eDP transcoder). */
219 enum transcoder cpu_transcoder;
220
221 /*
222 * Use reduced/limited/broadcast rbg range, compressing from the full
223 * range fed into the crtcs.
224 */
225 bool limited_color_range;
226
227 /* DP has a bunch of special case unfortunately, so mark the pipe
228 * accordingly. */
229 bool has_dp_encoder;
230
231 /*
232 * Enable dithering, used when the selected pipe bpp doesn't match the
233 * plane bpp.
234 */
235 bool dither;
236
237 /* Controls for the clock computation, to override various stages. */
238 bool clock_set;
239
240 /* SDVO TV has a bunch of special case. To make multifunction encoders
241 * work correctly, we need to track this at runtime.*/
242 bool sdvo_tv_clock;
243
244 /*
245 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
246 * required. This is set in the 2nd loop of calling encoder's
247 * ->compute_config if the first pick doesn't work out.
248 */
249 bool bw_constrained;
250
251 /* Settings for the intel dpll used on pretty much everything but
252 * haswell. */
253 struct dpll dpll;
254
255 int pipe_bpp;
256 struct intel_link_m_n dp_m_n;
257
258 /*
259 * Frequence the dpll for the port should run at. Differs from the
260 * adjusted dotclock e.g. for DP or 12bpc hdmi mode.
261 */
262 int port_clock;
263
264 /* Used by SDVO (and if we ever fix it, HDMI). */
265 unsigned pixel_multiplier;
266
267 /* Panel fitter controls for gen2-gen4 + VLV */
268 struct {
269 u32 control;
270 u32 pgm_ratios;
271 u32 lvds_border_bits;
272 } gmch_pfit;
273
274 /* Panel fitter placement and size for Ironlake+ */
275 struct {
276 u32 pos;
277 u32 size;
278 } pch_pfit;
279
280 /* FDI configuration, only valid if has_pch_encoder is set. */
281 int fdi_lanes;
282 struct intel_link_m_n fdi_m_n;
283
284 bool ips_enabled;
285};
286
287struct intel_crtc {
288 struct drm_crtc base;
289 enum pipe pipe;
290 enum plane plane;
291 u8 lut_r[256], lut_g[256], lut_b[256];
292 /*
293 * Whether the crtc and the connected output pipeline is active. Implies
294 * that crtc->enabled is set, i.e. the current mode configuration has
295 * some outputs connected to this crtc.
296 */
297 bool active;
298 bool eld_vld;
299 bool primary_disabled; /* is the crtc obscured by a plane? */
300 bool lowfreq_avail;
301 struct intel_overlay *overlay;
302 struct intel_unpin_work *unpin_work;
303
304 atomic_t unpin_work_count;
305
306 /* Display surface base address adjustement for pageflips. Note that on
307 * gen4+ this only adjusts up to a tile, offsets within a tile are
308 * handled in the hw itself (with the TILEOFF register). */
309 unsigned long dspaddr_offset;
310
311 struct drm_i915_gem_object *cursor_bo;
312 uint32_t cursor_addr;
313 int16_t cursor_x, cursor_y;
314 int16_t cursor_width, cursor_height;
315 bool cursor_visible;
316
317 struct intel_crtc_config config;
318
319 /* We can share PLLs across outputs if the timings match */
320 struct intel_pch_pll *pch_pll;
321 uint32_t ddi_pll_sel;
322
323 /* reset counter value when the last flip was submitted */
324 unsigned int reset_counter;
325
326 /* Access to these should be protected by dev_priv->irq_lock. */
327 bool cpu_fifo_underrun_disabled;
328 bool pch_fifo_underrun_disabled;
329};
330
331struct intel_plane {
332 struct drm_plane base;
333 int plane;
334 enum pipe pipe;
335 struct drm_i915_gem_object *obj;
336 bool can_scale;
337 int max_downscale;
338 u32 lut_r[1024], lut_g[1024], lut_b[1024];
339 int crtc_x, crtc_y;
340 unsigned int crtc_w, crtc_h;
341 uint32_t src_x, src_y;
342 uint32_t src_w, src_h;
343
344 /* Since we need to change the watermarks before/after
345 * enabling/disabling the planes, we need to store the parameters here
346 * as the other pieces of the struct may not reflect the values we want
347 * for the watermark calculations. Currently only Haswell uses this.
348 */
349 struct {
350 bool enable;
351 uint8_t bytes_per_pixel;
352 uint32_t horiz_pixels;
353 } wm;
354
355 void (*update_plane)(struct drm_plane *plane,
356 struct drm_framebuffer *fb,
357 struct drm_i915_gem_object *obj,
358 int crtc_x, int crtc_y,
359 unsigned int crtc_w, unsigned int crtc_h,
360 uint32_t x, uint32_t y,
361 uint32_t src_w, uint32_t src_h);
362 void (*disable_plane)(struct drm_plane *plane);
363 int (*update_colorkey)(struct drm_plane *plane,
364 struct drm_intel_sprite_colorkey *key);
365 void (*get_colorkey)(struct drm_plane *plane,
366 struct drm_intel_sprite_colorkey *key);
367};
368
369struct intel_watermark_params {
370 unsigned long fifo_size;
371 unsigned long max_wm;
372 unsigned long default_wm;
373 unsigned long guard_size;
374 unsigned long cacheline_size;
375};
376
377struct cxsr_latency {
378 int is_desktop;
379 int is_ddr3;
380 unsigned long fsb_freq;
381 unsigned long mem_freq;
382 unsigned long display_sr;
383 unsigned long display_hpll_disable;
384 unsigned long cursor_sr;
385 unsigned long cursor_hpll_disable;
386};
387
388#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
389#define to_intel_connector(x) container_of(x, struct intel_connector, base)
390#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
391#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
392#define to_intel_plane(x) container_of(x, struct intel_plane, base)
393
394#define DIP_HEADER_SIZE 5
395
396#define DIP_TYPE_AVI 0x82
397#define DIP_VERSION_AVI 0x2
398#define DIP_LEN_AVI 13
399#define DIP_AVI_PR_1 0
400#define DIP_AVI_PR_2 1
401#define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
402#define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
403#define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2)
404
405#define DIP_TYPE_SPD 0x83
406#define DIP_VERSION_SPD 0x1
407#define DIP_LEN_SPD 25
408#define DIP_SPD_UNKNOWN 0
409#define DIP_SPD_DSTB 0x1
410#define DIP_SPD_DVDP 0x2
411#define DIP_SPD_DVHS 0x3
412#define DIP_SPD_HDDVR 0x4
413#define DIP_SPD_DVC 0x5
414#define DIP_SPD_DSC 0x6
415#define DIP_SPD_VCD 0x7
416#define DIP_SPD_GAME 0x8
417#define DIP_SPD_PC 0x9
418#define DIP_SPD_BD 0xa
419#define DIP_SPD_SCD 0xb
420
421struct dip_infoframe {
422 uint8_t type; /* HB0 */
423 uint8_t ver; /* HB1 */
424 uint8_t len; /* HB2 - body len, not including checksum */
425 uint8_t ecc; /* Header ECC */
426 uint8_t checksum; /* PB0 */
427 union {
428 struct {
429 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
430 uint8_t Y_A_B_S;
431 /* PB2 - C 7:6, M 5:4, R 3:0 */
432 uint8_t C_M_R;
433 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
434 uint8_t ITC_EC_Q_SC;
435 /* PB4 - VIC 6:0 */
436 uint8_t VIC;
437 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
438 uint8_t YQ_CN_PR;
439 /* PB6 to PB13 */
440 uint16_t top_bar_end;
441 uint16_t bottom_bar_start;
442 uint16_t left_bar_end;
443 uint16_t right_bar_start;
444 } __attribute__ ((packed)) avi;
445 struct {
446 uint8_t vn[8];
447 uint8_t pd[16];
448 uint8_t sdi;
449 } __attribute__ ((packed)) spd;
450 uint8_t payload[27];
451 } __attribute__ ((packed)) body;
452} __attribute__((packed));
453
454struct intel_hdmi {
455 u32 hdmi_reg;
456 int ddc_bus;
457 uint32_t color_range;
458 bool color_range_auto;
459 bool has_hdmi_sink;
460 bool has_audio;
461 enum hdmi_force_audio force_audio;
462 bool rgb_quant_range_selectable;
463 void (*write_infoframe)(struct drm_encoder *encoder,
464 struct dip_infoframe *frame);
465 void (*set_infoframes)(struct drm_encoder *encoder,
466 struct drm_display_mode *adjusted_mode);
467};
468
469#define DP_MAX_DOWNSTREAM_PORTS 0x10
470#define DP_LINK_CONFIGURATION_SIZE 9
471
472struct intel_dp {
473 uint32_t output_reg;
474 uint32_t aux_ch_ctl_reg;
475 uint32_t DP;
476 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
477 bool has_audio;
478 enum hdmi_force_audio force_audio;
479 uint32_t color_range;
480 bool color_range_auto;
481 uint8_t link_bw;
482 uint8_t lane_count;
483 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
484 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
485 struct i2c_adapter adapter;
486 struct i2c_algo_dp_aux_data algo;
487 uint8_t train_set[4];
488 int panel_power_up_delay;
489 int panel_power_down_delay;
490 int panel_power_cycle_delay;
491 int backlight_on_delay;
492 int backlight_off_delay;
493 struct delayed_work panel_vdd_work;
494 bool want_panel_vdd;
495 struct intel_connector *attached_connector;
496};
497
498struct intel_digital_port {
499 struct intel_encoder base;
500 enum port port;
501 u32 port_reversal;
502 struct intel_dp dp;
503 struct intel_hdmi hdmi;
504};
505
506static inline int
507vlv_dport_to_channel(struct intel_digital_port *dport)
508{
509 switch (dport->port) {
510 case PORT_B:
511 return 0;
512 case PORT_C:
513 return 1;
514 default:
515 BUG();
516 }
517}
518
519static inline struct drm_crtc *
520intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
521{
522 struct drm_i915_private *dev_priv = dev->dev_private;
523 return dev_priv->pipe_to_crtc_mapping[pipe];
524}
525
526static inline struct drm_crtc *
527intel_get_crtc_for_plane(struct drm_device *dev, int plane)
528{
529 struct drm_i915_private *dev_priv = dev->dev_private;
530 return dev_priv->plane_to_crtc_mapping[plane];
531}
532
533struct intel_unpin_work {
534 struct work_struct work;
535 struct drm_crtc *crtc;
536 struct drm_i915_gem_object *old_fb_obj;
537 struct drm_i915_gem_object *pending_flip_obj;
538 struct drm_pending_vblank_event *event;
539 atomic_t pending;
540#define INTEL_FLIP_INACTIVE 0
541#define INTEL_FLIP_PENDING 1
542#define INTEL_FLIP_COMPLETE 2
543 bool enable_stall_check;
544};
545
546struct intel_fbc_work {
547 struct delayed_work work;
548 struct drm_crtc *crtc;
549 struct drm_framebuffer *fb;
550 int interval;
551};
552
553int intel_pch_rawclk(struct drm_device *dev);
554
555int intel_connector_update_modes(struct drm_connector *connector,
556 struct edid *edid);
557int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
558
559extern void intel_attach_force_audio_property(struct drm_connector *connector);
560extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
561
562extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
563extern void intel_crt_init(struct drm_device *dev);
564extern void intel_hdmi_init(struct drm_device *dev,
565 int hdmi_reg, enum port port);
566extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
567 struct intel_connector *intel_connector);
568extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
569extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
570 struct intel_crtc_config *pipe_config);
571extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
572extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
573 bool is_sdvob);
574extern void intel_dvo_init(struct drm_device *dev);
575extern void intel_tv_init(struct drm_device *dev);
576extern void intel_mark_busy(struct drm_device *dev);
577extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
578extern void intel_mark_idle(struct drm_device *dev);
579extern bool intel_lvds_init(struct drm_device *dev);
580extern bool intel_is_dual_link_lvds(struct drm_device *dev);
581extern void intel_dp_init(struct drm_device *dev, int output_reg,
582 enum port port);
583extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
584 struct intel_connector *intel_connector);
585extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
586extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
587extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
588extern void intel_dp_stop_link_train(struct intel_dp *intel_dp);
589extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
590extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
591extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
592extern bool intel_dp_compute_config(struct intel_encoder *encoder,
593 struct intel_crtc_config *pipe_config);
594extern bool intel_dpd_is_edp(struct drm_device *dev);
595extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
596extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
597extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
598extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
599extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
600extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
601extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
602extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
603 enum plane plane);
604
605/* intel_panel.c */
606extern int intel_panel_init(struct intel_panel *panel,
607 struct drm_display_mode *fixed_mode);
608extern void intel_panel_fini(struct intel_panel *panel);
609
610extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
611 struct drm_display_mode *adjusted_mode);
612extern void intel_pch_panel_fitting(struct intel_crtc *crtc,
613 struct intel_crtc_config *pipe_config,
614 int fitting_mode);
615extern void intel_gmch_panel_fitting(struct intel_crtc *crtc,
616 struct intel_crtc_config *pipe_config,
617 int fitting_mode);
618extern void intel_panel_set_backlight(struct drm_device *dev,
619 u32 level, u32 max);
620extern int intel_panel_setup_backlight(struct drm_connector *connector);
621extern void intel_panel_enable_backlight(struct drm_device *dev,
622 enum pipe pipe);
623extern void intel_panel_disable_backlight(struct drm_device *dev);
624extern void intel_panel_destroy_backlight(struct drm_device *dev);
625extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
626
627struct intel_set_config {
628 struct drm_encoder **save_connector_encoders;
629 struct drm_crtc **save_encoder_crtcs;
630
631 bool fb_changed;
632 bool mode_changed;
633};
634
635extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
636 int x, int y, struct drm_framebuffer *old_fb);
637extern void intel_modeset_disable(struct drm_device *dev);
638extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
639extern void intel_crtc_load_lut(struct drm_crtc *crtc);
640extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
641extern void intel_encoder_destroy(struct drm_encoder *encoder);
642extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
643extern void intel_connector_dpms(struct drm_connector *, int mode);
644extern bool intel_connector_get_hw_state(struct intel_connector *connector);
645extern void intel_modeset_check_state(struct drm_device *dev);
646extern void intel_plane_restore(struct drm_plane *plane);
647extern void intel_plane_disable(struct drm_plane *plane);
648
649
650static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
651{
652 return to_intel_connector(connector)->encoder;
653}
654
655static inline struct intel_digital_port *
656enc_to_dig_port(struct drm_encoder *encoder)
657{
658 return container_of(encoder, struct intel_digital_port, base.base);
659}
660
661static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
662{
663 return &enc_to_dig_port(encoder)->dp;
664}
665
666static inline struct intel_digital_port *
667dp_to_dig_port(struct intel_dp *intel_dp)
668{
669 return container_of(intel_dp, struct intel_digital_port, dp);
670}
671
672static inline struct intel_digital_port *
673hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
674{
675 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
676}
677
678bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
679 struct intel_digital_port *port);
680
681extern void intel_connector_attach_encoder(struct intel_connector *connector,
682 struct intel_encoder *encoder);
683extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
684
685extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
686 struct drm_crtc *crtc);
687int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
688 struct drm_file *file_priv);
689extern enum transcoder
690intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
691 enum pipe pipe);
692extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
693extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
694extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
695extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
696
697struct intel_load_detect_pipe {
698 struct drm_framebuffer *release_fb;
699 bool load_detect_temp;
700 int dpms_mode;
701};
702extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
703 struct drm_display_mode *mode,
704 struct intel_load_detect_pipe *old);
705extern void intel_release_load_detect_pipe(struct drm_connector *connector,
706 struct intel_load_detect_pipe *old);
707
708extern void intelfb_restore(void);
709extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
710 u16 blue, int regno);
711extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
712 u16 *blue, int regno);
713extern void intel_enable_clock_gating(struct drm_device *dev);
714
715extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
716 struct drm_i915_gem_object *obj,
717 struct intel_ring_buffer *pipelined);
718extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
719
720extern int intel_framebuffer_init(struct drm_device *dev,
721 struct intel_framebuffer *ifb,
722 struct drm_mode_fb_cmd2 *mode_cmd,
723 struct drm_i915_gem_object *obj);
724extern int intel_fbdev_init(struct drm_device *dev);
725extern void intel_fbdev_initial_config(struct drm_device *dev);
726extern void intel_fbdev_fini(struct drm_device *dev);
727extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
728extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
729extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
730extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
731
732extern void intel_setup_overlay(struct drm_device *dev);
733extern void intel_cleanup_overlay(struct drm_device *dev);
734extern int intel_overlay_switch_off(struct intel_overlay *overlay);
735extern int intel_overlay_put_image(struct drm_device *dev, void *data,
736 struct drm_file *file_priv);
737extern int intel_overlay_attrs(struct drm_device *dev, void *data,
738 struct drm_file *file_priv);
739
740extern void intel_fb_output_poll_changed(struct drm_device *dev);
741extern void intel_fb_restore_mode(struct drm_device *dev);
742
743extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
744 bool state);
745#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
746#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
747
748extern void intel_init_clock_gating(struct drm_device *dev);
749extern void intel_suspend_hw(struct drm_device *dev);
750extern void intel_write_eld(struct drm_encoder *encoder,
751 struct drm_display_mode *mode);
752extern void intel_prepare_ddi(struct drm_device *dev);
753extern void hsw_fdi_link_train(struct drm_crtc *crtc);
754extern void intel_ddi_init(struct drm_device *dev, enum port port);
755
756/* For use by IVB LP watermark workaround in intel_sprite.c */
757extern void intel_update_watermarks(struct drm_device *dev);
758extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
759 uint32_t sprite_width,
760 int pixel_size, bool enable);
761
762extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
763 unsigned int tiling_mode,
764 unsigned int bpp,
765 unsigned int pitch);
766
767extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
768 struct drm_file *file_priv);
769extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
770 struct drm_file *file_priv);
771
772/* Power-related functions, located in intel_pm.c */
773extern void intel_init_pm(struct drm_device *dev);
774/* FBC */
775extern bool intel_fbc_enabled(struct drm_device *dev);
776extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
777extern void intel_update_fbc(struct drm_device *dev);
778/* IPS */
779extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
780extern void intel_gpu_ips_teardown(void);
781
782/* Power well */
783extern int i915_init_power_well(struct drm_device *dev);
784extern void i915_remove_power_well(struct drm_device *dev);
785
786extern bool intel_display_power_enabled(struct drm_device *dev,
787 enum intel_display_power_domain domain);
788extern void intel_init_power_well(struct drm_device *dev);
789extern void intel_set_power_well(struct drm_device *dev, bool enable);
790extern void intel_enable_gt_powersave(struct drm_device *dev);
791extern void intel_disable_gt_powersave(struct drm_device *dev);
792extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
793extern void ironlake_teardown_rc6(struct drm_device *dev);
794
795extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
796 enum pipe *pipe);
797extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
798extern void intel_ddi_pll_init(struct drm_device *dev);
799extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
800extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
801 enum transcoder cpu_transcoder);
802extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
803extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
804extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
805extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc);
806extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
807extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
808extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
809extern bool
810intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
811extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
812
813extern void intel_display_handle_reset(struct drm_device *dev);
814extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
815 enum pipe pipe,
816 bool enable);
817extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
818 enum transcoder pch_transcoder,
819 bool enable);
820
821#endif /* __INTEL_DRV_H__ */
Linux kernel - Deliverables
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