| 1 | /* |
| 2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> |
| 3 | * Copyright (c) 2007-2008 Intel Corporation |
| 4 | * Jesse Barnes <jesse.barnes@intel.com> |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the next |
| 14 | * paragraph) shall be included in all copies or substantial portions of the |
| 15 | * Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 23 | * IN THE SOFTWARE. |
| 24 | */ |
| 25 | #ifndef __INTEL_DRV_H__ |
| 26 | #define __INTEL_DRV_H__ |
| 27 | |
| 28 | #include <linux/async.h> |
| 29 | #include <linux/i2c.h> |
| 30 | #include <linux/hdmi.h> |
| 31 | #include <drm/i915_drm.h> |
| 32 | #include "i915_drv.h" |
| 33 | #include <drm/drm_crtc.h> |
| 34 | #include <drm/drm_crtc_helper.h> |
| 35 | #include <drm/drm_fb_helper.h> |
| 36 | #include <drm/drm_dp_mst_helper.h> |
| 37 | #include <drm/drm_rect.h> |
| 38 | |
| 39 | #define DIV_ROUND_CLOSEST_ULL(ll, d) \ |
| 40 | ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; }) |
| 41 | |
| 42 | /** |
| 43 | * _wait_for - magic (register) wait macro |
| 44 | * |
| 45 | * Does the right thing for modeset paths when run under kdgb or similar atomic |
| 46 | * contexts. Note that it's important that we check the condition again after |
| 47 | * having timed out, since the timeout could be due to preemption or similar and |
| 48 | * we've never had a chance to check the condition before the timeout. |
| 49 | */ |
| 50 | #define _wait_for(COND, MS, W) ({ \ |
| 51 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ |
| 52 | int ret__ = 0; \ |
| 53 | while (!(COND)) { \ |
| 54 | if (time_after(jiffies, timeout__)) { \ |
| 55 | if (!(COND)) \ |
| 56 | ret__ = -ETIMEDOUT; \ |
| 57 | break; \ |
| 58 | } \ |
| 59 | if (W && drm_can_sleep()) { \ |
| 60 | msleep(W); \ |
| 61 | } else { \ |
| 62 | cpu_relax(); \ |
| 63 | } \ |
| 64 | } \ |
| 65 | ret__; \ |
| 66 | }) |
| 67 | |
| 68 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
| 69 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) |
| 70 | #define wait_for_atomic_us(COND, US) _wait_for((COND), \ |
| 71 | DIV_ROUND_UP((US), 1000), 0) |
| 72 | |
| 73 | #define KHz(x) (1000 * (x)) |
| 74 | #define MHz(x) KHz(1000 * (x)) |
| 75 | |
| 76 | /* |
| 77 | * Display related stuff |
| 78 | */ |
| 79 | |
| 80 | /* store information about an Ixxx DVO */ |
| 81 | /* The i830->i865 use multiple DVOs with multiple i2cs */ |
| 82 | /* the i915, i945 have a single sDVO i2c bus - which is different */ |
| 83 | #define MAX_OUTPUTS 6 |
| 84 | /* maximum connectors per crtcs in the mode set */ |
| 85 | |
| 86 | /* Maximum cursor sizes */ |
| 87 | #define GEN2_CURSOR_WIDTH 64 |
| 88 | #define GEN2_CURSOR_HEIGHT 64 |
| 89 | #define MAX_CURSOR_WIDTH 256 |
| 90 | #define MAX_CURSOR_HEIGHT 256 |
| 91 | |
| 92 | #define INTEL_I2C_BUS_DVO 1 |
| 93 | #define INTEL_I2C_BUS_SDVO 2 |
| 94 | |
| 95 | /* these are outputs from the chip - integrated only |
| 96 | external chips are via DVO or SDVO output */ |
| 97 | enum intel_output_type { |
| 98 | INTEL_OUTPUT_UNUSED = 0, |
| 99 | INTEL_OUTPUT_ANALOG = 1, |
| 100 | INTEL_OUTPUT_DVO = 2, |
| 101 | INTEL_OUTPUT_SDVO = 3, |
| 102 | INTEL_OUTPUT_LVDS = 4, |
| 103 | INTEL_OUTPUT_TVOUT = 5, |
| 104 | INTEL_OUTPUT_HDMI = 6, |
| 105 | INTEL_OUTPUT_DISPLAYPORT = 7, |
| 106 | INTEL_OUTPUT_EDP = 8, |
| 107 | INTEL_OUTPUT_DSI = 9, |
| 108 | INTEL_OUTPUT_UNKNOWN = 10, |
| 109 | INTEL_OUTPUT_DP_MST = 11, |
| 110 | }; |
| 111 | |
| 112 | #define INTEL_DVO_CHIP_NONE 0 |
| 113 | #define INTEL_DVO_CHIP_LVDS 1 |
| 114 | #define INTEL_DVO_CHIP_TMDS 2 |
| 115 | #define INTEL_DVO_CHIP_TVOUT 4 |
| 116 | |
| 117 | #define INTEL_DSI_VIDEO_MODE 0 |
| 118 | #define INTEL_DSI_COMMAND_MODE 1 |
| 119 | |
| 120 | struct intel_framebuffer { |
| 121 | struct drm_framebuffer base; |
| 122 | struct drm_i915_gem_object *obj; |
| 123 | }; |
| 124 | |
| 125 | struct intel_fbdev { |
| 126 | struct drm_fb_helper helper; |
| 127 | struct intel_framebuffer *fb; |
| 128 | struct list_head fbdev_list; |
| 129 | struct drm_display_mode *our_mode; |
| 130 | int preferred_bpp; |
| 131 | }; |
| 132 | |
| 133 | struct intel_encoder { |
| 134 | struct drm_encoder base; |
| 135 | /* |
| 136 | * The new crtc this encoder will be driven from. Only differs from |
| 137 | * base->crtc while a modeset is in progress. |
| 138 | */ |
| 139 | struct intel_crtc *new_crtc; |
| 140 | |
| 141 | enum intel_output_type type; |
| 142 | unsigned int cloneable; |
| 143 | bool connectors_active; |
| 144 | void (*hot_plug)(struct intel_encoder *); |
| 145 | bool (*compute_config)(struct intel_encoder *, |
| 146 | struct intel_crtc_state *); |
| 147 | void (*pre_pll_enable)(struct intel_encoder *); |
| 148 | void (*pre_enable)(struct intel_encoder *); |
| 149 | void (*enable)(struct intel_encoder *); |
| 150 | void (*mode_set)(struct intel_encoder *intel_encoder); |
| 151 | void (*disable)(struct intel_encoder *); |
| 152 | void (*post_disable)(struct intel_encoder *); |
| 153 | /* Read out the current hw state of this connector, returning true if |
| 154 | * the encoder is active. If the encoder is enabled it also set the pipe |
| 155 | * it is connected to in the pipe parameter. */ |
| 156 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); |
| 157 | /* Reconstructs the equivalent mode flags for the current hardware |
| 158 | * state. This must be called _after_ display->get_pipe_config has |
| 159 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
| 160 | * be set correctly before calling this function. */ |
| 161 | void (*get_config)(struct intel_encoder *, |
| 162 | struct intel_crtc_state *pipe_config); |
| 163 | /* |
| 164 | * Called during system suspend after all pending requests for the |
| 165 | * encoder are flushed (for example for DP AUX transactions) and |
| 166 | * device interrupts are disabled. |
| 167 | */ |
| 168 | void (*suspend)(struct intel_encoder *); |
| 169 | int crtc_mask; |
| 170 | enum hpd_pin hpd_pin; |
| 171 | }; |
| 172 | |
| 173 | struct intel_panel { |
| 174 | struct drm_display_mode *fixed_mode; |
| 175 | struct drm_display_mode *downclock_mode; |
| 176 | int fitting_mode; |
| 177 | |
| 178 | /* backlight */ |
| 179 | struct { |
| 180 | bool present; |
| 181 | u32 level; |
| 182 | u32 min; |
| 183 | u32 max; |
| 184 | bool enabled; |
| 185 | bool combination_mode; /* gen 2/4 only */ |
| 186 | bool active_low_pwm; |
| 187 | struct backlight_device *device; |
| 188 | } backlight; |
| 189 | |
| 190 | void (*backlight_power)(struct intel_connector *, bool enable); |
| 191 | }; |
| 192 | |
| 193 | struct intel_connector { |
| 194 | struct drm_connector base; |
| 195 | /* |
| 196 | * The fixed encoder this connector is connected to. |
| 197 | */ |
| 198 | struct intel_encoder *encoder; |
| 199 | |
| 200 | /* |
| 201 | * The new encoder this connector will be driven. Only differs from |
| 202 | * encoder while a modeset is in progress. |
| 203 | */ |
| 204 | struct intel_encoder *new_encoder; |
| 205 | |
| 206 | /* Reads out the current hw, returning true if the connector is enabled |
| 207 | * and active (i.e. dpms ON state). */ |
| 208 | bool (*get_hw_state)(struct intel_connector *); |
| 209 | |
| 210 | /* |
| 211 | * Removes all interfaces through which the connector is accessible |
| 212 | * - like sysfs, debugfs entries -, so that no new operations can be |
| 213 | * started on the connector. Also makes sure all currently pending |
| 214 | * operations finish before returing. |
| 215 | */ |
| 216 | void (*unregister)(struct intel_connector *); |
| 217 | |
| 218 | /* Panel info for eDP and LVDS */ |
| 219 | struct intel_panel panel; |
| 220 | |
| 221 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ |
| 222 | struct edid *edid; |
| 223 | struct edid *detect_edid; |
| 224 | |
| 225 | /* since POLL and HPD connectors may use the same HPD line keep the native |
| 226 | state of connector->polled in case hotplug storm detection changes it */ |
| 227 | u8 polled; |
| 228 | |
| 229 | void *port; /* store this opaque as its illegal to dereference it */ |
| 230 | |
| 231 | struct intel_dp *mst_port; |
| 232 | }; |
| 233 | |
| 234 | typedef struct dpll { |
| 235 | /* given values */ |
| 236 | int n; |
| 237 | int m1, m2; |
| 238 | int p1, p2; |
| 239 | /* derived values */ |
| 240 | int dot; |
| 241 | int vco; |
| 242 | int m; |
| 243 | int p; |
| 244 | } intel_clock_t; |
| 245 | |
| 246 | struct intel_plane_state { |
| 247 | struct drm_plane_state base; |
| 248 | struct drm_rect src; |
| 249 | struct drm_rect dst; |
| 250 | struct drm_rect clip; |
| 251 | bool visible; |
| 252 | |
| 253 | /* |
| 254 | * used only for sprite planes to determine when to implicitly |
| 255 | * enable/disable the primary plane |
| 256 | */ |
| 257 | bool hides_primary; |
| 258 | }; |
| 259 | |
| 260 | struct intel_plane_config { |
| 261 | bool tiled; |
| 262 | int size; |
| 263 | u32 base; |
| 264 | }; |
| 265 | |
| 266 | struct intel_crtc_state { |
| 267 | struct drm_crtc_state base; |
| 268 | |
| 269 | /** |
| 270 | * quirks - bitfield with hw state readout quirks |
| 271 | * |
| 272 | * For various reasons the hw state readout code might not be able to |
| 273 | * completely faithfully read out the current state. These cases are |
| 274 | * tracked with quirk flags so that fastboot and state checker can act |
| 275 | * accordingly. |
| 276 | */ |
| 277 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
| 278 | #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */ |
| 279 | unsigned long quirks; |
| 280 | |
| 281 | /* Pipe source size (ie. panel fitter input size) |
| 282 | * All planes will be positioned inside this space, |
| 283 | * and get clipped at the edges. */ |
| 284 | int pipe_src_w, pipe_src_h; |
| 285 | |
| 286 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
| 287 | * between pch encoders and cpu encoders. */ |
| 288 | bool has_pch_encoder; |
| 289 | |
| 290 | /* Are we sending infoframes on the attached port */ |
| 291 | bool has_infoframe; |
| 292 | |
| 293 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
| 294 | * pipe on Haswell (where we have a special eDP transcoder). */ |
| 295 | enum transcoder cpu_transcoder; |
| 296 | |
| 297 | /* |
| 298 | * Use reduced/limited/broadcast rbg range, compressing from the full |
| 299 | * range fed into the crtcs. |
| 300 | */ |
| 301 | bool limited_color_range; |
| 302 | |
| 303 | /* DP has a bunch of special case unfortunately, so mark the pipe |
| 304 | * accordingly. */ |
| 305 | bool has_dp_encoder; |
| 306 | |
| 307 | /* Whether we should send NULL infoframes. Required for audio. */ |
| 308 | bool has_hdmi_sink; |
| 309 | |
| 310 | /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or |
| 311 | * has_dp_encoder is set. */ |
| 312 | bool has_audio; |
| 313 | |
| 314 | /* |
| 315 | * Enable dithering, used when the selected pipe bpp doesn't match the |
| 316 | * plane bpp. |
| 317 | */ |
| 318 | bool dither; |
| 319 | |
| 320 | /* Controls for the clock computation, to override various stages. */ |
| 321 | bool clock_set; |
| 322 | |
| 323 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
| 324 | * work correctly, we need to track this at runtime.*/ |
| 325 | bool sdvo_tv_clock; |
| 326 | |
| 327 | /* |
| 328 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really |
| 329 | * required. This is set in the 2nd loop of calling encoder's |
| 330 | * ->compute_config if the first pick doesn't work out. |
| 331 | */ |
| 332 | bool bw_constrained; |
| 333 | |
| 334 | /* Settings for the intel dpll used on pretty much everything but |
| 335 | * haswell. */ |
| 336 | struct dpll dpll; |
| 337 | |
| 338 | /* Selected dpll when shared or DPLL_ID_PRIVATE. */ |
| 339 | enum intel_dpll_id shared_dpll; |
| 340 | |
| 341 | /* |
| 342 | * - PORT_CLK_SEL for DDI ports on HSW/BDW. |
| 343 | * - enum skl_dpll on SKL |
| 344 | */ |
| 345 | uint32_t ddi_pll_sel; |
| 346 | |
| 347 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
| 348 | struct intel_dpll_hw_state dpll_hw_state; |
| 349 | |
| 350 | int pipe_bpp; |
| 351 | struct intel_link_m_n dp_m_n; |
| 352 | |
| 353 | /* m2_n2 for eDP downclock */ |
| 354 | struct intel_link_m_n dp_m2_n2; |
| 355 | bool has_drrs; |
| 356 | |
| 357 | /* |
| 358 | * Frequence the dpll for the port should run at. Differs from the |
| 359 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
| 360 | * already multiplied by pixel_multiplier. |
| 361 | */ |
| 362 | int port_clock; |
| 363 | |
| 364 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
| 365 | unsigned pixel_multiplier; |
| 366 | |
| 367 | /* Panel fitter controls for gen2-gen4 + VLV */ |
| 368 | struct { |
| 369 | u32 control; |
| 370 | u32 pgm_ratios; |
| 371 | u32 lvds_border_bits; |
| 372 | } gmch_pfit; |
| 373 | |
| 374 | /* Panel fitter placement and size for Ironlake+ */ |
| 375 | struct { |
| 376 | u32 pos; |
| 377 | u32 size; |
| 378 | bool enabled; |
| 379 | bool force_thru; |
| 380 | } pch_pfit; |
| 381 | |
| 382 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
| 383 | int fdi_lanes; |
| 384 | struct intel_link_m_n fdi_m_n; |
| 385 | |
| 386 | bool ips_enabled; |
| 387 | |
| 388 | bool double_wide; |
| 389 | |
| 390 | bool dp_encoder_is_mst; |
| 391 | int pbn; |
| 392 | }; |
| 393 | |
| 394 | struct intel_pipe_wm { |
| 395 | struct intel_wm_level wm[5]; |
| 396 | uint32_t linetime; |
| 397 | bool fbc_wm_enabled; |
| 398 | bool pipe_enabled; |
| 399 | bool sprites_enabled; |
| 400 | bool sprites_scaled; |
| 401 | }; |
| 402 | |
| 403 | struct intel_mmio_flip { |
| 404 | struct drm_i915_gem_request *req; |
| 405 | struct work_struct work; |
| 406 | }; |
| 407 | |
| 408 | struct skl_pipe_wm { |
| 409 | struct skl_wm_level wm[8]; |
| 410 | struct skl_wm_level trans_wm; |
| 411 | uint32_t linetime; |
| 412 | }; |
| 413 | |
| 414 | /* |
| 415 | * Tracking of operations that need to be performed at the beginning/end of an |
| 416 | * atomic commit, outside the atomic section where interrupts are disabled. |
| 417 | * These are generally operations that grab mutexes or might otherwise sleep |
| 418 | * and thus can't be run with interrupts disabled. |
| 419 | */ |
| 420 | struct intel_crtc_atomic_commit { |
| 421 | /* vblank evasion */ |
| 422 | bool evade; |
| 423 | unsigned start_vbl_count; |
| 424 | |
| 425 | /* Sleepable operations to perform before commit */ |
| 426 | bool wait_for_flips; |
| 427 | bool disable_fbc; |
| 428 | bool pre_disable_primary; |
| 429 | bool update_wm; |
| 430 | unsigned disabled_planes; |
| 431 | |
| 432 | /* Sleepable operations to perform after commit */ |
| 433 | unsigned fb_bits; |
| 434 | bool wait_vblank; |
| 435 | bool update_fbc; |
| 436 | bool post_enable_primary; |
| 437 | unsigned update_sprite_watermarks; |
| 438 | }; |
| 439 | |
| 440 | struct intel_crtc { |
| 441 | struct drm_crtc base; |
| 442 | enum pipe pipe; |
| 443 | enum plane plane; |
| 444 | u8 lut_r[256], lut_g[256], lut_b[256]; |
| 445 | /* |
| 446 | * Whether the crtc and the connected output pipeline is active. Implies |
| 447 | * that crtc->enabled is set, i.e. the current mode configuration has |
| 448 | * some outputs connected to this crtc. |
| 449 | */ |
| 450 | bool active; |
| 451 | unsigned long enabled_power_domains; |
| 452 | bool primary_enabled; /* is the primary plane (partially) visible? */ |
| 453 | bool lowfreq_avail; |
| 454 | struct intel_overlay *overlay; |
| 455 | struct intel_unpin_work *unpin_work; |
| 456 | |
| 457 | atomic_t unpin_work_count; |
| 458 | |
| 459 | /* Display surface base address adjustement for pageflips. Note that on |
| 460 | * gen4+ this only adjusts up to a tile, offsets within a tile are |
| 461 | * handled in the hw itself (with the TILEOFF register). */ |
| 462 | unsigned long dspaddr_offset; |
| 463 | |
| 464 | struct drm_i915_gem_object *cursor_bo; |
| 465 | uint32_t cursor_addr; |
| 466 | int16_t cursor_width, cursor_height; |
| 467 | uint32_t cursor_cntl; |
| 468 | uint32_t cursor_size; |
| 469 | uint32_t cursor_base; |
| 470 | |
| 471 | struct intel_plane_config plane_config; |
| 472 | struct intel_crtc_state config; |
| 473 | struct intel_crtc_state *new_config; |
| 474 | bool new_enabled; |
| 475 | |
| 476 | /* reset counter value when the last flip was submitted */ |
| 477 | unsigned int reset_counter; |
| 478 | |
| 479 | /* Access to these should be protected by dev_priv->irq_lock. */ |
| 480 | bool cpu_fifo_underrun_disabled; |
| 481 | bool pch_fifo_underrun_disabled; |
| 482 | |
| 483 | /* per-pipe watermark state */ |
| 484 | struct { |
| 485 | /* watermarks currently being used */ |
| 486 | struct intel_pipe_wm active; |
| 487 | /* SKL wm values currently in use */ |
| 488 | struct skl_pipe_wm skl_active; |
| 489 | } wm; |
| 490 | |
| 491 | int scanline_offset; |
| 492 | struct intel_mmio_flip mmio_flip; |
| 493 | |
| 494 | struct intel_crtc_atomic_commit atomic; |
| 495 | }; |
| 496 | |
| 497 | struct intel_plane_wm_parameters { |
| 498 | uint32_t horiz_pixels; |
| 499 | uint32_t vert_pixels; |
| 500 | uint8_t bytes_per_pixel; |
| 501 | bool enabled; |
| 502 | bool scaled; |
| 503 | }; |
| 504 | |
| 505 | struct intel_plane { |
| 506 | struct drm_plane base; |
| 507 | int plane; |
| 508 | enum pipe pipe; |
| 509 | struct drm_i915_gem_object *obj; |
| 510 | bool can_scale; |
| 511 | int max_downscale; |
| 512 | unsigned int rotation; |
| 513 | |
| 514 | /* Since we need to change the watermarks before/after |
| 515 | * enabling/disabling the planes, we need to store the parameters here |
| 516 | * as the other pieces of the struct may not reflect the values we want |
| 517 | * for the watermark calculations. Currently only Haswell uses this. |
| 518 | */ |
| 519 | struct intel_plane_wm_parameters wm; |
| 520 | |
| 521 | void (*update_plane)(struct drm_plane *plane, |
| 522 | struct drm_crtc *crtc, |
| 523 | struct drm_framebuffer *fb, |
| 524 | struct drm_i915_gem_object *obj, |
| 525 | int crtc_x, int crtc_y, |
| 526 | unsigned int crtc_w, unsigned int crtc_h, |
| 527 | uint32_t x, uint32_t y, |
| 528 | uint32_t src_w, uint32_t src_h); |
| 529 | void (*disable_plane)(struct drm_plane *plane, |
| 530 | struct drm_crtc *crtc); |
| 531 | int (*check_plane)(struct drm_plane *plane, |
| 532 | struct intel_plane_state *state); |
| 533 | void (*commit_plane)(struct drm_plane *plane, |
| 534 | struct intel_plane_state *state); |
| 535 | int (*update_colorkey)(struct drm_plane *plane, |
| 536 | struct drm_intel_sprite_colorkey *key); |
| 537 | void (*get_colorkey)(struct drm_plane *plane, |
| 538 | struct drm_intel_sprite_colorkey *key); |
| 539 | }; |
| 540 | |
| 541 | struct intel_watermark_params { |
| 542 | unsigned long fifo_size; |
| 543 | unsigned long max_wm; |
| 544 | unsigned long default_wm; |
| 545 | unsigned long guard_size; |
| 546 | unsigned long cacheline_size; |
| 547 | }; |
| 548 | |
| 549 | struct cxsr_latency { |
| 550 | int is_desktop; |
| 551 | int is_ddr3; |
| 552 | unsigned long fsb_freq; |
| 553 | unsigned long mem_freq; |
| 554 | unsigned long display_sr; |
| 555 | unsigned long display_hpll_disable; |
| 556 | unsigned long cursor_sr; |
| 557 | unsigned long cursor_hpll_disable; |
| 558 | }; |
| 559 | |
| 560 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
| 561 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
| 562 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
| 563 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
| 564 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
| 565 | #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base) |
| 566 | #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL) |
| 567 | |
| 568 | struct intel_hdmi { |
| 569 | u32 hdmi_reg; |
| 570 | int ddc_bus; |
| 571 | uint32_t color_range; |
| 572 | bool color_range_auto; |
| 573 | bool has_hdmi_sink; |
| 574 | bool has_audio; |
| 575 | enum hdmi_force_audio force_audio; |
| 576 | bool rgb_quant_range_selectable; |
| 577 | enum hdmi_picture_aspect aspect_ratio; |
| 578 | void (*write_infoframe)(struct drm_encoder *encoder, |
| 579 | enum hdmi_infoframe_type type, |
| 580 | const void *frame, ssize_t len); |
| 581 | void (*set_infoframes)(struct drm_encoder *encoder, |
| 582 | bool enable, |
| 583 | struct drm_display_mode *adjusted_mode); |
| 584 | bool (*infoframe_enabled)(struct drm_encoder *encoder); |
| 585 | }; |
| 586 | |
| 587 | struct intel_dp_mst_encoder; |
| 588 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
| 589 | |
| 590 | struct intel_dp { |
| 591 | uint32_t output_reg; |
| 592 | uint32_t aux_ch_ctl_reg; |
| 593 | uint32_t DP; |
| 594 | bool has_audio; |
| 595 | enum hdmi_force_audio force_audio; |
| 596 | uint32_t color_range; |
| 597 | bool color_range_auto; |
| 598 | uint8_t link_bw; |
| 599 | uint8_t lane_count; |
| 600 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
| 601 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
| 602 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
| 603 | struct drm_dp_aux aux; |
| 604 | uint8_t train_set[4]; |
| 605 | int panel_power_up_delay; |
| 606 | int panel_power_down_delay; |
| 607 | int panel_power_cycle_delay; |
| 608 | int backlight_on_delay; |
| 609 | int backlight_off_delay; |
| 610 | struct delayed_work panel_vdd_work; |
| 611 | bool want_panel_vdd; |
| 612 | unsigned long last_power_cycle; |
| 613 | unsigned long last_power_on; |
| 614 | unsigned long last_backlight_off; |
| 615 | |
| 616 | struct notifier_block edp_notifier; |
| 617 | |
| 618 | /* |
| 619 | * Pipe whose power sequencer is currently locked into |
| 620 | * this port. Only relevant on VLV/CHV. |
| 621 | */ |
| 622 | enum pipe pps_pipe; |
| 623 | struct edp_power_seq pps_delays; |
| 624 | |
| 625 | bool use_tps3; |
| 626 | bool can_mst; /* this port supports mst */ |
| 627 | bool is_mst; |
| 628 | int active_mst_links; |
| 629 | /* connector directly attached - won't be use for modeset in mst world */ |
| 630 | struct intel_connector *attached_connector; |
| 631 | |
| 632 | /* mst connector list */ |
| 633 | struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; |
| 634 | struct drm_dp_mst_topology_mgr mst_mgr; |
| 635 | |
| 636 | uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); |
| 637 | /* |
| 638 | * This function returns the value we have to program the AUX_CTL |
| 639 | * register with to kick off an AUX transaction. |
| 640 | */ |
| 641 | uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, |
| 642 | bool has_aux_irq, |
| 643 | int send_bytes, |
| 644 | uint32_t aux_clock_divider); |
| 645 | }; |
| 646 | |
| 647 | struct intel_digital_port { |
| 648 | struct intel_encoder base; |
| 649 | enum port port; |
| 650 | u32 saved_port_bits; |
| 651 | struct intel_dp dp; |
| 652 | struct intel_hdmi hdmi; |
| 653 | bool (*hpd_pulse)(struct intel_digital_port *, bool); |
| 654 | }; |
| 655 | |
| 656 | struct intel_dp_mst_encoder { |
| 657 | struct intel_encoder base; |
| 658 | enum pipe pipe; |
| 659 | struct intel_digital_port *primary; |
| 660 | void *port; /* store this opaque as its illegal to dereference it */ |
| 661 | }; |
| 662 | |
| 663 | static inline int |
| 664 | vlv_dport_to_channel(struct intel_digital_port *dport) |
| 665 | { |
| 666 | switch (dport->port) { |
| 667 | case PORT_B: |
| 668 | case PORT_D: |
| 669 | return DPIO_CH0; |
| 670 | case PORT_C: |
| 671 | return DPIO_CH1; |
| 672 | default: |
| 673 | BUG(); |
| 674 | } |
| 675 | } |
| 676 | |
| 677 | static inline int |
| 678 | vlv_pipe_to_channel(enum pipe pipe) |
| 679 | { |
| 680 | switch (pipe) { |
| 681 | case PIPE_A: |
| 682 | case PIPE_C: |
| 683 | return DPIO_CH0; |
| 684 | case PIPE_B: |
| 685 | return DPIO_CH1; |
| 686 | default: |
| 687 | BUG(); |
| 688 | } |
| 689 | } |
| 690 | |
| 691 | static inline struct drm_crtc * |
| 692 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) |
| 693 | { |
| 694 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 695 | return dev_priv->pipe_to_crtc_mapping[pipe]; |
| 696 | } |
| 697 | |
| 698 | static inline struct drm_crtc * |
| 699 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) |
| 700 | { |
| 701 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 702 | return dev_priv->plane_to_crtc_mapping[plane]; |
| 703 | } |
| 704 | |
| 705 | struct intel_unpin_work { |
| 706 | struct work_struct work; |
| 707 | struct drm_crtc *crtc; |
| 708 | struct drm_i915_gem_object *old_fb_obj; |
| 709 | struct drm_i915_gem_object *pending_flip_obj; |
| 710 | struct drm_pending_vblank_event *event; |
| 711 | atomic_t pending; |
| 712 | #define INTEL_FLIP_INACTIVE 0 |
| 713 | #define INTEL_FLIP_PENDING 1 |
| 714 | #define INTEL_FLIP_COMPLETE 2 |
| 715 | u32 flip_count; |
| 716 | u32 gtt_offset; |
| 717 | struct drm_i915_gem_request *flip_queued_req; |
| 718 | int flip_queued_vblank; |
| 719 | int flip_ready_vblank; |
| 720 | bool enable_stall_check; |
| 721 | }; |
| 722 | |
| 723 | struct intel_set_config { |
| 724 | struct drm_encoder **save_connector_encoders; |
| 725 | struct drm_crtc **save_encoder_crtcs; |
| 726 | bool *save_crtc_enabled; |
| 727 | |
| 728 | bool fb_changed; |
| 729 | bool mode_changed; |
| 730 | }; |
| 731 | |
| 732 | struct intel_load_detect_pipe { |
| 733 | struct drm_framebuffer *release_fb; |
| 734 | bool load_detect_temp; |
| 735 | int dpms_mode; |
| 736 | }; |
| 737 | |
| 738 | static inline struct intel_encoder * |
| 739 | intel_attached_encoder(struct drm_connector *connector) |
| 740 | { |
| 741 | return to_intel_connector(connector)->encoder; |
| 742 | } |
| 743 | |
| 744 | static inline struct intel_digital_port * |
| 745 | enc_to_dig_port(struct drm_encoder *encoder) |
| 746 | { |
| 747 | return container_of(encoder, struct intel_digital_port, base.base); |
| 748 | } |
| 749 | |
| 750 | static inline struct intel_dp_mst_encoder * |
| 751 | enc_to_mst(struct drm_encoder *encoder) |
| 752 | { |
| 753 | return container_of(encoder, struct intel_dp_mst_encoder, base.base); |
| 754 | } |
| 755 | |
| 756 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
| 757 | { |
| 758 | return &enc_to_dig_port(encoder)->dp; |
| 759 | } |
| 760 | |
| 761 | static inline struct intel_digital_port * |
| 762 | dp_to_dig_port(struct intel_dp *intel_dp) |
| 763 | { |
| 764 | return container_of(intel_dp, struct intel_digital_port, dp); |
| 765 | } |
| 766 | |
| 767 | static inline struct intel_digital_port * |
| 768 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) |
| 769 | { |
| 770 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); |
| 771 | } |
| 772 | |
| 773 | /* |
| 774 | * Returns the number of planes for this pipe, ie the number of sprites + 1 |
| 775 | * (primary plane). This doesn't count the cursor plane then. |
| 776 | */ |
| 777 | static inline unsigned int intel_num_planes(struct intel_crtc *crtc) |
| 778 | { |
| 779 | return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1; |
| 780 | } |
| 781 | |
| 782 | /* intel_fifo_underrun.c */ |
| 783 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
| 784 | enum pipe pipe, bool enable); |
| 785 | bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
| 786 | enum transcoder pch_transcoder, |
| 787 | bool enable); |
| 788 | void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
| 789 | enum pipe pipe); |
| 790 | void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
| 791 | enum transcoder pch_transcoder); |
| 792 | void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv); |
| 793 | |
| 794 | /* i915_irq.c */ |
| 795 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| 796 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| 797 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| 798 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| 799 | void gen6_reset_rps_interrupts(struct drm_device *dev); |
| 800 | void gen6_enable_rps_interrupts(struct drm_device *dev); |
| 801 | void gen6_disable_rps_interrupts(struct drm_device *dev); |
| 802 | u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask); |
| 803 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); |
| 804 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); |
| 805 | static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) |
| 806 | { |
| 807 | /* |
| 808 | * We only use drm_irq_uninstall() at unload and VT switch, so |
| 809 | * this is the only thing we need to check. |
| 810 | */ |
| 811 | return dev_priv->pm.irqs_enabled; |
| 812 | } |
| 813 | |
| 814 | int intel_get_crtc_scanline(struct intel_crtc *crtc); |
| 815 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv); |
| 816 | |
| 817 | /* intel_crt.c */ |
| 818 | void intel_crt_init(struct drm_device *dev); |
| 819 | |
| 820 | |
| 821 | /* intel_ddi.c */ |
| 822 | void intel_prepare_ddi(struct drm_device *dev); |
| 823 | void hsw_fdi_link_train(struct drm_crtc *crtc); |
| 824 | void intel_ddi_init(struct drm_device *dev, enum port port); |
| 825 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); |
| 826 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); |
| 827 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); |
| 828 | void intel_ddi_pll_init(struct drm_device *dev); |
| 829 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); |
| 830 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
| 831 | enum transcoder cpu_transcoder); |
| 832 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); |
| 833 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); |
| 834 | bool intel_ddi_pll_select(struct intel_crtc *crtc, |
| 835 | struct intel_crtc_state *crtc_state); |
| 836 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
| 837 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); |
| 838 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); |
| 839 | void intel_ddi_fdi_disable(struct drm_crtc *crtc); |
| 840 | void intel_ddi_get_config(struct intel_encoder *encoder, |
| 841 | struct intel_crtc_state *pipe_config); |
| 842 | |
| 843 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder); |
| 844 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
| 845 | struct intel_crtc_state *pipe_config); |
| 846 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state); |
| 847 | |
| 848 | /* intel_frontbuffer.c */ |
| 849 | void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, |
| 850 | struct intel_engine_cs *ring); |
| 851 | void intel_frontbuffer_flip_prepare(struct drm_device *dev, |
| 852 | unsigned frontbuffer_bits); |
| 853 | void intel_frontbuffer_flip_complete(struct drm_device *dev, |
| 854 | unsigned frontbuffer_bits); |
| 855 | void intel_frontbuffer_flush(struct drm_device *dev, |
| 856 | unsigned frontbuffer_bits); |
| 857 | /** |
| 858 | * intel_frontbuffer_flip - synchronous frontbuffer flip |
| 859 | * @dev: DRM device |
| 860 | * @frontbuffer_bits: frontbuffer plane tracking bits |
| 861 | * |
| 862 | * This function gets called after scheduling a flip on @obj. This is for |
| 863 | * synchronous plane updates which will happen on the next vblank and which will |
| 864 | * not get delayed by pending gpu rendering. |
| 865 | * |
| 866 | * Can be called without any locks held. |
| 867 | */ |
| 868 | static inline |
| 869 | void intel_frontbuffer_flip(struct drm_device *dev, |
| 870 | unsigned frontbuffer_bits) |
| 871 | { |
| 872 | intel_frontbuffer_flush(dev, frontbuffer_bits); |
| 873 | } |
| 874 | |
| 875 | void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire); |
| 876 | |
| 877 | |
| 878 | /* intel_audio.c */ |
| 879 | void intel_init_audio(struct drm_device *dev); |
| 880 | void intel_audio_codec_enable(struct intel_encoder *encoder); |
| 881 | void intel_audio_codec_disable(struct intel_encoder *encoder); |
| 882 | void i915_audio_component_init(struct drm_i915_private *dev_priv); |
| 883 | void i915_audio_component_cleanup(struct drm_i915_private *dev_priv); |
| 884 | |
| 885 | /* intel_display.c */ |
| 886 | bool intel_has_pending_fb_unpin(struct drm_device *dev); |
| 887 | int intel_pch_rawclk(struct drm_device *dev); |
| 888 | void intel_mark_busy(struct drm_device *dev); |
| 889 | void intel_mark_idle(struct drm_device *dev); |
| 890 | void intel_crtc_restore_mode(struct drm_crtc *crtc); |
| 891 | void intel_crtc_control(struct drm_crtc *crtc, bool enable); |
| 892 | void intel_crtc_update_dpms(struct drm_crtc *crtc); |
| 893 | void intel_encoder_destroy(struct drm_encoder *encoder); |
| 894 | void intel_connector_dpms(struct drm_connector *, int mode); |
| 895 | bool intel_connector_get_hw_state(struct intel_connector *connector); |
| 896 | void intel_modeset_check_state(struct drm_device *dev); |
| 897 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
| 898 | struct intel_digital_port *port); |
| 899 | void intel_connector_attach_encoder(struct intel_connector *connector, |
| 900 | struct intel_encoder *encoder); |
| 901 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector); |
| 902 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
| 903 | struct drm_crtc *crtc); |
| 904 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector); |
| 905 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
| 906 | struct drm_file *file_priv); |
| 907 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
| 908 | enum pipe pipe); |
| 909 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type); |
| 910 | static inline void |
| 911 | intel_wait_for_vblank(struct drm_device *dev, int pipe) |
| 912 | { |
| 913 | drm_wait_one_vblank(dev, pipe); |
| 914 | } |
| 915 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
| 916 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
| 917 | struct intel_digital_port *dport); |
| 918 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
| 919 | struct drm_display_mode *mode, |
| 920 | struct intel_load_detect_pipe *old, |
| 921 | struct drm_modeset_acquire_ctx *ctx); |
| 922 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
| 923 | struct intel_load_detect_pipe *old); |
| 924 | int intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
| 925 | struct drm_framebuffer *fb, |
| 926 | struct intel_engine_cs *pipelined); |
| 927 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); |
| 928 | struct drm_framebuffer * |
| 929 | __intel_framebuffer_create(struct drm_device *dev, |
| 930 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 931 | struct drm_i915_gem_object *obj); |
| 932 | void intel_prepare_page_flip(struct drm_device *dev, int plane); |
| 933 | void intel_finish_page_flip(struct drm_device *dev, int pipe); |
| 934 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane); |
| 935 | void intel_check_page_flip(struct drm_device *dev, int pipe); |
| 936 | int intel_prepare_plane_fb(struct drm_plane *plane, |
| 937 | struct drm_framebuffer *fb); |
| 938 | void intel_cleanup_plane_fb(struct drm_plane *plane, |
| 939 | struct drm_framebuffer *fb); |
| 940 | |
| 941 | /* shared dpll functions */ |
| 942 | struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); |
| 943 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
| 944 | struct intel_shared_dpll *pll, |
| 945 | bool state); |
| 946 | #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) |
| 947 | #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) |
| 948 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
| 949 | struct intel_crtc_state *state); |
| 950 | void intel_put_shared_dpll(struct intel_crtc *crtc); |
| 951 | |
| 952 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
| 953 | const struct dpll *dpll); |
| 954 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe); |
| 955 | |
| 956 | /* modesetting asserts */ |
| 957 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
| 958 | enum pipe pipe); |
| 959 | void assert_pll(struct drm_i915_private *dev_priv, |
| 960 | enum pipe pipe, bool state); |
| 961 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) |
| 962 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) |
| 963 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
| 964 | enum pipe pipe, bool state); |
| 965 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) |
| 966 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) |
| 967 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); |
| 968 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
| 969 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) |
| 970 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
| 971 | unsigned int tiling_mode, |
| 972 | unsigned int bpp, |
| 973 | unsigned int pitch); |
| 974 | void intel_prepare_reset(struct drm_device *dev); |
| 975 | void intel_finish_reset(struct drm_device *dev); |
| 976 | void hsw_enable_pc8(struct drm_i915_private *dev_priv); |
| 977 | void hsw_disable_pc8(struct drm_i915_private *dev_priv); |
| 978 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
| 979 | struct intel_crtc_state *pipe_config); |
| 980 | void intel_dp_set_m_n(struct intel_crtc *crtc); |
| 981 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
| 982 | void |
| 983 | ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
| 984 | int dotclock); |
| 985 | bool intel_crtc_active(struct drm_crtc *crtc); |
| 986 | void hsw_enable_ips(struct intel_crtc *crtc); |
| 987 | void hsw_disable_ips(struct intel_crtc *crtc); |
| 988 | enum intel_display_power_domain |
| 989 | intel_display_port_power_domain(struct intel_encoder *intel_encoder); |
| 990 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
| 991 | struct intel_crtc_state *pipe_config); |
| 992 | int intel_format_to_fourcc(int format); |
| 993 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); |
| 994 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file); |
| 995 | |
| 996 | /* intel_dp.c */ |
| 997 | void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); |
| 998 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
| 999 | struct intel_connector *intel_connector); |
| 1000 | void intel_dp_start_link_train(struct intel_dp *intel_dp); |
| 1001 | void intel_dp_complete_link_train(struct intel_dp *intel_dp); |
| 1002 | void intel_dp_stop_link_train(struct intel_dp *intel_dp); |
| 1003 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
| 1004 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
| 1005 | void intel_dp_check_link_status(struct intel_dp *intel_dp); |
| 1006 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); |
| 1007 | bool intel_dp_compute_config(struct intel_encoder *encoder, |
| 1008 | struct intel_crtc_state *pipe_config); |
| 1009 | bool intel_dp_is_edp(struct drm_device *dev, enum port port); |
| 1010 | bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, |
| 1011 | bool long_hpd); |
| 1012 | void intel_edp_backlight_on(struct intel_dp *intel_dp); |
| 1013 | void intel_edp_backlight_off(struct intel_dp *intel_dp); |
| 1014 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); |
| 1015 | void intel_edp_panel_on(struct intel_dp *intel_dp); |
| 1016 | void intel_edp_panel_off(struct intel_dp *intel_dp); |
| 1017 | void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector); |
| 1018 | void intel_dp_mst_suspend(struct drm_device *dev); |
| 1019 | void intel_dp_mst_resume(struct drm_device *dev); |
| 1020 | int intel_dp_max_link_bw(struct intel_dp *intel_dp); |
| 1021 | void intel_dp_hot_plug(struct intel_encoder *intel_encoder); |
| 1022 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv); |
| 1023 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes); |
| 1024 | void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes); |
| 1025 | int intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
| 1026 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, |
| 1027 | unsigned int crtc_w, unsigned int crtc_h, |
| 1028 | uint32_t src_x, uint32_t src_y, |
| 1029 | uint32_t src_w, uint32_t src_h); |
| 1030 | int intel_disable_plane(struct drm_plane *plane); |
| 1031 | void intel_plane_destroy(struct drm_plane *plane); |
| 1032 | |
| 1033 | /* intel_dp_mst.c */ |
| 1034 | int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); |
| 1035 | void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); |
| 1036 | /* intel_dsi.c */ |
| 1037 | void intel_dsi_init(struct drm_device *dev); |
| 1038 | |
| 1039 | |
| 1040 | /* intel_dvo.c */ |
| 1041 | void intel_dvo_init(struct drm_device *dev); |
| 1042 | |
| 1043 | |
| 1044 | /* legacy fbdev emulation in intel_fbdev.c */ |
| 1045 | #ifdef CONFIG_DRM_I915_FBDEV |
| 1046 | extern int intel_fbdev_init(struct drm_device *dev); |
| 1047 | extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie); |
| 1048 | extern void intel_fbdev_fini(struct drm_device *dev); |
| 1049 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); |
| 1050 | extern void intel_fbdev_output_poll_changed(struct drm_device *dev); |
| 1051 | extern void intel_fbdev_restore_mode(struct drm_device *dev); |
| 1052 | #else |
| 1053 | static inline int intel_fbdev_init(struct drm_device *dev) |
| 1054 | { |
| 1055 | return 0; |
| 1056 | } |
| 1057 | |
| 1058 | static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie) |
| 1059 | { |
| 1060 | } |
| 1061 | |
| 1062 | static inline void intel_fbdev_fini(struct drm_device *dev) |
| 1063 | { |
| 1064 | } |
| 1065 | |
| 1066 | static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) |
| 1067 | { |
| 1068 | } |
| 1069 | |
| 1070 | static inline void intel_fbdev_restore_mode(struct drm_device *dev) |
| 1071 | { |
| 1072 | } |
| 1073 | #endif |
| 1074 | |
| 1075 | /* intel_fbc.c */ |
| 1076 | bool intel_fbc_enabled(struct drm_device *dev); |
| 1077 | void intel_fbc_update(struct drm_device *dev); |
| 1078 | void intel_fbc_init(struct drm_i915_private *dev_priv); |
| 1079 | void intel_fbc_disable(struct drm_device *dev); |
| 1080 | void bdw_fbc_sw_flush(struct drm_device *dev, u32 value); |
| 1081 | |
| 1082 | /* intel_hdmi.c */ |
| 1083 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port); |
| 1084 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
| 1085 | struct intel_connector *intel_connector); |
| 1086 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
| 1087 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
| 1088 | struct intel_crtc_state *pipe_config); |
| 1089 | |
| 1090 | |
| 1091 | /* intel_lvds.c */ |
| 1092 | void intel_lvds_init(struct drm_device *dev); |
| 1093 | bool intel_is_dual_link_lvds(struct drm_device *dev); |
| 1094 | |
| 1095 | |
| 1096 | /* intel_modes.c */ |
| 1097 | int intel_connector_update_modes(struct drm_connector *connector, |
| 1098 | struct edid *edid); |
| 1099 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
| 1100 | void intel_attach_force_audio_property(struct drm_connector *connector); |
| 1101 | void intel_attach_broadcast_rgb_property(struct drm_connector *connector); |
| 1102 | |
| 1103 | |
| 1104 | /* intel_overlay.c */ |
| 1105 | void intel_setup_overlay(struct drm_device *dev); |
| 1106 | void intel_cleanup_overlay(struct drm_device *dev); |
| 1107 | int intel_overlay_switch_off(struct intel_overlay *overlay); |
| 1108 | int intel_overlay_put_image(struct drm_device *dev, void *data, |
| 1109 | struct drm_file *file_priv); |
| 1110 | int intel_overlay_attrs(struct drm_device *dev, void *data, |
| 1111 | struct drm_file *file_priv); |
| 1112 | void intel_overlay_reset(struct drm_i915_private *dev_priv); |
| 1113 | |
| 1114 | |
| 1115 | /* intel_panel.c */ |
| 1116 | int intel_panel_init(struct intel_panel *panel, |
| 1117 | struct drm_display_mode *fixed_mode, |
| 1118 | struct drm_display_mode *downclock_mode); |
| 1119 | void intel_panel_fini(struct intel_panel *panel); |
| 1120 | void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, |
| 1121 | struct drm_display_mode *adjusted_mode); |
| 1122 | void intel_pch_panel_fitting(struct intel_crtc *crtc, |
| 1123 | struct intel_crtc_state *pipe_config, |
| 1124 | int fitting_mode); |
| 1125 | void intel_gmch_panel_fitting(struct intel_crtc *crtc, |
| 1126 | struct intel_crtc_state *pipe_config, |
| 1127 | int fitting_mode); |
| 1128 | void intel_panel_set_backlight_acpi(struct intel_connector *connector, |
| 1129 | u32 level, u32 max); |
| 1130 | int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe); |
| 1131 | void intel_panel_enable_backlight(struct intel_connector *connector); |
| 1132 | void intel_panel_disable_backlight(struct intel_connector *connector); |
| 1133 | void intel_panel_destroy_backlight(struct drm_connector *connector); |
| 1134 | void intel_panel_init_backlight_funcs(struct drm_device *dev); |
| 1135 | enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
| 1136 | extern struct drm_display_mode *intel_find_panel_downclock( |
| 1137 | struct drm_device *dev, |
| 1138 | struct drm_display_mode *fixed_mode, |
| 1139 | struct drm_connector *connector); |
| 1140 | void intel_backlight_register(struct drm_device *dev); |
| 1141 | void intel_backlight_unregister(struct drm_device *dev); |
| 1142 | |
| 1143 | |
| 1144 | /* intel_psr.c */ |
| 1145 | void intel_psr_enable(struct intel_dp *intel_dp); |
| 1146 | void intel_psr_disable(struct intel_dp *intel_dp); |
| 1147 | void intel_psr_invalidate(struct drm_device *dev, |
| 1148 | unsigned frontbuffer_bits); |
| 1149 | void intel_psr_flush(struct drm_device *dev, |
| 1150 | unsigned frontbuffer_bits); |
| 1151 | void intel_psr_init(struct drm_device *dev); |
| 1152 | |
| 1153 | /* intel_runtime_pm.c */ |
| 1154 | int intel_power_domains_init(struct drm_i915_private *); |
| 1155 | void intel_power_domains_fini(struct drm_i915_private *); |
| 1156 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv); |
| 1157 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv); |
| 1158 | |
| 1159 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
| 1160 | enum intel_display_power_domain domain); |
| 1161 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
| 1162 | enum intel_display_power_domain domain); |
| 1163 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
| 1164 | enum intel_display_power_domain domain); |
| 1165 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
| 1166 | enum intel_display_power_domain domain); |
| 1167 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); |
| 1168 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); |
| 1169 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv); |
| 1170 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); |
| 1171 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv); |
| 1172 | |
| 1173 | void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); |
| 1174 | |
| 1175 | /* intel_pm.c */ |
| 1176 | void intel_init_clock_gating(struct drm_device *dev); |
| 1177 | void intel_suspend_hw(struct drm_device *dev); |
| 1178 | int ilk_wm_max_level(const struct drm_device *dev); |
| 1179 | void intel_update_watermarks(struct drm_crtc *crtc); |
| 1180 | void intel_update_sprite_watermarks(struct drm_plane *plane, |
| 1181 | struct drm_crtc *crtc, |
| 1182 | uint32_t sprite_width, |
| 1183 | uint32_t sprite_height, |
| 1184 | int pixel_size, |
| 1185 | bool enabled, bool scaled); |
| 1186 | void intel_init_pm(struct drm_device *dev); |
| 1187 | void intel_pm_setup(struct drm_device *dev); |
| 1188 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
| 1189 | void intel_gpu_ips_teardown(void); |
| 1190 | void intel_init_gt_powersave(struct drm_device *dev); |
| 1191 | void intel_cleanup_gt_powersave(struct drm_device *dev); |
| 1192 | void intel_enable_gt_powersave(struct drm_device *dev); |
| 1193 | void intel_disable_gt_powersave(struct drm_device *dev); |
| 1194 | void intel_suspend_gt_powersave(struct drm_device *dev); |
| 1195 | void intel_reset_gt_powersave(struct drm_device *dev); |
| 1196 | void ironlake_teardown_rc6(struct drm_device *dev); |
| 1197 | void gen6_update_ring_freq(struct drm_device *dev); |
| 1198 | void gen6_rps_idle(struct drm_i915_private *dev_priv); |
| 1199 | void gen6_rps_boost(struct drm_i915_private *dev_priv); |
| 1200 | void ilk_wm_get_hw_state(struct drm_device *dev); |
| 1201 | void skl_wm_get_hw_state(struct drm_device *dev); |
| 1202 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
| 1203 | struct skl_ddb_allocation *ddb /* out */); |
| 1204 | |
| 1205 | |
| 1206 | /* intel_sdvo.c */ |
| 1207 | bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); |
| 1208 | |
| 1209 | |
| 1210 | /* intel_sprite.c */ |
| 1211 | int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
| 1212 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
| 1213 | enum plane plane); |
| 1214 | int intel_plane_set_property(struct drm_plane *plane, |
| 1215 | struct drm_property *prop, |
| 1216 | uint64_t val); |
| 1217 | int intel_plane_restore(struct drm_plane *plane); |
| 1218 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
| 1219 | struct drm_file *file_priv); |
| 1220 | int intel_sprite_get_colorkey(struct drm_device *dev, void *data, |
| 1221 | struct drm_file *file_priv); |
| 1222 | bool intel_pipe_update_start(struct intel_crtc *crtc, |
| 1223 | uint32_t *start_vbl_count); |
| 1224 | void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count); |
| 1225 | void intel_post_enable_primary(struct drm_crtc *crtc); |
| 1226 | void intel_pre_disable_primary(struct drm_crtc *crtc); |
| 1227 | |
| 1228 | /* intel_tv.c */ |
| 1229 | void intel_tv_init(struct drm_device *dev); |
| 1230 | |
| 1231 | /* intel_atomic.c */ |
| 1232 | struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane); |
| 1233 | void intel_plane_destroy_state(struct drm_plane *plane, |
| 1234 | struct drm_plane_state *state); |
| 1235 | extern const struct drm_plane_helper_funcs intel_plane_helper_funcs; |
| 1236 | |
| 1237 | #endif /* __INTEL_DRV_H__ */ |