| | 1 | /* |
| | 2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> |
| | 3 | * Copyright (c) 2007-2008 Intel Corporation |
| | 4 | * Jesse Barnes <jesse.barnes@intel.com> |
| | 5 | * |
| | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| | 7 | * copy of this software and associated documentation files (the "Software"), |
| | 8 | * to deal in the Software without restriction, including without limitation |
| | 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| | 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| | 11 | * Software is furnished to do so, subject to the following conditions: |
| | 12 | * |
| | 13 | * The above copyright notice and this permission notice (including the next |
| | 14 | * paragraph) shall be included in all copies or substantial portions of the |
| | 15 | * Software. |
| | 16 | * |
| | 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| | 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| | 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| | 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| | 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| | 22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| | 23 | * IN THE SOFTWARE. |
| | 24 | */ |
| | 25 | #ifndef __INTEL_DRV_H__ |
| | 26 | #define __INTEL_DRV_H__ |
| | 27 | |
| | 28 | #include <linux/i2c.h> |
| | 29 | #include <drm/i915_drm.h> |
| | 30 | #include "i915_drv.h" |
| | 31 | #include <drm/drm_crtc.h> |
| | 32 | #include <drm/drm_crtc_helper.h> |
| | 33 | #include <drm/drm_fb_helper.h> |
| | 34 | #include <drm/drm_dp_helper.h> |
| | 35 | |
| | 36 | /** |
| | 37 | * _wait_for - magic (register) wait macro |
| | 38 | * |
| | 39 | * Does the right thing for modeset paths when run under kdgb or similar atomic |
| | 40 | * contexts. Note that it's important that we check the condition again after |
| | 41 | * having timed out, since the timeout could be due to preemption or similar and |
| | 42 | * we've never had a chance to check the condition before the timeout. |
| | 43 | */ |
| | 44 | #define _wait_for(COND, MS, W) ({ \ |
| | 45 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ |
| | 46 | int ret__ = 0; \ |
| | 47 | while (!(COND)) { \ |
| | 48 | if (time_after(jiffies, timeout__)) { \ |
| | 49 | if (!(COND)) \ |
| | 50 | ret__ = -ETIMEDOUT; \ |
| | 51 | break; \ |
| | 52 | } \ |
| | 53 | if (W && drm_can_sleep()) { \ |
| | 54 | msleep(W); \ |
| | 55 | } else { \ |
| | 56 | cpu_relax(); \ |
| | 57 | } \ |
| | 58 | } \ |
| | 59 | ret__; \ |
| | 60 | }) |
| | 61 | |
| | 62 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
| | 63 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) |
| | 64 | #define wait_for_atomic_us(COND, US) _wait_for((COND), \ |
| | 65 | DIV_ROUND_UP((US), 1000), 0) |
| | 66 | |
| | 67 | #define KHz(x) (1000*x) |
| | 68 | #define MHz(x) KHz(1000*x) |
| | 69 | |
| | 70 | /* |
| | 71 | * Display related stuff |
| | 72 | */ |
| | 73 | |
| | 74 | /* store information about an Ixxx DVO */ |
| | 75 | /* The i830->i865 use multiple DVOs with multiple i2cs */ |
| | 76 | /* the i915, i945 have a single sDVO i2c bus - which is different */ |
| | 77 | #define MAX_OUTPUTS 6 |
| | 78 | /* maximum connectors per crtcs in the mode set */ |
| | 79 | #define INTELFB_CONN_LIMIT 4 |
| | 80 | |
| | 81 | #define INTEL_I2C_BUS_DVO 1 |
| | 82 | #define INTEL_I2C_BUS_SDVO 2 |
| | 83 | |
| | 84 | /* these are outputs from the chip - integrated only |
| | 85 | external chips are via DVO or SDVO output */ |
| | 86 | #define INTEL_OUTPUT_UNUSED 0 |
| | 87 | #define INTEL_OUTPUT_ANALOG 1 |
| | 88 | #define INTEL_OUTPUT_DVO 2 |
| | 89 | #define INTEL_OUTPUT_SDVO 3 |
| | 90 | #define INTEL_OUTPUT_LVDS 4 |
| | 91 | #define INTEL_OUTPUT_TVOUT 5 |
| | 92 | #define INTEL_OUTPUT_HDMI 6 |
| | 93 | #define INTEL_OUTPUT_DISPLAYPORT 7 |
| | 94 | #define INTEL_OUTPUT_EDP 8 |
| | 95 | #define INTEL_OUTPUT_UNKNOWN 9 |
| | 96 | |
| | 97 | #define INTEL_DVO_CHIP_NONE 0 |
| | 98 | #define INTEL_DVO_CHIP_LVDS 1 |
| | 99 | #define INTEL_DVO_CHIP_TMDS 2 |
| | 100 | #define INTEL_DVO_CHIP_TVOUT 4 |
| | 101 | |
| | 102 | struct intel_framebuffer { |
| | 103 | struct drm_framebuffer base; |
| | 104 | struct drm_i915_gem_object *obj; |
| | 105 | }; |
| | 106 | |
| | 107 | struct intel_fbdev { |
| | 108 | struct drm_fb_helper helper; |
| | 109 | struct intel_framebuffer ifb; |
| | 110 | struct list_head fbdev_list; |
| | 111 | struct drm_display_mode *our_mode; |
| | 112 | }; |
| | 113 | |
| | 114 | struct intel_encoder { |
| | 115 | struct drm_encoder base; |
| | 116 | /* |
| | 117 | * The new crtc this encoder will be driven from. Only differs from |
| | 118 | * base->crtc while a modeset is in progress. |
| | 119 | */ |
| | 120 | struct intel_crtc *new_crtc; |
| | 121 | |
| | 122 | int type; |
| | 123 | bool needs_tv_clock; |
| | 124 | /* |
| | 125 | * Intel hw has only one MUX where encoders could be clone, hence a |
| | 126 | * simple flag is enough to compute the possible_clones mask. |
| | 127 | */ |
| | 128 | bool cloneable; |
| | 129 | bool connectors_active; |
| | 130 | void (*hot_plug)(struct intel_encoder *); |
| | 131 | bool (*compute_config)(struct intel_encoder *, |
| | 132 | struct intel_crtc_config *); |
| | 133 | void (*pre_pll_enable)(struct intel_encoder *); |
| | 134 | void (*pre_enable)(struct intel_encoder *); |
| | 135 | void (*enable)(struct intel_encoder *); |
| | 136 | void (*mode_set)(struct intel_encoder *intel_encoder); |
| | 137 | void (*disable)(struct intel_encoder *); |
| | 138 | void (*post_disable)(struct intel_encoder *); |
| | 139 | /* Read out the current hw state of this connector, returning true if |
| | 140 | * the encoder is active. If the encoder is enabled it also set the pipe |
| | 141 | * it is connected to in the pipe parameter. */ |
| | 142 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); |
| | 143 | int crtc_mask; |
| | 144 | enum hpd_pin hpd_pin; |
| | 145 | }; |
| | 146 | |
| | 147 | struct intel_panel { |
| | 148 | struct drm_display_mode *fixed_mode; |
| | 149 | int fitting_mode; |
| | 150 | }; |
| | 151 | |
| | 152 | struct intel_connector { |
| | 153 | struct drm_connector base; |
| | 154 | /* |
| | 155 | * The fixed encoder this connector is connected to. |
| | 156 | */ |
| | 157 | struct intel_encoder *encoder; |
| | 158 | |
| | 159 | /* |
| | 160 | * The new encoder this connector will be driven. Only differs from |
| | 161 | * encoder while a modeset is in progress. |
| | 162 | */ |
| | 163 | struct intel_encoder *new_encoder; |
| | 164 | |
| | 165 | /* Reads out the current hw, returning true if the connector is enabled |
| | 166 | * and active (i.e. dpms ON state). */ |
| | 167 | bool (*get_hw_state)(struct intel_connector *); |
| | 168 | |
| | 169 | /* Panel info for eDP and LVDS */ |
| | 170 | struct intel_panel panel; |
| | 171 | |
| | 172 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ |
| | 173 | struct edid *edid; |
| | 174 | |
| | 175 | /* since POLL and HPD connectors may use the same HPD line keep the native |
| | 176 | state of connector->polled in case hotplug storm detection changes it */ |
| | 177 | u8 polled; |
| | 178 | }; |
| | 179 | |
| | 180 | typedef struct dpll { |
| | 181 | /* given values */ |
| | 182 | int n; |
| | 183 | int m1, m2; |
| | 184 | int p1, p2; |
| | 185 | /* derived values */ |
| | 186 | int dot; |
| | 187 | int vco; |
| | 188 | int m; |
| | 189 | int p; |
| | 190 | } intel_clock_t; |
| | 191 | |
| | 192 | struct intel_crtc_config { |
| | 193 | struct drm_display_mode requested_mode; |
| | 194 | struct drm_display_mode adjusted_mode; |
| | 195 | /* This flag must be set by the encoder's compute_config callback if it |
| | 196 | * changes the crtc timings in the mode to prevent the crtc fixup from |
| | 197 | * overwriting them. Currently only lvds needs that. */ |
| | 198 | bool timings_set; |
| | 199 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
| | 200 | * between pch encoders and cpu encoders. */ |
| | 201 | bool has_pch_encoder; |
| | 202 | |
| | 203 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
| | 204 | * pipe on Haswell (where we have a special eDP transcoder). */ |
| | 205 | enum transcoder cpu_transcoder; |
| | 206 | |
| | 207 | /* |
| | 208 | * Use reduced/limited/broadcast rbg range, compressing from the full |
| | 209 | * range fed into the crtcs. |
| | 210 | */ |
| | 211 | bool limited_color_range; |
| | 212 | |
| | 213 | /* DP has a bunch of special case unfortunately, so mark the pipe |
| | 214 | * accordingly. */ |
| | 215 | bool has_dp_encoder; |
| | 216 | |
| | 217 | /* |
| | 218 | * Enable dithering, used when the selected pipe bpp doesn't match the |
| | 219 | * plane bpp. |
| | 220 | */ |
| | 221 | bool dither; |
| | 222 | |
| | 223 | /* Controls for the clock computation, to override various stages. */ |
| | 224 | bool clock_set; |
| | 225 | |
| | 226 | /* |
| | 227 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really |
| | 228 | * required. This is set in the 2nd loop of calling encoder's |
| | 229 | * ->compute_config if the first pick doesn't work out. |
| | 230 | */ |
| | 231 | bool bw_constrained; |
| | 232 | |
| | 233 | /* Settings for the intel dpll used on pretty much everything but |
| | 234 | * haswell. */ |
| | 235 | struct dpll dpll; |
| | 236 | |
| | 237 | int pipe_bpp; |
| | 238 | struct intel_link_m_n dp_m_n; |
| | 239 | /** |
| | 240 | * This is currently used by DP and HDMI encoders since those can have a |
| | 241 | * target pixel clock != the port link clock (which is currently stored |
| | 242 | * in adjusted_mode->clock). |
| | 243 | */ |
| | 244 | int pixel_target_clock; |
| | 245 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
| | 246 | unsigned pixel_multiplier; |
| | 247 | |
| | 248 | /* Panel fitter controls for gen2-gen4 + VLV */ |
| | 249 | struct { |
| | 250 | u32 control; |
| | 251 | u32 pgm_ratios; |
| | 252 | u32 lvds_border_bits; |
| | 253 | } gmch_pfit; |
| | 254 | |
| | 255 | /* Panel fitter placement and size for Ironlake+ */ |
| | 256 | struct { |
| | 257 | u32 pos; |
| | 258 | u32 size; |
| | 259 | } pch_pfit; |
| | 260 | |
| | 261 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
| | 262 | int fdi_lanes; |
| | 263 | struct intel_link_m_n fdi_m_n; |
| | 264 | }; |
| | 265 | |
| | 266 | struct intel_crtc { |
| | 267 | struct drm_crtc base; |
| | 268 | enum pipe pipe; |
| | 269 | enum plane plane; |
| | 270 | u8 lut_r[256], lut_g[256], lut_b[256]; |
| | 271 | /* |
| | 272 | * Whether the crtc and the connected output pipeline is active. Implies |
| | 273 | * that crtc->enabled is set, i.e. the current mode configuration has |
| | 274 | * some outputs connected to this crtc. |
| | 275 | */ |
| | 276 | bool active; |
| | 277 | bool eld_vld; |
| | 278 | bool primary_disabled; /* is the crtc obscured by a plane? */ |
| | 279 | bool lowfreq_avail; |
| | 280 | struct intel_overlay *overlay; |
| | 281 | struct intel_unpin_work *unpin_work; |
| | 282 | |
| | 283 | atomic_t unpin_work_count; |
| | 284 | |
| | 285 | /* Display surface base address adjustement for pageflips. Note that on |
| | 286 | * gen4+ this only adjusts up to a tile, offsets within a tile are |
| | 287 | * handled in the hw itself (with the TILEOFF register). */ |
| | 288 | unsigned long dspaddr_offset; |
| | 289 | |
| | 290 | struct drm_i915_gem_object *cursor_bo; |
| | 291 | uint32_t cursor_addr; |
| | 292 | int16_t cursor_x, cursor_y; |
| | 293 | int16_t cursor_width, cursor_height; |
| | 294 | bool cursor_visible; |
| | 295 | |
| | 296 | struct intel_crtc_config config; |
| | 297 | |
| | 298 | /* We can share PLLs across outputs if the timings match */ |
| | 299 | struct intel_pch_pll *pch_pll; |
| | 300 | uint32_t ddi_pll_sel; |
| | 301 | |
| | 302 | /* reset counter value when the last flip was submitted */ |
| | 303 | unsigned int reset_counter; |
| | 304 | |
| | 305 | /* Access to these should be protected by dev_priv->irq_lock. */ |
| | 306 | bool cpu_fifo_underrun_disabled; |
| | 307 | bool pch_fifo_underrun_disabled; |
| | 308 | }; |
| | 309 | |
| | 310 | struct intel_plane { |
| | 311 | struct drm_plane base; |
| | 312 | int plane; |
| | 313 | enum pipe pipe; |
| | 314 | struct drm_i915_gem_object *obj; |
| | 315 | bool can_scale; |
| | 316 | int max_downscale; |
| | 317 | u32 lut_r[1024], lut_g[1024], lut_b[1024]; |
| | 318 | int crtc_x, crtc_y; |
| | 319 | unsigned int crtc_w, crtc_h; |
| | 320 | uint32_t src_x, src_y; |
| | 321 | uint32_t src_w, src_h; |
| | 322 | void (*update_plane)(struct drm_plane *plane, |
| | 323 | struct drm_framebuffer *fb, |
| | 324 | struct drm_i915_gem_object *obj, |
| | 325 | int crtc_x, int crtc_y, |
| | 326 | unsigned int crtc_w, unsigned int crtc_h, |
| | 327 | uint32_t x, uint32_t y, |
| | 328 | uint32_t src_w, uint32_t src_h); |
| | 329 | void (*disable_plane)(struct drm_plane *plane); |
| | 330 | int (*update_colorkey)(struct drm_plane *plane, |
| | 331 | struct drm_intel_sprite_colorkey *key); |
| | 332 | void (*get_colorkey)(struct drm_plane *plane, |
| | 333 | struct drm_intel_sprite_colorkey *key); |
| | 334 | }; |
| | 335 | |
| | 336 | struct intel_watermark_params { |
| | 337 | unsigned long fifo_size; |
| | 338 | unsigned long max_wm; |
| | 339 | unsigned long default_wm; |
| | 340 | unsigned long guard_size; |
| | 341 | unsigned long cacheline_size; |
| | 342 | }; |
| | 343 | |
| | 344 | struct cxsr_latency { |
| | 345 | int is_desktop; |
| | 346 | int is_ddr3; |
| | 347 | unsigned long fsb_freq; |
| | 348 | unsigned long mem_freq; |
| | 349 | unsigned long display_sr; |
| | 350 | unsigned long display_hpll_disable; |
| | 351 | unsigned long cursor_sr; |
| | 352 | unsigned long cursor_hpll_disable; |
| | 353 | }; |
| | 354 | |
| | 355 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
| | 356 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
| | 357 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
| | 358 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
| | 359 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
| | 360 | |
| | 361 | #define DIP_HEADER_SIZE 5 |
| | 362 | |
| | 363 | #define DIP_TYPE_AVI 0x82 |
| | 364 | #define DIP_VERSION_AVI 0x2 |
| | 365 | #define DIP_LEN_AVI 13 |
| | 366 | #define DIP_AVI_PR_1 0 |
| | 367 | #define DIP_AVI_PR_2 1 |
| | 368 | #define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2) |
| | 369 | #define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2) |
| | 370 | #define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2) |
| | 371 | |
| | 372 | #define DIP_TYPE_SPD 0x83 |
| | 373 | #define DIP_VERSION_SPD 0x1 |
| | 374 | #define DIP_LEN_SPD 25 |
| | 375 | #define DIP_SPD_UNKNOWN 0 |
| | 376 | #define DIP_SPD_DSTB 0x1 |
| | 377 | #define DIP_SPD_DVDP 0x2 |
| | 378 | #define DIP_SPD_DVHS 0x3 |
| | 379 | #define DIP_SPD_HDDVR 0x4 |
| | 380 | #define DIP_SPD_DVC 0x5 |
| | 381 | #define DIP_SPD_DSC 0x6 |
| | 382 | #define DIP_SPD_VCD 0x7 |
| | 383 | #define DIP_SPD_GAME 0x8 |
| | 384 | #define DIP_SPD_PC 0x9 |
| | 385 | #define DIP_SPD_BD 0xa |
| | 386 | #define DIP_SPD_SCD 0xb |
| | 387 | |
| | 388 | struct dip_infoframe { |
| | 389 | uint8_t type; /* HB0 */ |
| | 390 | uint8_t ver; /* HB1 */ |
| | 391 | uint8_t len; /* HB2 - body len, not including checksum */ |
| | 392 | uint8_t ecc; /* Header ECC */ |
| | 393 | uint8_t checksum; /* PB0 */ |
| | 394 | union { |
| | 395 | struct { |
| | 396 | /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */ |
| | 397 | uint8_t Y_A_B_S; |
| | 398 | /* PB2 - C 7:6, M 5:4, R 3:0 */ |
| | 399 | uint8_t C_M_R; |
| | 400 | /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */ |
| | 401 | uint8_t ITC_EC_Q_SC; |
| | 402 | /* PB4 - VIC 6:0 */ |
| | 403 | uint8_t VIC; |
| | 404 | /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */ |
| | 405 | uint8_t YQ_CN_PR; |
| | 406 | /* PB6 to PB13 */ |
| | 407 | uint16_t top_bar_end; |
| | 408 | uint16_t bottom_bar_start; |
| | 409 | uint16_t left_bar_end; |
| | 410 | uint16_t right_bar_start; |
| | 411 | } __attribute__ ((packed)) avi; |
| | 412 | struct { |
| | 413 | uint8_t vn[8]; |
| | 414 | uint8_t pd[16]; |
| | 415 | uint8_t sdi; |
| | 416 | } __attribute__ ((packed)) spd; |
| | 417 | uint8_t payload[27]; |
| | 418 | } __attribute__ ((packed)) body; |
| | 419 | } __attribute__((packed)); |
| | 420 | |
| | 421 | struct intel_hdmi { |
| | 422 | u32 hdmi_reg; |
| | 423 | int ddc_bus; |
| | 424 | uint32_t color_range; |
| | 425 | bool color_range_auto; |
| | 426 | bool has_hdmi_sink; |
| | 427 | bool has_audio; |
| | 428 | enum hdmi_force_audio force_audio; |
| | 429 | bool rgb_quant_range_selectable; |
| | 430 | void (*write_infoframe)(struct drm_encoder *encoder, |
| | 431 | struct dip_infoframe *frame); |
| | 432 | void (*set_infoframes)(struct drm_encoder *encoder, |
| | 433 | struct drm_display_mode *adjusted_mode); |
| | 434 | }; |
| | 435 | |
| | 436 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
| | 437 | #define DP_LINK_CONFIGURATION_SIZE 9 |
| | 438 | |
| | 439 | struct intel_dp { |
| | 440 | uint32_t output_reg; |
| | 441 | uint32_t aux_ch_ctl_reg; |
| | 442 | uint32_t DP; |
| | 443 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; |
| | 444 | bool has_audio; |
| | 445 | enum hdmi_force_audio force_audio; |
| | 446 | uint32_t color_range; |
| | 447 | bool color_range_auto; |
| | 448 | uint8_t link_bw; |
| | 449 | uint8_t lane_count; |
| | 450 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
| | 451 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
| | 452 | struct i2c_adapter adapter; |
| | 453 | struct i2c_algo_dp_aux_data algo; |
| | 454 | bool is_pch_edp; |
| | 455 | uint8_t train_set[4]; |
| | 456 | int panel_power_up_delay; |
| | 457 | int panel_power_down_delay; |
| | 458 | int panel_power_cycle_delay; |
| | 459 | int backlight_on_delay; |
| | 460 | int backlight_off_delay; |
| | 461 | struct delayed_work panel_vdd_work; |
| | 462 | bool want_panel_vdd; |
| | 463 | struct intel_connector *attached_connector; |
| | 464 | }; |
| | 465 | |
| | 466 | struct intel_digital_port { |
| | 467 | struct intel_encoder base; |
| | 468 | enum port port; |
| | 469 | u32 port_reversal; |
| | 470 | struct intel_dp dp; |
| | 471 | struct intel_hdmi hdmi; |
| | 472 | }; |
| | 473 | |
| | 474 | static inline int |
| | 475 | vlv_dport_to_channel(struct intel_digital_port *dport) |
| | 476 | { |
| | 477 | switch (dport->port) { |
| | 478 | case PORT_B: |
| | 479 | return 0; |
| | 480 | case PORT_C: |
| | 481 | return 1; |
| | 482 | default: |
| | 483 | BUG(); |
| | 484 | } |
| | 485 | } |
| | 486 | |
| | 487 | static inline struct drm_crtc * |
| | 488 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) |
| | 489 | { |
| | 490 | struct drm_i915_private *dev_priv = dev->dev_private; |
| | 491 | return dev_priv->pipe_to_crtc_mapping[pipe]; |
| | 492 | } |
| | 493 | |
| | 494 | static inline struct drm_crtc * |
| | 495 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) |
| | 496 | { |
| | 497 | struct drm_i915_private *dev_priv = dev->dev_private; |
| | 498 | return dev_priv->plane_to_crtc_mapping[plane]; |
| | 499 | } |
| | 500 | |
| | 501 | struct intel_unpin_work { |
| | 502 | struct work_struct work; |
| | 503 | struct drm_crtc *crtc; |
| | 504 | struct drm_i915_gem_object *old_fb_obj; |
| | 505 | struct drm_i915_gem_object *pending_flip_obj; |
| | 506 | struct drm_pending_vblank_event *event; |
| | 507 | atomic_t pending; |
| | 508 | #define INTEL_FLIP_INACTIVE 0 |
| | 509 | #define INTEL_FLIP_PENDING 1 |
| | 510 | #define INTEL_FLIP_COMPLETE 2 |
| | 511 | bool enable_stall_check; |
| | 512 | }; |
| | 513 | |
| | 514 | struct intel_fbc_work { |
| | 515 | struct delayed_work work; |
| | 516 | struct drm_crtc *crtc; |
| | 517 | struct drm_framebuffer *fb; |
| | 518 | int interval; |
| | 519 | }; |
| | 520 | |
| | 521 | int intel_pch_rawclk(struct drm_device *dev); |
| | 522 | |
| | 523 | int intel_connector_update_modes(struct drm_connector *connector, |
| | 524 | struct edid *edid); |
| | 525 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
| | 526 | |
| | 527 | extern void intel_attach_force_audio_property(struct drm_connector *connector); |
| | 528 | extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector); |
| | 529 | |
| | 530 | extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
| | 531 | extern void intel_crt_init(struct drm_device *dev); |
| | 532 | extern void intel_hdmi_init(struct drm_device *dev, |
| | 533 | int hdmi_reg, enum port port); |
| | 534 | extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
| | 535 | struct intel_connector *intel_connector); |
| | 536 | extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
| | 537 | extern bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
| | 538 | struct intel_crtc_config *pipe_config); |
| | 539 | extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if); |
| | 540 | extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, |
| | 541 | bool is_sdvob); |
| | 542 | extern void intel_dvo_init(struct drm_device *dev); |
| | 543 | extern void intel_tv_init(struct drm_device *dev); |
| | 544 | extern void intel_mark_busy(struct drm_device *dev); |
| | 545 | extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj); |
| | 546 | extern void intel_mark_idle(struct drm_device *dev); |
| | 547 | extern bool intel_lvds_init(struct drm_device *dev); |
| | 548 | extern bool intel_is_dual_link_lvds(struct drm_device *dev); |
| | 549 | extern void intel_dp_init(struct drm_device *dev, int output_reg, |
| | 550 | enum port port); |
| | 551 | extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
| | 552 | struct intel_connector *intel_connector); |
| | 553 | extern void intel_dp_init_link_config(struct intel_dp *intel_dp); |
| | 554 | extern void intel_dp_start_link_train(struct intel_dp *intel_dp); |
| | 555 | extern void intel_dp_complete_link_train(struct intel_dp *intel_dp); |
| | 556 | extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
| | 557 | extern void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
| | 558 | extern void intel_dp_check_link_status(struct intel_dp *intel_dp); |
| | 559 | extern bool intel_dp_compute_config(struct intel_encoder *encoder, |
| | 560 | struct intel_crtc_config *pipe_config); |
| | 561 | extern bool intel_dpd_is_edp(struct drm_device *dev); |
| | 562 | extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp); |
| | 563 | extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp); |
| | 564 | extern void ironlake_edp_panel_on(struct intel_dp *intel_dp); |
| | 565 | extern void ironlake_edp_panel_off(struct intel_dp *intel_dp); |
| | 566 | extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); |
| | 567 | extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
| | 568 | extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder); |
| | 569 | extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
| | 570 | extern void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
| | 571 | enum plane plane); |
| | 572 | |
| | 573 | /* intel_panel.c */ |
| | 574 | extern int intel_panel_init(struct intel_panel *panel, |
| | 575 | struct drm_display_mode *fixed_mode); |
| | 576 | extern void intel_panel_fini(struct intel_panel *panel); |
| | 577 | |
| | 578 | extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, |
| | 579 | struct drm_display_mode *adjusted_mode); |
| | 580 | extern void intel_pch_panel_fitting(struct intel_crtc *crtc, |
| | 581 | struct intel_crtc_config *pipe_config, |
| | 582 | int fitting_mode); |
| | 583 | extern void intel_gmch_panel_fitting(struct intel_crtc *crtc, |
| | 584 | struct intel_crtc_config *pipe_config, |
| | 585 | int fitting_mode); |
| | 586 | extern void intel_panel_set_backlight(struct drm_device *dev, |
| | 587 | u32 level, u32 max); |
| | 588 | extern int intel_panel_setup_backlight(struct drm_connector *connector); |
| | 589 | extern void intel_panel_enable_backlight(struct drm_device *dev, |
| | 590 | enum pipe pipe); |
| | 591 | extern void intel_panel_disable_backlight(struct drm_device *dev); |
| | 592 | extern void intel_panel_destroy_backlight(struct drm_device *dev); |
| | 593 | extern enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
| | 594 | |
| | 595 | struct intel_set_config { |
| | 596 | struct drm_encoder **save_connector_encoders; |
| | 597 | struct drm_crtc **save_encoder_crtcs; |
| | 598 | |
| | 599 | bool fb_changed; |
| | 600 | bool mode_changed; |
| | 601 | }; |
| | 602 | |
| | 603 | extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
| | 604 | int x, int y, struct drm_framebuffer *old_fb); |
| | 605 | extern void intel_modeset_disable(struct drm_device *dev); |
| | 606 | extern void intel_crtc_restore_mode(struct drm_crtc *crtc); |
| | 607 | extern void intel_crtc_load_lut(struct drm_crtc *crtc); |
| | 608 | extern void intel_crtc_update_dpms(struct drm_crtc *crtc); |
| | 609 | extern void intel_encoder_destroy(struct drm_encoder *encoder); |
| | 610 | extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode); |
| | 611 | extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder); |
| | 612 | extern void intel_connector_dpms(struct drm_connector *, int mode); |
| | 613 | extern bool intel_connector_get_hw_state(struct intel_connector *connector); |
| | 614 | extern void intel_modeset_check_state(struct drm_device *dev); |
| | 615 | extern void intel_plane_restore(struct drm_plane *plane); |
| | 616 | |
| | 617 | |
| | 618 | static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) |
| | 619 | { |
| | 620 | return to_intel_connector(connector)->encoder; |
| | 621 | } |
| | 622 | |
| | 623 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
| | 624 | { |
| | 625 | struct intel_digital_port *intel_dig_port = |
| | 626 | container_of(encoder, struct intel_digital_port, base.base); |
| | 627 | return &intel_dig_port->dp; |
| | 628 | } |
| | 629 | |
| | 630 | static inline struct intel_digital_port * |
| | 631 | enc_to_dig_port(struct drm_encoder *encoder) |
| | 632 | { |
| | 633 | return container_of(encoder, struct intel_digital_port, base.base); |
| | 634 | } |
| | 635 | |
| | 636 | static inline struct intel_digital_port * |
| | 637 | dp_to_dig_port(struct intel_dp *intel_dp) |
| | 638 | { |
| | 639 | return container_of(intel_dp, struct intel_digital_port, dp); |
| | 640 | } |
| | 641 | |
| | 642 | static inline struct intel_digital_port * |
| | 643 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) |
| | 644 | { |
| | 645 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); |
| | 646 | } |
| | 647 | |
| | 648 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
| | 649 | struct intel_digital_port *port); |
| | 650 | |
| | 651 | extern void intel_connector_attach_encoder(struct intel_connector *connector, |
| | 652 | struct intel_encoder *encoder); |
| | 653 | extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector); |
| | 654 | |
| | 655 | extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
| | 656 | struct drm_crtc *crtc); |
| | 657 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
| | 658 | struct drm_file *file_priv); |
| | 659 | extern enum transcoder |
| | 660 | intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
| | 661 | enum pipe pipe); |
| | 662 | extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); |
| | 663 | extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); |
| | 664 | extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
| | 665 | extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port); |
| | 666 | |
| | 667 | struct intel_load_detect_pipe { |
| | 668 | struct drm_framebuffer *release_fb; |
| | 669 | bool load_detect_temp; |
| | 670 | int dpms_mode; |
| | 671 | }; |
| | 672 | extern bool intel_get_load_detect_pipe(struct drm_connector *connector, |
| | 673 | struct drm_display_mode *mode, |
| | 674 | struct intel_load_detect_pipe *old); |
| | 675 | extern void intel_release_load_detect_pipe(struct drm_connector *connector, |
| | 676 | struct intel_load_detect_pipe *old); |
| | 677 | |
| | 678 | extern void intelfb_restore(void); |
| | 679 | extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
| | 680 | u16 blue, int regno); |
| | 681 | extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
| | 682 | u16 *blue, int regno); |
| | 683 | extern void intel_enable_clock_gating(struct drm_device *dev); |
| | 684 | |
| | 685 | extern int intel_pin_and_fence_fb_obj(struct drm_device *dev, |
| | 686 | struct drm_i915_gem_object *obj, |
| | 687 | struct intel_ring_buffer *pipelined); |
| | 688 | extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); |
| | 689 | |
| | 690 | extern int intel_framebuffer_init(struct drm_device *dev, |
| | 691 | struct intel_framebuffer *ifb, |
| | 692 | struct drm_mode_fb_cmd2 *mode_cmd, |
| | 693 | struct drm_i915_gem_object *obj); |
| | 694 | extern int intel_fbdev_init(struct drm_device *dev); |
| | 695 | extern void intel_fbdev_initial_config(struct drm_device *dev); |
| | 696 | extern void intel_fbdev_fini(struct drm_device *dev); |
| | 697 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state); |
| | 698 | extern void intel_prepare_page_flip(struct drm_device *dev, int plane); |
| | 699 | extern void intel_finish_page_flip(struct drm_device *dev, int pipe); |
| | 700 | extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane); |
| | 701 | |
| | 702 | extern void intel_setup_overlay(struct drm_device *dev); |
| | 703 | extern void intel_cleanup_overlay(struct drm_device *dev); |
| | 704 | extern int intel_overlay_switch_off(struct intel_overlay *overlay); |
| | 705 | extern int intel_overlay_put_image(struct drm_device *dev, void *data, |
| | 706 | struct drm_file *file_priv); |
| | 707 | extern int intel_overlay_attrs(struct drm_device *dev, void *data, |
| | 708 | struct drm_file *file_priv); |
| | 709 | |
| | 710 | extern void intel_fb_output_poll_changed(struct drm_device *dev); |
| | 711 | extern void intel_fb_restore_mode(struct drm_device *dev); |
| | 712 | |
| | 713 | extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
| | 714 | bool state); |
| | 715 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
| | 716 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) |
| | 717 | |
| | 718 | extern void intel_init_clock_gating(struct drm_device *dev); |
| | 719 | extern void intel_write_eld(struct drm_encoder *encoder, |
| | 720 | struct drm_display_mode *mode); |
| | 721 | extern void intel_prepare_ddi(struct drm_device *dev); |
| | 722 | extern void hsw_fdi_link_train(struct drm_crtc *crtc); |
| | 723 | extern void intel_ddi_init(struct drm_device *dev, enum port port); |
| | 724 | |
| | 725 | /* For use by IVB LP watermark workaround in intel_sprite.c */ |
| | 726 | extern void intel_update_watermarks(struct drm_device *dev); |
| | 727 | extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
| | 728 | uint32_t sprite_width, |
| | 729 | int pixel_size); |
| | 730 | extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe, |
| | 731 | struct drm_display_mode *mode); |
| | 732 | |
| | 733 | extern unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
| | 734 | unsigned int tiling_mode, |
| | 735 | unsigned int bpp, |
| | 736 | unsigned int pitch); |
| | 737 | |
| | 738 | extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
| | 739 | struct drm_file *file_priv); |
| | 740 | extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data, |
| | 741 | struct drm_file *file_priv); |
| | 742 | |
| | 743 | extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg); |
| | 744 | extern void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, |
| | 745 | u32 val); |
| | 746 | |
| | 747 | /* Power-related functions, located in intel_pm.c */ |
| | 748 | extern void intel_init_pm(struct drm_device *dev); |
| | 749 | /* FBC */ |
| | 750 | extern bool intel_fbc_enabled(struct drm_device *dev); |
| | 751 | extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); |
| | 752 | extern void intel_update_fbc(struct drm_device *dev); |
| | 753 | /* IPS */ |
| | 754 | extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
| | 755 | extern void intel_gpu_ips_teardown(void); |
| | 756 | |
| | 757 | extern bool intel_display_power_enabled(struct drm_device *dev, |
| | 758 | enum intel_display_power_domain domain); |
| | 759 | extern void intel_init_power_well(struct drm_device *dev); |
| | 760 | extern void intel_set_power_well(struct drm_device *dev, bool enable); |
| | 761 | extern void intel_enable_gt_powersave(struct drm_device *dev); |
| | 762 | extern void intel_disable_gt_powersave(struct drm_device *dev); |
| | 763 | extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv); |
| | 764 | extern void ironlake_teardown_rc6(struct drm_device *dev); |
| | 765 | |
| | 766 | extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
| | 767 | enum pipe *pipe); |
| | 768 | extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); |
| | 769 | extern void intel_ddi_pll_init(struct drm_device *dev); |
| | 770 | extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); |
| | 771 | extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
| | 772 | enum transcoder cpu_transcoder); |
| | 773 | extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); |
| | 774 | extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); |
| | 775 | extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev); |
| | 776 | extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock); |
| | 777 | extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc); |
| | 778 | extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
| | 779 | extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); |
| | 780 | extern bool |
| | 781 | intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); |
| | 782 | extern void intel_ddi_fdi_disable(struct drm_crtc *crtc); |
| | 783 | |
| | 784 | extern void intel_display_handle_reset(struct drm_device *dev); |
| | 785 | extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
| | 786 | enum pipe pipe, |
| | 787 | bool enable); |
| | 788 | extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, |
| | 789 | enum transcoder pch_transcoder, |
| | 790 | bool enable); |
| | 791 | |
| | 792 | #endif /* __INTEL_DRV_H__ */ |
projects / deliverable / linux.git / blame_incremental