| 1 | /* |
| 2 | * Copyright © 2014 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Author: Shobhit Kumar <shobhit.kumar@intel.com> |
| 24 | * |
| 25 | */ |
| 26 | |
| 27 | #include <drm/drmP.h> |
| 28 | #include <drm/drm_crtc.h> |
| 29 | #include <drm/drm_edid.h> |
| 30 | #include <drm/i915_drm.h> |
| 31 | #include <linux/slab.h> |
| 32 | #include <video/mipi_display.h> |
| 33 | #include <asm/intel-mid.h> |
| 34 | #include <video/mipi_display.h> |
| 35 | #include "i915_drv.h" |
| 36 | #include "intel_drv.h" |
| 37 | #include "intel_dsi.h" |
| 38 | #include "intel_dsi_cmd.h" |
| 39 | |
| 40 | #define MIPI_TRANSFER_MODE_SHIFT 0 |
| 41 | #define MIPI_VIRTUAL_CHANNEL_SHIFT 1 |
| 42 | #define MIPI_PORT_SHIFT 3 |
| 43 | |
| 44 | #define PREPARE_CNT_MAX 0x3F |
| 45 | #define EXIT_ZERO_CNT_MAX 0x3F |
| 46 | #define CLK_ZERO_CNT_MAX 0xFF |
| 47 | #define TRAIL_CNT_MAX 0x1F |
| 48 | |
| 49 | #define NS_KHZ_RATIO 1000000 |
| 50 | |
| 51 | #define GPI0_NC_0_HV_DDI0_HPD 0x4130 |
| 52 | #define GPIO_NC_0_HV_DDI0_PAD 0x4138 |
| 53 | #define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 |
| 54 | #define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128 |
| 55 | #define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 |
| 56 | #define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118 |
| 57 | #define GPIO_NC_3_PANEL0_VDDEN 0x4140 |
| 58 | #define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148 |
| 59 | #define GPIO_NC_4_PANEL0_BLKEN 0x4150 |
| 60 | #define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158 |
| 61 | #define GPIO_NC_5_PANEL0_BLKCTL 0x4160 |
| 62 | #define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168 |
| 63 | #define GPIO_NC_6_PCONF0 0x4180 |
| 64 | #define GPIO_NC_6_PAD 0x4188 |
| 65 | #define GPIO_NC_7_PCONF0 0x4190 |
| 66 | #define GPIO_NC_7_PAD 0x4198 |
| 67 | #define GPIO_NC_8_PCONF0 0x4170 |
| 68 | #define GPIO_NC_8_PAD 0x4178 |
| 69 | #define GPIO_NC_9_PCONF0 0x4100 |
| 70 | #define GPIO_NC_9_PAD 0x4108 |
| 71 | #define GPIO_NC_10_PCONF0 0x40E0 |
| 72 | #define GPIO_NC_10_PAD 0x40E8 |
| 73 | #define GPIO_NC_11_PCONF0 0x40F0 |
| 74 | #define GPIO_NC_11_PAD 0x40F8 |
| 75 | |
| 76 | struct gpio_table { |
| 77 | u16 function_reg; |
| 78 | u16 pad_reg; |
| 79 | u8 init; |
| 80 | }; |
| 81 | |
| 82 | static struct gpio_table gtable[] = { |
| 83 | { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 }, |
| 84 | { GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 }, |
| 85 | { GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 }, |
| 86 | { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 }, |
| 87 | { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 }, |
| 88 | { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 }, |
| 89 | { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 }, |
| 90 | { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 }, |
| 91 | { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 }, |
| 92 | { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 }, |
| 93 | { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0}, |
| 94 | { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0} |
| 95 | }; |
| 96 | |
| 97 | static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data) |
| 98 | { |
| 99 | u8 type, byte, mode, vc, port; |
| 100 | u16 len; |
| 101 | |
| 102 | byte = *data++; |
| 103 | mode = (byte >> MIPI_TRANSFER_MODE_SHIFT) & 0x1; |
| 104 | vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3; |
| 105 | port = (byte >> MIPI_PORT_SHIFT) & 0x3; |
| 106 | |
| 107 | /* LP or HS mode */ |
| 108 | intel_dsi->hs = mode; |
| 109 | |
| 110 | /* get packet type and increment the pointer */ |
| 111 | type = *data++; |
| 112 | |
| 113 | len = *((u16 *) data); |
| 114 | data += 2; |
| 115 | |
| 116 | switch (type) { |
| 117 | case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: |
| 118 | dsi_vc_generic_write_0(intel_dsi, vc); |
| 119 | break; |
| 120 | case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: |
| 121 | dsi_vc_generic_write_1(intel_dsi, vc, *data); |
| 122 | break; |
| 123 | case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: |
| 124 | dsi_vc_generic_write_2(intel_dsi, vc, *data, *(data + 1)); |
| 125 | break; |
| 126 | case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: |
| 127 | case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: |
| 128 | case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: |
| 129 | DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n"); |
| 130 | break; |
| 131 | case MIPI_DSI_GENERIC_LONG_WRITE: |
| 132 | dsi_vc_generic_write(intel_dsi, vc, data, len); |
| 133 | break; |
| 134 | case MIPI_DSI_DCS_SHORT_WRITE: |
| 135 | dsi_vc_dcs_write_0(intel_dsi, vc, *data); |
| 136 | break; |
| 137 | case MIPI_DSI_DCS_SHORT_WRITE_PARAM: |
| 138 | dsi_vc_dcs_write_1(intel_dsi, vc, *data, *(data + 1)); |
| 139 | break; |
| 140 | case MIPI_DSI_DCS_READ: |
| 141 | DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n"); |
| 142 | break; |
| 143 | case MIPI_DSI_DCS_LONG_WRITE: |
| 144 | dsi_vc_dcs_write(intel_dsi, vc, data, len); |
| 145 | break; |
| 146 | } |
| 147 | |
| 148 | data += len; |
| 149 | |
| 150 | return data; |
| 151 | } |
| 152 | |
| 153 | static u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, u8 *data) |
| 154 | { |
| 155 | u32 delay = *((u32 *) data); |
| 156 | |
| 157 | usleep_range(delay, delay + 10); |
| 158 | data += 4; |
| 159 | |
| 160 | return data; |
| 161 | } |
| 162 | |
| 163 | static u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, u8 *data) |
| 164 | { |
| 165 | u8 gpio, action; |
| 166 | u16 function, pad; |
| 167 | u32 val; |
| 168 | struct drm_device *dev = intel_dsi->base.base.dev; |
| 169 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 170 | |
| 171 | gpio = *data++; |
| 172 | |
| 173 | /* pull up/down */ |
| 174 | action = *data++; |
| 175 | |
| 176 | function = gtable[gpio].function_reg; |
| 177 | pad = gtable[gpio].pad_reg; |
| 178 | |
| 179 | mutex_lock(&dev_priv->dpio_lock); |
| 180 | if (!gtable[gpio].init) { |
| 181 | /* program the function */ |
| 182 | /* FIXME: remove constant below */ |
| 183 | vlv_gpio_nc_write(dev_priv, function, 0x2000CC00); |
| 184 | gtable[gpio].init = 1; |
| 185 | } |
| 186 | |
| 187 | val = 0x4 | action; |
| 188 | |
| 189 | /* pull up/down */ |
| 190 | vlv_gpio_nc_write(dev_priv, pad, val); |
| 191 | mutex_unlock(&dev_priv->dpio_lock); |
| 192 | |
| 193 | return data; |
| 194 | } |
| 195 | |
| 196 | typedef u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, u8 *data); |
| 197 | static const fn_mipi_elem_exec exec_elem[] = { |
| 198 | NULL, /* reserved */ |
| 199 | mipi_exec_send_packet, |
| 200 | mipi_exec_delay, |
| 201 | mipi_exec_gpio, |
| 202 | NULL, /* status read; later */ |
| 203 | }; |
| 204 | |
| 205 | /* |
| 206 | * MIPI Sequence from VBT #53 parsing logic |
| 207 | * We have already separated each seqence during bios parsing |
| 208 | * Following is generic execution function for any sequence |
| 209 | */ |
| 210 | |
| 211 | static const char * const seq_name[] = { |
| 212 | "UNDEFINED", |
| 213 | "MIPI_SEQ_ASSERT_RESET", |
| 214 | "MIPI_SEQ_INIT_OTP", |
| 215 | "MIPI_SEQ_DISPLAY_ON", |
| 216 | "MIPI_SEQ_DISPLAY_OFF", |
| 217 | "MIPI_SEQ_DEASSERT_RESET" |
| 218 | }; |
| 219 | |
| 220 | static void generic_exec_sequence(struct intel_dsi *intel_dsi, char *sequence) |
| 221 | { |
| 222 | u8 *data = sequence; |
| 223 | fn_mipi_elem_exec mipi_elem_exec; |
| 224 | int index; |
| 225 | |
| 226 | if (!sequence) |
| 227 | return; |
| 228 | |
| 229 | DRM_DEBUG_DRIVER("Starting MIPI sequence - %s\n", seq_name[*data]); |
| 230 | |
| 231 | /* go to the first element of the sequence */ |
| 232 | data++; |
| 233 | |
| 234 | /* parse each byte till we reach end of sequence byte - 0x00 */ |
| 235 | while (1) { |
| 236 | index = *data; |
| 237 | mipi_elem_exec = exec_elem[index]; |
| 238 | if (!mipi_elem_exec) { |
| 239 | DRM_ERROR("Unsupported MIPI element, skipping sequence execution\n"); |
| 240 | return; |
| 241 | } |
| 242 | |
| 243 | /* goto element payload */ |
| 244 | data++; |
| 245 | |
| 246 | /* execute the element specific rotines */ |
| 247 | data = mipi_elem_exec(intel_dsi, data); |
| 248 | |
| 249 | /* |
| 250 | * After processing the element, data should point to |
| 251 | * next element or end of sequence |
| 252 | * check if have we reached end of sequence |
| 253 | */ |
| 254 | if (*data == 0x00) |
| 255 | break; |
| 256 | } |
| 257 | } |
| 258 | |
| 259 | static bool generic_init(struct intel_dsi_device *dsi) |
| 260 | { |
| 261 | struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); |
| 262 | struct drm_device *dev = intel_dsi->base.base.dev; |
| 263 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 264 | struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; |
| 265 | struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps; |
| 266 | struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode; |
| 267 | u32 bits_per_pixel = 24; |
| 268 | u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui; |
| 269 | u32 ui_num, ui_den; |
| 270 | u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; |
| 271 | u32 ths_prepare_ns, tclk_trail_ns; |
| 272 | u32 tclk_prepare_clkzero, ths_prepare_hszero; |
| 273 | u32 lp_to_hs_switch, hs_to_lp_switch; |
| 274 | u32 pclk, computed_ddr; |
| 275 | u16 burst_mode_ratio; |
| 276 | |
| 277 | DRM_DEBUG_KMS("\n"); |
| 278 | |
| 279 | intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; |
| 280 | intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; |
| 281 | intel_dsi->lane_count = mipi_config->lane_cnt + 1; |
| 282 | intel_dsi->pixel_format = mipi_config->videomode_color_format << 7; |
| 283 | |
| 284 | if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666) |
| 285 | bits_per_pixel = 18; |
| 286 | else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565) |
| 287 | bits_per_pixel = 16; |
| 288 | |
| 289 | intel_dsi->operation_mode = mipi_config->is_cmd_mode; |
| 290 | intel_dsi->video_mode_format = mipi_config->video_transfer_mode; |
| 291 | intel_dsi->escape_clk_div = mipi_config->byte_clk_sel; |
| 292 | intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout; |
| 293 | intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout; |
| 294 | intel_dsi->rst_timer_val = mipi_config->device_reset_timer; |
| 295 | intel_dsi->init_count = mipi_config->master_init_timer; |
| 296 | intel_dsi->bw_timer = mipi_config->dbi_bw_timer; |
| 297 | intel_dsi->video_frmt_cfg_bits = |
| 298 | mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0; |
| 299 | |
| 300 | pclk = mode->clock; |
| 301 | |
| 302 | /* Burst Mode Ratio |
| 303 | * Target ddr frequency from VBT / non burst ddr freq |
| 304 | * multiply by 100 to preserve remainder |
| 305 | */ |
| 306 | if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) { |
| 307 | if (mipi_config->target_burst_mode_freq) { |
| 308 | computed_ddr = |
| 309 | (pclk * bits_per_pixel) / intel_dsi->lane_count; |
| 310 | |
| 311 | if (mipi_config->target_burst_mode_freq < |
| 312 | computed_ddr) { |
| 313 | DRM_ERROR("Burst mode freq is less than computed\n"); |
| 314 | return false; |
| 315 | } |
| 316 | |
| 317 | burst_mode_ratio = DIV_ROUND_UP( |
| 318 | mipi_config->target_burst_mode_freq * 100, |
| 319 | computed_ddr); |
| 320 | |
| 321 | pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100); |
| 322 | } else { |
| 323 | DRM_ERROR("Burst mode target is not set\n"); |
| 324 | return false; |
| 325 | } |
| 326 | } else |
| 327 | burst_mode_ratio = 100; |
| 328 | |
| 329 | intel_dsi->burst_mode_ratio = burst_mode_ratio; |
| 330 | intel_dsi->pclk = pclk; |
| 331 | |
| 332 | bitrate = (pclk * bits_per_pixel) / intel_dsi->lane_count; |
| 333 | |
| 334 | switch (intel_dsi->escape_clk_div) { |
| 335 | case 0: |
| 336 | tlpx_ns = 50; |
| 337 | break; |
| 338 | case 1: |
| 339 | tlpx_ns = 100; |
| 340 | break; |
| 341 | |
| 342 | case 2: |
| 343 | tlpx_ns = 200; |
| 344 | break; |
| 345 | default: |
| 346 | tlpx_ns = 50; |
| 347 | break; |
| 348 | } |
| 349 | |
| 350 | switch (intel_dsi->lane_count) { |
| 351 | case 1: |
| 352 | case 2: |
| 353 | extra_byte_count = 2; |
| 354 | break; |
| 355 | case 3: |
| 356 | extra_byte_count = 4; |
| 357 | break; |
| 358 | case 4: |
| 359 | default: |
| 360 | extra_byte_count = 3; |
| 361 | break; |
| 362 | } |
| 363 | |
| 364 | /* |
| 365 | * ui(s) = 1/f [f in hz] |
| 366 | * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz) |
| 367 | */ |
| 368 | |
| 369 | /* in Kbps */ |
| 370 | ui_num = NS_KHZ_RATIO; |
| 371 | ui_den = bitrate; |
| 372 | |
| 373 | tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; |
| 374 | ths_prepare_hszero = mipi_config->ths_prepare_hszero; |
| 375 | |
| 376 | /* |
| 377 | * B060 |
| 378 | * LP byte clock = TLPX/ (8UI) |
| 379 | */ |
| 380 | intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); |
| 381 | |
| 382 | /* count values in UI = (ns value) * (bitrate / (2 * 10^6)) |
| 383 | * |
| 384 | * Since txddrclkhs_i is 2xUI, all the count values programmed in |
| 385 | * DPHY param register are divided by 2 |
| 386 | * |
| 387 | * prepare count |
| 388 | */ |
| 389 | ths_prepare_ns = max(mipi_config->ths_prepare, |
| 390 | mipi_config->tclk_prepare); |
| 391 | prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2); |
| 392 | |
| 393 | /* exit zero count */ |
| 394 | exit_zero_cnt = DIV_ROUND_UP( |
| 395 | (ths_prepare_hszero - ths_prepare_ns) * ui_den, |
| 396 | ui_num * 2 |
| 397 | ); |
| 398 | |
| 399 | /* |
| 400 | * Exit zero is unified val ths_zero and ths_exit |
| 401 | * minimum value for ths_exit = 110ns |
| 402 | * min (exit_zero_cnt * 2) = 110/UI |
| 403 | * exit_zero_cnt = 55/UI |
| 404 | */ |
| 405 | if (exit_zero_cnt < (55 * ui_den / ui_num)) |
| 406 | if ((55 * ui_den) % ui_num) |
| 407 | exit_zero_cnt += 1; |
| 408 | |
| 409 | /* clk zero count */ |
| 410 | clk_zero_cnt = DIV_ROUND_UP( |
| 411 | (tclk_prepare_clkzero - ths_prepare_ns) |
| 412 | * ui_den, 2 * ui_num); |
| 413 | |
| 414 | /* trail count */ |
| 415 | tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); |
| 416 | trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num); |
| 417 | |
| 418 | if (prepare_cnt > PREPARE_CNT_MAX || |
| 419 | exit_zero_cnt > EXIT_ZERO_CNT_MAX || |
| 420 | clk_zero_cnt > CLK_ZERO_CNT_MAX || |
| 421 | trail_cnt > TRAIL_CNT_MAX) |
| 422 | DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n"); |
| 423 | |
| 424 | if (prepare_cnt > PREPARE_CNT_MAX) |
| 425 | prepare_cnt = PREPARE_CNT_MAX; |
| 426 | |
| 427 | if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) |
| 428 | exit_zero_cnt = EXIT_ZERO_CNT_MAX; |
| 429 | |
| 430 | if (clk_zero_cnt > CLK_ZERO_CNT_MAX) |
| 431 | clk_zero_cnt = CLK_ZERO_CNT_MAX; |
| 432 | |
| 433 | if (trail_cnt > TRAIL_CNT_MAX) |
| 434 | trail_cnt = TRAIL_CNT_MAX; |
| 435 | |
| 436 | /* B080 */ |
| 437 | intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | |
| 438 | clk_zero_cnt << 8 | prepare_cnt; |
| 439 | |
| 440 | /* |
| 441 | * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2 |
| 442 | * + 10UI + Extra Byte Count |
| 443 | * |
| 444 | * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count |
| 445 | * Extra Byte Count is calculated according to number of lanes. |
| 446 | * High Low Switch Count is the Max of LP to HS and |
| 447 | * HS to LP switch count |
| 448 | * |
| 449 | */ |
| 450 | tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num); |
| 451 | |
| 452 | /* B044 */ |
| 453 | /* FIXME: |
| 454 | * The comment above does not match with the code */ |
| 455 | lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 + |
| 456 | exit_zero_cnt * 2 + 10, 8); |
| 457 | |
| 458 | hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); |
| 459 | |
| 460 | intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); |
| 461 | intel_dsi->hs_to_lp_count += extra_byte_count; |
| 462 | |
| 463 | /* B088 */ |
| 464 | /* LP -> HS for clock lanes |
| 465 | * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero + |
| 466 | * extra byte count |
| 467 | * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt * |
| 468 | * 2(in UI) + extra byte count |
| 469 | * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) / |
| 470 | * 8 + extra byte count |
| 471 | */ |
| 472 | intel_dsi->clk_lp_to_hs_count = |
| 473 | DIV_ROUND_UP( |
| 474 | 4 * tlpx_ui + prepare_cnt * 2 + |
| 475 | clk_zero_cnt * 2, |
| 476 | 8); |
| 477 | |
| 478 | intel_dsi->clk_lp_to_hs_count += extra_byte_count; |
| 479 | |
| 480 | /* HS->LP for Clock Lanes |
| 481 | * Low Power clock synchronisations + 1Tx byteclk + tclk_trail + |
| 482 | * Extra byte count |
| 483 | * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count |
| 484 | * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 + |
| 485 | * Extra byte count |
| 486 | */ |
| 487 | intel_dsi->clk_hs_to_lp_count = |
| 488 | DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8, |
| 489 | 8); |
| 490 | intel_dsi->clk_hs_to_lp_count += extra_byte_count; |
| 491 | |
| 492 | DRM_DEBUG_KMS("Eot %s\n", intel_dsi->eotp_pkt ? "enabled" : "disabled"); |
| 493 | DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ? |
| 494 | "disabled" : "enabled"); |
| 495 | DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video"); |
| 496 | DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format); |
| 497 | DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div); |
| 498 | DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout); |
| 499 | DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val); |
| 500 | DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count); |
| 501 | DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count); |
| 502 | DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk); |
| 503 | DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer); |
| 504 | DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count); |
| 505 | DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count); |
| 506 | DRM_DEBUG_KMS("BTA %s\n", |
| 507 | intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA ? |
| 508 | "disabled" : "enabled"); |
| 509 | |
| 510 | /* delays in VBT are in unit of 100us, so need to convert |
| 511 | * here in ms |
| 512 | * Delay (100us) * 100 /1000 = Delay / 10 (ms) */ |
| 513 | intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10; |
| 514 | intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10; |
| 515 | intel_dsi->panel_on_delay = pps->panel_on_delay / 10; |
| 516 | intel_dsi->panel_off_delay = pps->panel_off_delay / 10; |
| 517 | intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10; |
| 518 | |
| 519 | return true; |
| 520 | } |
| 521 | |
| 522 | static int generic_mode_valid(struct intel_dsi_device *dsi, |
| 523 | struct drm_display_mode *mode) |
| 524 | { |
| 525 | return MODE_OK; |
| 526 | } |
| 527 | |
| 528 | static bool generic_mode_fixup(struct intel_dsi_device *dsi, |
| 529 | const struct drm_display_mode *mode, |
| 530 | struct drm_display_mode *adjusted_mode) { |
| 531 | return true; |
| 532 | } |
| 533 | |
| 534 | static void generic_panel_reset(struct intel_dsi_device *dsi) |
| 535 | { |
| 536 | struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); |
| 537 | struct drm_device *dev = intel_dsi->base.base.dev; |
| 538 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 539 | |
| 540 | char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET]; |
| 541 | |
| 542 | generic_exec_sequence(intel_dsi, sequence); |
| 543 | } |
| 544 | |
| 545 | static void generic_disable_panel_power(struct intel_dsi_device *dsi) |
| 546 | { |
| 547 | struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); |
| 548 | struct drm_device *dev = intel_dsi->base.base.dev; |
| 549 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 550 | |
| 551 | char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]; |
| 552 | |
| 553 | generic_exec_sequence(intel_dsi, sequence); |
| 554 | } |
| 555 | |
| 556 | static void generic_send_otp_cmds(struct intel_dsi_device *dsi) |
| 557 | { |
| 558 | struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); |
| 559 | struct drm_device *dev = intel_dsi->base.base.dev; |
| 560 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 561 | |
| 562 | char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; |
| 563 | |
| 564 | generic_exec_sequence(intel_dsi, sequence); |
| 565 | } |
| 566 | |
| 567 | static void generic_enable(struct intel_dsi_device *dsi) |
| 568 | { |
| 569 | struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); |
| 570 | struct drm_device *dev = intel_dsi->base.base.dev; |
| 571 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 572 | |
| 573 | char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_ON]; |
| 574 | |
| 575 | generic_exec_sequence(intel_dsi, sequence); |
| 576 | } |
| 577 | |
| 578 | static void generic_disable(struct intel_dsi_device *dsi) |
| 579 | { |
| 580 | struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); |
| 581 | struct drm_device *dev = intel_dsi->base.base.dev; |
| 582 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 583 | |
| 584 | char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_OFF]; |
| 585 | |
| 586 | generic_exec_sequence(intel_dsi, sequence); |
| 587 | } |
| 588 | |
| 589 | static enum drm_connector_status generic_detect(struct intel_dsi_device *dsi) |
| 590 | { |
| 591 | return connector_status_connected; |
| 592 | } |
| 593 | |
| 594 | static bool generic_get_hw_state(struct intel_dsi_device *dev) |
| 595 | { |
| 596 | return true; |
| 597 | } |
| 598 | |
| 599 | static struct drm_display_mode *generic_get_modes(struct intel_dsi_device *dsi) |
| 600 | { |
| 601 | struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); |
| 602 | struct drm_device *dev = intel_dsi->base.base.dev; |
| 603 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 604 | |
| 605 | dev_priv->vbt.lfp_lvds_vbt_mode->type |= DRM_MODE_TYPE_PREFERRED; |
| 606 | return dev_priv->vbt.lfp_lvds_vbt_mode; |
| 607 | } |
| 608 | |
| 609 | static void generic_destroy(struct intel_dsi_device *dsi) { } |
| 610 | |
| 611 | /* Callbacks. We might not need them all. */ |
| 612 | struct intel_dsi_dev_ops vbt_generic_dsi_display_ops = { |
| 613 | .init = generic_init, |
| 614 | .mode_valid = generic_mode_valid, |
| 615 | .mode_fixup = generic_mode_fixup, |
| 616 | .panel_reset = generic_panel_reset, |
| 617 | .disable_panel_power = generic_disable_panel_power, |
| 618 | .send_otp_cmds = generic_send_otp_cmds, |
| 619 | .enable = generic_enable, |
| 620 | .disable = generic_disable, |
| 621 | .detect = generic_detect, |
| 622 | .get_hw_state = generic_get_hw_state, |
| 623 | .get_modes = generic_get_modes, |
| 624 | .destroy = generic_destroy, |
| 625 | }; |