| 1 | /* |
| 2 | * Copyright © 2014 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Ben Widawsky <ben@bwidawsk.net> |
| 25 | * Michel Thierry <michel.thierry@intel.com> |
| 26 | * Thomas Daniel <thomas.daniel@intel.com> |
| 27 | * Oscar Mateo <oscar.mateo@intel.com> |
| 28 | * |
| 29 | */ |
| 30 | |
| 31 | /* |
| 32 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
| 33 | * These expanded contexts enable a number of new abilities, especially |
| 34 | * "Execlists" (also implemented in this file). |
| 35 | * |
| 36 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
| 37 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). |
| 38 | */ |
| 39 | |
| 40 | #include <drm/drmP.h> |
| 41 | #include <drm/i915_drm.h> |
| 42 | #include "i915_drv.h" |
| 43 | |
| 44 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
| 45 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) |
| 46 | |
| 47 | #define GEN8_LR_CONTEXT_ALIGN 4096 |
| 48 | |
| 49 | #define RING_ELSP(ring) ((ring)->mmio_base+0x230) |
| 50 | #define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244) |
| 51 | |
| 52 | #define CTX_LRI_HEADER_0 0x01 |
| 53 | #define CTX_CONTEXT_CONTROL 0x02 |
| 54 | #define CTX_RING_HEAD 0x04 |
| 55 | #define CTX_RING_TAIL 0x06 |
| 56 | #define CTX_RING_BUFFER_START 0x08 |
| 57 | #define CTX_RING_BUFFER_CONTROL 0x0a |
| 58 | #define CTX_BB_HEAD_U 0x0c |
| 59 | #define CTX_BB_HEAD_L 0x0e |
| 60 | #define CTX_BB_STATE 0x10 |
| 61 | #define CTX_SECOND_BB_HEAD_U 0x12 |
| 62 | #define CTX_SECOND_BB_HEAD_L 0x14 |
| 63 | #define CTX_SECOND_BB_STATE 0x16 |
| 64 | #define CTX_BB_PER_CTX_PTR 0x18 |
| 65 | #define CTX_RCS_INDIRECT_CTX 0x1a |
| 66 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c |
| 67 | #define CTX_LRI_HEADER_1 0x21 |
| 68 | #define CTX_CTX_TIMESTAMP 0x22 |
| 69 | #define CTX_PDP3_UDW 0x24 |
| 70 | #define CTX_PDP3_LDW 0x26 |
| 71 | #define CTX_PDP2_UDW 0x28 |
| 72 | #define CTX_PDP2_LDW 0x2a |
| 73 | #define CTX_PDP1_UDW 0x2c |
| 74 | #define CTX_PDP1_LDW 0x2e |
| 75 | #define CTX_PDP0_UDW 0x30 |
| 76 | #define CTX_PDP0_LDW 0x32 |
| 77 | #define CTX_LRI_HEADER_2 0x41 |
| 78 | #define CTX_R_PWR_CLK_STATE 0x42 |
| 79 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 |
| 80 | |
| 81 | int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists) |
| 82 | { |
| 83 | WARN_ON(i915.enable_ppgtt == -1); |
| 84 | |
| 85 | if (enable_execlists == 0) |
| 86 | return 0; |
| 87 | |
| 88 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev)) |
| 89 | return 1; |
| 90 | |
| 91 | return 0; |
| 92 | } |
| 93 | |
| 94 | static int |
| 95 | populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, |
| 96 | struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) |
| 97 | { |
| 98 | struct drm_i915_gem_object *ring_obj = ringbuf->obj; |
| 99 | struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx); |
| 100 | struct page *page; |
| 101 | uint32_t *reg_state; |
| 102 | int ret; |
| 103 | |
| 104 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); |
| 105 | if (ret) { |
| 106 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); |
| 107 | return ret; |
| 108 | } |
| 109 | |
| 110 | ret = i915_gem_object_get_pages(ctx_obj); |
| 111 | if (ret) { |
| 112 | DRM_DEBUG_DRIVER("Could not get object pages\n"); |
| 113 | return ret; |
| 114 | } |
| 115 | |
| 116 | i915_gem_object_pin_pages(ctx_obj); |
| 117 | |
| 118 | /* The second page of the context object contains some fields which must |
| 119 | * be set up prior to the first execution. */ |
| 120 | page = i915_gem_object_get_page(ctx_obj, 1); |
| 121 | reg_state = kmap_atomic(page); |
| 122 | |
| 123 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM |
| 124 | * commands followed by (reg, value) pairs. The values we are setting here are |
| 125 | * only for the first context restore: on a subsequent save, the GPU will |
| 126 | * recreate this batchbuffer with new values (including all the missing |
| 127 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ |
| 128 | if (ring->id == RCS) |
| 129 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14); |
| 130 | else |
| 131 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11); |
| 132 | reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED; |
| 133 | reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring); |
| 134 | reg_state[CTX_CONTEXT_CONTROL+1] = |
| 135 | _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT); |
| 136 | reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base); |
| 137 | reg_state[CTX_RING_HEAD+1] = 0; |
| 138 | reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base); |
| 139 | reg_state[CTX_RING_TAIL+1] = 0; |
| 140 | reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base); |
| 141 | reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj); |
| 142 | reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base); |
| 143 | reg_state[CTX_RING_BUFFER_CONTROL+1] = |
| 144 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID; |
| 145 | reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168; |
| 146 | reg_state[CTX_BB_HEAD_U+1] = 0; |
| 147 | reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140; |
| 148 | reg_state[CTX_BB_HEAD_L+1] = 0; |
| 149 | reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110; |
| 150 | reg_state[CTX_BB_STATE+1] = (1<<5); |
| 151 | reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c; |
| 152 | reg_state[CTX_SECOND_BB_HEAD_U+1] = 0; |
| 153 | reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114; |
| 154 | reg_state[CTX_SECOND_BB_HEAD_L+1] = 0; |
| 155 | reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118; |
| 156 | reg_state[CTX_SECOND_BB_STATE+1] = 0; |
| 157 | if (ring->id == RCS) { |
| 158 | /* TODO: according to BSpec, the register state context |
| 159 | * for CHV does not have these. OTOH, these registers do |
| 160 | * exist in CHV. I'm waiting for a clarification */ |
| 161 | reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0; |
| 162 | reg_state[CTX_BB_PER_CTX_PTR+1] = 0; |
| 163 | reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4; |
| 164 | reg_state[CTX_RCS_INDIRECT_CTX+1] = 0; |
| 165 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8; |
| 166 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0; |
| 167 | } |
| 168 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9); |
| 169 | reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED; |
| 170 | reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8; |
| 171 | reg_state[CTX_CTX_TIMESTAMP+1] = 0; |
| 172 | reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3); |
| 173 | reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3); |
| 174 | reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2); |
| 175 | reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2); |
| 176 | reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1); |
| 177 | reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1); |
| 178 | reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0); |
| 179 | reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0); |
| 180 | reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]); |
| 181 | reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]); |
| 182 | reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]); |
| 183 | reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]); |
| 184 | reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]); |
| 185 | reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]); |
| 186 | reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]); |
| 187 | reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]); |
| 188 | if (ring->id == RCS) { |
| 189 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); |
| 190 | reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8; |
| 191 | reg_state[CTX_R_PWR_CLK_STATE+1] = 0; |
| 192 | } |
| 193 | |
| 194 | kunmap_atomic(reg_state); |
| 195 | |
| 196 | ctx_obj->dirty = 1; |
| 197 | set_page_dirty(page); |
| 198 | i915_gem_object_unpin_pages(ctx_obj); |
| 199 | |
| 200 | return 0; |
| 201 | } |
| 202 | |
| 203 | void intel_lr_context_free(struct intel_context *ctx) |
| 204 | { |
| 205 | int i; |
| 206 | |
| 207 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 208 | struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; |
| 209 | struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf; |
| 210 | |
| 211 | if (ctx_obj) { |
| 212 | intel_destroy_ringbuffer_obj(ringbuf); |
| 213 | kfree(ringbuf); |
| 214 | i915_gem_object_ggtt_unpin(ctx_obj); |
| 215 | drm_gem_object_unreference(&ctx_obj->base); |
| 216 | } |
| 217 | } |
| 218 | } |
| 219 | |
| 220 | static uint32_t get_lr_context_size(struct intel_engine_cs *ring) |
| 221 | { |
| 222 | int ret = 0; |
| 223 | |
| 224 | WARN_ON(INTEL_INFO(ring->dev)->gen != 8); |
| 225 | |
| 226 | switch (ring->id) { |
| 227 | case RCS: |
| 228 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; |
| 229 | break; |
| 230 | case VCS: |
| 231 | case BCS: |
| 232 | case VECS: |
| 233 | case VCS2: |
| 234 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; |
| 235 | break; |
| 236 | } |
| 237 | |
| 238 | return ret; |
| 239 | } |
| 240 | |
| 241 | int intel_lr_context_deferred_create(struct intel_context *ctx, |
| 242 | struct intel_engine_cs *ring) |
| 243 | { |
| 244 | struct drm_device *dev = ring->dev; |
| 245 | struct drm_i915_gem_object *ctx_obj; |
| 246 | uint32_t context_size; |
| 247 | struct intel_ringbuffer *ringbuf; |
| 248 | int ret; |
| 249 | |
| 250 | WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); |
| 251 | |
| 252 | context_size = round_up(get_lr_context_size(ring), 4096); |
| 253 | |
| 254 | ctx_obj = i915_gem_alloc_context_obj(dev, context_size); |
| 255 | if (IS_ERR(ctx_obj)) { |
| 256 | ret = PTR_ERR(ctx_obj); |
| 257 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret); |
| 258 | return ret; |
| 259 | } |
| 260 | |
| 261 | ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0); |
| 262 | if (ret) { |
| 263 | DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", ret); |
| 264 | drm_gem_object_unreference(&ctx_obj->base); |
| 265 | return ret; |
| 266 | } |
| 267 | |
| 268 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); |
| 269 | if (!ringbuf) { |
| 270 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", |
| 271 | ring->name); |
| 272 | i915_gem_object_ggtt_unpin(ctx_obj); |
| 273 | drm_gem_object_unreference(&ctx_obj->base); |
| 274 | ret = -ENOMEM; |
| 275 | return ret; |
| 276 | } |
| 277 | |
| 278 | ringbuf->ring = ring; |
| 279 | ringbuf->size = 32 * PAGE_SIZE; |
| 280 | ringbuf->effective_size = ringbuf->size; |
| 281 | ringbuf->head = 0; |
| 282 | ringbuf->tail = 0; |
| 283 | ringbuf->space = ringbuf->size; |
| 284 | ringbuf->last_retired_head = -1; |
| 285 | |
| 286 | /* TODO: For now we put this in the mappable region so that we can reuse |
| 287 | * the existing ringbuffer code which ioremaps it. When we start |
| 288 | * creating many contexts, this will no longer work and we must switch |
| 289 | * to a kmapish interface. |
| 290 | */ |
| 291 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); |
| 292 | if (ret) { |
| 293 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer obj %s: %d\n", |
| 294 | ring->name, ret); |
| 295 | goto error; |
| 296 | } |
| 297 | |
| 298 | ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf); |
| 299 | if (ret) { |
| 300 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); |
| 301 | intel_destroy_ringbuffer_obj(ringbuf); |
| 302 | goto error; |
| 303 | } |
| 304 | |
| 305 | ctx->engine[ring->id].ringbuf = ringbuf; |
| 306 | ctx->engine[ring->id].state = ctx_obj; |
| 307 | |
| 308 | return 0; |
| 309 | |
| 310 | error: |
| 311 | kfree(ringbuf); |
| 312 | i915_gem_object_ggtt_unpin(ctx_obj); |
| 313 | drm_gem_object_unreference(&ctx_obj->base); |
| 314 | return ret; |
| 315 | } |