| 1 | /* |
| 2 | * Copyright © 2014 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Ben Widawsky <ben@bwidawsk.net> |
| 25 | * Michel Thierry <michel.thierry@intel.com> |
| 26 | * Thomas Daniel <thomas.daniel@intel.com> |
| 27 | * Oscar Mateo <oscar.mateo@intel.com> |
| 28 | * |
| 29 | */ |
| 30 | |
| 31 | /** |
| 32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists |
| 33 | * |
| 34 | * Motivation: |
| 35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
| 36 | * These expanded contexts enable a number of new abilities, especially |
| 37 | * "Execlists" (also implemented in this file). |
| 38 | * |
| 39 | * One of the main differences with the legacy HW contexts is that logical |
| 40 | * ring contexts incorporate many more things to the context's state, like |
| 41 | * PDPs or ringbuffer control registers: |
| 42 | * |
| 43 | * The reason why PDPs are included in the context is straightforward: as |
| 44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs |
| 45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, |
| 46 | * instead, the GPU will do it for you on the context switch. |
| 47 | * |
| 48 | * But, what about the ringbuffer control registers (head, tail, etc..)? |
| 49 | * shouldn't we just need a set of those per engine command streamer? This is |
| 50 | * where the name "Logical Rings" starts to make sense: by virtualizing the |
| 51 | * rings, the engine cs shifts to a new "ring buffer" with every context |
| 52 | * switch. When you want to submit a workload to the GPU you: A) choose your |
| 53 | * context, B) find its appropriate virtualized ring, C) write commands to it |
| 54 | * and then, finally, D) tell the GPU to switch to that context. |
| 55 | * |
| 56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch |
| 57 | * to a contexts is via a context execution list, ergo "Execlists". |
| 58 | * |
| 59 | * LRC implementation: |
| 60 | * Regarding the creation of contexts, we have: |
| 61 | * |
| 62 | * - One global default context. |
| 63 | * - One local default context for each opened fd. |
| 64 | * - One local extra context for each context create ioctl call. |
| 65 | * |
| 66 | * Now that ringbuffers belong per-context (and not per-engine, like before) |
| 67 | * and that contexts are uniquely tied to a given engine (and not reusable, |
| 68 | * like before) we need: |
| 69 | * |
| 70 | * - One ringbuffer per-engine inside each context. |
| 71 | * - One backing object per-engine inside each context. |
| 72 | * |
| 73 | * The global default context starts its life with these new objects fully |
| 74 | * allocated and populated. The local default context for each opened fd is |
| 75 | * more complex, because we don't know at creation time which engine is going |
| 76 | * to use them. To handle this, we have implemented a deferred creation of LR |
| 77 | * contexts: |
| 78 | * |
| 79 | * The local context starts its life as a hollow or blank holder, that only |
| 80 | * gets populated for a given engine once we receive an execbuffer. If later |
| 81 | * on we receive another execbuffer ioctl for the same context but a different |
| 82 | * engine, we allocate/populate a new ringbuffer and context backing object and |
| 83 | * so on. |
| 84 | * |
| 85 | * Finally, regarding local contexts created using the ioctl call: as they are |
| 86 | * only allowed with the render ring, we can allocate & populate them right |
| 87 | * away (no need to defer anything, at least for now). |
| 88 | * |
| 89 | * Execlists implementation: |
| 90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
| 91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). |
| 92 | * This method works as follows: |
| 93 | * |
| 94 | * When a request is committed, its commands (the BB start and any leading or |
| 95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer |
| 96 | * for the appropriate context. The tail pointer in the hardware context is not |
| 97 | * updated at this time, but instead, kept by the driver in the ringbuffer |
| 98 | * structure. A structure representing this request is added to a request queue |
| 99 | * for the appropriate engine: this structure contains a copy of the context's |
| 100 | * tail after the request was written to the ring buffer and a pointer to the |
| 101 | * context itself. |
| 102 | * |
| 103 | * If the engine's request queue was empty before the request was added, the |
| 104 | * queue is processed immediately. Otherwise the queue will be processed during |
| 105 | * a context switch interrupt. In any case, elements on the queue will get sent |
| 106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a |
| 107 | * globally unique 20-bits submission ID. |
| 108 | * |
| 109 | * When execution of a request completes, the GPU updates the context status |
| 110 | * buffer with a context complete event and generates a context switch interrupt. |
| 111 | * During the interrupt handling, the driver examines the events in the buffer: |
| 112 | * for each context complete event, if the announced ID matches that on the head |
| 113 | * of the request queue, then that request is retired and removed from the queue. |
| 114 | * |
| 115 | * After processing, if any requests were retired and the queue is not empty |
| 116 | * then a new execution list can be submitted. The two requests at the front of |
| 117 | * the queue are next to be submitted but since a context may not occur twice in |
| 118 | * an execution list, if subsequent requests have the same ID as the first then |
| 119 | * the two requests must be combined. This is done simply by discarding requests |
| 120 | * at the head of the queue until either only one requests is left (in which case |
| 121 | * we use a NULL second context) or the first two requests have unique IDs. |
| 122 | * |
| 123 | * By always executing the first two requests in the queue the driver ensures |
| 124 | * that the GPU is kept as busy as possible. In the case where a single context |
| 125 | * completes but a second context is still executing, the request for this second |
| 126 | * context will be at the head of the queue when we remove the first one. This |
| 127 | * request will then be resubmitted along with a new request for a different context, |
| 128 | * which will cause the hardware to continue executing the second request and queue |
| 129 | * the new request (the GPU detects the condition of a context getting preempted |
| 130 | * with the same context and optimizes the context switch flow by not doing |
| 131 | * preemption, but just sampling the new tail pointer). |
| 132 | * |
| 133 | */ |
| 134 | #include <linux/interrupt.h> |
| 135 | |
| 136 | #include <drm/drmP.h> |
| 137 | #include <drm/i915_drm.h> |
| 138 | #include "i915_drv.h" |
| 139 | #include "intel_mocs.h" |
| 140 | |
| 141 | #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) |
| 142 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
| 143 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) |
| 144 | |
| 145 | #define RING_EXECLIST_QFULL (1 << 0x2) |
| 146 | #define RING_EXECLIST1_VALID (1 << 0x3) |
| 147 | #define RING_EXECLIST0_VALID (1 << 0x4) |
| 148 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) |
| 149 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) |
| 150 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) |
| 151 | |
| 152 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) |
| 153 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) |
| 154 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) |
| 155 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) |
| 156 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) |
| 157 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) |
| 158 | |
| 159 | #define CTX_LRI_HEADER_0 0x01 |
| 160 | #define CTX_CONTEXT_CONTROL 0x02 |
| 161 | #define CTX_RING_HEAD 0x04 |
| 162 | #define CTX_RING_TAIL 0x06 |
| 163 | #define CTX_RING_BUFFER_START 0x08 |
| 164 | #define CTX_RING_BUFFER_CONTROL 0x0a |
| 165 | #define CTX_BB_HEAD_U 0x0c |
| 166 | #define CTX_BB_HEAD_L 0x0e |
| 167 | #define CTX_BB_STATE 0x10 |
| 168 | #define CTX_SECOND_BB_HEAD_U 0x12 |
| 169 | #define CTX_SECOND_BB_HEAD_L 0x14 |
| 170 | #define CTX_SECOND_BB_STATE 0x16 |
| 171 | #define CTX_BB_PER_CTX_PTR 0x18 |
| 172 | #define CTX_RCS_INDIRECT_CTX 0x1a |
| 173 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c |
| 174 | #define CTX_LRI_HEADER_1 0x21 |
| 175 | #define CTX_CTX_TIMESTAMP 0x22 |
| 176 | #define CTX_PDP3_UDW 0x24 |
| 177 | #define CTX_PDP3_LDW 0x26 |
| 178 | #define CTX_PDP2_UDW 0x28 |
| 179 | #define CTX_PDP2_LDW 0x2a |
| 180 | #define CTX_PDP1_UDW 0x2c |
| 181 | #define CTX_PDP1_LDW 0x2e |
| 182 | #define CTX_PDP0_UDW 0x30 |
| 183 | #define CTX_PDP0_LDW 0x32 |
| 184 | #define CTX_LRI_HEADER_2 0x41 |
| 185 | #define CTX_R_PWR_CLK_STATE 0x42 |
| 186 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 |
| 187 | |
| 188 | #define GEN8_CTX_VALID (1<<0) |
| 189 | #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) |
| 190 | #define GEN8_CTX_FORCE_RESTORE (1<<2) |
| 191 | #define GEN8_CTX_L3LLC_COHERENT (1<<5) |
| 192 | #define GEN8_CTX_PRIVILEGE (1<<8) |
| 193 | |
| 194 | #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \ |
| 195 | (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \ |
| 196 | (reg_state)[(pos)+1] = (val); \ |
| 197 | } while (0) |
| 198 | |
| 199 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \ |
| 200 | const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \ |
| 201 | reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ |
| 202 | reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ |
| 203 | } while (0) |
| 204 | |
| 205 | #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \ |
| 206 | reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \ |
| 207 | reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \ |
| 208 | } while (0) |
| 209 | |
| 210 | enum { |
| 211 | ADVANCED_CONTEXT = 0, |
| 212 | LEGACY_32B_CONTEXT, |
| 213 | ADVANCED_AD_CONTEXT, |
| 214 | LEGACY_64B_CONTEXT |
| 215 | }; |
| 216 | #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 |
| 217 | #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ |
| 218 | LEGACY_64B_CONTEXT :\ |
| 219 | LEGACY_32B_CONTEXT) |
| 220 | enum { |
| 221 | FAULT_AND_HANG = 0, |
| 222 | FAULT_AND_HALT, /* Debug only */ |
| 223 | FAULT_AND_STREAM, |
| 224 | FAULT_AND_CONTINUE /* Unsupported */ |
| 225 | }; |
| 226 | #define GEN8_CTX_ID_SHIFT 32 |
| 227 | #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
| 228 | #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 |
| 229 | |
| 230 | static int intel_lr_context_pin(struct intel_context *ctx, |
| 231 | struct intel_engine_cs *engine); |
| 232 | |
| 233 | /** |
| 234 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists |
| 235 | * @dev: DRM device. |
| 236 | * @enable_execlists: value of i915.enable_execlists module parameter. |
| 237 | * |
| 238 | * Only certain platforms support Execlists (the prerequisites being |
| 239 | * support for Logical Ring Contexts and Aliasing PPGTT or better). |
| 240 | * |
| 241 | * Return: 1 if Execlists is supported and has to be enabled. |
| 242 | */ |
| 243 | int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists) |
| 244 | { |
| 245 | WARN_ON(i915.enable_ppgtt == -1); |
| 246 | |
| 247 | /* On platforms with execlist available, vGPU will only |
| 248 | * support execlist mode, no ring buffer mode. |
| 249 | */ |
| 250 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev)) |
| 251 | return 1; |
| 252 | |
| 253 | if (INTEL_INFO(dev)->gen >= 9) |
| 254 | return 1; |
| 255 | |
| 256 | if (enable_execlists == 0) |
| 257 | return 0; |
| 258 | |
| 259 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) && |
| 260 | i915.use_mmio_flip >= 0) |
| 261 | return 1; |
| 262 | |
| 263 | return 0; |
| 264 | } |
| 265 | |
| 266 | static void |
| 267 | logical_ring_init_platform_invariants(struct intel_engine_cs *engine) |
| 268 | { |
| 269 | struct drm_device *dev = engine->dev; |
| 270 | |
| 271 | if (IS_GEN8(dev) || IS_GEN9(dev)) |
| 272 | engine->idle_lite_restore_wa = ~0; |
| 273 | |
| 274 | engine->disable_lite_restore_wa = (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || |
| 275 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) && |
| 276 | (engine->id == VCS || engine->id == VCS2); |
| 277 | |
| 278 | engine->ctx_desc_template = GEN8_CTX_VALID; |
| 279 | engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev) << |
| 280 | GEN8_CTX_ADDRESSING_MODE_SHIFT; |
| 281 | if (IS_GEN8(dev)) |
| 282 | engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT; |
| 283 | engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE; |
| 284 | |
| 285 | /* TODO: WaDisableLiteRestore when we start using semaphore |
| 286 | * signalling between Command Streamers */ |
| 287 | /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */ |
| 288 | |
| 289 | /* WaEnableForceRestoreInCtxtDescForVCS:skl */ |
| 290 | /* WaEnableForceRestoreInCtxtDescForVCS:bxt */ |
| 291 | if (engine->disable_lite_restore_wa) |
| 292 | engine->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; |
| 293 | } |
| 294 | |
| 295 | /** |
| 296 | * intel_lr_context_descriptor_update() - calculate & cache the descriptor |
| 297 | * descriptor for a pinned context |
| 298 | * |
| 299 | * @ctx: Context to work on |
| 300 | * @ring: Engine the descriptor will be used with |
| 301 | * |
| 302 | * The context descriptor encodes various attributes of a context, |
| 303 | * including its GTT address and some flags. Because it's fairly |
| 304 | * expensive to calculate, we'll just do it once and cache the result, |
| 305 | * which remains valid until the context is unpinned. |
| 306 | * |
| 307 | * This is what a descriptor looks like, from LSB to MSB: |
| 308 | * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template) |
| 309 | * bits 12-31: LRCA, GTT address of (the HWSP of) this context |
| 310 | * bits 32-51: ctx ID, a globally unique tag (the LRCA again!) |
| 311 | * bits 52-63: reserved, may encode the engine ID (for GuC) |
| 312 | */ |
| 313 | static void |
| 314 | intel_lr_context_descriptor_update(struct intel_context *ctx, |
| 315 | struct intel_engine_cs *engine) |
| 316 | { |
| 317 | uint64_t lrca, desc; |
| 318 | |
| 319 | lrca = ctx->engine[engine->id].lrc_vma->node.start + |
| 320 | LRC_PPHWSP_PN * PAGE_SIZE; |
| 321 | |
| 322 | desc = engine->ctx_desc_template; /* bits 0-11 */ |
| 323 | desc |= lrca; /* bits 12-31 */ |
| 324 | desc |= (lrca >> PAGE_SHIFT) << GEN8_CTX_ID_SHIFT; /* bits 32-51 */ |
| 325 | |
| 326 | ctx->engine[engine->id].lrc_desc = desc; |
| 327 | } |
| 328 | |
| 329 | uint64_t intel_lr_context_descriptor(struct intel_context *ctx, |
| 330 | struct intel_engine_cs *engine) |
| 331 | { |
| 332 | return ctx->engine[engine->id].lrc_desc; |
| 333 | } |
| 334 | |
| 335 | /** |
| 336 | * intel_execlists_ctx_id() - get the Execlists Context ID |
| 337 | * @ctx: Context to get the ID for |
| 338 | * @ring: Engine to get the ID for |
| 339 | * |
| 340 | * Do not confuse with ctx->id! Unfortunately we have a name overload |
| 341 | * here: the old context ID we pass to userspace as a handler so that |
| 342 | * they can refer to a context, and the new context ID we pass to the |
| 343 | * ELSP so that the GPU can inform us of the context status via |
| 344 | * interrupts. |
| 345 | * |
| 346 | * The context ID is a portion of the context descriptor, so we can |
| 347 | * just extract the required part from the cached descriptor. |
| 348 | * |
| 349 | * Return: 20-bits globally unique context ID. |
| 350 | */ |
| 351 | u32 intel_execlists_ctx_id(struct intel_context *ctx, |
| 352 | struct intel_engine_cs *engine) |
| 353 | { |
| 354 | return intel_lr_context_descriptor(ctx, engine) >> GEN8_CTX_ID_SHIFT; |
| 355 | } |
| 356 | |
| 357 | static void execlists_elsp_write(struct drm_i915_gem_request *rq0, |
| 358 | struct drm_i915_gem_request *rq1) |
| 359 | { |
| 360 | |
| 361 | struct intel_engine_cs *engine = rq0->engine; |
| 362 | struct drm_device *dev = engine->dev; |
| 363 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 364 | uint64_t desc[2]; |
| 365 | |
| 366 | if (rq1) { |
| 367 | desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->engine); |
| 368 | rq1->elsp_submitted++; |
| 369 | } else { |
| 370 | desc[1] = 0; |
| 371 | } |
| 372 | |
| 373 | desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->engine); |
| 374 | rq0->elsp_submitted++; |
| 375 | |
| 376 | /* You must always write both descriptors in the order below. */ |
| 377 | I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[1])); |
| 378 | I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[1])); |
| 379 | |
| 380 | I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[0])); |
| 381 | /* The context is automatically loaded after the following */ |
| 382 | I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[0])); |
| 383 | |
| 384 | /* ELSP is a wo register, use another nearby reg for posting */ |
| 385 | POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine)); |
| 386 | } |
| 387 | |
| 388 | static void |
| 389 | execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state) |
| 390 | { |
| 391 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); |
| 392 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); |
| 393 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); |
| 394 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); |
| 395 | } |
| 396 | |
| 397 | static void execlists_update_context(struct drm_i915_gem_request *rq) |
| 398 | { |
| 399 | struct intel_engine_cs *engine = rq->engine; |
| 400 | struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt; |
| 401 | uint32_t *reg_state = rq->ctx->engine[engine->id].lrc_reg_state; |
| 402 | |
| 403 | reg_state[CTX_RING_TAIL+1] = rq->tail; |
| 404 | |
| 405 | /* True 32b PPGTT with dynamic page allocation: update PDP |
| 406 | * registers and point the unallocated PDPs to scratch page. |
| 407 | * PML4 is allocated during ppgtt init, so this is not needed |
| 408 | * in 48-bit mode. |
| 409 | */ |
| 410 | if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) |
| 411 | execlists_update_context_pdps(ppgtt, reg_state); |
| 412 | } |
| 413 | |
| 414 | static void execlists_submit_requests(struct drm_i915_gem_request *rq0, |
| 415 | struct drm_i915_gem_request *rq1) |
| 416 | { |
| 417 | struct drm_i915_private *dev_priv = rq0->i915; |
| 418 | unsigned int fw_domains = rq0->engine->fw_domains; |
| 419 | |
| 420 | execlists_update_context(rq0); |
| 421 | |
| 422 | if (rq1) |
| 423 | execlists_update_context(rq1); |
| 424 | |
| 425 | spin_lock_irq(&dev_priv->uncore.lock); |
| 426 | intel_uncore_forcewake_get__locked(dev_priv, fw_domains); |
| 427 | |
| 428 | execlists_elsp_write(rq0, rq1); |
| 429 | |
| 430 | intel_uncore_forcewake_put__locked(dev_priv, fw_domains); |
| 431 | spin_unlock_irq(&dev_priv->uncore.lock); |
| 432 | } |
| 433 | |
| 434 | static void execlists_context_unqueue(struct intel_engine_cs *engine) |
| 435 | { |
| 436 | struct drm_i915_gem_request *req0 = NULL, *req1 = NULL; |
| 437 | struct drm_i915_gem_request *cursor, *tmp; |
| 438 | |
| 439 | assert_spin_locked(&engine->execlist_lock); |
| 440 | |
| 441 | /* |
| 442 | * If irqs are not active generate a warning as batches that finish |
| 443 | * without the irqs may get lost and a GPU Hang may occur. |
| 444 | */ |
| 445 | WARN_ON(!intel_irqs_enabled(engine->dev->dev_private)); |
| 446 | |
| 447 | /* Try to read in pairs */ |
| 448 | list_for_each_entry_safe(cursor, tmp, &engine->execlist_queue, |
| 449 | execlist_link) { |
| 450 | if (!req0) { |
| 451 | req0 = cursor; |
| 452 | } else if (req0->ctx == cursor->ctx) { |
| 453 | /* Same ctx: ignore first request, as second request |
| 454 | * will update tail past first request's workload */ |
| 455 | cursor->elsp_submitted = req0->elsp_submitted; |
| 456 | list_move_tail(&req0->execlist_link, |
| 457 | &engine->execlist_retired_req_list); |
| 458 | req0 = cursor; |
| 459 | } else { |
| 460 | req1 = cursor; |
| 461 | WARN_ON(req1->elsp_submitted); |
| 462 | break; |
| 463 | } |
| 464 | } |
| 465 | |
| 466 | if (unlikely(!req0)) |
| 467 | return; |
| 468 | |
| 469 | if (req0->elsp_submitted & engine->idle_lite_restore_wa) { |
| 470 | /* |
| 471 | * WaIdleLiteRestore: make sure we never cause a lite restore |
| 472 | * with HEAD==TAIL. |
| 473 | * |
| 474 | * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we |
| 475 | * resubmit the request. See gen8_emit_request() for where we |
| 476 | * prepare the padding after the end of the request. |
| 477 | */ |
| 478 | struct intel_ringbuffer *ringbuf; |
| 479 | |
| 480 | ringbuf = req0->ctx->engine[engine->id].ringbuf; |
| 481 | req0->tail += 8; |
| 482 | req0->tail &= ringbuf->size - 1; |
| 483 | } |
| 484 | |
| 485 | execlists_submit_requests(req0, req1); |
| 486 | } |
| 487 | |
| 488 | static unsigned int |
| 489 | execlists_check_remove_request(struct intel_engine_cs *engine, u32 request_id) |
| 490 | { |
| 491 | struct drm_i915_gem_request *head_req; |
| 492 | |
| 493 | assert_spin_locked(&engine->execlist_lock); |
| 494 | |
| 495 | head_req = list_first_entry_or_null(&engine->execlist_queue, |
| 496 | struct drm_i915_gem_request, |
| 497 | execlist_link); |
| 498 | |
| 499 | if (!head_req) |
| 500 | return 0; |
| 501 | |
| 502 | if (unlikely(intel_execlists_ctx_id(head_req->ctx, engine) != request_id)) |
| 503 | return 0; |
| 504 | |
| 505 | WARN(head_req->elsp_submitted == 0, "Never submitted head request\n"); |
| 506 | |
| 507 | if (--head_req->elsp_submitted > 0) |
| 508 | return 0; |
| 509 | |
| 510 | list_move_tail(&head_req->execlist_link, |
| 511 | &engine->execlist_retired_req_list); |
| 512 | |
| 513 | return 1; |
| 514 | } |
| 515 | |
| 516 | static u32 |
| 517 | get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer, |
| 518 | u32 *context_id) |
| 519 | { |
| 520 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
| 521 | u32 status; |
| 522 | |
| 523 | read_pointer %= GEN8_CSB_ENTRIES; |
| 524 | |
| 525 | status = I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine, read_pointer)); |
| 526 | |
| 527 | if (status & GEN8_CTX_STATUS_IDLE_ACTIVE) |
| 528 | return 0; |
| 529 | |
| 530 | *context_id = I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine, |
| 531 | read_pointer)); |
| 532 | |
| 533 | return status; |
| 534 | } |
| 535 | |
| 536 | /** |
| 537 | * intel_lrc_irq_handler() - handle Context Switch interrupts |
| 538 | * @engine: Engine Command Streamer to handle. |
| 539 | * |
| 540 | * Check the unread Context Status Buffers and manage the submission of new |
| 541 | * contexts to the ELSP accordingly. |
| 542 | */ |
| 543 | static void intel_lrc_irq_handler(unsigned long data) |
| 544 | { |
| 545 | struct intel_engine_cs *engine = (struct intel_engine_cs *)data; |
| 546 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
| 547 | u32 status_pointer; |
| 548 | unsigned int read_pointer, write_pointer; |
| 549 | u32 csb[GEN8_CSB_ENTRIES][2]; |
| 550 | unsigned int csb_read = 0, i; |
| 551 | unsigned int submit_contexts = 0; |
| 552 | |
| 553 | intel_uncore_forcewake_get(dev_priv, engine->fw_domains); |
| 554 | |
| 555 | status_pointer = I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine)); |
| 556 | |
| 557 | read_pointer = engine->next_context_status_buffer; |
| 558 | write_pointer = GEN8_CSB_WRITE_PTR(status_pointer); |
| 559 | if (read_pointer > write_pointer) |
| 560 | write_pointer += GEN8_CSB_ENTRIES; |
| 561 | |
| 562 | while (read_pointer < write_pointer) { |
| 563 | if (WARN_ON_ONCE(csb_read == GEN8_CSB_ENTRIES)) |
| 564 | break; |
| 565 | csb[csb_read][0] = get_context_status(engine, ++read_pointer, |
| 566 | &csb[csb_read][1]); |
| 567 | csb_read++; |
| 568 | } |
| 569 | |
| 570 | engine->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES; |
| 571 | |
| 572 | /* Update the read pointer to the old write pointer. Manual ringbuffer |
| 573 | * management ftw </sarcasm> */ |
| 574 | I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine), |
| 575 | _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, |
| 576 | engine->next_context_status_buffer << 8)); |
| 577 | |
| 578 | intel_uncore_forcewake_put(dev_priv, engine->fw_domains); |
| 579 | |
| 580 | spin_lock(&engine->execlist_lock); |
| 581 | |
| 582 | for (i = 0; i < csb_read; i++) { |
| 583 | if (unlikely(csb[i][0] & GEN8_CTX_STATUS_PREEMPTED)) { |
| 584 | if (csb[i][0] & GEN8_CTX_STATUS_LITE_RESTORE) { |
| 585 | if (execlists_check_remove_request(engine, csb[i][1])) |
| 586 | WARN(1, "Lite Restored request removed from queue\n"); |
| 587 | } else |
| 588 | WARN(1, "Preemption without Lite Restore\n"); |
| 589 | } |
| 590 | |
| 591 | if (csb[i][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE | |
| 592 | GEN8_CTX_STATUS_ELEMENT_SWITCH)) |
| 593 | submit_contexts += |
| 594 | execlists_check_remove_request(engine, csb[i][1]); |
| 595 | } |
| 596 | |
| 597 | if (submit_contexts) { |
| 598 | if (!engine->disable_lite_restore_wa || |
| 599 | (csb[i][0] & GEN8_CTX_STATUS_ACTIVE_IDLE)) |
| 600 | execlists_context_unqueue(engine); |
| 601 | } |
| 602 | |
| 603 | spin_unlock(&engine->execlist_lock); |
| 604 | |
| 605 | if (unlikely(submit_contexts > 2)) |
| 606 | DRM_ERROR("More than two context complete events?\n"); |
| 607 | } |
| 608 | |
| 609 | static void execlists_context_queue(struct drm_i915_gem_request *request) |
| 610 | { |
| 611 | struct intel_engine_cs *engine = request->engine; |
| 612 | struct drm_i915_gem_request *cursor; |
| 613 | int num_elements = 0; |
| 614 | |
| 615 | if (request->ctx != request->i915->kernel_context) |
| 616 | intel_lr_context_pin(request->ctx, engine); |
| 617 | |
| 618 | i915_gem_request_reference(request); |
| 619 | |
| 620 | spin_lock_bh(&engine->execlist_lock); |
| 621 | |
| 622 | list_for_each_entry(cursor, &engine->execlist_queue, execlist_link) |
| 623 | if (++num_elements > 2) |
| 624 | break; |
| 625 | |
| 626 | if (num_elements > 2) { |
| 627 | struct drm_i915_gem_request *tail_req; |
| 628 | |
| 629 | tail_req = list_last_entry(&engine->execlist_queue, |
| 630 | struct drm_i915_gem_request, |
| 631 | execlist_link); |
| 632 | |
| 633 | if (request->ctx == tail_req->ctx) { |
| 634 | WARN(tail_req->elsp_submitted != 0, |
| 635 | "More than 2 already-submitted reqs queued\n"); |
| 636 | list_move_tail(&tail_req->execlist_link, |
| 637 | &engine->execlist_retired_req_list); |
| 638 | } |
| 639 | } |
| 640 | |
| 641 | list_add_tail(&request->execlist_link, &engine->execlist_queue); |
| 642 | if (num_elements == 0) |
| 643 | execlists_context_unqueue(engine); |
| 644 | |
| 645 | spin_unlock_bh(&engine->execlist_lock); |
| 646 | } |
| 647 | |
| 648 | static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req) |
| 649 | { |
| 650 | struct intel_engine_cs *engine = req->engine; |
| 651 | uint32_t flush_domains; |
| 652 | int ret; |
| 653 | |
| 654 | flush_domains = 0; |
| 655 | if (engine->gpu_caches_dirty) |
| 656 | flush_domains = I915_GEM_GPU_DOMAINS; |
| 657 | |
| 658 | ret = engine->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
| 659 | if (ret) |
| 660 | return ret; |
| 661 | |
| 662 | engine->gpu_caches_dirty = false; |
| 663 | return 0; |
| 664 | } |
| 665 | |
| 666 | static int execlists_move_to_gpu(struct drm_i915_gem_request *req, |
| 667 | struct list_head *vmas) |
| 668 | { |
| 669 | const unsigned other_rings = ~intel_engine_flag(req->engine); |
| 670 | struct i915_vma *vma; |
| 671 | uint32_t flush_domains = 0; |
| 672 | bool flush_chipset = false; |
| 673 | int ret; |
| 674 | |
| 675 | list_for_each_entry(vma, vmas, exec_list) { |
| 676 | struct drm_i915_gem_object *obj = vma->obj; |
| 677 | |
| 678 | if (obj->active & other_rings) { |
| 679 | ret = i915_gem_object_sync(obj, req->engine, &req); |
| 680 | if (ret) |
| 681 | return ret; |
| 682 | } |
| 683 | |
| 684 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) |
| 685 | flush_chipset |= i915_gem_clflush_object(obj, false); |
| 686 | |
| 687 | flush_domains |= obj->base.write_domain; |
| 688 | } |
| 689 | |
| 690 | if (flush_domains & I915_GEM_DOMAIN_GTT) |
| 691 | wmb(); |
| 692 | |
| 693 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
| 694 | * any residual writes from the previous batch. |
| 695 | */ |
| 696 | return logical_ring_invalidate_all_caches(req); |
| 697 | } |
| 698 | |
| 699 | int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
| 700 | { |
| 701 | int ret = 0; |
| 702 | |
| 703 | request->ringbuf = request->ctx->engine[request->engine->id].ringbuf; |
| 704 | |
| 705 | if (i915.enable_guc_submission) { |
| 706 | /* |
| 707 | * Check that the GuC has space for the request before |
| 708 | * going any further, as the i915_add_request() call |
| 709 | * later on mustn't fail ... |
| 710 | */ |
| 711 | struct intel_guc *guc = &request->i915->guc; |
| 712 | |
| 713 | ret = i915_guc_wq_check_space(guc->execbuf_client); |
| 714 | if (ret) |
| 715 | return ret; |
| 716 | } |
| 717 | |
| 718 | if (request->ctx != request->i915->kernel_context) |
| 719 | ret = intel_lr_context_pin(request->ctx, request->engine); |
| 720 | |
| 721 | return ret; |
| 722 | } |
| 723 | |
| 724 | static int logical_ring_wait_for_space(struct drm_i915_gem_request *req, |
| 725 | int bytes) |
| 726 | { |
| 727 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
| 728 | struct intel_engine_cs *engine = req->engine; |
| 729 | struct drm_i915_gem_request *target; |
| 730 | unsigned space; |
| 731 | int ret; |
| 732 | |
| 733 | if (intel_ring_space(ringbuf) >= bytes) |
| 734 | return 0; |
| 735 | |
| 736 | /* The whole point of reserving space is to not wait! */ |
| 737 | WARN_ON(ringbuf->reserved_in_use); |
| 738 | |
| 739 | list_for_each_entry(target, &engine->request_list, list) { |
| 740 | /* |
| 741 | * The request queue is per-engine, so can contain requests |
| 742 | * from multiple ringbuffers. Here, we must ignore any that |
| 743 | * aren't from the ringbuffer we're considering. |
| 744 | */ |
| 745 | if (target->ringbuf != ringbuf) |
| 746 | continue; |
| 747 | |
| 748 | /* Would completion of this request free enough space? */ |
| 749 | space = __intel_ring_space(target->postfix, ringbuf->tail, |
| 750 | ringbuf->size); |
| 751 | if (space >= bytes) |
| 752 | break; |
| 753 | } |
| 754 | |
| 755 | if (WARN_ON(&target->list == &engine->request_list)) |
| 756 | return -ENOSPC; |
| 757 | |
| 758 | ret = i915_wait_request(target); |
| 759 | if (ret) |
| 760 | return ret; |
| 761 | |
| 762 | ringbuf->space = space; |
| 763 | return 0; |
| 764 | } |
| 765 | |
| 766 | /* |
| 767 | * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload |
| 768 | * @request: Request to advance the logical ringbuffer of. |
| 769 | * |
| 770 | * The tail is updated in our logical ringbuffer struct, not in the actual context. What |
| 771 | * really happens during submission is that the context and current tail will be placed |
| 772 | * on a queue waiting for the ELSP to be ready to accept a new context submission. At that |
| 773 | * point, the tail *inside* the context is updated and the ELSP written to. |
| 774 | */ |
| 775 | static int |
| 776 | intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request) |
| 777 | { |
| 778 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
| 779 | struct drm_i915_private *dev_priv = request->i915; |
| 780 | struct intel_engine_cs *engine = request->engine; |
| 781 | |
| 782 | intel_logical_ring_advance(ringbuf); |
| 783 | request->tail = ringbuf->tail; |
| 784 | |
| 785 | /* |
| 786 | * Here we add two extra NOOPs as padding to avoid |
| 787 | * lite restore of a context with HEAD==TAIL. |
| 788 | * |
| 789 | * Caller must reserve WA_TAIL_DWORDS for us! |
| 790 | */ |
| 791 | intel_logical_ring_emit(ringbuf, MI_NOOP); |
| 792 | intel_logical_ring_emit(ringbuf, MI_NOOP); |
| 793 | intel_logical_ring_advance(ringbuf); |
| 794 | |
| 795 | if (intel_engine_stopped(engine)) |
| 796 | return 0; |
| 797 | |
| 798 | if (engine->last_context != request->ctx) { |
| 799 | if (engine->last_context) |
| 800 | intel_lr_context_unpin(engine->last_context, engine); |
| 801 | if (request->ctx != request->i915->kernel_context) { |
| 802 | intel_lr_context_pin(request->ctx, engine); |
| 803 | engine->last_context = request->ctx; |
| 804 | } else { |
| 805 | engine->last_context = NULL; |
| 806 | } |
| 807 | } |
| 808 | |
| 809 | if (dev_priv->guc.execbuf_client) |
| 810 | i915_guc_submit(dev_priv->guc.execbuf_client, request); |
| 811 | else |
| 812 | execlists_context_queue(request); |
| 813 | |
| 814 | return 0; |
| 815 | } |
| 816 | |
| 817 | static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf) |
| 818 | { |
| 819 | uint32_t __iomem *virt; |
| 820 | int rem = ringbuf->size - ringbuf->tail; |
| 821 | |
| 822 | virt = ringbuf->virtual_start + ringbuf->tail; |
| 823 | rem /= 4; |
| 824 | while (rem--) |
| 825 | iowrite32(MI_NOOP, virt++); |
| 826 | |
| 827 | ringbuf->tail = 0; |
| 828 | intel_ring_update_space(ringbuf); |
| 829 | } |
| 830 | |
| 831 | static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes) |
| 832 | { |
| 833 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
| 834 | int remain_usable = ringbuf->effective_size - ringbuf->tail; |
| 835 | int remain_actual = ringbuf->size - ringbuf->tail; |
| 836 | int ret, total_bytes, wait_bytes = 0; |
| 837 | bool need_wrap = false; |
| 838 | |
| 839 | if (ringbuf->reserved_in_use) |
| 840 | total_bytes = bytes; |
| 841 | else |
| 842 | total_bytes = bytes + ringbuf->reserved_size; |
| 843 | |
| 844 | if (unlikely(bytes > remain_usable)) { |
| 845 | /* |
| 846 | * Not enough space for the basic request. So need to flush |
| 847 | * out the remainder and then wait for base + reserved. |
| 848 | */ |
| 849 | wait_bytes = remain_actual + total_bytes; |
| 850 | need_wrap = true; |
| 851 | } else { |
| 852 | if (unlikely(total_bytes > remain_usable)) { |
| 853 | /* |
| 854 | * The base request will fit but the reserved space |
| 855 | * falls off the end. So don't need an immediate wrap |
| 856 | * and only need to effectively wait for the reserved |
| 857 | * size space from the start of ringbuffer. |
| 858 | */ |
| 859 | wait_bytes = remain_actual + ringbuf->reserved_size; |
| 860 | } else if (total_bytes > ringbuf->space) { |
| 861 | /* No wrapping required, just waiting. */ |
| 862 | wait_bytes = total_bytes; |
| 863 | } |
| 864 | } |
| 865 | |
| 866 | if (wait_bytes) { |
| 867 | ret = logical_ring_wait_for_space(req, wait_bytes); |
| 868 | if (unlikely(ret)) |
| 869 | return ret; |
| 870 | |
| 871 | if (need_wrap) |
| 872 | __wrap_ring_buffer(ringbuf); |
| 873 | } |
| 874 | |
| 875 | return 0; |
| 876 | } |
| 877 | |
| 878 | /** |
| 879 | * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands |
| 880 | * |
| 881 | * @req: The request to start some new work for |
| 882 | * @num_dwords: number of DWORDs that we plan to write to the ringbuffer. |
| 883 | * |
| 884 | * The ringbuffer might not be ready to accept the commands right away (maybe it needs to |
| 885 | * be wrapped, or wait a bit for the tail to be updated). This function takes care of that |
| 886 | * and also preallocates a request (every workload submission is still mediated through |
| 887 | * requests, same as it did with legacy ringbuffer submission). |
| 888 | * |
| 889 | * Return: non-zero if the ringbuffer is not ready to be written to. |
| 890 | */ |
| 891 | int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
| 892 | { |
| 893 | int ret; |
| 894 | |
| 895 | WARN_ON(req == NULL); |
| 896 | |
| 897 | ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t)); |
| 898 | if (ret) |
| 899 | return ret; |
| 900 | |
| 901 | req->ringbuf->space -= num_dwords * sizeof(uint32_t); |
| 902 | return 0; |
| 903 | } |
| 904 | |
| 905 | int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request) |
| 906 | { |
| 907 | /* |
| 908 | * The first call merely notes the reserve request and is common for |
| 909 | * all back ends. The subsequent localised _begin() call actually |
| 910 | * ensures that the reservation is available. Without the begin, if |
| 911 | * the request creator immediately submitted the request without |
| 912 | * adding any commands to it then there might not actually be |
| 913 | * sufficient room for the submission commands. |
| 914 | */ |
| 915 | intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST); |
| 916 | |
| 917 | return intel_logical_ring_begin(request, 0); |
| 918 | } |
| 919 | |
| 920 | /** |
| 921 | * execlists_submission() - submit a batchbuffer for execution, Execlists style |
| 922 | * @dev: DRM device. |
| 923 | * @file: DRM file. |
| 924 | * @ring: Engine Command Streamer to submit to. |
| 925 | * @ctx: Context to employ for this submission. |
| 926 | * @args: execbuffer call arguments. |
| 927 | * @vmas: list of vmas. |
| 928 | * @batch_obj: the batchbuffer to submit. |
| 929 | * @exec_start: batchbuffer start virtual address pointer. |
| 930 | * @dispatch_flags: translated execbuffer call flags. |
| 931 | * |
| 932 | * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts |
| 933 | * away the submission details of the execbuffer ioctl call. |
| 934 | * |
| 935 | * Return: non-zero if the submission fails. |
| 936 | */ |
| 937 | int intel_execlists_submission(struct i915_execbuffer_params *params, |
| 938 | struct drm_i915_gem_execbuffer2 *args, |
| 939 | struct list_head *vmas) |
| 940 | { |
| 941 | struct drm_device *dev = params->dev; |
| 942 | struct intel_engine_cs *engine = params->engine; |
| 943 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 944 | struct intel_ringbuffer *ringbuf = params->ctx->engine[engine->id].ringbuf; |
| 945 | u64 exec_start; |
| 946 | int instp_mode; |
| 947 | u32 instp_mask; |
| 948 | int ret; |
| 949 | |
| 950 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
| 951 | instp_mask = I915_EXEC_CONSTANTS_MASK; |
| 952 | switch (instp_mode) { |
| 953 | case I915_EXEC_CONSTANTS_REL_GENERAL: |
| 954 | case I915_EXEC_CONSTANTS_ABSOLUTE: |
| 955 | case I915_EXEC_CONSTANTS_REL_SURFACE: |
| 956 | if (instp_mode != 0 && engine != &dev_priv->engine[RCS]) { |
| 957 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); |
| 958 | return -EINVAL; |
| 959 | } |
| 960 | |
| 961 | if (instp_mode != dev_priv->relative_constants_mode) { |
| 962 | if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { |
| 963 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); |
| 964 | return -EINVAL; |
| 965 | } |
| 966 | |
| 967 | /* The HW changed the meaning on this bit on gen6 */ |
| 968 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; |
| 969 | } |
| 970 | break; |
| 971 | default: |
| 972 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); |
| 973 | return -EINVAL; |
| 974 | } |
| 975 | |
| 976 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
| 977 | DRM_DEBUG("sol reset is gen7 only\n"); |
| 978 | return -EINVAL; |
| 979 | } |
| 980 | |
| 981 | ret = execlists_move_to_gpu(params->request, vmas); |
| 982 | if (ret) |
| 983 | return ret; |
| 984 | |
| 985 | if (engine == &dev_priv->engine[RCS] && |
| 986 | instp_mode != dev_priv->relative_constants_mode) { |
| 987 | ret = intel_logical_ring_begin(params->request, 4); |
| 988 | if (ret) |
| 989 | return ret; |
| 990 | |
| 991 | intel_logical_ring_emit(ringbuf, MI_NOOP); |
| 992 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1)); |
| 993 | intel_logical_ring_emit_reg(ringbuf, INSTPM); |
| 994 | intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode); |
| 995 | intel_logical_ring_advance(ringbuf); |
| 996 | |
| 997 | dev_priv->relative_constants_mode = instp_mode; |
| 998 | } |
| 999 | |
| 1000 | exec_start = params->batch_obj_vm_offset + |
| 1001 | args->batch_start_offset; |
| 1002 | |
| 1003 | ret = engine->emit_bb_start(params->request, exec_start, params->dispatch_flags); |
| 1004 | if (ret) |
| 1005 | return ret; |
| 1006 | |
| 1007 | trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags); |
| 1008 | |
| 1009 | i915_gem_execbuffer_move_to_active(vmas, params->request); |
| 1010 | i915_gem_execbuffer_retire_commands(params); |
| 1011 | |
| 1012 | return 0; |
| 1013 | } |
| 1014 | |
| 1015 | void intel_execlists_retire_requests(struct intel_engine_cs *engine) |
| 1016 | { |
| 1017 | struct drm_i915_gem_request *req, *tmp; |
| 1018 | struct list_head retired_list; |
| 1019 | |
| 1020 | WARN_ON(!mutex_is_locked(&engine->dev->struct_mutex)); |
| 1021 | if (list_empty(&engine->execlist_retired_req_list)) |
| 1022 | return; |
| 1023 | |
| 1024 | INIT_LIST_HEAD(&retired_list); |
| 1025 | spin_lock_bh(&engine->execlist_lock); |
| 1026 | list_replace_init(&engine->execlist_retired_req_list, &retired_list); |
| 1027 | spin_unlock_bh(&engine->execlist_lock); |
| 1028 | |
| 1029 | list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) { |
| 1030 | struct intel_context *ctx = req->ctx; |
| 1031 | struct drm_i915_gem_object *ctx_obj = |
| 1032 | ctx->engine[engine->id].state; |
| 1033 | |
| 1034 | if (ctx_obj && (ctx != req->i915->kernel_context)) |
| 1035 | intel_lr_context_unpin(ctx, engine); |
| 1036 | |
| 1037 | list_del(&req->execlist_link); |
| 1038 | i915_gem_request_unreference(req); |
| 1039 | } |
| 1040 | } |
| 1041 | |
| 1042 | void intel_logical_ring_stop(struct intel_engine_cs *engine) |
| 1043 | { |
| 1044 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
| 1045 | int ret; |
| 1046 | |
| 1047 | if (!intel_engine_initialized(engine)) |
| 1048 | return; |
| 1049 | |
| 1050 | ret = intel_engine_idle(engine); |
| 1051 | if (ret && !i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) |
| 1052 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
| 1053 | engine->name, ret); |
| 1054 | |
| 1055 | /* TODO: Is this correct with Execlists enabled? */ |
| 1056 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
| 1057 | if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) { |
| 1058 | DRM_ERROR("%s :timed out trying to stop ring\n", engine->name); |
| 1059 | return; |
| 1060 | } |
| 1061 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); |
| 1062 | } |
| 1063 | |
| 1064 | int logical_ring_flush_all_caches(struct drm_i915_gem_request *req) |
| 1065 | { |
| 1066 | struct intel_engine_cs *engine = req->engine; |
| 1067 | int ret; |
| 1068 | |
| 1069 | if (!engine->gpu_caches_dirty) |
| 1070 | return 0; |
| 1071 | |
| 1072 | ret = engine->emit_flush(req, 0, I915_GEM_GPU_DOMAINS); |
| 1073 | if (ret) |
| 1074 | return ret; |
| 1075 | |
| 1076 | engine->gpu_caches_dirty = false; |
| 1077 | return 0; |
| 1078 | } |
| 1079 | |
| 1080 | static int intel_lr_context_do_pin(struct intel_context *ctx, |
| 1081 | struct intel_engine_cs *engine) |
| 1082 | { |
| 1083 | struct drm_device *dev = engine->dev; |
| 1084 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1085 | struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state; |
| 1086 | struct intel_ringbuffer *ringbuf = ctx->engine[engine->id].ringbuf; |
| 1087 | void *vaddr; |
| 1088 | u32 *lrc_reg_state; |
| 1089 | int ret; |
| 1090 | |
| 1091 | WARN_ON(!mutex_is_locked(&engine->dev->struct_mutex)); |
| 1092 | |
| 1093 | ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, |
| 1094 | PIN_OFFSET_BIAS | GUC_WOPCM_TOP); |
| 1095 | if (ret) |
| 1096 | return ret; |
| 1097 | |
| 1098 | vaddr = i915_gem_object_pin_map(ctx_obj); |
| 1099 | if (IS_ERR(vaddr)) { |
| 1100 | ret = PTR_ERR(vaddr); |
| 1101 | goto unpin_ctx_obj; |
| 1102 | } |
| 1103 | |
| 1104 | lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
| 1105 | |
| 1106 | ret = intel_pin_and_map_ringbuffer_obj(engine->dev, ringbuf); |
| 1107 | if (ret) |
| 1108 | goto unpin_map; |
| 1109 | |
| 1110 | ctx->engine[engine->id].lrc_vma = i915_gem_obj_to_ggtt(ctx_obj); |
| 1111 | intel_lr_context_descriptor_update(ctx, engine); |
| 1112 | lrc_reg_state[CTX_RING_BUFFER_START+1] = ringbuf->vma->node.start; |
| 1113 | ctx->engine[engine->id].lrc_reg_state = lrc_reg_state; |
| 1114 | ctx_obj->dirty = true; |
| 1115 | |
| 1116 | /* Invalidate GuC TLB. */ |
| 1117 | if (i915.enable_guc_submission) |
| 1118 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); |
| 1119 | |
| 1120 | return ret; |
| 1121 | |
| 1122 | unpin_map: |
| 1123 | i915_gem_object_unpin_map(ctx_obj); |
| 1124 | unpin_ctx_obj: |
| 1125 | i915_gem_object_ggtt_unpin(ctx_obj); |
| 1126 | |
| 1127 | return ret; |
| 1128 | } |
| 1129 | |
| 1130 | static int intel_lr_context_pin(struct intel_context *ctx, |
| 1131 | struct intel_engine_cs *engine) |
| 1132 | { |
| 1133 | int ret = 0; |
| 1134 | |
| 1135 | if (ctx->engine[engine->id].pin_count++ == 0) { |
| 1136 | ret = intel_lr_context_do_pin(ctx, engine); |
| 1137 | if (ret) |
| 1138 | goto reset_pin_count; |
| 1139 | |
| 1140 | i915_gem_context_reference(ctx); |
| 1141 | } |
| 1142 | return ret; |
| 1143 | |
| 1144 | reset_pin_count: |
| 1145 | ctx->engine[engine->id].pin_count = 0; |
| 1146 | return ret; |
| 1147 | } |
| 1148 | |
| 1149 | void intel_lr_context_unpin(struct intel_context *ctx, |
| 1150 | struct intel_engine_cs *engine) |
| 1151 | { |
| 1152 | struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state; |
| 1153 | |
| 1154 | WARN_ON(!mutex_is_locked(&ctx->i915->dev->struct_mutex)); |
| 1155 | if (--ctx->engine[engine->id].pin_count == 0) { |
| 1156 | i915_gem_object_unpin_map(ctx_obj); |
| 1157 | intel_unpin_ringbuffer_obj(ctx->engine[engine->id].ringbuf); |
| 1158 | i915_gem_object_ggtt_unpin(ctx_obj); |
| 1159 | ctx->engine[engine->id].lrc_vma = NULL; |
| 1160 | ctx->engine[engine->id].lrc_desc = 0; |
| 1161 | ctx->engine[engine->id].lrc_reg_state = NULL; |
| 1162 | |
| 1163 | i915_gem_context_unreference(ctx); |
| 1164 | } |
| 1165 | } |
| 1166 | |
| 1167 | static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req) |
| 1168 | { |
| 1169 | int ret, i; |
| 1170 | struct intel_engine_cs *engine = req->engine; |
| 1171 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
| 1172 | struct drm_device *dev = engine->dev; |
| 1173 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1174 | struct i915_workarounds *w = &dev_priv->workarounds; |
| 1175 | |
| 1176 | if (w->count == 0) |
| 1177 | return 0; |
| 1178 | |
| 1179 | engine->gpu_caches_dirty = true; |
| 1180 | ret = logical_ring_flush_all_caches(req); |
| 1181 | if (ret) |
| 1182 | return ret; |
| 1183 | |
| 1184 | ret = intel_logical_ring_begin(req, w->count * 2 + 2); |
| 1185 | if (ret) |
| 1186 | return ret; |
| 1187 | |
| 1188 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count)); |
| 1189 | for (i = 0; i < w->count; i++) { |
| 1190 | intel_logical_ring_emit_reg(ringbuf, w->reg[i].addr); |
| 1191 | intel_logical_ring_emit(ringbuf, w->reg[i].value); |
| 1192 | } |
| 1193 | intel_logical_ring_emit(ringbuf, MI_NOOP); |
| 1194 | |
| 1195 | intel_logical_ring_advance(ringbuf); |
| 1196 | |
| 1197 | engine->gpu_caches_dirty = true; |
| 1198 | ret = logical_ring_flush_all_caches(req); |
| 1199 | if (ret) |
| 1200 | return ret; |
| 1201 | |
| 1202 | return 0; |
| 1203 | } |
| 1204 | |
| 1205 | #define wa_ctx_emit(batch, index, cmd) \ |
| 1206 | do { \ |
| 1207 | int __index = (index)++; \ |
| 1208 | if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \ |
| 1209 | return -ENOSPC; \ |
| 1210 | } \ |
| 1211 | batch[__index] = (cmd); \ |
| 1212 | } while (0) |
| 1213 | |
| 1214 | #define wa_ctx_emit_reg(batch, index, reg) \ |
| 1215 | wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg)) |
| 1216 | |
| 1217 | /* |
| 1218 | * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after |
| 1219 | * PIPE_CONTROL instruction. This is required for the flush to happen correctly |
| 1220 | * but there is a slight complication as this is applied in WA batch where the |
| 1221 | * values are only initialized once so we cannot take register value at the |
| 1222 | * beginning and reuse it further; hence we save its value to memory, upload a |
| 1223 | * constant value with bit21 set and then we restore it back with the saved value. |
| 1224 | * To simplify the WA, a constant value is formed by using the default value |
| 1225 | * of this register. This shouldn't be a problem because we are only modifying |
| 1226 | * it for a short period and this batch in non-premptible. We can ofcourse |
| 1227 | * use additional instructions that read the actual value of the register |
| 1228 | * at that time and set our bit of interest but it makes the WA complicated. |
| 1229 | * |
| 1230 | * This WA is also required for Gen9 so extracting as a function avoids |
| 1231 | * code duplication. |
| 1232 | */ |
| 1233 | static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, |
| 1234 | uint32_t *const batch, |
| 1235 | uint32_t index) |
| 1236 | { |
| 1237 | uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES); |
| 1238 | |
| 1239 | /* |
| 1240 | * WaDisableLSQCROPERFforOCL:skl |
| 1241 | * This WA is implemented in skl_init_clock_gating() but since |
| 1242 | * this batch updates GEN8_L3SQCREG4 with default value we need to |
| 1243 | * set this bit here to retain the WA during flush. |
| 1244 | */ |
| 1245 | if (IS_SKL_REVID(engine->dev, 0, SKL_REVID_E0)) |
| 1246 | l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS; |
| 1247 | |
| 1248 | wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 | |
| 1249 | MI_SRM_LRM_GLOBAL_GTT)); |
| 1250 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
| 1251 | wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256); |
| 1252 | wa_ctx_emit(batch, index, 0); |
| 1253 | |
| 1254 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); |
| 1255 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
| 1256 | wa_ctx_emit(batch, index, l3sqc4_flush); |
| 1257 | |
| 1258 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); |
| 1259 | wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | |
| 1260 | PIPE_CONTROL_DC_FLUSH_ENABLE)); |
| 1261 | wa_ctx_emit(batch, index, 0); |
| 1262 | wa_ctx_emit(batch, index, 0); |
| 1263 | wa_ctx_emit(batch, index, 0); |
| 1264 | wa_ctx_emit(batch, index, 0); |
| 1265 | |
| 1266 | wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 | |
| 1267 | MI_SRM_LRM_GLOBAL_GTT)); |
| 1268 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
| 1269 | wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256); |
| 1270 | wa_ctx_emit(batch, index, 0); |
| 1271 | |
| 1272 | return index; |
| 1273 | } |
| 1274 | |
| 1275 | static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx, |
| 1276 | uint32_t offset, |
| 1277 | uint32_t start_alignment) |
| 1278 | { |
| 1279 | return wa_ctx->offset = ALIGN(offset, start_alignment); |
| 1280 | } |
| 1281 | |
| 1282 | static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx, |
| 1283 | uint32_t offset, |
| 1284 | uint32_t size_alignment) |
| 1285 | { |
| 1286 | wa_ctx->size = offset - wa_ctx->offset; |
| 1287 | |
| 1288 | WARN(wa_ctx->size % size_alignment, |
| 1289 | "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n", |
| 1290 | wa_ctx->size, size_alignment); |
| 1291 | return 0; |
| 1292 | } |
| 1293 | |
| 1294 | /** |
| 1295 | * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA |
| 1296 | * |
| 1297 | * @ring: only applicable for RCS |
| 1298 | * @wa_ctx: structure representing wa_ctx |
| 1299 | * offset: specifies start of the batch, should be cache-aligned. This is updated |
| 1300 | * with the offset value received as input. |
| 1301 | * size: size of the batch in DWORDS but HW expects in terms of cachelines |
| 1302 | * @batch: page in which WA are loaded |
| 1303 | * @offset: This field specifies the start of the batch, it should be |
| 1304 | * cache-aligned otherwise it is adjusted accordingly. |
| 1305 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are |
| 1306 | * initialized at the beginning and shared across all contexts but this field |
| 1307 | * helps us to have multiple batches at different offsets and select them based |
| 1308 | * on a criteria. At the moment this batch always start at the beginning of the page |
| 1309 | * and at this point we don't have multiple wa_ctx batch buffers. |
| 1310 | * |
| 1311 | * The number of WA applied are not known at the beginning; we use this field |
| 1312 | * to return the no of DWORDS written. |
| 1313 | * |
| 1314 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
| 1315 | * so it adds NOOPs as padding to make it cacheline aligned. |
| 1316 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together |
| 1317 | * makes a complete batch buffer. |
| 1318 | * |
| 1319 | * Return: non-zero if we exceed the PAGE_SIZE limit. |
| 1320 | */ |
| 1321 | |
| 1322 | static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine, |
| 1323 | struct i915_wa_ctx_bb *wa_ctx, |
| 1324 | uint32_t *const batch, |
| 1325 | uint32_t *offset) |
| 1326 | { |
| 1327 | uint32_t scratch_addr; |
| 1328 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
| 1329 | |
| 1330 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
| 1331 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
| 1332 | |
| 1333 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
| 1334 | if (IS_BROADWELL(engine->dev)) { |
| 1335 | int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index); |
| 1336 | if (rc < 0) |
| 1337 | return rc; |
| 1338 | index = rc; |
| 1339 | } |
| 1340 | |
| 1341 | /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
| 1342 | /* Actual scratch location is at 128 bytes offset */ |
| 1343 | scratch_addr = engine->scratch.gtt_offset + 2*CACHELINE_BYTES; |
| 1344 | |
| 1345 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); |
| 1346 | wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | |
| 1347 | PIPE_CONTROL_GLOBAL_GTT_IVB | |
| 1348 | PIPE_CONTROL_CS_STALL | |
| 1349 | PIPE_CONTROL_QW_WRITE)); |
| 1350 | wa_ctx_emit(batch, index, scratch_addr); |
| 1351 | wa_ctx_emit(batch, index, 0); |
| 1352 | wa_ctx_emit(batch, index, 0); |
| 1353 | wa_ctx_emit(batch, index, 0); |
| 1354 | |
| 1355 | /* Pad to end of cacheline */ |
| 1356 | while (index % CACHELINE_DWORDS) |
| 1357 | wa_ctx_emit(batch, index, MI_NOOP); |
| 1358 | |
| 1359 | /* |
| 1360 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because |
| 1361 | * execution depends on the length specified in terms of cache lines |
| 1362 | * in the register CTX_RCS_INDIRECT_CTX |
| 1363 | */ |
| 1364 | |
| 1365 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); |
| 1366 | } |
| 1367 | |
| 1368 | /** |
| 1369 | * gen8_init_perctx_bb() - initialize per ctx batch with WA |
| 1370 | * |
| 1371 | * @ring: only applicable for RCS |
| 1372 | * @wa_ctx: structure representing wa_ctx |
| 1373 | * offset: specifies start of the batch, should be cache-aligned. |
| 1374 | * size: size of the batch in DWORDS but HW expects in terms of cachelines |
| 1375 | * @batch: page in which WA are loaded |
| 1376 | * @offset: This field specifies the start of this batch. |
| 1377 | * This batch is started immediately after indirect_ctx batch. Since we ensure |
| 1378 | * that indirect_ctx ends on a cacheline this batch is aligned automatically. |
| 1379 | * |
| 1380 | * The number of DWORDS written are returned using this field. |
| 1381 | * |
| 1382 | * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding |
| 1383 | * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. |
| 1384 | */ |
| 1385 | static int gen8_init_perctx_bb(struct intel_engine_cs *engine, |
| 1386 | struct i915_wa_ctx_bb *wa_ctx, |
| 1387 | uint32_t *const batch, |
| 1388 | uint32_t *offset) |
| 1389 | { |
| 1390 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
| 1391 | |
| 1392 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
| 1393 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
| 1394 | |
| 1395 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
| 1396 | |
| 1397 | return wa_ctx_end(wa_ctx, *offset = index, 1); |
| 1398 | } |
| 1399 | |
| 1400 | static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, |
| 1401 | struct i915_wa_ctx_bb *wa_ctx, |
| 1402 | uint32_t *const batch, |
| 1403 | uint32_t *offset) |
| 1404 | { |
| 1405 | int ret; |
| 1406 | struct drm_device *dev = engine->dev; |
| 1407 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
| 1408 | |
| 1409 | /* WaDisableCtxRestoreArbitration:skl,bxt */ |
| 1410 | if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || |
| 1411 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
| 1412 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
| 1413 | |
| 1414 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ |
| 1415 | ret = gen8_emit_flush_coherentl3_wa(engine, batch, index); |
| 1416 | if (ret < 0) |
| 1417 | return ret; |
| 1418 | index = ret; |
| 1419 | |
| 1420 | /* Pad to end of cacheline */ |
| 1421 | while (index % CACHELINE_DWORDS) |
| 1422 | wa_ctx_emit(batch, index, MI_NOOP); |
| 1423 | |
| 1424 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); |
| 1425 | } |
| 1426 | |
| 1427 | static int gen9_init_perctx_bb(struct intel_engine_cs *engine, |
| 1428 | struct i915_wa_ctx_bb *wa_ctx, |
| 1429 | uint32_t *const batch, |
| 1430 | uint32_t *offset) |
| 1431 | { |
| 1432 | struct drm_device *dev = engine->dev; |
| 1433 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
| 1434 | |
| 1435 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
| 1436 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || |
| 1437 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
| 1438 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); |
| 1439 | wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0); |
| 1440 | wa_ctx_emit(batch, index, |
| 1441 | _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING)); |
| 1442 | wa_ctx_emit(batch, index, MI_NOOP); |
| 1443 | } |
| 1444 | |
| 1445 | /* WaClearTdlStateAckDirtyBits:bxt */ |
| 1446 | if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) { |
| 1447 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4)); |
| 1448 | |
| 1449 | wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK); |
| 1450 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); |
| 1451 | |
| 1452 | wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE1); |
| 1453 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); |
| 1454 | |
| 1455 | wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE2); |
| 1456 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); |
| 1457 | |
| 1458 | wa_ctx_emit_reg(batch, index, GEN7_ROW_CHICKEN2); |
| 1459 | /* dummy write to CS, mask bits are 0 to ensure the register is not modified */ |
| 1460 | wa_ctx_emit(batch, index, 0x0); |
| 1461 | wa_ctx_emit(batch, index, MI_NOOP); |
| 1462 | } |
| 1463 | |
| 1464 | /* WaDisableCtxRestoreArbitration:skl,bxt */ |
| 1465 | if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || |
| 1466 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
| 1467 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
| 1468 | |
| 1469 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
| 1470 | |
| 1471 | return wa_ctx_end(wa_ctx, *offset = index, 1); |
| 1472 | } |
| 1473 | |
| 1474 | static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size) |
| 1475 | { |
| 1476 | int ret; |
| 1477 | |
| 1478 | engine->wa_ctx.obj = i915_gem_alloc_object(engine->dev, |
| 1479 | PAGE_ALIGN(size)); |
| 1480 | if (!engine->wa_ctx.obj) { |
| 1481 | DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n"); |
| 1482 | return -ENOMEM; |
| 1483 | } |
| 1484 | |
| 1485 | ret = i915_gem_obj_ggtt_pin(engine->wa_ctx.obj, PAGE_SIZE, 0); |
| 1486 | if (ret) { |
| 1487 | DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n", |
| 1488 | ret); |
| 1489 | drm_gem_object_unreference(&engine->wa_ctx.obj->base); |
| 1490 | return ret; |
| 1491 | } |
| 1492 | |
| 1493 | return 0; |
| 1494 | } |
| 1495 | |
| 1496 | static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine) |
| 1497 | { |
| 1498 | if (engine->wa_ctx.obj) { |
| 1499 | i915_gem_object_ggtt_unpin(engine->wa_ctx.obj); |
| 1500 | drm_gem_object_unreference(&engine->wa_ctx.obj->base); |
| 1501 | engine->wa_ctx.obj = NULL; |
| 1502 | } |
| 1503 | } |
| 1504 | |
| 1505 | static int intel_init_workaround_bb(struct intel_engine_cs *engine) |
| 1506 | { |
| 1507 | int ret; |
| 1508 | uint32_t *batch; |
| 1509 | uint32_t offset; |
| 1510 | struct page *page; |
| 1511 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
| 1512 | |
| 1513 | WARN_ON(engine->id != RCS); |
| 1514 | |
| 1515 | /* update this when WA for higher Gen are added */ |
| 1516 | if (INTEL_INFO(engine->dev)->gen > 9) { |
| 1517 | DRM_ERROR("WA batch buffer is not initialized for Gen%d\n", |
| 1518 | INTEL_INFO(engine->dev)->gen); |
| 1519 | return 0; |
| 1520 | } |
| 1521 | |
| 1522 | /* some WA perform writes to scratch page, ensure it is valid */ |
| 1523 | if (engine->scratch.obj == NULL) { |
| 1524 | DRM_ERROR("scratch page not allocated for %s\n", engine->name); |
| 1525 | return -EINVAL; |
| 1526 | } |
| 1527 | |
| 1528 | ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE); |
| 1529 | if (ret) { |
| 1530 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); |
| 1531 | return ret; |
| 1532 | } |
| 1533 | |
| 1534 | page = i915_gem_object_get_dirty_page(wa_ctx->obj, 0); |
| 1535 | batch = kmap_atomic(page); |
| 1536 | offset = 0; |
| 1537 | |
| 1538 | if (INTEL_INFO(engine->dev)->gen == 8) { |
| 1539 | ret = gen8_init_indirectctx_bb(engine, |
| 1540 | &wa_ctx->indirect_ctx, |
| 1541 | batch, |
| 1542 | &offset); |
| 1543 | if (ret) |
| 1544 | goto out; |
| 1545 | |
| 1546 | ret = gen8_init_perctx_bb(engine, |
| 1547 | &wa_ctx->per_ctx, |
| 1548 | batch, |
| 1549 | &offset); |
| 1550 | if (ret) |
| 1551 | goto out; |
| 1552 | } else if (INTEL_INFO(engine->dev)->gen == 9) { |
| 1553 | ret = gen9_init_indirectctx_bb(engine, |
| 1554 | &wa_ctx->indirect_ctx, |
| 1555 | batch, |
| 1556 | &offset); |
| 1557 | if (ret) |
| 1558 | goto out; |
| 1559 | |
| 1560 | ret = gen9_init_perctx_bb(engine, |
| 1561 | &wa_ctx->per_ctx, |
| 1562 | batch, |
| 1563 | &offset); |
| 1564 | if (ret) |
| 1565 | goto out; |
| 1566 | } |
| 1567 | |
| 1568 | out: |
| 1569 | kunmap_atomic(batch); |
| 1570 | if (ret) |
| 1571 | lrc_destroy_wa_ctx_obj(engine); |
| 1572 | |
| 1573 | return ret; |
| 1574 | } |
| 1575 | |
| 1576 | static void lrc_init_hws(struct intel_engine_cs *engine) |
| 1577 | { |
| 1578 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
| 1579 | |
| 1580 | I915_WRITE(RING_HWS_PGA(engine->mmio_base), |
| 1581 | (u32)engine->status_page.gfx_addr); |
| 1582 | POSTING_READ(RING_HWS_PGA(engine->mmio_base)); |
| 1583 | } |
| 1584 | |
| 1585 | static int gen8_init_common_ring(struct intel_engine_cs *engine) |
| 1586 | { |
| 1587 | struct drm_device *dev = engine->dev; |
| 1588 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1589 | unsigned int next_context_status_buffer_hw; |
| 1590 | |
| 1591 | lrc_init_hws(engine); |
| 1592 | |
| 1593 | I915_WRITE_IMR(engine, |
| 1594 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); |
| 1595 | I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); |
| 1596 | |
| 1597 | I915_WRITE(RING_MODE_GEN7(engine), |
| 1598 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | |
| 1599 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); |
| 1600 | POSTING_READ(RING_MODE_GEN7(engine)); |
| 1601 | |
| 1602 | /* |
| 1603 | * Instead of resetting the Context Status Buffer (CSB) read pointer to |
| 1604 | * zero, we need to read the write pointer from hardware and use its |
| 1605 | * value because "this register is power context save restored". |
| 1606 | * Effectively, these states have been observed: |
| 1607 | * |
| 1608 | * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) | |
| 1609 | * BDW | CSB regs not reset | CSB regs reset | |
| 1610 | * CHT | CSB regs not reset | CSB regs not reset | |
| 1611 | * SKL | ? | ? | |
| 1612 | * BXT | ? | ? | |
| 1613 | */ |
| 1614 | next_context_status_buffer_hw = |
| 1615 | GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine))); |
| 1616 | |
| 1617 | /* |
| 1618 | * When the CSB registers are reset (also after power-up / gpu reset), |
| 1619 | * CSB write pointer is set to all 1's, which is not valid, use '5' in |
| 1620 | * this special case, so the first element read is CSB[0]. |
| 1621 | */ |
| 1622 | if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK) |
| 1623 | next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1); |
| 1624 | |
| 1625 | engine->next_context_status_buffer = next_context_status_buffer_hw; |
| 1626 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); |
| 1627 | |
| 1628 | intel_engine_init_hangcheck(engine); |
| 1629 | |
| 1630 | return 0; |
| 1631 | } |
| 1632 | |
| 1633 | static int gen8_init_render_ring(struct intel_engine_cs *engine) |
| 1634 | { |
| 1635 | struct drm_device *dev = engine->dev; |
| 1636 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1637 | int ret; |
| 1638 | |
| 1639 | ret = gen8_init_common_ring(engine); |
| 1640 | if (ret) |
| 1641 | return ret; |
| 1642 | |
| 1643 | /* We need to disable the AsyncFlip performance optimisations in order |
| 1644 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be |
| 1645 | * programmed to '1' on all products. |
| 1646 | * |
| 1647 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv |
| 1648 | */ |
| 1649 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
| 1650 | |
| 1651 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
| 1652 | |
| 1653 | return init_workarounds_ring(engine); |
| 1654 | } |
| 1655 | |
| 1656 | static int gen9_init_render_ring(struct intel_engine_cs *engine) |
| 1657 | { |
| 1658 | int ret; |
| 1659 | |
| 1660 | ret = gen8_init_common_ring(engine); |
| 1661 | if (ret) |
| 1662 | return ret; |
| 1663 | |
| 1664 | return init_workarounds_ring(engine); |
| 1665 | } |
| 1666 | |
| 1667 | static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) |
| 1668 | { |
| 1669 | struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; |
| 1670 | struct intel_engine_cs *engine = req->engine; |
| 1671 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
| 1672 | const int num_lri_cmds = GEN8_LEGACY_PDPES * 2; |
| 1673 | int i, ret; |
| 1674 | |
| 1675 | ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2); |
| 1676 | if (ret) |
| 1677 | return ret; |
| 1678 | |
| 1679 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds)); |
| 1680 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
| 1681 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
| 1682 | |
| 1683 | intel_logical_ring_emit_reg(ringbuf, |
| 1684 | GEN8_RING_PDP_UDW(engine, i)); |
| 1685 | intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr)); |
| 1686 | intel_logical_ring_emit_reg(ringbuf, |
| 1687 | GEN8_RING_PDP_LDW(engine, i)); |
| 1688 | intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr)); |
| 1689 | } |
| 1690 | |
| 1691 | intel_logical_ring_emit(ringbuf, MI_NOOP); |
| 1692 | intel_logical_ring_advance(ringbuf); |
| 1693 | |
| 1694 | return 0; |
| 1695 | } |
| 1696 | |
| 1697 | static int gen8_emit_bb_start(struct drm_i915_gem_request *req, |
| 1698 | u64 offset, unsigned dispatch_flags) |
| 1699 | { |
| 1700 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
| 1701 | bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE); |
| 1702 | int ret; |
| 1703 | |
| 1704 | /* Don't rely in hw updating PDPs, specially in lite-restore. |
| 1705 | * Ideally, we should set Force PD Restore in ctx descriptor, |
| 1706 | * but we can't. Force Restore would be a second option, but |
| 1707 | * it is unsafe in case of lite-restore (because the ctx is |
| 1708 | * not idle). PML4 is allocated during ppgtt init so this is |
| 1709 | * not needed in 48-bit.*/ |
| 1710 | if (req->ctx->ppgtt && |
| 1711 | (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) { |
| 1712 | if (!USES_FULL_48BIT_PPGTT(req->i915) && |
| 1713 | !intel_vgpu_active(req->i915->dev)) { |
| 1714 | ret = intel_logical_ring_emit_pdps(req); |
| 1715 | if (ret) |
| 1716 | return ret; |
| 1717 | } |
| 1718 | |
| 1719 | req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine); |
| 1720 | } |
| 1721 | |
| 1722 | ret = intel_logical_ring_begin(req, 4); |
| 1723 | if (ret) |
| 1724 | return ret; |
| 1725 | |
| 1726 | /* FIXME(BDW): Address space and security selectors. */ |
| 1727 | intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | |
| 1728 | (ppgtt<<8) | |
| 1729 | (dispatch_flags & I915_DISPATCH_RS ? |
| 1730 | MI_BATCH_RESOURCE_STREAMER : 0)); |
| 1731 | intel_logical_ring_emit(ringbuf, lower_32_bits(offset)); |
| 1732 | intel_logical_ring_emit(ringbuf, upper_32_bits(offset)); |
| 1733 | intel_logical_ring_emit(ringbuf, MI_NOOP); |
| 1734 | intel_logical_ring_advance(ringbuf); |
| 1735 | |
| 1736 | return 0; |
| 1737 | } |
| 1738 | |
| 1739 | static bool gen8_logical_ring_get_irq(struct intel_engine_cs *engine) |
| 1740 | { |
| 1741 | struct drm_device *dev = engine->dev; |
| 1742 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1743 | unsigned long flags; |
| 1744 | |
| 1745 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
| 1746 | return false; |
| 1747 | |
| 1748 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 1749 | if (engine->irq_refcount++ == 0) { |
| 1750 | I915_WRITE_IMR(engine, |
| 1751 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); |
| 1752 | POSTING_READ(RING_IMR(engine->mmio_base)); |
| 1753 | } |
| 1754 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1755 | |
| 1756 | return true; |
| 1757 | } |
| 1758 | |
| 1759 | static void gen8_logical_ring_put_irq(struct intel_engine_cs *engine) |
| 1760 | { |
| 1761 | struct drm_device *dev = engine->dev; |
| 1762 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1763 | unsigned long flags; |
| 1764 | |
| 1765 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 1766 | if (--engine->irq_refcount == 0) { |
| 1767 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
| 1768 | POSTING_READ(RING_IMR(engine->mmio_base)); |
| 1769 | } |
| 1770 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1771 | } |
| 1772 | |
| 1773 | static int gen8_emit_flush(struct drm_i915_gem_request *request, |
| 1774 | u32 invalidate_domains, |
| 1775 | u32 unused) |
| 1776 | { |
| 1777 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
| 1778 | struct intel_engine_cs *engine = ringbuf->engine; |
| 1779 | struct drm_device *dev = engine->dev; |
| 1780 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1781 | uint32_t cmd; |
| 1782 | int ret; |
| 1783 | |
| 1784 | ret = intel_logical_ring_begin(request, 4); |
| 1785 | if (ret) |
| 1786 | return ret; |
| 1787 | |
| 1788 | cmd = MI_FLUSH_DW + 1; |
| 1789 | |
| 1790 | /* We always require a command barrier so that subsequent |
| 1791 | * commands, such as breadcrumb interrupts, are strictly ordered |
| 1792 | * wrt the contents of the write cache being flushed to memory |
| 1793 | * (and thus being coherent from the CPU). |
| 1794 | */ |
| 1795 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; |
| 1796 | |
| 1797 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) { |
| 1798 | cmd |= MI_INVALIDATE_TLB; |
| 1799 | if (engine == &dev_priv->engine[VCS]) |
| 1800 | cmd |= MI_INVALIDATE_BSD; |
| 1801 | } |
| 1802 | |
| 1803 | intel_logical_ring_emit(ringbuf, cmd); |
| 1804 | intel_logical_ring_emit(ringbuf, |
| 1805 | I915_GEM_HWS_SCRATCH_ADDR | |
| 1806 | MI_FLUSH_DW_USE_GTT); |
| 1807 | intel_logical_ring_emit(ringbuf, 0); /* upper addr */ |
| 1808 | intel_logical_ring_emit(ringbuf, 0); /* value */ |
| 1809 | intel_logical_ring_advance(ringbuf); |
| 1810 | |
| 1811 | return 0; |
| 1812 | } |
| 1813 | |
| 1814 | static int gen8_emit_flush_render(struct drm_i915_gem_request *request, |
| 1815 | u32 invalidate_domains, |
| 1816 | u32 flush_domains) |
| 1817 | { |
| 1818 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
| 1819 | struct intel_engine_cs *engine = ringbuf->engine; |
| 1820 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
| 1821 | bool vf_flush_wa = false; |
| 1822 | u32 flags = 0; |
| 1823 | int ret; |
| 1824 | |
| 1825 | flags |= PIPE_CONTROL_CS_STALL; |
| 1826 | |
| 1827 | if (flush_domains) { |
| 1828 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 1829 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 1830 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
| 1831 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
| 1832 | } |
| 1833 | |
| 1834 | if (invalidate_domains) { |
| 1835 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 1836 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 1837 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 1838 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 1839 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 1840 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 1841 | flags |= PIPE_CONTROL_QW_WRITE; |
| 1842 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
| 1843 | |
| 1844 | /* |
| 1845 | * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL |
| 1846 | * pipe control. |
| 1847 | */ |
| 1848 | if (IS_GEN9(engine->dev)) |
| 1849 | vf_flush_wa = true; |
| 1850 | } |
| 1851 | |
| 1852 | ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6); |
| 1853 | if (ret) |
| 1854 | return ret; |
| 1855 | |
| 1856 | if (vf_flush_wa) { |
| 1857 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); |
| 1858 | intel_logical_ring_emit(ringbuf, 0); |
| 1859 | intel_logical_ring_emit(ringbuf, 0); |
| 1860 | intel_logical_ring_emit(ringbuf, 0); |
| 1861 | intel_logical_ring_emit(ringbuf, 0); |
| 1862 | intel_logical_ring_emit(ringbuf, 0); |
| 1863 | } |
| 1864 | |
| 1865 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); |
| 1866 | intel_logical_ring_emit(ringbuf, flags); |
| 1867 | intel_logical_ring_emit(ringbuf, scratch_addr); |
| 1868 | intel_logical_ring_emit(ringbuf, 0); |
| 1869 | intel_logical_ring_emit(ringbuf, 0); |
| 1870 | intel_logical_ring_emit(ringbuf, 0); |
| 1871 | intel_logical_ring_advance(ringbuf); |
| 1872 | |
| 1873 | return 0; |
| 1874 | } |
| 1875 | |
| 1876 | static u32 gen8_get_seqno(struct intel_engine_cs *engine) |
| 1877 | { |
| 1878 | return intel_read_status_page(engine, I915_GEM_HWS_INDEX); |
| 1879 | } |
| 1880 | |
| 1881 | static void gen8_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
| 1882 | { |
| 1883 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); |
| 1884 | } |
| 1885 | |
| 1886 | static void bxt_a_seqno_barrier(struct intel_engine_cs *engine) |
| 1887 | { |
| 1888 | /* |
| 1889 | * On BXT A steppings there is a HW coherency issue whereby the |
| 1890 | * MI_STORE_DATA_IMM storing the completed request's seqno |
| 1891 | * occasionally doesn't invalidate the CPU cache. Work around this by |
| 1892 | * clflushing the corresponding cacheline whenever the caller wants |
| 1893 | * the coherency to be guaranteed. Note that this cacheline is known |
| 1894 | * to be clean at this point, since we only write it in |
| 1895 | * bxt_a_set_seqno(), where we also do a clflush after the write. So |
| 1896 | * this clflush in practice becomes an invalidate operation. |
| 1897 | */ |
| 1898 | intel_flush_status_page(engine, I915_GEM_HWS_INDEX); |
| 1899 | } |
| 1900 | |
| 1901 | static void bxt_a_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
| 1902 | { |
| 1903 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); |
| 1904 | |
| 1905 | /* See bxt_a_get_seqno() explaining the reason for the clflush. */ |
| 1906 | intel_flush_status_page(engine, I915_GEM_HWS_INDEX); |
| 1907 | } |
| 1908 | |
| 1909 | /* |
| 1910 | * Reserve space for 2 NOOPs at the end of each request to be |
| 1911 | * used as a workaround for not being allowed to do lite |
| 1912 | * restore with HEAD==TAIL (WaIdleLiteRestore). |
| 1913 | */ |
| 1914 | #define WA_TAIL_DWORDS 2 |
| 1915 | |
| 1916 | static inline u32 hws_seqno_address(struct intel_engine_cs *engine) |
| 1917 | { |
| 1918 | return engine->status_page.gfx_addr + I915_GEM_HWS_INDEX_ADDR; |
| 1919 | } |
| 1920 | |
| 1921 | static int gen8_emit_request(struct drm_i915_gem_request *request) |
| 1922 | { |
| 1923 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
| 1924 | int ret; |
| 1925 | |
| 1926 | ret = intel_logical_ring_begin(request, 6 + WA_TAIL_DWORDS); |
| 1927 | if (ret) |
| 1928 | return ret; |
| 1929 | |
| 1930 | /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */ |
| 1931 | BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5)); |
| 1932 | |
| 1933 | intel_logical_ring_emit(ringbuf, |
| 1934 | (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW); |
| 1935 | intel_logical_ring_emit(ringbuf, |
| 1936 | hws_seqno_address(request->engine) | |
| 1937 | MI_FLUSH_DW_USE_GTT); |
| 1938 | intel_logical_ring_emit(ringbuf, 0); |
| 1939 | intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request)); |
| 1940 | intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); |
| 1941 | intel_logical_ring_emit(ringbuf, MI_NOOP); |
| 1942 | return intel_logical_ring_advance_and_submit(request); |
| 1943 | } |
| 1944 | |
| 1945 | static int gen8_emit_request_render(struct drm_i915_gem_request *request) |
| 1946 | { |
| 1947 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
| 1948 | int ret; |
| 1949 | |
| 1950 | ret = intel_logical_ring_begin(request, 8 + WA_TAIL_DWORDS); |
| 1951 | if (ret) |
| 1952 | return ret; |
| 1953 | |
| 1954 | /* We're using qword write, seqno should be aligned to 8 bytes. */ |
| 1955 | BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1); |
| 1956 | |
| 1957 | /* w/a for post sync ops following a GPGPU operation we |
| 1958 | * need a prior CS_STALL, which is emitted by the flush |
| 1959 | * following the batch. |
| 1960 | */ |
| 1961 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); |
| 1962 | intel_logical_ring_emit(ringbuf, |
| 1963 | (PIPE_CONTROL_GLOBAL_GTT_IVB | |
| 1964 | PIPE_CONTROL_CS_STALL | |
| 1965 | PIPE_CONTROL_QW_WRITE)); |
| 1966 | intel_logical_ring_emit(ringbuf, hws_seqno_address(request->engine)); |
| 1967 | intel_logical_ring_emit(ringbuf, 0); |
| 1968 | intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request)); |
| 1969 | /* We're thrashing one dword of HWS. */ |
| 1970 | intel_logical_ring_emit(ringbuf, 0); |
| 1971 | intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); |
| 1972 | intel_logical_ring_emit(ringbuf, MI_NOOP); |
| 1973 | return intel_logical_ring_advance_and_submit(request); |
| 1974 | } |
| 1975 | |
| 1976 | static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req) |
| 1977 | { |
| 1978 | struct render_state so; |
| 1979 | int ret; |
| 1980 | |
| 1981 | ret = i915_gem_render_state_prepare(req->engine, &so); |
| 1982 | if (ret) |
| 1983 | return ret; |
| 1984 | |
| 1985 | if (so.rodata == NULL) |
| 1986 | return 0; |
| 1987 | |
| 1988 | ret = req->engine->emit_bb_start(req, so.ggtt_offset, |
| 1989 | I915_DISPATCH_SECURE); |
| 1990 | if (ret) |
| 1991 | goto out; |
| 1992 | |
| 1993 | ret = req->engine->emit_bb_start(req, |
| 1994 | (so.ggtt_offset + so.aux_batch_offset), |
| 1995 | I915_DISPATCH_SECURE); |
| 1996 | if (ret) |
| 1997 | goto out; |
| 1998 | |
| 1999 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req); |
| 2000 | |
| 2001 | out: |
| 2002 | i915_gem_render_state_fini(&so); |
| 2003 | return ret; |
| 2004 | } |
| 2005 | |
| 2006 | static int gen8_init_rcs_context(struct drm_i915_gem_request *req) |
| 2007 | { |
| 2008 | int ret; |
| 2009 | |
| 2010 | ret = intel_logical_ring_workarounds_emit(req); |
| 2011 | if (ret) |
| 2012 | return ret; |
| 2013 | |
| 2014 | ret = intel_rcs_context_init_mocs(req); |
| 2015 | /* |
| 2016 | * Failing to program the MOCS is non-fatal.The system will not |
| 2017 | * run at peak performance. So generate an error and carry on. |
| 2018 | */ |
| 2019 | if (ret) |
| 2020 | DRM_ERROR("MOCS failed to program: expect performance issues.\n"); |
| 2021 | |
| 2022 | return intel_lr_context_render_state_init(req); |
| 2023 | } |
| 2024 | |
| 2025 | /** |
| 2026 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer |
| 2027 | * |
| 2028 | * @ring: Engine Command Streamer. |
| 2029 | * |
| 2030 | */ |
| 2031 | void intel_logical_ring_cleanup(struct intel_engine_cs *engine) |
| 2032 | { |
| 2033 | struct drm_i915_private *dev_priv; |
| 2034 | |
| 2035 | if (!intel_engine_initialized(engine)) |
| 2036 | return; |
| 2037 | |
| 2038 | /* |
| 2039 | * Tasklet cannot be active at this point due intel_mark_active/idle |
| 2040 | * so this is just for documentation. |
| 2041 | */ |
| 2042 | if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state))) |
| 2043 | tasklet_kill(&engine->irq_tasklet); |
| 2044 | |
| 2045 | dev_priv = engine->dev->dev_private; |
| 2046 | |
| 2047 | if (engine->buffer) { |
| 2048 | intel_logical_ring_stop(engine); |
| 2049 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
| 2050 | } |
| 2051 | |
| 2052 | if (engine->cleanup) |
| 2053 | engine->cleanup(engine); |
| 2054 | |
| 2055 | i915_cmd_parser_fini_ring(engine); |
| 2056 | i915_gem_batch_pool_fini(&engine->batch_pool); |
| 2057 | |
| 2058 | if (engine->status_page.obj) { |
| 2059 | i915_gem_object_unpin_map(engine->status_page.obj); |
| 2060 | engine->status_page.obj = NULL; |
| 2061 | } |
| 2062 | |
| 2063 | engine->idle_lite_restore_wa = 0; |
| 2064 | engine->disable_lite_restore_wa = false; |
| 2065 | engine->ctx_desc_template = 0; |
| 2066 | |
| 2067 | lrc_destroy_wa_ctx_obj(engine); |
| 2068 | engine->dev = NULL; |
| 2069 | } |
| 2070 | |
| 2071 | static void |
| 2072 | logical_ring_default_vfuncs(struct drm_device *dev, |
| 2073 | struct intel_engine_cs *engine) |
| 2074 | { |
| 2075 | /* Default vfuncs which can be overriden by each engine. */ |
| 2076 | engine->init_hw = gen8_init_common_ring; |
| 2077 | engine->emit_request = gen8_emit_request; |
| 2078 | engine->emit_flush = gen8_emit_flush; |
| 2079 | engine->irq_get = gen8_logical_ring_get_irq; |
| 2080 | engine->irq_put = gen8_logical_ring_put_irq; |
| 2081 | engine->emit_bb_start = gen8_emit_bb_start; |
| 2082 | engine->get_seqno = gen8_get_seqno; |
| 2083 | engine->set_seqno = gen8_set_seqno; |
| 2084 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
| 2085 | engine->irq_seqno_barrier = bxt_a_seqno_barrier; |
| 2086 | engine->set_seqno = bxt_a_set_seqno; |
| 2087 | } |
| 2088 | } |
| 2089 | |
| 2090 | static inline void |
| 2091 | logical_ring_default_irqs(struct intel_engine_cs *engine, unsigned shift) |
| 2092 | { |
| 2093 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; |
| 2094 | engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; |
| 2095 | } |
| 2096 | |
| 2097 | static int |
| 2098 | lrc_setup_hws(struct intel_engine_cs *engine, |
| 2099 | struct drm_i915_gem_object *dctx_obj) |
| 2100 | { |
| 2101 | void *hws; |
| 2102 | |
| 2103 | /* The HWSP is part of the default context object in LRC mode. */ |
| 2104 | engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(dctx_obj) + |
| 2105 | LRC_PPHWSP_PN * PAGE_SIZE; |
| 2106 | hws = i915_gem_object_pin_map(dctx_obj); |
| 2107 | if (IS_ERR(hws)) |
| 2108 | return PTR_ERR(hws); |
| 2109 | engine->status_page.page_addr = hws + LRC_PPHWSP_PN * PAGE_SIZE; |
| 2110 | engine->status_page.obj = dctx_obj; |
| 2111 | |
| 2112 | return 0; |
| 2113 | } |
| 2114 | |
| 2115 | static int |
| 2116 | logical_ring_init(struct drm_device *dev, struct intel_engine_cs *engine) |
| 2117 | { |
| 2118 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 2119 | struct intel_context *dctx = dev_priv->kernel_context; |
| 2120 | enum forcewake_domains fw_domains; |
| 2121 | int ret; |
| 2122 | |
| 2123 | /* Intentionally left blank. */ |
| 2124 | engine->buffer = NULL; |
| 2125 | |
| 2126 | engine->dev = dev; |
| 2127 | INIT_LIST_HEAD(&engine->active_list); |
| 2128 | INIT_LIST_HEAD(&engine->request_list); |
| 2129 | i915_gem_batch_pool_init(dev, &engine->batch_pool); |
| 2130 | init_waitqueue_head(&engine->irq_queue); |
| 2131 | |
| 2132 | INIT_LIST_HEAD(&engine->buffers); |
| 2133 | INIT_LIST_HEAD(&engine->execlist_queue); |
| 2134 | INIT_LIST_HEAD(&engine->execlist_retired_req_list); |
| 2135 | spin_lock_init(&engine->execlist_lock); |
| 2136 | |
| 2137 | tasklet_init(&engine->irq_tasklet, |
| 2138 | intel_lrc_irq_handler, (unsigned long)engine); |
| 2139 | |
| 2140 | logical_ring_init_platform_invariants(engine); |
| 2141 | |
| 2142 | fw_domains = intel_uncore_forcewake_for_reg(dev_priv, |
| 2143 | RING_ELSP(engine), |
| 2144 | FW_REG_WRITE); |
| 2145 | |
| 2146 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, |
| 2147 | RING_CONTEXT_STATUS_PTR(engine), |
| 2148 | FW_REG_READ | FW_REG_WRITE); |
| 2149 | |
| 2150 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, |
| 2151 | RING_CONTEXT_STATUS_BUF_BASE(engine), |
| 2152 | FW_REG_READ); |
| 2153 | |
| 2154 | engine->fw_domains = fw_domains; |
| 2155 | |
| 2156 | ret = i915_cmd_parser_init_ring(engine); |
| 2157 | if (ret) |
| 2158 | goto error; |
| 2159 | |
| 2160 | ret = intel_lr_context_deferred_alloc(dctx, engine); |
| 2161 | if (ret) |
| 2162 | goto error; |
| 2163 | |
| 2164 | /* As this is the default context, always pin it */ |
| 2165 | ret = intel_lr_context_do_pin(dctx, engine); |
| 2166 | if (ret) { |
| 2167 | DRM_ERROR( |
| 2168 | "Failed to pin and map ringbuffer %s: %d\n", |
| 2169 | engine->name, ret); |
| 2170 | goto error; |
| 2171 | } |
| 2172 | |
| 2173 | /* And setup the hardware status page. */ |
| 2174 | ret = lrc_setup_hws(engine, dctx->engine[engine->id].state); |
| 2175 | if (ret) { |
| 2176 | DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret); |
| 2177 | goto error; |
| 2178 | } |
| 2179 | |
| 2180 | return 0; |
| 2181 | |
| 2182 | error: |
| 2183 | intel_logical_ring_cleanup(engine); |
| 2184 | return ret; |
| 2185 | } |
| 2186 | |
| 2187 | static int logical_render_ring_init(struct drm_device *dev) |
| 2188 | { |
| 2189 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2190 | struct intel_engine_cs *engine = &dev_priv->engine[RCS]; |
| 2191 | int ret; |
| 2192 | |
| 2193 | engine->name = "render ring"; |
| 2194 | engine->id = RCS; |
| 2195 | engine->exec_id = I915_EXEC_RENDER; |
| 2196 | engine->guc_id = GUC_RENDER_ENGINE; |
| 2197 | engine->mmio_base = RENDER_RING_BASE; |
| 2198 | |
| 2199 | logical_ring_default_irqs(engine, GEN8_RCS_IRQ_SHIFT); |
| 2200 | if (HAS_L3_DPF(dev)) |
| 2201 | engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; |
| 2202 | |
| 2203 | logical_ring_default_vfuncs(dev, engine); |
| 2204 | |
| 2205 | /* Override some for render ring. */ |
| 2206 | if (INTEL_INFO(dev)->gen >= 9) |
| 2207 | engine->init_hw = gen9_init_render_ring; |
| 2208 | else |
| 2209 | engine->init_hw = gen8_init_render_ring; |
| 2210 | engine->init_context = gen8_init_rcs_context; |
| 2211 | engine->cleanup = intel_fini_pipe_control; |
| 2212 | engine->emit_flush = gen8_emit_flush_render; |
| 2213 | engine->emit_request = gen8_emit_request_render; |
| 2214 | |
| 2215 | engine->dev = dev; |
| 2216 | |
| 2217 | ret = intel_init_pipe_control(engine); |
| 2218 | if (ret) |
| 2219 | return ret; |
| 2220 | |
| 2221 | ret = intel_init_workaround_bb(engine); |
| 2222 | if (ret) { |
| 2223 | /* |
| 2224 | * We continue even if we fail to initialize WA batch |
| 2225 | * because we only expect rare glitches but nothing |
| 2226 | * critical to prevent us from using GPU |
| 2227 | */ |
| 2228 | DRM_ERROR("WA batch buffer initialization failed: %d\n", |
| 2229 | ret); |
| 2230 | } |
| 2231 | |
| 2232 | ret = logical_ring_init(dev, engine); |
| 2233 | if (ret) { |
| 2234 | lrc_destroy_wa_ctx_obj(engine); |
| 2235 | } |
| 2236 | |
| 2237 | return ret; |
| 2238 | } |
| 2239 | |
| 2240 | static int logical_bsd_ring_init(struct drm_device *dev) |
| 2241 | { |
| 2242 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2243 | struct intel_engine_cs *engine = &dev_priv->engine[VCS]; |
| 2244 | |
| 2245 | engine->name = "bsd ring"; |
| 2246 | engine->id = VCS; |
| 2247 | engine->exec_id = I915_EXEC_BSD; |
| 2248 | engine->guc_id = GUC_VIDEO_ENGINE; |
| 2249 | engine->mmio_base = GEN6_BSD_RING_BASE; |
| 2250 | |
| 2251 | logical_ring_default_irqs(engine, GEN8_VCS1_IRQ_SHIFT); |
| 2252 | logical_ring_default_vfuncs(dev, engine); |
| 2253 | |
| 2254 | return logical_ring_init(dev, engine); |
| 2255 | } |
| 2256 | |
| 2257 | static int logical_bsd2_ring_init(struct drm_device *dev) |
| 2258 | { |
| 2259 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2260 | struct intel_engine_cs *engine = &dev_priv->engine[VCS2]; |
| 2261 | |
| 2262 | engine->name = "bsd2 ring"; |
| 2263 | engine->id = VCS2; |
| 2264 | engine->exec_id = I915_EXEC_BSD; |
| 2265 | engine->guc_id = GUC_VIDEO_ENGINE2; |
| 2266 | engine->mmio_base = GEN8_BSD2_RING_BASE; |
| 2267 | |
| 2268 | logical_ring_default_irqs(engine, GEN8_VCS2_IRQ_SHIFT); |
| 2269 | logical_ring_default_vfuncs(dev, engine); |
| 2270 | |
| 2271 | return logical_ring_init(dev, engine); |
| 2272 | } |
| 2273 | |
| 2274 | static int logical_blt_ring_init(struct drm_device *dev) |
| 2275 | { |
| 2276 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2277 | struct intel_engine_cs *engine = &dev_priv->engine[BCS]; |
| 2278 | |
| 2279 | engine->name = "blitter ring"; |
| 2280 | engine->id = BCS; |
| 2281 | engine->exec_id = I915_EXEC_BLT; |
| 2282 | engine->guc_id = GUC_BLITTER_ENGINE; |
| 2283 | engine->mmio_base = BLT_RING_BASE; |
| 2284 | |
| 2285 | logical_ring_default_irqs(engine, GEN8_BCS_IRQ_SHIFT); |
| 2286 | logical_ring_default_vfuncs(dev, engine); |
| 2287 | |
| 2288 | return logical_ring_init(dev, engine); |
| 2289 | } |
| 2290 | |
| 2291 | static int logical_vebox_ring_init(struct drm_device *dev) |
| 2292 | { |
| 2293 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2294 | struct intel_engine_cs *engine = &dev_priv->engine[VECS]; |
| 2295 | |
| 2296 | engine->name = "video enhancement ring"; |
| 2297 | engine->id = VECS; |
| 2298 | engine->exec_id = I915_EXEC_VEBOX; |
| 2299 | engine->guc_id = GUC_VIDEOENHANCE_ENGINE; |
| 2300 | engine->mmio_base = VEBOX_RING_BASE; |
| 2301 | |
| 2302 | logical_ring_default_irqs(engine, GEN8_VECS_IRQ_SHIFT); |
| 2303 | logical_ring_default_vfuncs(dev, engine); |
| 2304 | |
| 2305 | return logical_ring_init(dev, engine); |
| 2306 | } |
| 2307 | |
| 2308 | /** |
| 2309 | * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers |
| 2310 | * @dev: DRM device. |
| 2311 | * |
| 2312 | * This function inits the engines for an Execlists submission style (the equivalent in the |
| 2313 | * legacy ringbuffer submission world would be i915_gem_init_engines). It does it only for |
| 2314 | * those engines that are present in the hardware. |
| 2315 | * |
| 2316 | * Return: non-zero if the initialization failed. |
| 2317 | */ |
| 2318 | int intel_logical_rings_init(struct drm_device *dev) |
| 2319 | { |
| 2320 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2321 | int ret; |
| 2322 | |
| 2323 | ret = logical_render_ring_init(dev); |
| 2324 | if (ret) |
| 2325 | return ret; |
| 2326 | |
| 2327 | if (HAS_BSD(dev)) { |
| 2328 | ret = logical_bsd_ring_init(dev); |
| 2329 | if (ret) |
| 2330 | goto cleanup_render_ring; |
| 2331 | } |
| 2332 | |
| 2333 | if (HAS_BLT(dev)) { |
| 2334 | ret = logical_blt_ring_init(dev); |
| 2335 | if (ret) |
| 2336 | goto cleanup_bsd_ring; |
| 2337 | } |
| 2338 | |
| 2339 | if (HAS_VEBOX(dev)) { |
| 2340 | ret = logical_vebox_ring_init(dev); |
| 2341 | if (ret) |
| 2342 | goto cleanup_blt_ring; |
| 2343 | } |
| 2344 | |
| 2345 | if (HAS_BSD2(dev)) { |
| 2346 | ret = logical_bsd2_ring_init(dev); |
| 2347 | if (ret) |
| 2348 | goto cleanup_vebox_ring; |
| 2349 | } |
| 2350 | |
| 2351 | return 0; |
| 2352 | |
| 2353 | cleanup_vebox_ring: |
| 2354 | intel_logical_ring_cleanup(&dev_priv->engine[VECS]); |
| 2355 | cleanup_blt_ring: |
| 2356 | intel_logical_ring_cleanup(&dev_priv->engine[BCS]); |
| 2357 | cleanup_bsd_ring: |
| 2358 | intel_logical_ring_cleanup(&dev_priv->engine[VCS]); |
| 2359 | cleanup_render_ring: |
| 2360 | intel_logical_ring_cleanup(&dev_priv->engine[RCS]); |
| 2361 | |
| 2362 | return ret; |
| 2363 | } |
| 2364 | |
| 2365 | static u32 |
| 2366 | make_rpcs(struct drm_device *dev) |
| 2367 | { |
| 2368 | u32 rpcs = 0; |
| 2369 | |
| 2370 | /* |
| 2371 | * No explicit RPCS request is needed to ensure full |
| 2372 | * slice/subslice/EU enablement prior to Gen9. |
| 2373 | */ |
| 2374 | if (INTEL_INFO(dev)->gen < 9) |
| 2375 | return 0; |
| 2376 | |
| 2377 | /* |
| 2378 | * Starting in Gen9, render power gating can leave |
| 2379 | * slice/subslice/EU in a partially enabled state. We |
| 2380 | * must make an explicit request through RPCS for full |
| 2381 | * enablement. |
| 2382 | */ |
| 2383 | if (INTEL_INFO(dev)->has_slice_pg) { |
| 2384 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; |
| 2385 | rpcs |= INTEL_INFO(dev)->slice_total << |
| 2386 | GEN8_RPCS_S_CNT_SHIFT; |
| 2387 | rpcs |= GEN8_RPCS_ENABLE; |
| 2388 | } |
| 2389 | |
| 2390 | if (INTEL_INFO(dev)->has_subslice_pg) { |
| 2391 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; |
| 2392 | rpcs |= INTEL_INFO(dev)->subslice_per_slice << |
| 2393 | GEN8_RPCS_SS_CNT_SHIFT; |
| 2394 | rpcs |= GEN8_RPCS_ENABLE; |
| 2395 | } |
| 2396 | |
| 2397 | if (INTEL_INFO(dev)->has_eu_pg) { |
| 2398 | rpcs |= INTEL_INFO(dev)->eu_per_subslice << |
| 2399 | GEN8_RPCS_EU_MIN_SHIFT; |
| 2400 | rpcs |= INTEL_INFO(dev)->eu_per_subslice << |
| 2401 | GEN8_RPCS_EU_MAX_SHIFT; |
| 2402 | rpcs |= GEN8_RPCS_ENABLE; |
| 2403 | } |
| 2404 | |
| 2405 | return rpcs; |
| 2406 | } |
| 2407 | |
| 2408 | static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) |
| 2409 | { |
| 2410 | u32 indirect_ctx_offset; |
| 2411 | |
| 2412 | switch (INTEL_INFO(engine->dev)->gen) { |
| 2413 | default: |
| 2414 | MISSING_CASE(INTEL_INFO(engine->dev)->gen); |
| 2415 | /* fall through */ |
| 2416 | case 9: |
| 2417 | indirect_ctx_offset = |
| 2418 | GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; |
| 2419 | break; |
| 2420 | case 8: |
| 2421 | indirect_ctx_offset = |
| 2422 | GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; |
| 2423 | break; |
| 2424 | } |
| 2425 | |
| 2426 | return indirect_ctx_offset; |
| 2427 | } |
| 2428 | |
| 2429 | static int |
| 2430 | populate_lr_context(struct intel_context *ctx, |
| 2431 | struct drm_i915_gem_object *ctx_obj, |
| 2432 | struct intel_engine_cs *engine, |
| 2433 | struct intel_ringbuffer *ringbuf) |
| 2434 | { |
| 2435 | struct drm_device *dev = engine->dev; |
| 2436 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2437 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
| 2438 | void *vaddr; |
| 2439 | u32 *reg_state; |
| 2440 | int ret; |
| 2441 | |
| 2442 | if (!ppgtt) |
| 2443 | ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 2444 | |
| 2445 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); |
| 2446 | if (ret) { |
| 2447 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); |
| 2448 | return ret; |
| 2449 | } |
| 2450 | |
| 2451 | vaddr = i915_gem_object_pin_map(ctx_obj); |
| 2452 | if (IS_ERR(vaddr)) { |
| 2453 | ret = PTR_ERR(vaddr); |
| 2454 | DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); |
| 2455 | return ret; |
| 2456 | } |
| 2457 | ctx_obj->dirty = true; |
| 2458 | |
| 2459 | /* The second page of the context object contains some fields which must |
| 2460 | * be set up prior to the first execution. */ |
| 2461 | reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
| 2462 | |
| 2463 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM |
| 2464 | * commands followed by (reg, value) pairs. The values we are setting here are |
| 2465 | * only for the first context restore: on a subsequent save, the GPU will |
| 2466 | * recreate this batchbuffer with new values (including all the missing |
| 2467 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ |
| 2468 | reg_state[CTX_LRI_HEADER_0] = |
| 2469 | MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED; |
| 2470 | ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL, |
| 2471 | RING_CONTEXT_CONTROL(engine), |
| 2472 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | |
| 2473 | CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | |
| 2474 | (HAS_RESOURCE_STREAMER(dev) ? |
| 2475 | CTX_CTRL_RS_CTX_ENABLE : 0))); |
| 2476 | ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base), |
| 2477 | 0); |
| 2478 | ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base), |
| 2479 | 0); |
| 2480 | /* Ring buffer start address is not known until the buffer is pinned. |
| 2481 | * It is written to the context image in execlists_update_context() |
| 2482 | */ |
| 2483 | ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START, |
| 2484 | RING_START(engine->mmio_base), 0); |
| 2485 | ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL, |
| 2486 | RING_CTL(engine->mmio_base), |
| 2487 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID); |
| 2488 | ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U, |
| 2489 | RING_BBADDR_UDW(engine->mmio_base), 0); |
| 2490 | ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L, |
| 2491 | RING_BBADDR(engine->mmio_base), 0); |
| 2492 | ASSIGN_CTX_REG(reg_state, CTX_BB_STATE, |
| 2493 | RING_BBSTATE(engine->mmio_base), |
| 2494 | RING_BB_PPGTT); |
| 2495 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U, |
| 2496 | RING_SBBADDR_UDW(engine->mmio_base), 0); |
| 2497 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L, |
| 2498 | RING_SBBADDR(engine->mmio_base), 0); |
| 2499 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE, |
| 2500 | RING_SBBSTATE(engine->mmio_base), 0); |
| 2501 | if (engine->id == RCS) { |
| 2502 | ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR, |
| 2503 | RING_BB_PER_CTX_PTR(engine->mmio_base), 0); |
| 2504 | ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX, |
| 2505 | RING_INDIRECT_CTX(engine->mmio_base), 0); |
| 2506 | ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET, |
| 2507 | RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0); |
| 2508 | if (engine->wa_ctx.obj) { |
| 2509 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
| 2510 | uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj); |
| 2511 | |
| 2512 | reg_state[CTX_RCS_INDIRECT_CTX+1] = |
| 2513 | (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) | |
| 2514 | (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS); |
| 2515 | |
| 2516 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = |
| 2517 | intel_lr_indirect_ctx_offset(engine) << 6; |
| 2518 | |
| 2519 | reg_state[CTX_BB_PER_CTX_PTR+1] = |
| 2520 | (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) | |
| 2521 | 0x01; |
| 2522 | } |
| 2523 | } |
| 2524 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; |
| 2525 | ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP, |
| 2526 | RING_CTX_TIMESTAMP(engine->mmio_base), 0); |
| 2527 | /* PDP values well be assigned later if needed */ |
| 2528 | ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), |
| 2529 | 0); |
| 2530 | ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), |
| 2531 | 0); |
| 2532 | ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), |
| 2533 | 0); |
| 2534 | ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), |
| 2535 | 0); |
| 2536 | ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), |
| 2537 | 0); |
| 2538 | ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), |
| 2539 | 0); |
| 2540 | ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), |
| 2541 | 0); |
| 2542 | ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), |
| 2543 | 0); |
| 2544 | |
| 2545 | if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { |
| 2546 | /* 64b PPGTT (48bit canonical) |
| 2547 | * PDP0_DESCRIPTOR contains the base address to PML4 and |
| 2548 | * other PDP Descriptors are ignored. |
| 2549 | */ |
| 2550 | ASSIGN_CTX_PML4(ppgtt, reg_state); |
| 2551 | } else { |
| 2552 | /* 32b PPGTT |
| 2553 | * PDP*_DESCRIPTOR contains the base address of space supported. |
| 2554 | * With dynamic page allocation, PDPs may not be allocated at |
| 2555 | * this point. Point the unallocated PDPs to the scratch page |
| 2556 | */ |
| 2557 | execlists_update_context_pdps(ppgtt, reg_state); |
| 2558 | } |
| 2559 | |
| 2560 | if (engine->id == RCS) { |
| 2561 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); |
| 2562 | ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, |
| 2563 | make_rpcs(dev)); |
| 2564 | } |
| 2565 | |
| 2566 | i915_gem_object_unpin_map(ctx_obj); |
| 2567 | |
| 2568 | return 0; |
| 2569 | } |
| 2570 | |
| 2571 | /** |
| 2572 | * intel_lr_context_free() - free the LRC specific bits of a context |
| 2573 | * @ctx: the LR context to free. |
| 2574 | * |
| 2575 | * The real context freeing is done in i915_gem_context_free: this only |
| 2576 | * takes care of the bits that are LRC related: the per-engine backing |
| 2577 | * objects and the logical ringbuffer. |
| 2578 | */ |
| 2579 | void intel_lr_context_free(struct intel_context *ctx) |
| 2580 | { |
| 2581 | int i; |
| 2582 | |
| 2583 | for (i = I915_NUM_ENGINES; --i >= 0; ) { |
| 2584 | struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf; |
| 2585 | struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; |
| 2586 | |
| 2587 | if (!ctx_obj) |
| 2588 | continue; |
| 2589 | |
| 2590 | if (ctx == ctx->i915->kernel_context) { |
| 2591 | intel_unpin_ringbuffer_obj(ringbuf); |
| 2592 | i915_gem_object_ggtt_unpin(ctx_obj); |
| 2593 | i915_gem_object_unpin_map(ctx_obj); |
| 2594 | } |
| 2595 | |
| 2596 | WARN_ON(ctx->engine[i].pin_count); |
| 2597 | intel_ringbuffer_free(ringbuf); |
| 2598 | drm_gem_object_unreference(&ctx_obj->base); |
| 2599 | } |
| 2600 | } |
| 2601 | |
| 2602 | /** |
| 2603 | * intel_lr_context_size() - return the size of the context for an engine |
| 2604 | * @ring: which engine to find the context size for |
| 2605 | * |
| 2606 | * Each engine may require a different amount of space for a context image, |
| 2607 | * so when allocating (or copying) an image, this function can be used to |
| 2608 | * find the right size for the specific engine. |
| 2609 | * |
| 2610 | * Return: size (in bytes) of an engine-specific context image |
| 2611 | * |
| 2612 | * Note: this size includes the HWSP, which is part of the context image |
| 2613 | * in LRC mode, but does not include the "shared data page" used with |
| 2614 | * GuC submission. The caller should account for this if using the GuC. |
| 2615 | */ |
| 2616 | uint32_t intel_lr_context_size(struct intel_engine_cs *engine) |
| 2617 | { |
| 2618 | int ret = 0; |
| 2619 | |
| 2620 | WARN_ON(INTEL_INFO(engine->dev)->gen < 8); |
| 2621 | |
| 2622 | switch (engine->id) { |
| 2623 | case RCS: |
| 2624 | if (INTEL_INFO(engine->dev)->gen >= 9) |
| 2625 | ret = GEN9_LR_CONTEXT_RENDER_SIZE; |
| 2626 | else |
| 2627 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; |
| 2628 | break; |
| 2629 | case VCS: |
| 2630 | case BCS: |
| 2631 | case VECS: |
| 2632 | case VCS2: |
| 2633 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; |
| 2634 | break; |
| 2635 | } |
| 2636 | |
| 2637 | return ret; |
| 2638 | } |
| 2639 | |
| 2640 | /** |
| 2641 | * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context |
| 2642 | * @ctx: LR context to create. |
| 2643 | * @ring: engine to be used with the context. |
| 2644 | * |
| 2645 | * This function can be called more than once, with different engines, if we plan |
| 2646 | * to use the context with them. The context backing objects and the ringbuffers |
| 2647 | * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why |
| 2648 | * the creation is a deferred call: it's better to make sure first that we need to use |
| 2649 | * a given ring with the context. |
| 2650 | * |
| 2651 | * Return: non-zero on error. |
| 2652 | */ |
| 2653 | |
| 2654 | int intel_lr_context_deferred_alloc(struct intel_context *ctx, |
| 2655 | struct intel_engine_cs *engine) |
| 2656 | { |
| 2657 | struct drm_device *dev = engine->dev; |
| 2658 | struct drm_i915_gem_object *ctx_obj; |
| 2659 | uint32_t context_size; |
| 2660 | struct intel_ringbuffer *ringbuf; |
| 2661 | int ret; |
| 2662 | |
| 2663 | WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); |
| 2664 | WARN_ON(ctx->engine[engine->id].state); |
| 2665 | |
| 2666 | context_size = round_up(intel_lr_context_size(engine), 4096); |
| 2667 | |
| 2668 | /* One extra page as the sharing data between driver and GuC */ |
| 2669 | context_size += PAGE_SIZE * LRC_PPHWSP_PN; |
| 2670 | |
| 2671 | ctx_obj = i915_gem_alloc_object(dev, context_size); |
| 2672 | if (!ctx_obj) { |
| 2673 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); |
| 2674 | return -ENOMEM; |
| 2675 | } |
| 2676 | |
| 2677 | ringbuf = intel_engine_create_ringbuffer(engine, 4 * PAGE_SIZE); |
| 2678 | if (IS_ERR(ringbuf)) { |
| 2679 | ret = PTR_ERR(ringbuf); |
| 2680 | goto error_deref_obj; |
| 2681 | } |
| 2682 | |
| 2683 | ret = populate_lr_context(ctx, ctx_obj, engine, ringbuf); |
| 2684 | if (ret) { |
| 2685 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); |
| 2686 | goto error_ringbuf; |
| 2687 | } |
| 2688 | |
| 2689 | ctx->engine[engine->id].ringbuf = ringbuf; |
| 2690 | ctx->engine[engine->id].state = ctx_obj; |
| 2691 | |
| 2692 | if (ctx != ctx->i915->kernel_context && engine->init_context) { |
| 2693 | struct drm_i915_gem_request *req; |
| 2694 | |
| 2695 | req = i915_gem_request_alloc(engine, ctx); |
| 2696 | if (IS_ERR(req)) { |
| 2697 | ret = PTR_ERR(req); |
| 2698 | DRM_ERROR("ring create req: %d\n", ret); |
| 2699 | goto error_ringbuf; |
| 2700 | } |
| 2701 | |
| 2702 | ret = engine->init_context(req); |
| 2703 | if (ret) { |
| 2704 | DRM_ERROR("ring init context: %d\n", |
| 2705 | ret); |
| 2706 | i915_gem_request_cancel(req); |
| 2707 | goto error_ringbuf; |
| 2708 | } |
| 2709 | i915_add_request_no_flush(req); |
| 2710 | } |
| 2711 | return 0; |
| 2712 | |
| 2713 | error_ringbuf: |
| 2714 | intel_ringbuffer_free(ringbuf); |
| 2715 | error_deref_obj: |
| 2716 | drm_gem_object_unreference(&ctx_obj->base); |
| 2717 | ctx->engine[engine->id].ringbuf = NULL; |
| 2718 | ctx->engine[engine->id].state = NULL; |
| 2719 | return ret; |
| 2720 | } |
| 2721 | |
| 2722 | void intel_lr_context_reset(struct drm_i915_private *dev_priv, |
| 2723 | struct intel_context *ctx) |
| 2724 | { |
| 2725 | struct intel_engine_cs *engine; |
| 2726 | |
| 2727 | for_each_engine(engine, dev_priv) { |
| 2728 | struct drm_i915_gem_object *ctx_obj = |
| 2729 | ctx->engine[engine->id].state; |
| 2730 | struct intel_ringbuffer *ringbuf = |
| 2731 | ctx->engine[engine->id].ringbuf; |
| 2732 | void *vaddr; |
| 2733 | uint32_t *reg_state; |
| 2734 | |
| 2735 | if (!ctx_obj) |
| 2736 | continue; |
| 2737 | |
| 2738 | vaddr = i915_gem_object_pin_map(ctx_obj); |
| 2739 | if (WARN_ON(IS_ERR(vaddr))) |
| 2740 | continue; |
| 2741 | |
| 2742 | reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
| 2743 | ctx_obj->dirty = true; |
| 2744 | |
| 2745 | reg_state[CTX_RING_HEAD+1] = 0; |
| 2746 | reg_state[CTX_RING_TAIL+1] = 0; |
| 2747 | |
| 2748 | i915_gem_object_unpin_map(ctx_obj); |
| 2749 | |
| 2750 | ringbuf->head = 0; |
| 2751 | ringbuf->tail = 0; |
| 2752 | } |
| 2753 | } |