| 1 | /* |
| 2 | * Copyright © 2014 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | */ |
| 23 | |
| 24 | #ifndef _INTEL_LRC_H_ |
| 25 | #define _INTEL_LRC_H_ |
| 26 | |
| 27 | #define GEN8_LR_CONTEXT_ALIGN 4096 |
| 28 | |
| 29 | /* Execlists regs */ |
| 30 | #define RING_ELSP(ring) ((ring)->mmio_base+0x230) |
| 31 | #define RING_EXECLIST_STATUS_LO(ring) ((ring)->mmio_base+0x234) |
| 32 | #define RING_EXECLIST_STATUS_HI(ring) ((ring)->mmio_base+0x234 + 4) |
| 33 | #define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244) |
| 34 | #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3) |
| 35 | #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0) |
| 36 | #define CTX_CTRL_RS_CTX_ENABLE (1 << 1) |
| 37 | #define RING_CONTEXT_STATUS_BUF_LO(ring, i) ((ring)->mmio_base+0x370 + (i) * 8) |
| 38 | #define RING_CONTEXT_STATUS_BUF_HI(ring, i) ((ring)->mmio_base+0x370 + (i) * 8 + 4) |
| 39 | #define RING_CONTEXT_STATUS_PTR(ring) ((ring)->mmio_base+0x3a0) |
| 40 | |
| 41 | /* Logical Rings */ |
| 42 | int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request); |
| 43 | int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request); |
| 44 | void intel_logical_ring_stop(struct intel_engine_cs *ring); |
| 45 | void intel_logical_ring_cleanup(struct intel_engine_cs *ring); |
| 46 | int intel_logical_rings_init(struct drm_device *dev); |
| 47 | int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords); |
| 48 | |
| 49 | int logical_ring_flush_all_caches(struct drm_i915_gem_request *req); |
| 50 | /** |
| 51 | * intel_logical_ring_advance() - advance the ringbuffer tail |
| 52 | * @ringbuf: Ringbuffer to advance. |
| 53 | * |
| 54 | * The tail is only updated in our logical ringbuffer struct. |
| 55 | */ |
| 56 | static inline void intel_logical_ring_advance(struct intel_ringbuffer *ringbuf) |
| 57 | { |
| 58 | ringbuf->tail &= ringbuf->size - 1; |
| 59 | } |
| 60 | /** |
| 61 | * intel_logical_ring_emit() - write a DWORD to the ringbuffer. |
| 62 | * @ringbuf: Ringbuffer to write to. |
| 63 | * @data: DWORD to write. |
| 64 | */ |
| 65 | static inline void intel_logical_ring_emit(struct intel_ringbuffer *ringbuf, |
| 66 | u32 data) |
| 67 | { |
| 68 | iowrite32(data, ringbuf->virtual_start + ringbuf->tail); |
| 69 | ringbuf->tail += 4; |
| 70 | } |
| 71 | |
| 72 | /* Logical Ring Contexts */ |
| 73 | |
| 74 | /* One extra page is added before LRC for GuC as shared data */ |
| 75 | #define LRC_GUCSHR_PN (0) |
| 76 | #define LRC_PPHWSP_PN (LRC_GUCSHR_PN + 1) |
| 77 | #define LRC_STATE_PN (LRC_PPHWSP_PN + 1) |
| 78 | |
| 79 | void intel_lr_context_free(struct intel_context *ctx); |
| 80 | int intel_lr_context_deferred_alloc(struct intel_context *ctx, |
| 81 | struct intel_engine_cs *ring); |
| 82 | void intel_lr_context_unpin(struct drm_i915_gem_request *req); |
| 83 | void intel_lr_context_reset(struct drm_device *dev, |
| 84 | struct intel_context *ctx); |
| 85 | uint64_t intel_lr_context_descriptor(struct intel_context *ctx, |
| 86 | struct intel_engine_cs *ring); |
| 87 | |
| 88 | /* Execlists */ |
| 89 | int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists); |
| 90 | struct i915_execbuffer_params; |
| 91 | int intel_execlists_submission(struct i915_execbuffer_params *params, |
| 92 | struct drm_i915_gem_execbuffer2 *args, |
| 93 | struct list_head *vmas); |
| 94 | u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj); |
| 95 | |
| 96 | void intel_lrc_irq_handler(struct intel_engine_cs *ring); |
| 97 | void intel_execlists_retire_requests(struct intel_engine_cs *ring); |
| 98 | |
| 99 | #endif /* _INTEL_LRC_H_ */ |