| 1 | /* |
| 2 | * Copyright © 2008-2010 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Zou Nan hai <nanhai.zou@intel.com> |
| 26 | * Xiang Hai hao<haihao.xiang@intel.com> |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #include <drm/drmP.h> |
| 31 | #include "i915_drv.h" |
| 32 | #include <drm/i915_drm.h> |
| 33 | #include "i915_trace.h" |
| 34 | #include "intel_drv.h" |
| 35 | |
| 36 | static inline int ring_space(struct intel_ring_buffer *ring) |
| 37 | { |
| 38 | int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE); |
| 39 | if (space < 0) |
| 40 | space += ring->size; |
| 41 | return space; |
| 42 | } |
| 43 | |
| 44 | void __intel_ring_advance(struct intel_ring_buffer *ring) |
| 45 | { |
| 46 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 47 | |
| 48 | ring->tail &= ring->size - 1; |
| 49 | if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring)) |
| 50 | return; |
| 51 | ring->write_tail(ring, ring->tail); |
| 52 | } |
| 53 | |
| 54 | static int |
| 55 | gen2_render_ring_flush(struct intel_ring_buffer *ring, |
| 56 | u32 invalidate_domains, |
| 57 | u32 flush_domains) |
| 58 | { |
| 59 | u32 cmd; |
| 60 | int ret; |
| 61 | |
| 62 | cmd = MI_FLUSH; |
| 63 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
| 64 | cmd |= MI_NO_WRITE_FLUSH; |
| 65 | |
| 66 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
| 67 | cmd |= MI_READ_FLUSH; |
| 68 | |
| 69 | ret = intel_ring_begin(ring, 2); |
| 70 | if (ret) |
| 71 | return ret; |
| 72 | |
| 73 | intel_ring_emit(ring, cmd); |
| 74 | intel_ring_emit(ring, MI_NOOP); |
| 75 | intel_ring_advance(ring); |
| 76 | |
| 77 | return 0; |
| 78 | } |
| 79 | |
| 80 | static int |
| 81 | gen4_render_ring_flush(struct intel_ring_buffer *ring, |
| 82 | u32 invalidate_domains, |
| 83 | u32 flush_domains) |
| 84 | { |
| 85 | struct drm_device *dev = ring->dev; |
| 86 | u32 cmd; |
| 87 | int ret; |
| 88 | |
| 89 | /* |
| 90 | * read/write caches: |
| 91 | * |
| 92 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
| 93 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
| 94 | * also flushed at 2d versus 3d pipeline switches. |
| 95 | * |
| 96 | * read-only caches: |
| 97 | * |
| 98 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
| 99 | * MI_READ_FLUSH is set, and is always flushed on 965. |
| 100 | * |
| 101 | * I915_GEM_DOMAIN_COMMAND may not exist? |
| 102 | * |
| 103 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
| 104 | * invalidated when MI_EXE_FLUSH is set. |
| 105 | * |
| 106 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
| 107 | * invalidated with every MI_FLUSH. |
| 108 | * |
| 109 | * TLBs: |
| 110 | * |
| 111 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
| 112 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
| 113 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
| 114 | * are flushed at any MI_FLUSH. |
| 115 | */ |
| 116 | |
| 117 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
| 118 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
| 119 | cmd &= ~MI_NO_WRITE_FLUSH; |
| 120 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
| 121 | cmd |= MI_EXE_FLUSH; |
| 122 | |
| 123 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
| 124 | (IS_G4X(dev) || IS_GEN5(dev))) |
| 125 | cmd |= MI_INVALIDATE_ISP; |
| 126 | |
| 127 | ret = intel_ring_begin(ring, 2); |
| 128 | if (ret) |
| 129 | return ret; |
| 130 | |
| 131 | intel_ring_emit(ring, cmd); |
| 132 | intel_ring_emit(ring, MI_NOOP); |
| 133 | intel_ring_advance(ring); |
| 134 | |
| 135 | return 0; |
| 136 | } |
| 137 | |
| 138 | /** |
| 139 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
| 140 | * implementing two workarounds on gen6. From section 1.4.7.1 |
| 141 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: |
| 142 | * |
| 143 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those |
| 144 | * produced by non-pipelined state commands), software needs to first |
| 145 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != |
| 146 | * 0. |
| 147 | * |
| 148 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable |
| 149 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. |
| 150 | * |
| 151 | * And the workaround for these two requires this workaround first: |
| 152 | * |
| 153 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent |
| 154 | * BEFORE the pipe-control with a post-sync op and no write-cache |
| 155 | * flushes. |
| 156 | * |
| 157 | * And this last workaround is tricky because of the requirements on |
| 158 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM |
| 159 | * volume 2 part 1: |
| 160 | * |
| 161 | * "1 of the following must also be set: |
| 162 | * - Render Target Cache Flush Enable ([12] of DW1) |
| 163 | * - Depth Cache Flush Enable ([0] of DW1) |
| 164 | * - Stall at Pixel Scoreboard ([1] of DW1) |
| 165 | * - Depth Stall ([13] of DW1) |
| 166 | * - Post-Sync Operation ([13] of DW1) |
| 167 | * - Notify Enable ([8] of DW1)" |
| 168 | * |
| 169 | * The cache flushes require the workaround flush that triggered this |
| 170 | * one, so we can't use it. Depth stall would trigger the same. |
| 171 | * Post-sync nonzero is what triggered this second workaround, so we |
| 172 | * can't use that one either. Notify enable is IRQs, which aren't |
| 173 | * really our business. That leaves only stall at scoreboard. |
| 174 | */ |
| 175 | static int |
| 176 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) |
| 177 | { |
| 178 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
| 179 | int ret; |
| 180 | |
| 181 | |
| 182 | ret = intel_ring_begin(ring, 6); |
| 183 | if (ret) |
| 184 | return ret; |
| 185 | |
| 186 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 187 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
| 188 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
| 189 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 190 | intel_ring_emit(ring, 0); /* low dword */ |
| 191 | intel_ring_emit(ring, 0); /* high dword */ |
| 192 | intel_ring_emit(ring, MI_NOOP); |
| 193 | intel_ring_advance(ring); |
| 194 | |
| 195 | ret = intel_ring_begin(ring, 6); |
| 196 | if (ret) |
| 197 | return ret; |
| 198 | |
| 199 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 200 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); |
| 201 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 202 | intel_ring_emit(ring, 0); |
| 203 | intel_ring_emit(ring, 0); |
| 204 | intel_ring_emit(ring, MI_NOOP); |
| 205 | intel_ring_advance(ring); |
| 206 | |
| 207 | return 0; |
| 208 | } |
| 209 | |
| 210 | static int |
| 211 | gen6_render_ring_flush(struct intel_ring_buffer *ring, |
| 212 | u32 invalidate_domains, u32 flush_domains) |
| 213 | { |
| 214 | u32 flags = 0; |
| 215 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
| 216 | int ret; |
| 217 | |
| 218 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
| 219 | ret = intel_emit_post_sync_nonzero_flush(ring); |
| 220 | if (ret) |
| 221 | return ret; |
| 222 | |
| 223 | /* Just flush everything. Experiments have shown that reducing the |
| 224 | * number of bits based on the write domains has little performance |
| 225 | * impact. |
| 226 | */ |
| 227 | if (flush_domains) { |
| 228 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 229 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 230 | /* |
| 231 | * Ensure that any following seqno writes only happen |
| 232 | * when the render cache is indeed flushed. |
| 233 | */ |
| 234 | flags |= PIPE_CONTROL_CS_STALL; |
| 235 | } |
| 236 | if (invalidate_domains) { |
| 237 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 238 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 239 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 240 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 241 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 242 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 243 | /* |
| 244 | * TLB invalidate requires a post-sync write. |
| 245 | */ |
| 246 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
| 247 | } |
| 248 | |
| 249 | ret = intel_ring_begin(ring, 4); |
| 250 | if (ret) |
| 251 | return ret; |
| 252 | |
| 253 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
| 254 | intel_ring_emit(ring, flags); |
| 255 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
| 256 | intel_ring_emit(ring, 0); |
| 257 | intel_ring_advance(ring); |
| 258 | |
| 259 | return 0; |
| 260 | } |
| 261 | |
| 262 | static int |
| 263 | gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring) |
| 264 | { |
| 265 | int ret; |
| 266 | |
| 267 | ret = intel_ring_begin(ring, 4); |
| 268 | if (ret) |
| 269 | return ret; |
| 270 | |
| 271 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
| 272 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
| 273 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
| 274 | intel_ring_emit(ring, 0); |
| 275 | intel_ring_emit(ring, 0); |
| 276 | intel_ring_advance(ring); |
| 277 | |
| 278 | return 0; |
| 279 | } |
| 280 | |
| 281 | static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value) |
| 282 | { |
| 283 | int ret; |
| 284 | |
| 285 | if (!ring->fbc_dirty) |
| 286 | return 0; |
| 287 | |
| 288 | ret = intel_ring_begin(ring, 6); |
| 289 | if (ret) |
| 290 | return ret; |
| 291 | /* WaFbcNukeOn3DBlt:ivb/hsw */ |
| 292 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 293 | intel_ring_emit(ring, MSG_FBC_REND_STATE); |
| 294 | intel_ring_emit(ring, value); |
| 295 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT); |
| 296 | intel_ring_emit(ring, MSG_FBC_REND_STATE); |
| 297 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
| 298 | intel_ring_advance(ring); |
| 299 | |
| 300 | ring->fbc_dirty = false; |
| 301 | return 0; |
| 302 | } |
| 303 | |
| 304 | static int |
| 305 | gen7_render_ring_flush(struct intel_ring_buffer *ring, |
| 306 | u32 invalidate_domains, u32 flush_domains) |
| 307 | { |
| 308 | u32 flags = 0; |
| 309 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
| 310 | int ret; |
| 311 | |
| 312 | /* |
| 313 | * Ensure that any following seqno writes only happen when the render |
| 314 | * cache is indeed flushed. |
| 315 | * |
| 316 | * Workaround: 4th PIPE_CONTROL command (except the ones with only |
| 317 | * read-cache invalidate bits set) must have the CS_STALL bit set. We |
| 318 | * don't try to be clever and just set it unconditionally. |
| 319 | */ |
| 320 | flags |= PIPE_CONTROL_CS_STALL; |
| 321 | |
| 322 | /* Just flush everything. Experiments have shown that reducing the |
| 323 | * number of bits based on the write domains has little performance |
| 324 | * impact. |
| 325 | */ |
| 326 | if (flush_domains) { |
| 327 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 328 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 329 | } |
| 330 | if (invalidate_domains) { |
| 331 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 332 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 333 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 334 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 335 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 336 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 337 | /* |
| 338 | * TLB invalidate requires a post-sync write. |
| 339 | */ |
| 340 | flags |= PIPE_CONTROL_QW_WRITE; |
| 341 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
| 342 | |
| 343 | /* Workaround: we must issue a pipe_control with CS-stall bit |
| 344 | * set before a pipe_control command that has the state cache |
| 345 | * invalidate bit set. */ |
| 346 | gen7_render_ring_cs_stall_wa(ring); |
| 347 | } |
| 348 | |
| 349 | ret = intel_ring_begin(ring, 4); |
| 350 | if (ret) |
| 351 | return ret; |
| 352 | |
| 353 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
| 354 | intel_ring_emit(ring, flags); |
| 355 | intel_ring_emit(ring, scratch_addr); |
| 356 | intel_ring_emit(ring, 0); |
| 357 | intel_ring_advance(ring); |
| 358 | |
| 359 | if (!invalidate_domains && flush_domains) |
| 360 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); |
| 361 | |
| 362 | return 0; |
| 363 | } |
| 364 | |
| 365 | static int |
| 366 | gen8_render_ring_flush(struct intel_ring_buffer *ring, |
| 367 | u32 invalidate_domains, u32 flush_domains) |
| 368 | { |
| 369 | u32 flags = 0; |
| 370 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
| 371 | int ret; |
| 372 | |
| 373 | flags |= PIPE_CONTROL_CS_STALL; |
| 374 | |
| 375 | if (flush_domains) { |
| 376 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 377 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 378 | } |
| 379 | if (invalidate_domains) { |
| 380 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 381 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 382 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 383 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 384 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 385 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 386 | flags |= PIPE_CONTROL_QW_WRITE; |
| 387 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
| 388 | } |
| 389 | |
| 390 | ret = intel_ring_begin(ring, 6); |
| 391 | if (ret) |
| 392 | return ret; |
| 393 | |
| 394 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
| 395 | intel_ring_emit(ring, flags); |
| 396 | intel_ring_emit(ring, scratch_addr); |
| 397 | intel_ring_emit(ring, 0); |
| 398 | intel_ring_emit(ring, 0); |
| 399 | intel_ring_emit(ring, 0); |
| 400 | intel_ring_advance(ring); |
| 401 | |
| 402 | return 0; |
| 403 | |
| 404 | } |
| 405 | |
| 406 | static void ring_write_tail(struct intel_ring_buffer *ring, |
| 407 | u32 value) |
| 408 | { |
| 409 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
| 410 | I915_WRITE_TAIL(ring, value); |
| 411 | } |
| 412 | |
| 413 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
| 414 | { |
| 415 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
| 416 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? |
| 417 | RING_ACTHD(ring->mmio_base) : ACTHD; |
| 418 | |
| 419 | return I915_READ(acthd_reg); |
| 420 | } |
| 421 | |
| 422 | static void ring_setup_phys_status_page(struct intel_ring_buffer *ring) |
| 423 | { |
| 424 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 425 | u32 addr; |
| 426 | |
| 427 | addr = dev_priv->status_page_dmah->busaddr; |
| 428 | if (INTEL_INFO(ring->dev)->gen >= 4) |
| 429 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
| 430 | I915_WRITE(HWS_PGA, addr); |
| 431 | } |
| 432 | |
| 433 | static int init_ring_common(struct intel_ring_buffer *ring) |
| 434 | { |
| 435 | struct drm_device *dev = ring->dev; |
| 436 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 437 | struct drm_i915_gem_object *obj = ring->obj; |
| 438 | int ret = 0; |
| 439 | u32 head; |
| 440 | |
| 441 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
| 442 | |
| 443 | /* Stop the ring if it's running. */ |
| 444 | I915_WRITE_CTL(ring, 0); |
| 445 | I915_WRITE_HEAD(ring, 0); |
| 446 | ring->write_tail(ring, 0); |
| 447 | if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) |
| 448 | DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); |
| 449 | |
| 450 | if (I915_NEED_GFX_HWS(dev)) |
| 451 | intel_ring_setup_status_page(ring); |
| 452 | else |
| 453 | ring_setup_phys_status_page(ring); |
| 454 | |
| 455 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
| 456 | |
| 457 | /* G45 ring initialization fails to reset head to zero */ |
| 458 | if (head != 0) { |
| 459 | DRM_DEBUG_KMS("%s head not reset to zero " |
| 460 | "ctl %08x head %08x tail %08x start %08x\n", |
| 461 | ring->name, |
| 462 | I915_READ_CTL(ring), |
| 463 | I915_READ_HEAD(ring), |
| 464 | I915_READ_TAIL(ring), |
| 465 | I915_READ_START(ring)); |
| 466 | |
| 467 | I915_WRITE_HEAD(ring, 0); |
| 468 | |
| 469 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
| 470 | DRM_ERROR("failed to set %s head to zero " |
| 471 | "ctl %08x head %08x tail %08x start %08x\n", |
| 472 | ring->name, |
| 473 | I915_READ_CTL(ring), |
| 474 | I915_READ_HEAD(ring), |
| 475 | I915_READ_TAIL(ring), |
| 476 | I915_READ_START(ring)); |
| 477 | } |
| 478 | } |
| 479 | |
| 480 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
| 481 | * registers with the above sequence (the readback of the HEAD registers |
| 482 | * also enforces ordering), otherwise the hw might lose the new ring |
| 483 | * register values. */ |
| 484 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
| 485 | I915_WRITE_CTL(ring, |
| 486 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
| 487 | | RING_VALID); |
| 488 | |
| 489 | /* If the head is still not zero, the ring is dead */ |
| 490 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
| 491 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
| 492 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
| 493 | DRM_ERROR("%s initialization failed " |
| 494 | "ctl %08x head %08x tail %08x start %08x\n", |
| 495 | ring->name, |
| 496 | I915_READ_CTL(ring), |
| 497 | I915_READ_HEAD(ring), |
| 498 | I915_READ_TAIL(ring), |
| 499 | I915_READ_START(ring)); |
| 500 | ret = -EIO; |
| 501 | goto out; |
| 502 | } |
| 503 | |
| 504 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
| 505 | i915_kernel_lost_context(ring->dev); |
| 506 | else { |
| 507 | ring->head = I915_READ_HEAD(ring); |
| 508 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
| 509 | ring->space = ring_space(ring); |
| 510 | ring->last_retired_head = -1; |
| 511 | } |
| 512 | |
| 513 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
| 514 | |
| 515 | out: |
| 516 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
| 517 | |
| 518 | return ret; |
| 519 | } |
| 520 | |
| 521 | static int |
| 522 | init_pipe_control(struct intel_ring_buffer *ring) |
| 523 | { |
| 524 | int ret; |
| 525 | |
| 526 | if (ring->scratch.obj) |
| 527 | return 0; |
| 528 | |
| 529 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
| 530 | if (ring->scratch.obj == NULL) { |
| 531 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 532 | ret = -ENOMEM; |
| 533 | goto err; |
| 534 | } |
| 535 | |
| 536 | ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
| 537 | if (ret) |
| 538 | goto err_unref; |
| 539 | |
| 540 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0); |
| 541 | if (ret) |
| 542 | goto err_unref; |
| 543 | |
| 544 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
| 545 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); |
| 546 | if (ring->scratch.cpu_page == NULL) { |
| 547 | ret = -ENOMEM; |
| 548 | goto err_unpin; |
| 549 | } |
| 550 | |
| 551 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
| 552 | ring->name, ring->scratch.gtt_offset); |
| 553 | return 0; |
| 554 | |
| 555 | err_unpin: |
| 556 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
| 557 | err_unref: |
| 558 | drm_gem_object_unreference(&ring->scratch.obj->base); |
| 559 | err: |
| 560 | return ret; |
| 561 | } |
| 562 | |
| 563 | static int init_render_ring(struct intel_ring_buffer *ring) |
| 564 | { |
| 565 | struct drm_device *dev = ring->dev; |
| 566 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 567 | int ret = init_ring_common(ring); |
| 568 | |
| 569 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
| 570 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) |
| 571 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
| 572 | |
| 573 | /* We need to disable the AsyncFlip performance optimisations in order |
| 574 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be |
| 575 | * programmed to '1' on all products. |
| 576 | * |
| 577 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw |
| 578 | */ |
| 579 | if (INTEL_INFO(dev)->gen >= 6) |
| 580 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
| 581 | |
| 582 | /* Required for the hardware to program scanline values for waiting */ |
| 583 | if (INTEL_INFO(dev)->gen == 6) |
| 584 | I915_WRITE(GFX_MODE, |
| 585 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS)); |
| 586 | |
| 587 | if (IS_GEN7(dev)) |
| 588 | I915_WRITE(GFX_MODE_GEN7, |
| 589 | _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | |
| 590 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
| 591 | |
| 592 | if (INTEL_INFO(dev)->gen >= 5) { |
| 593 | ret = init_pipe_control(ring); |
| 594 | if (ret) |
| 595 | return ret; |
| 596 | } |
| 597 | |
| 598 | if (IS_GEN6(dev)) { |
| 599 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
| 600 | * "If this bit is set, STCunit will have LRA as replacement |
| 601 | * policy. [...] This bit must be reset. LRA replacement |
| 602 | * policy is not supported." |
| 603 | */ |
| 604 | I915_WRITE(CACHE_MODE_0, |
| 605 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
| 606 | |
| 607 | /* This is not explicitly set for GEN6, so read the register. |
| 608 | * see intel_ring_mi_set_context() for why we care. |
| 609 | * TODO: consider explicitly setting the bit for GEN5 |
| 610 | */ |
| 611 | ring->itlb_before_ctx_switch = |
| 612 | !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS); |
| 613 | } |
| 614 | |
| 615 | if (INTEL_INFO(dev)->gen >= 6) |
| 616 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
| 617 | |
| 618 | if (HAS_L3_DPF(dev)) |
| 619 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
| 620 | |
| 621 | return ret; |
| 622 | } |
| 623 | |
| 624 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
| 625 | { |
| 626 | struct drm_device *dev = ring->dev; |
| 627 | |
| 628 | if (ring->scratch.obj == NULL) |
| 629 | return; |
| 630 | |
| 631 | if (INTEL_INFO(dev)->gen >= 5) { |
| 632 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); |
| 633 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
| 634 | } |
| 635 | |
| 636 | drm_gem_object_unreference(&ring->scratch.obj->base); |
| 637 | ring->scratch.obj = NULL; |
| 638 | } |
| 639 | |
| 640 | static void |
| 641 | update_mboxes(struct intel_ring_buffer *ring, |
| 642 | u32 mmio_offset) |
| 643 | { |
| 644 | /* NB: In order to be able to do semaphore MBOX updates for varying number |
| 645 | * of rings, it's easiest if we round up each individual update to a |
| 646 | * multiple of 2 (since ring updates must always be a multiple of 2) |
| 647 | * even though the actual update only requires 3 dwords. |
| 648 | */ |
| 649 | #define MBOX_UPDATE_DWORDS 4 |
| 650 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 651 | intel_ring_emit(ring, mmio_offset); |
| 652 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
| 653 | intel_ring_emit(ring, MI_NOOP); |
| 654 | } |
| 655 | |
| 656 | /** |
| 657 | * gen6_add_request - Update the semaphore mailbox registers |
| 658 | * |
| 659 | * @ring - ring that is adding a request |
| 660 | * @seqno - return seqno stuck into the ring |
| 661 | * |
| 662 | * Update the mailbox registers in the *other* rings with the current seqno. |
| 663 | * This acts like a signal in the canonical semaphore. |
| 664 | */ |
| 665 | static int |
| 666 | gen6_add_request(struct intel_ring_buffer *ring) |
| 667 | { |
| 668 | struct drm_device *dev = ring->dev; |
| 669 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 670 | struct intel_ring_buffer *useless; |
| 671 | int i, ret, num_dwords = 4; |
| 672 | |
| 673 | if (i915_semaphore_is_enabled(dev)) |
| 674 | num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS); |
| 675 | #undef MBOX_UPDATE_DWORDS |
| 676 | |
| 677 | ret = intel_ring_begin(ring, num_dwords); |
| 678 | if (ret) |
| 679 | return ret; |
| 680 | |
| 681 | if (i915_semaphore_is_enabled(dev)) { |
| 682 | for_each_ring(useless, dev_priv, i) { |
| 683 | u32 mbox_reg = ring->signal_mbox[i]; |
| 684 | if (mbox_reg != GEN6_NOSYNC) |
| 685 | update_mboxes(ring, mbox_reg); |
| 686 | } |
| 687 | } |
| 688 | |
| 689 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 690 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 691 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
| 692 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
| 693 | __intel_ring_advance(ring); |
| 694 | |
| 695 | return 0; |
| 696 | } |
| 697 | |
| 698 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
| 699 | u32 seqno) |
| 700 | { |
| 701 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 702 | return dev_priv->last_seqno < seqno; |
| 703 | } |
| 704 | |
| 705 | /** |
| 706 | * intel_ring_sync - sync the waiter to the signaller on seqno |
| 707 | * |
| 708 | * @waiter - ring that is waiting |
| 709 | * @signaller - ring which has, or will signal |
| 710 | * @seqno - seqno which the waiter will block on |
| 711 | */ |
| 712 | static int |
| 713 | gen6_ring_sync(struct intel_ring_buffer *waiter, |
| 714 | struct intel_ring_buffer *signaller, |
| 715 | u32 seqno) |
| 716 | { |
| 717 | int ret; |
| 718 | u32 dw1 = MI_SEMAPHORE_MBOX | |
| 719 | MI_SEMAPHORE_COMPARE | |
| 720 | MI_SEMAPHORE_REGISTER; |
| 721 | |
| 722 | /* Throughout all of the GEM code, seqno passed implies our current |
| 723 | * seqno is >= the last seqno executed. However for hardware the |
| 724 | * comparison is strictly greater than. |
| 725 | */ |
| 726 | seqno -= 1; |
| 727 | |
| 728 | WARN_ON(signaller->semaphore_register[waiter->id] == |
| 729 | MI_SEMAPHORE_SYNC_INVALID); |
| 730 | |
| 731 | ret = intel_ring_begin(waiter, 4); |
| 732 | if (ret) |
| 733 | return ret; |
| 734 | |
| 735 | /* If seqno wrap happened, omit the wait with no-ops */ |
| 736 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { |
| 737 | intel_ring_emit(waiter, |
| 738 | dw1 | |
| 739 | signaller->semaphore_register[waiter->id]); |
| 740 | intel_ring_emit(waiter, seqno); |
| 741 | intel_ring_emit(waiter, 0); |
| 742 | intel_ring_emit(waiter, MI_NOOP); |
| 743 | } else { |
| 744 | intel_ring_emit(waiter, MI_NOOP); |
| 745 | intel_ring_emit(waiter, MI_NOOP); |
| 746 | intel_ring_emit(waiter, MI_NOOP); |
| 747 | intel_ring_emit(waiter, MI_NOOP); |
| 748 | } |
| 749 | intel_ring_advance(waiter); |
| 750 | |
| 751 | return 0; |
| 752 | } |
| 753 | |
| 754 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
| 755 | do { \ |
| 756 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
| 757 | PIPE_CONTROL_DEPTH_STALL); \ |
| 758 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
| 759 | intel_ring_emit(ring__, 0); \ |
| 760 | intel_ring_emit(ring__, 0); \ |
| 761 | } while (0) |
| 762 | |
| 763 | static int |
| 764 | pc_render_add_request(struct intel_ring_buffer *ring) |
| 765 | { |
| 766 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
| 767 | int ret; |
| 768 | |
| 769 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently |
| 770 | * incoherent with writes to memory, i.e. completely fubar, |
| 771 | * so we need to use PIPE_NOTIFY instead. |
| 772 | * |
| 773 | * However, we also need to workaround the qword write |
| 774 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to |
| 775 | * memory before requesting an interrupt. |
| 776 | */ |
| 777 | ret = intel_ring_begin(ring, 32); |
| 778 | if (ret) |
| 779 | return ret; |
| 780 | |
| 781 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
| 782 | PIPE_CONTROL_WRITE_FLUSH | |
| 783 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); |
| 784 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
| 785 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
| 786 | intel_ring_emit(ring, 0); |
| 787 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 788 | scratch_addr += 128; /* write to separate cachelines */ |
| 789 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 790 | scratch_addr += 128; |
| 791 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 792 | scratch_addr += 128; |
| 793 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 794 | scratch_addr += 128; |
| 795 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 796 | scratch_addr += 128; |
| 797 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 798 | |
| 799 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
| 800 | PIPE_CONTROL_WRITE_FLUSH | |
| 801 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | |
| 802 | PIPE_CONTROL_NOTIFY); |
| 803 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
| 804 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
| 805 | intel_ring_emit(ring, 0); |
| 806 | __intel_ring_advance(ring); |
| 807 | |
| 808 | return 0; |
| 809 | } |
| 810 | |
| 811 | static u32 |
| 812 | gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
| 813 | { |
| 814 | /* Workaround to force correct ordering between irq and seqno writes on |
| 815 | * ivb (and maybe also on snb) by reading from a CS register (like |
| 816 | * ACTHD) before reading the status page. */ |
| 817 | if (!lazy_coherency) |
| 818 | intel_ring_get_active_head(ring); |
| 819 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 820 | } |
| 821 | |
| 822 | static u32 |
| 823 | ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
| 824 | { |
| 825 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 826 | } |
| 827 | |
| 828 | static void |
| 829 | ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno) |
| 830 | { |
| 831 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); |
| 832 | } |
| 833 | |
| 834 | static u32 |
| 835 | pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
| 836 | { |
| 837 | return ring->scratch.cpu_page[0]; |
| 838 | } |
| 839 | |
| 840 | static void |
| 841 | pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno) |
| 842 | { |
| 843 | ring->scratch.cpu_page[0] = seqno; |
| 844 | } |
| 845 | |
| 846 | static bool |
| 847 | gen5_ring_get_irq(struct intel_ring_buffer *ring) |
| 848 | { |
| 849 | struct drm_device *dev = ring->dev; |
| 850 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 851 | unsigned long flags; |
| 852 | |
| 853 | if (!dev->irq_enabled) |
| 854 | return false; |
| 855 | |
| 856 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 857 | if (ring->irq_refcount++ == 0) |
| 858 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
| 859 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 860 | |
| 861 | return true; |
| 862 | } |
| 863 | |
| 864 | static void |
| 865 | gen5_ring_put_irq(struct intel_ring_buffer *ring) |
| 866 | { |
| 867 | struct drm_device *dev = ring->dev; |
| 868 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 869 | unsigned long flags; |
| 870 | |
| 871 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 872 | if (--ring->irq_refcount == 0) |
| 873 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
| 874 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 875 | } |
| 876 | |
| 877 | static bool |
| 878 | i9xx_ring_get_irq(struct intel_ring_buffer *ring) |
| 879 | { |
| 880 | struct drm_device *dev = ring->dev; |
| 881 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 882 | unsigned long flags; |
| 883 | |
| 884 | if (!dev->irq_enabled) |
| 885 | return false; |
| 886 | |
| 887 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 888 | if (ring->irq_refcount++ == 0) { |
| 889 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
| 890 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 891 | POSTING_READ(IMR); |
| 892 | } |
| 893 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 894 | |
| 895 | return true; |
| 896 | } |
| 897 | |
| 898 | static void |
| 899 | i9xx_ring_put_irq(struct intel_ring_buffer *ring) |
| 900 | { |
| 901 | struct drm_device *dev = ring->dev; |
| 902 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 903 | unsigned long flags; |
| 904 | |
| 905 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 906 | if (--ring->irq_refcount == 0) { |
| 907 | dev_priv->irq_mask |= ring->irq_enable_mask; |
| 908 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 909 | POSTING_READ(IMR); |
| 910 | } |
| 911 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 912 | } |
| 913 | |
| 914 | static bool |
| 915 | i8xx_ring_get_irq(struct intel_ring_buffer *ring) |
| 916 | { |
| 917 | struct drm_device *dev = ring->dev; |
| 918 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 919 | unsigned long flags; |
| 920 | |
| 921 | if (!dev->irq_enabled) |
| 922 | return false; |
| 923 | |
| 924 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 925 | if (ring->irq_refcount++ == 0) { |
| 926 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
| 927 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 928 | POSTING_READ16(IMR); |
| 929 | } |
| 930 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 931 | |
| 932 | return true; |
| 933 | } |
| 934 | |
| 935 | static void |
| 936 | i8xx_ring_put_irq(struct intel_ring_buffer *ring) |
| 937 | { |
| 938 | struct drm_device *dev = ring->dev; |
| 939 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 940 | unsigned long flags; |
| 941 | |
| 942 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 943 | if (--ring->irq_refcount == 0) { |
| 944 | dev_priv->irq_mask |= ring->irq_enable_mask; |
| 945 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 946 | POSTING_READ16(IMR); |
| 947 | } |
| 948 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 949 | } |
| 950 | |
| 951 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
| 952 | { |
| 953 | struct drm_device *dev = ring->dev; |
| 954 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
| 955 | u32 mmio = 0; |
| 956 | |
| 957 | /* The ring status page addresses are no longer next to the rest of |
| 958 | * the ring registers as of gen7. |
| 959 | */ |
| 960 | if (IS_GEN7(dev)) { |
| 961 | switch (ring->id) { |
| 962 | case RCS: |
| 963 | mmio = RENDER_HWS_PGA_GEN7; |
| 964 | break; |
| 965 | case BCS: |
| 966 | mmio = BLT_HWS_PGA_GEN7; |
| 967 | break; |
| 968 | case VCS: |
| 969 | mmio = BSD_HWS_PGA_GEN7; |
| 970 | break; |
| 971 | case VECS: |
| 972 | mmio = VEBOX_HWS_PGA_GEN7; |
| 973 | break; |
| 974 | } |
| 975 | } else if (IS_GEN6(ring->dev)) { |
| 976 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); |
| 977 | } else { |
| 978 | /* XXX: gen8 returns to sanity */ |
| 979 | mmio = RING_HWS_PGA(ring->mmio_base); |
| 980 | } |
| 981 | |
| 982 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
| 983 | POSTING_READ(mmio); |
| 984 | |
| 985 | /* |
| 986 | * Flush the TLB for this page |
| 987 | * |
| 988 | * FIXME: These two bits have disappeared on gen8, so a question |
| 989 | * arises: do we still need this and if so how should we go about |
| 990 | * invalidating the TLB? |
| 991 | */ |
| 992 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { |
| 993 | u32 reg = RING_INSTPM(ring->mmio_base); |
| 994 | |
| 995 | /* ring should be idle before issuing a sync flush*/ |
| 996 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); |
| 997 | |
| 998 | I915_WRITE(reg, |
| 999 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | |
| 1000 | INSTPM_SYNC_FLUSH)); |
| 1001 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, |
| 1002 | 1000)) |
| 1003 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
| 1004 | ring->name); |
| 1005 | } |
| 1006 | } |
| 1007 | |
| 1008 | static int |
| 1009 | bsd_ring_flush(struct intel_ring_buffer *ring, |
| 1010 | u32 invalidate_domains, |
| 1011 | u32 flush_domains) |
| 1012 | { |
| 1013 | int ret; |
| 1014 | |
| 1015 | ret = intel_ring_begin(ring, 2); |
| 1016 | if (ret) |
| 1017 | return ret; |
| 1018 | |
| 1019 | intel_ring_emit(ring, MI_FLUSH); |
| 1020 | intel_ring_emit(ring, MI_NOOP); |
| 1021 | intel_ring_advance(ring); |
| 1022 | return 0; |
| 1023 | } |
| 1024 | |
| 1025 | static int |
| 1026 | i9xx_add_request(struct intel_ring_buffer *ring) |
| 1027 | { |
| 1028 | int ret; |
| 1029 | |
| 1030 | ret = intel_ring_begin(ring, 4); |
| 1031 | if (ret) |
| 1032 | return ret; |
| 1033 | |
| 1034 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 1035 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 1036 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
| 1037 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
| 1038 | __intel_ring_advance(ring); |
| 1039 | |
| 1040 | return 0; |
| 1041 | } |
| 1042 | |
| 1043 | static bool |
| 1044 | gen6_ring_get_irq(struct intel_ring_buffer *ring) |
| 1045 | { |
| 1046 | struct drm_device *dev = ring->dev; |
| 1047 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1048 | unsigned long flags; |
| 1049 | |
| 1050 | if (!dev->irq_enabled) |
| 1051 | return false; |
| 1052 | |
| 1053 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 1054 | if (ring->irq_refcount++ == 0) { |
| 1055 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
| 1056 | I915_WRITE_IMR(ring, |
| 1057 | ~(ring->irq_enable_mask | |
| 1058 | GT_PARITY_ERROR(dev))); |
| 1059 | else |
| 1060 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
| 1061 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
| 1062 | } |
| 1063 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1064 | |
| 1065 | return true; |
| 1066 | } |
| 1067 | |
| 1068 | static void |
| 1069 | gen6_ring_put_irq(struct intel_ring_buffer *ring) |
| 1070 | { |
| 1071 | struct drm_device *dev = ring->dev; |
| 1072 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1073 | unsigned long flags; |
| 1074 | |
| 1075 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 1076 | if (--ring->irq_refcount == 0) { |
| 1077 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
| 1078 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
| 1079 | else |
| 1080 | I915_WRITE_IMR(ring, ~0); |
| 1081 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
| 1082 | } |
| 1083 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1084 | } |
| 1085 | |
| 1086 | static bool |
| 1087 | hsw_vebox_get_irq(struct intel_ring_buffer *ring) |
| 1088 | { |
| 1089 | struct drm_device *dev = ring->dev; |
| 1090 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1091 | unsigned long flags; |
| 1092 | |
| 1093 | if (!dev->irq_enabled) |
| 1094 | return false; |
| 1095 | |
| 1096 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 1097 | if (ring->irq_refcount++ == 0) { |
| 1098 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
| 1099 | snb_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
| 1100 | } |
| 1101 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1102 | |
| 1103 | return true; |
| 1104 | } |
| 1105 | |
| 1106 | static void |
| 1107 | hsw_vebox_put_irq(struct intel_ring_buffer *ring) |
| 1108 | { |
| 1109 | struct drm_device *dev = ring->dev; |
| 1110 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1111 | unsigned long flags; |
| 1112 | |
| 1113 | if (!dev->irq_enabled) |
| 1114 | return; |
| 1115 | |
| 1116 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 1117 | if (--ring->irq_refcount == 0) { |
| 1118 | I915_WRITE_IMR(ring, ~0); |
| 1119 | snb_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
| 1120 | } |
| 1121 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1122 | } |
| 1123 | |
| 1124 | static bool |
| 1125 | gen8_ring_get_irq(struct intel_ring_buffer *ring) |
| 1126 | { |
| 1127 | struct drm_device *dev = ring->dev; |
| 1128 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1129 | unsigned long flags; |
| 1130 | |
| 1131 | if (!dev->irq_enabled) |
| 1132 | return false; |
| 1133 | |
| 1134 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 1135 | if (ring->irq_refcount++ == 0) { |
| 1136 | if (HAS_L3_DPF(dev) && ring->id == RCS) { |
| 1137 | I915_WRITE_IMR(ring, |
| 1138 | ~(ring->irq_enable_mask | |
| 1139 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); |
| 1140 | } else { |
| 1141 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
| 1142 | } |
| 1143 | POSTING_READ(RING_IMR(ring->mmio_base)); |
| 1144 | } |
| 1145 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1146 | |
| 1147 | return true; |
| 1148 | } |
| 1149 | |
| 1150 | static void |
| 1151 | gen8_ring_put_irq(struct intel_ring_buffer *ring) |
| 1152 | { |
| 1153 | struct drm_device *dev = ring->dev; |
| 1154 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1155 | unsigned long flags; |
| 1156 | |
| 1157 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 1158 | if (--ring->irq_refcount == 0) { |
| 1159 | if (HAS_L3_DPF(dev) && ring->id == RCS) { |
| 1160 | I915_WRITE_IMR(ring, |
| 1161 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); |
| 1162 | } else { |
| 1163 | I915_WRITE_IMR(ring, ~0); |
| 1164 | } |
| 1165 | POSTING_READ(RING_IMR(ring->mmio_base)); |
| 1166 | } |
| 1167 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1168 | } |
| 1169 | |
| 1170 | static int |
| 1171 | i965_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 1172 | u32 offset, u32 length, |
| 1173 | unsigned flags) |
| 1174 | { |
| 1175 | int ret; |
| 1176 | |
| 1177 | ret = intel_ring_begin(ring, 2); |
| 1178 | if (ret) |
| 1179 | return ret; |
| 1180 | |
| 1181 | intel_ring_emit(ring, |
| 1182 | MI_BATCH_BUFFER_START | |
| 1183 | MI_BATCH_GTT | |
| 1184 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
| 1185 | intel_ring_emit(ring, offset); |
| 1186 | intel_ring_advance(ring); |
| 1187 | |
| 1188 | return 0; |
| 1189 | } |
| 1190 | |
| 1191 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
| 1192 | #define I830_BATCH_LIMIT (256*1024) |
| 1193 | static int |
| 1194 | i830_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 1195 | u32 offset, u32 len, |
| 1196 | unsigned flags) |
| 1197 | { |
| 1198 | int ret; |
| 1199 | |
| 1200 | if (flags & I915_DISPATCH_PINNED) { |
| 1201 | ret = intel_ring_begin(ring, 4); |
| 1202 | if (ret) |
| 1203 | return ret; |
| 1204 | |
| 1205 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
| 1206 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
| 1207 | intel_ring_emit(ring, offset + len - 8); |
| 1208 | intel_ring_emit(ring, MI_NOOP); |
| 1209 | intel_ring_advance(ring); |
| 1210 | } else { |
| 1211 | u32 cs_offset = ring->scratch.gtt_offset; |
| 1212 | |
| 1213 | if (len > I830_BATCH_LIMIT) |
| 1214 | return -ENOSPC; |
| 1215 | |
| 1216 | ret = intel_ring_begin(ring, 9+3); |
| 1217 | if (ret) |
| 1218 | return ret; |
| 1219 | /* Blit the batch (which has now all relocs applied) to the stable batch |
| 1220 | * scratch bo area (so that the CS never stumbles over its tlb |
| 1221 | * invalidation bug) ... */ |
| 1222 | intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD | |
| 1223 | XY_SRC_COPY_BLT_WRITE_ALPHA | |
| 1224 | XY_SRC_COPY_BLT_WRITE_RGB); |
| 1225 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096); |
| 1226 | intel_ring_emit(ring, 0); |
| 1227 | intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024); |
| 1228 | intel_ring_emit(ring, cs_offset); |
| 1229 | intel_ring_emit(ring, 0); |
| 1230 | intel_ring_emit(ring, 4096); |
| 1231 | intel_ring_emit(ring, offset); |
| 1232 | intel_ring_emit(ring, MI_FLUSH); |
| 1233 | |
| 1234 | /* ... and execute it. */ |
| 1235 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
| 1236 | intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
| 1237 | intel_ring_emit(ring, cs_offset + len - 8); |
| 1238 | intel_ring_advance(ring); |
| 1239 | } |
| 1240 | |
| 1241 | return 0; |
| 1242 | } |
| 1243 | |
| 1244 | static int |
| 1245 | i915_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 1246 | u32 offset, u32 len, |
| 1247 | unsigned flags) |
| 1248 | { |
| 1249 | int ret; |
| 1250 | |
| 1251 | ret = intel_ring_begin(ring, 2); |
| 1252 | if (ret) |
| 1253 | return ret; |
| 1254 | |
| 1255 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
| 1256 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
| 1257 | intel_ring_advance(ring); |
| 1258 | |
| 1259 | return 0; |
| 1260 | } |
| 1261 | |
| 1262 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
| 1263 | { |
| 1264 | struct drm_i915_gem_object *obj; |
| 1265 | |
| 1266 | obj = ring->status_page.obj; |
| 1267 | if (obj == NULL) |
| 1268 | return; |
| 1269 | |
| 1270 | kunmap(sg_page(obj->pages->sgl)); |
| 1271 | i915_gem_object_ggtt_unpin(obj); |
| 1272 | drm_gem_object_unreference(&obj->base); |
| 1273 | ring->status_page.obj = NULL; |
| 1274 | } |
| 1275 | |
| 1276 | static int init_status_page(struct intel_ring_buffer *ring) |
| 1277 | { |
| 1278 | struct drm_device *dev = ring->dev; |
| 1279 | struct drm_i915_gem_object *obj; |
| 1280 | int ret; |
| 1281 | |
| 1282 | obj = i915_gem_alloc_object(dev, 4096); |
| 1283 | if (obj == NULL) { |
| 1284 | DRM_ERROR("Failed to allocate status page\n"); |
| 1285 | ret = -ENOMEM; |
| 1286 | goto err; |
| 1287 | } |
| 1288 | |
| 1289 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
| 1290 | if (ret) |
| 1291 | goto err_unref; |
| 1292 | |
| 1293 | ret = i915_gem_obj_ggtt_pin(obj, 4096, 0); |
| 1294 | if (ret) |
| 1295 | goto err_unref; |
| 1296 | |
| 1297 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
| 1298 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
| 1299 | if (ring->status_page.page_addr == NULL) { |
| 1300 | ret = -ENOMEM; |
| 1301 | goto err_unpin; |
| 1302 | } |
| 1303 | ring->status_page.obj = obj; |
| 1304 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
| 1305 | |
| 1306 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
| 1307 | ring->name, ring->status_page.gfx_addr); |
| 1308 | |
| 1309 | return 0; |
| 1310 | |
| 1311 | err_unpin: |
| 1312 | i915_gem_object_ggtt_unpin(obj); |
| 1313 | err_unref: |
| 1314 | drm_gem_object_unreference(&obj->base); |
| 1315 | err: |
| 1316 | return ret; |
| 1317 | } |
| 1318 | |
| 1319 | static int init_phys_status_page(struct intel_ring_buffer *ring) |
| 1320 | { |
| 1321 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 1322 | |
| 1323 | if (!dev_priv->status_page_dmah) { |
| 1324 | dev_priv->status_page_dmah = |
| 1325 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); |
| 1326 | if (!dev_priv->status_page_dmah) |
| 1327 | return -ENOMEM; |
| 1328 | } |
| 1329 | |
| 1330 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
| 1331 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
| 1332 | |
| 1333 | return 0; |
| 1334 | } |
| 1335 | |
| 1336 | static int intel_init_ring_buffer(struct drm_device *dev, |
| 1337 | struct intel_ring_buffer *ring) |
| 1338 | { |
| 1339 | struct drm_i915_gem_object *obj; |
| 1340 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1341 | int ret; |
| 1342 | |
| 1343 | ring->dev = dev; |
| 1344 | INIT_LIST_HEAD(&ring->active_list); |
| 1345 | INIT_LIST_HEAD(&ring->request_list); |
| 1346 | ring->size = 32 * PAGE_SIZE; |
| 1347 | memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno)); |
| 1348 | |
| 1349 | init_waitqueue_head(&ring->irq_queue); |
| 1350 | |
| 1351 | if (I915_NEED_GFX_HWS(dev)) { |
| 1352 | ret = init_status_page(ring); |
| 1353 | if (ret) |
| 1354 | return ret; |
| 1355 | } else { |
| 1356 | BUG_ON(ring->id != RCS); |
| 1357 | ret = init_phys_status_page(ring); |
| 1358 | if (ret) |
| 1359 | return ret; |
| 1360 | } |
| 1361 | |
| 1362 | obj = NULL; |
| 1363 | if (!HAS_LLC(dev)) |
| 1364 | obj = i915_gem_object_create_stolen(dev, ring->size); |
| 1365 | if (obj == NULL) |
| 1366 | obj = i915_gem_alloc_object(dev, ring->size); |
| 1367 | if (obj == NULL) { |
| 1368 | DRM_ERROR("Failed to allocate ringbuffer\n"); |
| 1369 | ret = -ENOMEM; |
| 1370 | goto err_hws; |
| 1371 | } |
| 1372 | |
| 1373 | ring->obj = obj; |
| 1374 | |
| 1375 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); |
| 1376 | if (ret) |
| 1377 | goto err_unref; |
| 1378 | |
| 1379 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 1380 | if (ret) |
| 1381 | goto err_unpin; |
| 1382 | |
| 1383 | ring->virtual_start = |
| 1384 | ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj), |
| 1385 | ring->size); |
| 1386 | if (ring->virtual_start == NULL) { |
| 1387 | DRM_ERROR("Failed to map ringbuffer.\n"); |
| 1388 | ret = -EINVAL; |
| 1389 | goto err_unpin; |
| 1390 | } |
| 1391 | |
| 1392 | ret = ring->init(ring); |
| 1393 | if (ret) |
| 1394 | goto err_unmap; |
| 1395 | |
| 1396 | /* Workaround an erratum on the i830 which causes a hang if |
| 1397 | * the TAIL pointer points to within the last 2 cachelines |
| 1398 | * of the buffer. |
| 1399 | */ |
| 1400 | ring->effective_size = ring->size; |
| 1401 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
| 1402 | ring->effective_size -= 128; |
| 1403 | |
| 1404 | i915_cmd_parser_init_ring(ring); |
| 1405 | |
| 1406 | return 0; |
| 1407 | |
| 1408 | err_unmap: |
| 1409 | iounmap(ring->virtual_start); |
| 1410 | err_unpin: |
| 1411 | i915_gem_object_ggtt_unpin(obj); |
| 1412 | err_unref: |
| 1413 | drm_gem_object_unreference(&obj->base); |
| 1414 | ring->obj = NULL; |
| 1415 | err_hws: |
| 1416 | cleanup_status_page(ring); |
| 1417 | return ret; |
| 1418 | } |
| 1419 | |
| 1420 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
| 1421 | { |
| 1422 | struct drm_i915_private *dev_priv; |
| 1423 | int ret; |
| 1424 | |
| 1425 | if (ring->obj == NULL) |
| 1426 | return; |
| 1427 | |
| 1428 | /* Disable the ring buffer. The ring must be idle at this point */ |
| 1429 | dev_priv = ring->dev->dev_private; |
| 1430 | ret = intel_ring_idle(ring); |
| 1431 | if (ret && !i915_reset_in_progress(&dev_priv->gpu_error)) |
| 1432 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
| 1433 | ring->name, ret); |
| 1434 | |
| 1435 | I915_WRITE_CTL(ring, 0); |
| 1436 | |
| 1437 | iounmap(ring->virtual_start); |
| 1438 | |
| 1439 | i915_gem_object_ggtt_unpin(ring->obj); |
| 1440 | drm_gem_object_unreference(&ring->obj->base); |
| 1441 | ring->obj = NULL; |
| 1442 | ring->preallocated_lazy_request = NULL; |
| 1443 | ring->outstanding_lazy_seqno = 0; |
| 1444 | |
| 1445 | if (ring->cleanup) |
| 1446 | ring->cleanup(ring); |
| 1447 | |
| 1448 | cleanup_status_page(ring); |
| 1449 | } |
| 1450 | |
| 1451 | static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) |
| 1452 | { |
| 1453 | struct drm_i915_gem_request *request; |
| 1454 | u32 seqno = 0, tail; |
| 1455 | int ret; |
| 1456 | |
| 1457 | if (ring->last_retired_head != -1) { |
| 1458 | ring->head = ring->last_retired_head; |
| 1459 | ring->last_retired_head = -1; |
| 1460 | |
| 1461 | ring->space = ring_space(ring); |
| 1462 | if (ring->space >= n) |
| 1463 | return 0; |
| 1464 | } |
| 1465 | |
| 1466 | list_for_each_entry(request, &ring->request_list, list) { |
| 1467 | int space; |
| 1468 | |
| 1469 | if (request->tail == -1) |
| 1470 | continue; |
| 1471 | |
| 1472 | space = request->tail - (ring->tail + I915_RING_FREE_SPACE); |
| 1473 | if (space < 0) |
| 1474 | space += ring->size; |
| 1475 | if (space >= n) { |
| 1476 | seqno = request->seqno; |
| 1477 | tail = request->tail; |
| 1478 | break; |
| 1479 | } |
| 1480 | |
| 1481 | /* Consume this request in case we need more space than |
| 1482 | * is available and so need to prevent a race between |
| 1483 | * updating last_retired_head and direct reads of |
| 1484 | * I915_RING_HEAD. It also provides a nice sanity check. |
| 1485 | */ |
| 1486 | request->tail = -1; |
| 1487 | } |
| 1488 | |
| 1489 | if (seqno == 0) |
| 1490 | return -ENOSPC; |
| 1491 | |
| 1492 | ret = i915_wait_seqno(ring, seqno); |
| 1493 | if (ret) |
| 1494 | return ret; |
| 1495 | |
| 1496 | ring->head = tail; |
| 1497 | ring->space = ring_space(ring); |
| 1498 | if (WARN_ON(ring->space < n)) |
| 1499 | return -ENOSPC; |
| 1500 | |
| 1501 | return 0; |
| 1502 | } |
| 1503 | |
| 1504 | static int ring_wait_for_space(struct intel_ring_buffer *ring, int n) |
| 1505 | { |
| 1506 | struct drm_device *dev = ring->dev; |
| 1507 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1508 | unsigned long end; |
| 1509 | int ret; |
| 1510 | |
| 1511 | ret = intel_ring_wait_request(ring, n); |
| 1512 | if (ret != -ENOSPC) |
| 1513 | return ret; |
| 1514 | |
| 1515 | /* force the tail write in case we have been skipping them */ |
| 1516 | __intel_ring_advance(ring); |
| 1517 | |
| 1518 | trace_i915_ring_wait_begin(ring); |
| 1519 | /* With GEM the hangcheck timer should kick us out of the loop, |
| 1520 | * leaving it early runs the risk of corrupting GEM state (due |
| 1521 | * to running on almost untested codepaths). But on resume |
| 1522 | * timers don't work yet, so prevent a complete hang in that |
| 1523 | * case by choosing an insanely large timeout. */ |
| 1524 | end = jiffies + 60 * HZ; |
| 1525 | |
| 1526 | do { |
| 1527 | ring->head = I915_READ_HEAD(ring); |
| 1528 | ring->space = ring_space(ring); |
| 1529 | if (ring->space >= n) { |
| 1530 | trace_i915_ring_wait_end(ring); |
| 1531 | return 0; |
| 1532 | } |
| 1533 | |
| 1534 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && |
| 1535 | dev->primary->master) { |
| 1536 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
| 1537 | if (master_priv->sarea_priv) |
| 1538 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
| 1539 | } |
| 1540 | |
| 1541 | msleep(1); |
| 1542 | |
| 1543 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
| 1544 | dev_priv->mm.interruptible); |
| 1545 | if (ret) |
| 1546 | return ret; |
| 1547 | } while (!time_after(jiffies, end)); |
| 1548 | trace_i915_ring_wait_end(ring); |
| 1549 | return -EBUSY; |
| 1550 | } |
| 1551 | |
| 1552 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
| 1553 | { |
| 1554 | uint32_t __iomem *virt; |
| 1555 | int rem = ring->size - ring->tail; |
| 1556 | |
| 1557 | if (ring->space < rem) { |
| 1558 | int ret = ring_wait_for_space(ring, rem); |
| 1559 | if (ret) |
| 1560 | return ret; |
| 1561 | } |
| 1562 | |
| 1563 | virt = ring->virtual_start + ring->tail; |
| 1564 | rem /= 4; |
| 1565 | while (rem--) |
| 1566 | iowrite32(MI_NOOP, virt++); |
| 1567 | |
| 1568 | ring->tail = 0; |
| 1569 | ring->space = ring_space(ring); |
| 1570 | |
| 1571 | return 0; |
| 1572 | } |
| 1573 | |
| 1574 | int intel_ring_idle(struct intel_ring_buffer *ring) |
| 1575 | { |
| 1576 | u32 seqno; |
| 1577 | int ret; |
| 1578 | |
| 1579 | /* We need to add any requests required to flush the objects and ring */ |
| 1580 | if (ring->outstanding_lazy_seqno) { |
| 1581 | ret = i915_add_request(ring, NULL); |
| 1582 | if (ret) |
| 1583 | return ret; |
| 1584 | } |
| 1585 | |
| 1586 | /* Wait upon the last request to be completed */ |
| 1587 | if (list_empty(&ring->request_list)) |
| 1588 | return 0; |
| 1589 | |
| 1590 | seqno = list_entry(ring->request_list.prev, |
| 1591 | struct drm_i915_gem_request, |
| 1592 | list)->seqno; |
| 1593 | |
| 1594 | return i915_wait_seqno(ring, seqno); |
| 1595 | } |
| 1596 | |
| 1597 | static int |
| 1598 | intel_ring_alloc_seqno(struct intel_ring_buffer *ring) |
| 1599 | { |
| 1600 | if (ring->outstanding_lazy_seqno) |
| 1601 | return 0; |
| 1602 | |
| 1603 | if (ring->preallocated_lazy_request == NULL) { |
| 1604 | struct drm_i915_gem_request *request; |
| 1605 | |
| 1606 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
| 1607 | if (request == NULL) |
| 1608 | return -ENOMEM; |
| 1609 | |
| 1610 | ring->preallocated_lazy_request = request; |
| 1611 | } |
| 1612 | |
| 1613 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); |
| 1614 | } |
| 1615 | |
| 1616 | static int __intel_ring_prepare(struct intel_ring_buffer *ring, |
| 1617 | int bytes) |
| 1618 | { |
| 1619 | int ret; |
| 1620 | |
| 1621 | if (unlikely(ring->tail + bytes > ring->effective_size)) { |
| 1622 | ret = intel_wrap_ring_buffer(ring); |
| 1623 | if (unlikely(ret)) |
| 1624 | return ret; |
| 1625 | } |
| 1626 | |
| 1627 | if (unlikely(ring->space < bytes)) { |
| 1628 | ret = ring_wait_for_space(ring, bytes); |
| 1629 | if (unlikely(ret)) |
| 1630 | return ret; |
| 1631 | } |
| 1632 | |
| 1633 | return 0; |
| 1634 | } |
| 1635 | |
| 1636 | int intel_ring_begin(struct intel_ring_buffer *ring, |
| 1637 | int num_dwords) |
| 1638 | { |
| 1639 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
| 1640 | int ret; |
| 1641 | |
| 1642 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
| 1643 | dev_priv->mm.interruptible); |
| 1644 | if (ret) |
| 1645 | return ret; |
| 1646 | |
| 1647 | ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t)); |
| 1648 | if (ret) |
| 1649 | return ret; |
| 1650 | |
| 1651 | /* Preallocate the olr before touching the ring */ |
| 1652 | ret = intel_ring_alloc_seqno(ring); |
| 1653 | if (ret) |
| 1654 | return ret; |
| 1655 | |
| 1656 | ring->space -= num_dwords * sizeof(uint32_t); |
| 1657 | return 0; |
| 1658 | } |
| 1659 | |
| 1660 | /* Align the ring tail to a cacheline boundary */ |
| 1661 | int intel_ring_cacheline_align(struct intel_ring_buffer *ring) |
| 1662 | { |
| 1663 | int num_dwords = (64 - (ring->tail & 63)) / sizeof(uint32_t); |
| 1664 | int ret; |
| 1665 | |
| 1666 | if (num_dwords == 0) |
| 1667 | return 0; |
| 1668 | |
| 1669 | ret = intel_ring_begin(ring, num_dwords); |
| 1670 | if (ret) |
| 1671 | return ret; |
| 1672 | |
| 1673 | while (num_dwords--) |
| 1674 | intel_ring_emit(ring, MI_NOOP); |
| 1675 | |
| 1676 | intel_ring_advance(ring); |
| 1677 | |
| 1678 | return 0; |
| 1679 | } |
| 1680 | |
| 1681 | void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno) |
| 1682 | { |
| 1683 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 1684 | |
| 1685 | BUG_ON(ring->outstanding_lazy_seqno); |
| 1686 | |
| 1687 | if (INTEL_INFO(ring->dev)->gen >= 6) { |
| 1688 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); |
| 1689 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); |
| 1690 | if (HAS_VEBOX(ring->dev)) |
| 1691 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); |
| 1692 | } |
| 1693 | |
| 1694 | ring->set_seqno(ring, seqno); |
| 1695 | ring->hangcheck.seqno = seqno; |
| 1696 | } |
| 1697 | |
| 1698 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
| 1699 | u32 value) |
| 1700 | { |
| 1701 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
| 1702 | |
| 1703 | /* Every tail move must follow the sequence below */ |
| 1704 | |
| 1705 | /* Disable notification that the ring is IDLE. The GT |
| 1706 | * will then assume that it is busy and bring it out of rc6. |
| 1707 | */ |
| 1708 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 1709 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
| 1710 | |
| 1711 | /* Clear the context id. Here be magic! */ |
| 1712 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); |
| 1713 | |
| 1714 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
| 1715 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
| 1716 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
| 1717 | 50)) |
| 1718 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
| 1719 | |
| 1720 | /* Now that the ring is fully powered up, update the tail */ |
| 1721 | I915_WRITE_TAIL(ring, value); |
| 1722 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
| 1723 | |
| 1724 | /* Let the ring send IDLE messages to the GT again, |
| 1725 | * and so let it sleep to conserve power when idle. |
| 1726 | */ |
| 1727 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 1728 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
| 1729 | } |
| 1730 | |
| 1731 | static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring, |
| 1732 | u32 invalidate, u32 flush) |
| 1733 | { |
| 1734 | uint32_t cmd; |
| 1735 | int ret; |
| 1736 | |
| 1737 | ret = intel_ring_begin(ring, 4); |
| 1738 | if (ret) |
| 1739 | return ret; |
| 1740 | |
| 1741 | cmd = MI_FLUSH_DW; |
| 1742 | if (INTEL_INFO(ring->dev)->gen >= 8) |
| 1743 | cmd += 1; |
| 1744 | /* |
| 1745 | * Bspec vol 1c.5 - video engine command streamer: |
| 1746 | * "If ENABLED, all TLBs will be invalidated once the flush |
| 1747 | * operation is complete. This bit is only valid when the |
| 1748 | * Post-Sync Operation field is a value of 1h or 3h." |
| 1749 | */ |
| 1750 | if (invalidate & I915_GEM_GPU_DOMAINS) |
| 1751 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
| 1752 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; |
| 1753 | intel_ring_emit(ring, cmd); |
| 1754 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
| 1755 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
| 1756 | intel_ring_emit(ring, 0); /* upper addr */ |
| 1757 | intel_ring_emit(ring, 0); /* value */ |
| 1758 | } else { |
| 1759 | intel_ring_emit(ring, 0); |
| 1760 | intel_ring_emit(ring, MI_NOOP); |
| 1761 | } |
| 1762 | intel_ring_advance(ring); |
| 1763 | return 0; |
| 1764 | } |
| 1765 | |
| 1766 | static int |
| 1767 | gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 1768 | u32 offset, u32 len, |
| 1769 | unsigned flags) |
| 1770 | { |
| 1771 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 1772 | bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL && |
| 1773 | !(flags & I915_DISPATCH_SECURE); |
| 1774 | int ret; |
| 1775 | |
| 1776 | ret = intel_ring_begin(ring, 4); |
| 1777 | if (ret) |
| 1778 | return ret; |
| 1779 | |
| 1780 | /* FIXME(BDW): Address space and security selectors. */ |
| 1781 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); |
| 1782 | intel_ring_emit(ring, offset); |
| 1783 | intel_ring_emit(ring, 0); |
| 1784 | intel_ring_emit(ring, MI_NOOP); |
| 1785 | intel_ring_advance(ring); |
| 1786 | |
| 1787 | return 0; |
| 1788 | } |
| 1789 | |
| 1790 | static int |
| 1791 | hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 1792 | u32 offset, u32 len, |
| 1793 | unsigned flags) |
| 1794 | { |
| 1795 | int ret; |
| 1796 | |
| 1797 | ret = intel_ring_begin(ring, 2); |
| 1798 | if (ret) |
| 1799 | return ret; |
| 1800 | |
| 1801 | intel_ring_emit(ring, |
| 1802 | MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW | |
| 1803 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW)); |
| 1804 | /* bit0-7 is the length on GEN6+ */ |
| 1805 | intel_ring_emit(ring, offset); |
| 1806 | intel_ring_advance(ring); |
| 1807 | |
| 1808 | return 0; |
| 1809 | } |
| 1810 | |
| 1811 | static int |
| 1812 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 1813 | u32 offset, u32 len, |
| 1814 | unsigned flags) |
| 1815 | { |
| 1816 | int ret; |
| 1817 | |
| 1818 | ret = intel_ring_begin(ring, 2); |
| 1819 | if (ret) |
| 1820 | return ret; |
| 1821 | |
| 1822 | intel_ring_emit(ring, |
| 1823 | MI_BATCH_BUFFER_START | |
| 1824 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
| 1825 | /* bit0-7 is the length on GEN6+ */ |
| 1826 | intel_ring_emit(ring, offset); |
| 1827 | intel_ring_advance(ring); |
| 1828 | |
| 1829 | return 0; |
| 1830 | } |
| 1831 | |
| 1832 | /* Blitter support (SandyBridge+) */ |
| 1833 | |
| 1834 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
| 1835 | u32 invalidate, u32 flush) |
| 1836 | { |
| 1837 | struct drm_device *dev = ring->dev; |
| 1838 | uint32_t cmd; |
| 1839 | int ret; |
| 1840 | |
| 1841 | ret = intel_ring_begin(ring, 4); |
| 1842 | if (ret) |
| 1843 | return ret; |
| 1844 | |
| 1845 | cmd = MI_FLUSH_DW; |
| 1846 | if (INTEL_INFO(ring->dev)->gen >= 8) |
| 1847 | cmd += 1; |
| 1848 | /* |
| 1849 | * Bspec vol 1c.3 - blitter engine command streamer: |
| 1850 | * "If ENABLED, all TLBs will be invalidated once the flush |
| 1851 | * operation is complete. This bit is only valid when the |
| 1852 | * Post-Sync Operation field is a value of 1h or 3h." |
| 1853 | */ |
| 1854 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
| 1855 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
| 1856 | MI_FLUSH_DW_OP_STOREDW; |
| 1857 | intel_ring_emit(ring, cmd); |
| 1858 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
| 1859 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
| 1860 | intel_ring_emit(ring, 0); /* upper addr */ |
| 1861 | intel_ring_emit(ring, 0); /* value */ |
| 1862 | } else { |
| 1863 | intel_ring_emit(ring, 0); |
| 1864 | intel_ring_emit(ring, MI_NOOP); |
| 1865 | } |
| 1866 | intel_ring_advance(ring); |
| 1867 | |
| 1868 | if (IS_GEN7(dev) && !invalidate && flush) |
| 1869 | return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); |
| 1870 | |
| 1871 | return 0; |
| 1872 | } |
| 1873 | |
| 1874 | int intel_init_render_ring_buffer(struct drm_device *dev) |
| 1875 | { |
| 1876 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1877 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
| 1878 | |
| 1879 | ring->name = "render ring"; |
| 1880 | ring->id = RCS; |
| 1881 | ring->mmio_base = RENDER_RING_BASE; |
| 1882 | |
| 1883 | if (INTEL_INFO(dev)->gen >= 6) { |
| 1884 | ring->add_request = gen6_add_request; |
| 1885 | ring->flush = gen7_render_ring_flush; |
| 1886 | if (INTEL_INFO(dev)->gen == 6) |
| 1887 | ring->flush = gen6_render_ring_flush; |
| 1888 | if (INTEL_INFO(dev)->gen >= 8) { |
| 1889 | ring->flush = gen8_render_ring_flush; |
| 1890 | ring->irq_get = gen8_ring_get_irq; |
| 1891 | ring->irq_put = gen8_ring_put_irq; |
| 1892 | } else { |
| 1893 | ring->irq_get = gen6_ring_get_irq; |
| 1894 | ring->irq_put = gen6_ring_put_irq; |
| 1895 | } |
| 1896 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
| 1897 | ring->get_seqno = gen6_ring_get_seqno; |
| 1898 | ring->set_seqno = ring_set_seqno; |
| 1899 | ring->sync_to = gen6_ring_sync; |
| 1900 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 1901 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV; |
| 1902 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB; |
| 1903 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE; |
| 1904 | ring->signal_mbox[RCS] = GEN6_NOSYNC; |
| 1905 | ring->signal_mbox[VCS] = GEN6_VRSYNC; |
| 1906 | ring->signal_mbox[BCS] = GEN6_BRSYNC; |
| 1907 | ring->signal_mbox[VECS] = GEN6_VERSYNC; |
| 1908 | } else if (IS_GEN5(dev)) { |
| 1909 | ring->add_request = pc_render_add_request; |
| 1910 | ring->flush = gen4_render_ring_flush; |
| 1911 | ring->get_seqno = pc_render_get_seqno; |
| 1912 | ring->set_seqno = pc_render_set_seqno; |
| 1913 | ring->irq_get = gen5_ring_get_irq; |
| 1914 | ring->irq_put = gen5_ring_put_irq; |
| 1915 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
| 1916 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; |
| 1917 | } else { |
| 1918 | ring->add_request = i9xx_add_request; |
| 1919 | if (INTEL_INFO(dev)->gen < 4) |
| 1920 | ring->flush = gen2_render_ring_flush; |
| 1921 | else |
| 1922 | ring->flush = gen4_render_ring_flush; |
| 1923 | ring->get_seqno = ring_get_seqno; |
| 1924 | ring->set_seqno = ring_set_seqno; |
| 1925 | if (IS_GEN2(dev)) { |
| 1926 | ring->irq_get = i8xx_ring_get_irq; |
| 1927 | ring->irq_put = i8xx_ring_put_irq; |
| 1928 | } else { |
| 1929 | ring->irq_get = i9xx_ring_get_irq; |
| 1930 | ring->irq_put = i9xx_ring_put_irq; |
| 1931 | } |
| 1932 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
| 1933 | } |
| 1934 | ring->write_tail = ring_write_tail; |
| 1935 | if (IS_HASWELL(dev)) |
| 1936 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; |
| 1937 | else if (IS_GEN8(dev)) |
| 1938 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
| 1939 | else if (INTEL_INFO(dev)->gen >= 6) |
| 1940 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
| 1941 | else if (INTEL_INFO(dev)->gen >= 4) |
| 1942 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
| 1943 | else if (IS_I830(dev) || IS_845G(dev)) |
| 1944 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; |
| 1945 | else |
| 1946 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; |
| 1947 | ring->init = init_render_ring; |
| 1948 | ring->cleanup = render_ring_cleanup; |
| 1949 | |
| 1950 | /* Workaround batchbuffer to combat CS tlb bug. */ |
| 1951 | if (HAS_BROKEN_CS_TLB(dev)) { |
| 1952 | struct drm_i915_gem_object *obj; |
| 1953 | int ret; |
| 1954 | |
| 1955 | obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT); |
| 1956 | if (obj == NULL) { |
| 1957 | DRM_ERROR("Failed to allocate batch bo\n"); |
| 1958 | return -ENOMEM; |
| 1959 | } |
| 1960 | |
| 1961 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
| 1962 | if (ret != 0) { |
| 1963 | drm_gem_object_unreference(&obj->base); |
| 1964 | DRM_ERROR("Failed to ping batch bo\n"); |
| 1965 | return ret; |
| 1966 | } |
| 1967 | |
| 1968 | ring->scratch.obj = obj; |
| 1969 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); |
| 1970 | } |
| 1971 | |
| 1972 | return intel_init_ring_buffer(dev, ring); |
| 1973 | } |
| 1974 | |
| 1975 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
| 1976 | { |
| 1977 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1978 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
| 1979 | int ret; |
| 1980 | |
| 1981 | ring->name = "render ring"; |
| 1982 | ring->id = RCS; |
| 1983 | ring->mmio_base = RENDER_RING_BASE; |
| 1984 | |
| 1985 | if (INTEL_INFO(dev)->gen >= 6) { |
| 1986 | /* non-kms not supported on gen6+ */ |
| 1987 | return -ENODEV; |
| 1988 | } |
| 1989 | |
| 1990 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding |
| 1991 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up |
| 1992 | * the special gen5 functions. */ |
| 1993 | ring->add_request = i9xx_add_request; |
| 1994 | if (INTEL_INFO(dev)->gen < 4) |
| 1995 | ring->flush = gen2_render_ring_flush; |
| 1996 | else |
| 1997 | ring->flush = gen4_render_ring_flush; |
| 1998 | ring->get_seqno = ring_get_seqno; |
| 1999 | ring->set_seqno = ring_set_seqno; |
| 2000 | if (IS_GEN2(dev)) { |
| 2001 | ring->irq_get = i8xx_ring_get_irq; |
| 2002 | ring->irq_put = i8xx_ring_put_irq; |
| 2003 | } else { |
| 2004 | ring->irq_get = i9xx_ring_get_irq; |
| 2005 | ring->irq_put = i9xx_ring_put_irq; |
| 2006 | } |
| 2007 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
| 2008 | ring->write_tail = ring_write_tail; |
| 2009 | if (INTEL_INFO(dev)->gen >= 4) |
| 2010 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
| 2011 | else if (IS_I830(dev) || IS_845G(dev)) |
| 2012 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; |
| 2013 | else |
| 2014 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; |
| 2015 | ring->init = init_render_ring; |
| 2016 | ring->cleanup = render_ring_cleanup; |
| 2017 | |
| 2018 | ring->dev = dev; |
| 2019 | INIT_LIST_HEAD(&ring->active_list); |
| 2020 | INIT_LIST_HEAD(&ring->request_list); |
| 2021 | |
| 2022 | ring->size = size; |
| 2023 | ring->effective_size = ring->size; |
| 2024 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
| 2025 | ring->effective_size -= 128; |
| 2026 | |
| 2027 | ring->virtual_start = ioremap_wc(start, size); |
| 2028 | if (ring->virtual_start == NULL) { |
| 2029 | DRM_ERROR("can not ioremap virtual address for" |
| 2030 | " ring buffer\n"); |
| 2031 | return -ENOMEM; |
| 2032 | } |
| 2033 | |
| 2034 | if (!I915_NEED_GFX_HWS(dev)) { |
| 2035 | ret = init_phys_status_page(ring); |
| 2036 | if (ret) |
| 2037 | return ret; |
| 2038 | } |
| 2039 | |
| 2040 | return 0; |
| 2041 | } |
| 2042 | |
| 2043 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
| 2044 | { |
| 2045 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2046 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
| 2047 | |
| 2048 | ring->name = "bsd ring"; |
| 2049 | ring->id = VCS; |
| 2050 | |
| 2051 | ring->write_tail = ring_write_tail; |
| 2052 | if (INTEL_INFO(dev)->gen >= 6) { |
| 2053 | ring->mmio_base = GEN6_BSD_RING_BASE; |
| 2054 | /* gen6 bsd needs a special wa for tail updates */ |
| 2055 | if (IS_GEN6(dev)) |
| 2056 | ring->write_tail = gen6_bsd_ring_write_tail; |
| 2057 | ring->flush = gen6_bsd_ring_flush; |
| 2058 | ring->add_request = gen6_add_request; |
| 2059 | ring->get_seqno = gen6_ring_get_seqno; |
| 2060 | ring->set_seqno = ring_set_seqno; |
| 2061 | if (INTEL_INFO(dev)->gen >= 8) { |
| 2062 | ring->irq_enable_mask = |
| 2063 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; |
| 2064 | ring->irq_get = gen8_ring_get_irq; |
| 2065 | ring->irq_put = gen8_ring_put_irq; |
| 2066 | ring->dispatch_execbuffer = |
| 2067 | gen8_ring_dispatch_execbuffer; |
| 2068 | } else { |
| 2069 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
| 2070 | ring->irq_get = gen6_ring_get_irq; |
| 2071 | ring->irq_put = gen6_ring_put_irq; |
| 2072 | ring->dispatch_execbuffer = |
| 2073 | gen6_ring_dispatch_execbuffer; |
| 2074 | } |
| 2075 | ring->sync_to = gen6_ring_sync; |
| 2076 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR; |
| 2077 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 2078 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB; |
| 2079 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE; |
| 2080 | ring->signal_mbox[RCS] = GEN6_RVSYNC; |
| 2081 | ring->signal_mbox[VCS] = GEN6_NOSYNC; |
| 2082 | ring->signal_mbox[BCS] = GEN6_BVSYNC; |
| 2083 | ring->signal_mbox[VECS] = GEN6_VEVSYNC; |
| 2084 | } else { |
| 2085 | ring->mmio_base = BSD_RING_BASE; |
| 2086 | ring->flush = bsd_ring_flush; |
| 2087 | ring->add_request = i9xx_add_request; |
| 2088 | ring->get_seqno = ring_get_seqno; |
| 2089 | ring->set_seqno = ring_set_seqno; |
| 2090 | if (IS_GEN5(dev)) { |
| 2091 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
| 2092 | ring->irq_get = gen5_ring_get_irq; |
| 2093 | ring->irq_put = gen5_ring_put_irq; |
| 2094 | } else { |
| 2095 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
| 2096 | ring->irq_get = i9xx_ring_get_irq; |
| 2097 | ring->irq_put = i9xx_ring_put_irq; |
| 2098 | } |
| 2099 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
| 2100 | } |
| 2101 | ring->init = init_ring_common; |
| 2102 | |
| 2103 | return intel_init_ring_buffer(dev, ring); |
| 2104 | } |
| 2105 | |
| 2106 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
| 2107 | { |
| 2108 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2109 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
| 2110 | |
| 2111 | ring->name = "blitter ring"; |
| 2112 | ring->id = BCS; |
| 2113 | |
| 2114 | ring->mmio_base = BLT_RING_BASE; |
| 2115 | ring->write_tail = ring_write_tail; |
| 2116 | ring->flush = gen6_ring_flush; |
| 2117 | ring->add_request = gen6_add_request; |
| 2118 | ring->get_seqno = gen6_ring_get_seqno; |
| 2119 | ring->set_seqno = ring_set_seqno; |
| 2120 | if (INTEL_INFO(dev)->gen >= 8) { |
| 2121 | ring->irq_enable_mask = |
| 2122 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
| 2123 | ring->irq_get = gen8_ring_get_irq; |
| 2124 | ring->irq_put = gen8_ring_put_irq; |
| 2125 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
| 2126 | } else { |
| 2127 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
| 2128 | ring->irq_get = gen6_ring_get_irq; |
| 2129 | ring->irq_put = gen6_ring_put_irq; |
| 2130 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
| 2131 | } |
| 2132 | ring->sync_to = gen6_ring_sync; |
| 2133 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR; |
| 2134 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV; |
| 2135 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 2136 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE; |
| 2137 | ring->signal_mbox[RCS] = GEN6_RBSYNC; |
| 2138 | ring->signal_mbox[VCS] = GEN6_VBSYNC; |
| 2139 | ring->signal_mbox[BCS] = GEN6_NOSYNC; |
| 2140 | ring->signal_mbox[VECS] = GEN6_VEBSYNC; |
| 2141 | ring->init = init_ring_common; |
| 2142 | |
| 2143 | return intel_init_ring_buffer(dev, ring); |
| 2144 | } |
| 2145 | |
| 2146 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
| 2147 | { |
| 2148 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2149 | struct intel_ring_buffer *ring = &dev_priv->ring[VECS]; |
| 2150 | |
| 2151 | ring->name = "video enhancement ring"; |
| 2152 | ring->id = VECS; |
| 2153 | |
| 2154 | ring->mmio_base = VEBOX_RING_BASE; |
| 2155 | ring->write_tail = ring_write_tail; |
| 2156 | ring->flush = gen6_ring_flush; |
| 2157 | ring->add_request = gen6_add_request; |
| 2158 | ring->get_seqno = gen6_ring_get_seqno; |
| 2159 | ring->set_seqno = ring_set_seqno; |
| 2160 | |
| 2161 | if (INTEL_INFO(dev)->gen >= 8) { |
| 2162 | ring->irq_enable_mask = |
| 2163 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
| 2164 | ring->irq_get = gen8_ring_get_irq; |
| 2165 | ring->irq_put = gen8_ring_put_irq; |
| 2166 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
| 2167 | } else { |
| 2168 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
| 2169 | ring->irq_get = hsw_vebox_get_irq; |
| 2170 | ring->irq_put = hsw_vebox_put_irq; |
| 2171 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
| 2172 | } |
| 2173 | ring->sync_to = gen6_ring_sync; |
| 2174 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER; |
| 2175 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV; |
| 2176 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB; |
| 2177 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID; |
| 2178 | ring->signal_mbox[RCS] = GEN6_RVESYNC; |
| 2179 | ring->signal_mbox[VCS] = GEN6_VVESYNC; |
| 2180 | ring->signal_mbox[BCS] = GEN6_BVESYNC; |
| 2181 | ring->signal_mbox[VECS] = GEN6_NOSYNC; |
| 2182 | ring->init = init_ring_common; |
| 2183 | |
| 2184 | return intel_init_ring_buffer(dev, ring); |
| 2185 | } |
| 2186 | |
| 2187 | int |
| 2188 | intel_ring_flush_all_caches(struct intel_ring_buffer *ring) |
| 2189 | { |
| 2190 | int ret; |
| 2191 | |
| 2192 | if (!ring->gpu_caches_dirty) |
| 2193 | return 0; |
| 2194 | |
| 2195 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); |
| 2196 | if (ret) |
| 2197 | return ret; |
| 2198 | |
| 2199 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); |
| 2200 | |
| 2201 | ring->gpu_caches_dirty = false; |
| 2202 | return 0; |
| 2203 | } |
| 2204 | |
| 2205 | int |
| 2206 | intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring) |
| 2207 | { |
| 2208 | uint32_t flush_domains; |
| 2209 | int ret; |
| 2210 | |
| 2211 | flush_domains = 0; |
| 2212 | if (ring->gpu_caches_dirty) |
| 2213 | flush_domains = I915_GEM_GPU_DOMAINS; |
| 2214 | |
| 2215 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); |
| 2216 | if (ret) |
| 2217 | return ret; |
| 2218 | |
| 2219 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); |
| 2220 | |
| 2221 | ring->gpu_caches_dirty = false; |
| 2222 | return 0; |
| 2223 | } |