| 1 | /* |
| 2 | * Copyright © 2013 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | */ |
| 23 | |
| 24 | #include "i915_drv.h" |
| 25 | #include "intel_drv.h" |
| 26 | |
| 27 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 |
| 28 | |
| 29 | #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__)) |
| 30 | #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__)) |
| 31 | |
| 32 | #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__)) |
| 33 | #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__)) |
| 34 | |
| 35 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) |
| 36 | #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__)) |
| 37 | |
| 38 | #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__)) |
| 39 | #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__)) |
| 40 | |
| 41 | #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__) |
| 42 | |
| 43 | |
| 44 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) |
| 45 | { |
| 46 | u32 gt_thread_status_mask; |
| 47 | |
| 48 | if (IS_HASWELL(dev_priv->dev)) |
| 49 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; |
| 50 | else |
| 51 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; |
| 52 | |
| 53 | /* w/a for a sporadic read returning 0 by waiting for the GT |
| 54 | * thread to wake up. |
| 55 | */ |
| 56 | if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) |
| 57 | DRM_ERROR("GT thread status wait timed out\n"); |
| 58 | } |
| 59 | |
| 60 | static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) |
| 61 | { |
| 62 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
| 63 | /* something from same cacheline, but !FORCEWAKE */ |
| 64 | __raw_posting_read(dev_priv, ECOBUS); |
| 65 | } |
| 66 | |
| 67 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
| 68 | { |
| 69 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0, |
| 70 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 71 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
| 72 | |
| 73 | __raw_i915_write32(dev_priv, FORCEWAKE, 1); |
| 74 | /* something from same cacheline, but !FORCEWAKE */ |
| 75 | __raw_posting_read(dev_priv, ECOBUS); |
| 76 | |
| 77 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1), |
| 78 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 79 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
| 80 | |
| 81 | /* WaRsForcewakeWaitTC0:snb */ |
| 82 | __gen6_gt_wait_for_thread_c0(dev_priv); |
| 83 | } |
| 84 | |
| 85 | static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) |
| 86 | { |
| 87 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); |
| 88 | /* something from same cacheline, but !FORCEWAKE_MT */ |
| 89 | __raw_posting_read(dev_priv, ECOBUS); |
| 90 | } |
| 91 | |
| 92 | static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) |
| 93 | { |
| 94 | u32 forcewake_ack; |
| 95 | |
| 96 | if (IS_HASWELL(dev_priv->dev)) |
| 97 | forcewake_ack = FORCEWAKE_ACK_HSW; |
| 98 | else |
| 99 | forcewake_ack = FORCEWAKE_MT_ACK; |
| 100 | |
| 101 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0, |
| 102 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 103 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
| 104 | |
| 105 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
| 106 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
| 107 | /* something from same cacheline, but !FORCEWAKE_MT */ |
| 108 | __raw_posting_read(dev_priv, ECOBUS); |
| 109 | |
| 110 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL), |
| 111 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 112 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
| 113 | |
| 114 | /* WaRsForcewakeWaitTC0:ivb,hsw */ |
| 115 | __gen6_gt_wait_for_thread_c0(dev_priv); |
| 116 | } |
| 117 | |
| 118 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) |
| 119 | { |
| 120 | u32 gtfifodbg; |
| 121 | |
| 122 | gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); |
| 123 | if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, |
| 124 | "MMIO read or write has been dropped %x\n", gtfifodbg)) |
| 125 | __raw_i915_write32(dev_priv, GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); |
| 126 | } |
| 127 | |
| 128 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
| 129 | { |
| 130 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
| 131 | /* something from same cacheline, but !FORCEWAKE */ |
| 132 | __raw_posting_read(dev_priv, ECOBUS); |
| 133 | gen6_gt_check_fifodbg(dev_priv); |
| 134 | } |
| 135 | |
| 136 | static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) |
| 137 | { |
| 138 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
| 139 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
| 140 | /* something from same cacheline, but !FORCEWAKE_MT */ |
| 141 | __raw_posting_read(dev_priv, ECOBUS); |
| 142 | gen6_gt_check_fifodbg(dev_priv); |
| 143 | } |
| 144 | |
| 145 | static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
| 146 | { |
| 147 | int ret = 0; |
| 148 | |
| 149 | if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
| 150 | int loop = 500; |
| 151 | u32 fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); |
| 152 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
| 153 | udelay(10); |
| 154 | fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); |
| 155 | } |
| 156 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) |
| 157 | ++ret; |
| 158 | dev_priv->uncore.fifo_count = fifo; |
| 159 | } |
| 160 | dev_priv->uncore.fifo_count--; |
| 161 | |
| 162 | return ret; |
| 163 | } |
| 164 | |
| 165 | static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) |
| 166 | { |
| 167 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
| 168 | _MASKED_BIT_DISABLE(0xffff)); |
| 169 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
| 170 | __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); |
| 171 | } |
| 172 | |
| 173 | static void vlv_force_wake_get(struct drm_i915_private *dev_priv) |
| 174 | { |
| 175 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0, |
| 176 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 177 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
| 178 | |
| 179 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
| 180 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
| 181 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, |
| 182 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
| 183 | |
| 184 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL), |
| 185 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 186 | DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n"); |
| 187 | |
| 188 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_MEDIA_VLV) & |
| 189 | FORCEWAKE_KERNEL), |
| 190 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 191 | DRM_ERROR("Timed out waiting for media to ack forcewake request.\n"); |
| 192 | |
| 193 | /* WaRsForcewakeWaitTC0:vlv */ |
| 194 | __gen6_gt_wait_for_thread_c0(dev_priv); |
| 195 | } |
| 196 | |
| 197 | static void vlv_force_wake_put(struct drm_i915_private *dev_priv) |
| 198 | { |
| 199 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
| 200 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
| 201 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, |
| 202 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
| 203 | /* The below doubles as a POSTING_READ */ |
| 204 | gen6_gt_check_fifodbg(dev_priv); |
| 205 | } |
| 206 | |
| 207 | static void gen6_force_wake_work(struct work_struct *work) |
| 208 | { |
| 209 | struct drm_i915_private *dev_priv = |
| 210 | container_of(work, typeof(*dev_priv), uncore.force_wake_work.work); |
| 211 | unsigned long irqflags; |
| 212 | |
| 213 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 214 | if (--dev_priv->uncore.forcewake_count == 0) |
| 215 | dev_priv->uncore.funcs.force_wake_put(dev_priv); |
| 216 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 217 | } |
| 218 | |
| 219 | void intel_uncore_early_sanitize(struct drm_device *dev) |
| 220 | { |
| 221 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 222 | |
| 223 | if (HAS_FPGA_DBG_UNCLAIMED(dev)) |
| 224 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
| 225 | } |
| 226 | |
| 227 | void intel_uncore_init(struct drm_device *dev) |
| 228 | { |
| 229 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 230 | |
| 231 | INIT_DELAYED_WORK(&dev_priv->uncore.force_wake_work, |
| 232 | gen6_force_wake_work); |
| 233 | |
| 234 | if (IS_VALLEYVIEW(dev)) { |
| 235 | dev_priv->uncore.funcs.force_wake_get = vlv_force_wake_get; |
| 236 | dev_priv->uncore.funcs.force_wake_put = vlv_force_wake_put; |
| 237 | } else if (IS_HASWELL(dev)) { |
| 238 | dev_priv->uncore.funcs.force_wake_get = __gen6_gt_force_wake_mt_get; |
| 239 | dev_priv->uncore.funcs.force_wake_put = __gen6_gt_force_wake_mt_put; |
| 240 | } else if (IS_IVYBRIDGE(dev)) { |
| 241 | u32 ecobus; |
| 242 | |
| 243 | /* IVB configs may use multi-threaded forcewake */ |
| 244 | |
| 245 | /* A small trick here - if the bios hasn't configured |
| 246 | * MT forcewake, and if the device is in RC6, then |
| 247 | * force_wake_mt_get will not wake the device and the |
| 248 | * ECOBUS read will return zero. Which will be |
| 249 | * (correctly) interpreted by the test below as MT |
| 250 | * forcewake being disabled. |
| 251 | */ |
| 252 | mutex_lock(&dev->struct_mutex); |
| 253 | __gen6_gt_force_wake_mt_get(dev_priv); |
| 254 | ecobus = __raw_i915_read32(dev_priv, ECOBUS); |
| 255 | __gen6_gt_force_wake_mt_put(dev_priv); |
| 256 | mutex_unlock(&dev->struct_mutex); |
| 257 | |
| 258 | if (ecobus & FORCEWAKE_MT_ENABLE) { |
| 259 | dev_priv->uncore.funcs.force_wake_get = |
| 260 | __gen6_gt_force_wake_mt_get; |
| 261 | dev_priv->uncore.funcs.force_wake_put = |
| 262 | __gen6_gt_force_wake_mt_put; |
| 263 | } else { |
| 264 | DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); |
| 265 | DRM_INFO("when using vblank-synced partial screen updates.\n"); |
| 266 | dev_priv->uncore.funcs.force_wake_get = |
| 267 | __gen6_gt_force_wake_get; |
| 268 | dev_priv->uncore.funcs.force_wake_put = |
| 269 | __gen6_gt_force_wake_put; |
| 270 | } |
| 271 | } else if (IS_GEN6(dev)) { |
| 272 | dev_priv->uncore.funcs.force_wake_get = |
| 273 | __gen6_gt_force_wake_get; |
| 274 | dev_priv->uncore.funcs.force_wake_put = |
| 275 | __gen6_gt_force_wake_put; |
| 276 | } |
| 277 | } |
| 278 | |
| 279 | void intel_uncore_fini(struct drm_device *dev) |
| 280 | { |
| 281 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 282 | |
| 283 | flush_delayed_work(&dev_priv->uncore.force_wake_work); |
| 284 | |
| 285 | /* Paranoia: make sure we have disabled everything before we exit. */ |
| 286 | intel_uncore_sanitize(dev); |
| 287 | } |
| 288 | |
| 289 | static void intel_uncore_forcewake_reset(struct drm_device *dev) |
| 290 | { |
| 291 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 292 | |
| 293 | if (IS_VALLEYVIEW(dev)) { |
| 294 | vlv_force_wake_reset(dev_priv); |
| 295 | } else if (INTEL_INFO(dev)->gen >= 6) { |
| 296 | __gen6_gt_force_wake_reset(dev_priv); |
| 297 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
| 298 | __gen6_gt_force_wake_mt_reset(dev_priv); |
| 299 | } |
| 300 | } |
| 301 | |
| 302 | void intel_uncore_sanitize(struct drm_device *dev) |
| 303 | { |
| 304 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 305 | u32 reg_val; |
| 306 | |
| 307 | intel_uncore_forcewake_reset(dev); |
| 308 | |
| 309 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ |
| 310 | intel_disable_gt_powersave(dev); |
| 311 | |
| 312 | /* Turn off power gate, require especially for the BIOS less system */ |
| 313 | if (IS_VALLEYVIEW(dev)) { |
| 314 | |
| 315 | mutex_lock(&dev_priv->rps.hw_lock); |
| 316 | reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS); |
| 317 | |
| 318 | if (reg_val & (RENDER_PWRGT | MEDIA_PWRGT | DISP2D_PWRGT)) |
| 319 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0); |
| 320 | |
| 321 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 322 | |
| 323 | } |
| 324 | } |
| 325 | |
| 326 | /* |
| 327 | * Generally this is called implicitly by the register read function. However, |
| 328 | * if some sequence requires the GT to not power down then this function should |
| 329 | * be called at the beginning of the sequence followed by a call to |
| 330 | * gen6_gt_force_wake_put() at the end of the sequence. |
| 331 | */ |
| 332 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
| 333 | { |
| 334 | unsigned long irqflags; |
| 335 | |
| 336 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 337 | if (dev_priv->uncore.forcewake_count++ == 0) |
| 338 | dev_priv->uncore.funcs.force_wake_get(dev_priv); |
| 339 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 340 | } |
| 341 | |
| 342 | /* |
| 343 | * see gen6_gt_force_wake_get() |
| 344 | */ |
| 345 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
| 346 | { |
| 347 | unsigned long irqflags; |
| 348 | |
| 349 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 350 | if (--dev_priv->uncore.forcewake_count == 0) { |
| 351 | dev_priv->uncore.forcewake_count++; |
| 352 | mod_delayed_work(dev_priv->wq, |
| 353 | &dev_priv->uncore.force_wake_work, |
| 354 | 1); |
| 355 | } |
| 356 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 357 | } |
| 358 | |
| 359 | /* We give fast paths for the really cool registers */ |
| 360 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
| 361 | ((HAS_FORCE_WAKE((dev_priv)->dev)) && \ |
| 362 | ((reg) < 0x40000) && \ |
| 363 | ((reg) != FORCEWAKE)) |
| 364 | |
| 365 | static void |
| 366 | ilk_dummy_write(struct drm_i915_private *dev_priv) |
| 367 | { |
| 368 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up |
| 369 | * the chip from rc6 before touching it for real. MI_MODE is masked, |
| 370 | * hence harmless to write 0 into. */ |
| 371 | __raw_i915_write32(dev_priv, MI_MODE, 0); |
| 372 | } |
| 373 | |
| 374 | static void |
| 375 | hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg) |
| 376 | { |
| 377 | if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) && |
| 378 | (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
| 379 | DRM_ERROR("Unknown unclaimed register before writing to %x\n", |
| 380 | reg); |
| 381 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
| 382 | } |
| 383 | } |
| 384 | |
| 385 | static void |
| 386 | hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) |
| 387 | { |
| 388 | if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) && |
| 389 | (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
| 390 | DRM_ERROR("Unclaimed write to %x\n", reg); |
| 391 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
| 392 | } |
| 393 | } |
| 394 | |
| 395 | #define __i915_read(x) \ |
| 396 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace) { \ |
| 397 | unsigned long irqflags; \ |
| 398 | u##x val = 0; \ |
| 399 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \ |
| 400 | if (dev_priv->info->gen == 5) \ |
| 401 | ilk_dummy_write(dev_priv); \ |
| 402 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 403 | if (dev_priv->uncore.forcewake_count == 0) \ |
| 404 | dev_priv->uncore.funcs.force_wake_get(dev_priv); \ |
| 405 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 406 | if (dev_priv->uncore.forcewake_count == 0) \ |
| 407 | dev_priv->uncore.funcs.force_wake_put(dev_priv); \ |
| 408 | } else { \ |
| 409 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 410 | } \ |
| 411 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ |
| 412 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ |
| 413 | return val; \ |
| 414 | } |
| 415 | |
| 416 | __i915_read(8) |
| 417 | __i915_read(16) |
| 418 | __i915_read(32) |
| 419 | __i915_read(64) |
| 420 | #undef __i915_read |
| 421 | |
| 422 | #define __i915_write(x) \ |
| 423 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool trace) { \ |
| 424 | unsigned long irqflags; \ |
| 425 | u32 __fifo_ret = 0; \ |
| 426 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ |
| 427 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \ |
| 428 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 429 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
| 430 | } \ |
| 431 | if (dev_priv->info->gen == 5) \ |
| 432 | ilk_dummy_write(dev_priv); \ |
| 433 | hsw_unclaimed_reg_clear(dev_priv, reg); \ |
| 434 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 435 | if (unlikely(__fifo_ret)) { \ |
| 436 | gen6_gt_check_fifodbg(dev_priv); \ |
| 437 | } \ |
| 438 | hsw_unclaimed_reg_check(dev_priv, reg); \ |
| 439 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ |
| 440 | } |
| 441 | __i915_write(8) |
| 442 | __i915_write(16) |
| 443 | __i915_write(32) |
| 444 | __i915_write(64) |
| 445 | #undef __i915_write |
| 446 | |
| 447 | static const struct register_whitelist { |
| 448 | uint64_t offset; |
| 449 | uint32_t size; |
| 450 | uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ |
| 451 | } whitelist[] = { |
| 452 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 }, |
| 453 | }; |
| 454 | |
| 455 | int i915_reg_read_ioctl(struct drm_device *dev, |
| 456 | void *data, struct drm_file *file) |
| 457 | { |
| 458 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 459 | struct drm_i915_reg_read *reg = data; |
| 460 | struct register_whitelist const *entry = whitelist; |
| 461 | int i; |
| 462 | |
| 463 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { |
| 464 | if (entry->offset == reg->offset && |
| 465 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) |
| 466 | break; |
| 467 | } |
| 468 | |
| 469 | if (i == ARRAY_SIZE(whitelist)) |
| 470 | return -EINVAL; |
| 471 | |
| 472 | switch (entry->size) { |
| 473 | case 8: |
| 474 | reg->val = I915_READ64(reg->offset); |
| 475 | break; |
| 476 | case 4: |
| 477 | reg->val = I915_READ(reg->offset); |
| 478 | break; |
| 479 | case 2: |
| 480 | reg->val = I915_READ16(reg->offset); |
| 481 | break; |
| 482 | case 1: |
| 483 | reg->val = I915_READ8(reg->offset); |
| 484 | break; |
| 485 | default: |
| 486 | WARN_ON(1); |
| 487 | return -EINVAL; |
| 488 | } |
| 489 | |
| 490 | return 0; |
| 491 | } |
| 492 | |
| 493 | static int i8xx_do_reset(struct drm_device *dev) |
| 494 | { |
| 495 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 496 | |
| 497 | if (IS_I85X(dev)) |
| 498 | return -ENODEV; |
| 499 | |
| 500 | I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); |
| 501 | POSTING_READ(D_STATE); |
| 502 | |
| 503 | if (IS_I830(dev) || IS_845G(dev)) { |
| 504 | I915_WRITE(DEBUG_RESET_I830, |
| 505 | DEBUG_RESET_DISPLAY | |
| 506 | DEBUG_RESET_RENDER | |
| 507 | DEBUG_RESET_FULL); |
| 508 | POSTING_READ(DEBUG_RESET_I830); |
| 509 | msleep(1); |
| 510 | |
| 511 | I915_WRITE(DEBUG_RESET_I830, 0); |
| 512 | POSTING_READ(DEBUG_RESET_I830); |
| 513 | } |
| 514 | |
| 515 | msleep(1); |
| 516 | |
| 517 | I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); |
| 518 | POSTING_READ(D_STATE); |
| 519 | |
| 520 | return 0; |
| 521 | } |
| 522 | |
| 523 | static int i965_reset_complete(struct drm_device *dev) |
| 524 | { |
| 525 | u8 gdrst; |
| 526 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
| 527 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
| 528 | } |
| 529 | |
| 530 | static int i965_do_reset(struct drm_device *dev) |
| 531 | { |
| 532 | int ret; |
| 533 | |
| 534 | /* |
| 535 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as |
| 536 | * well as the reset bit (GR/bit 0). Setting the GR bit |
| 537 | * triggers the reset; when done, the hardware will clear it. |
| 538 | */ |
| 539 | pci_write_config_byte(dev->pdev, I965_GDRST, |
| 540 | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
| 541 | ret = wait_for(i965_reset_complete(dev), 500); |
| 542 | if (ret) |
| 543 | return ret; |
| 544 | |
| 545 | /* We can't reset render&media without also resetting display ... */ |
| 546 | pci_write_config_byte(dev->pdev, I965_GDRST, |
| 547 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
| 548 | |
| 549 | ret = wait_for(i965_reset_complete(dev), 500); |
| 550 | if (ret) |
| 551 | return ret; |
| 552 | |
| 553 | pci_write_config_byte(dev->pdev, I965_GDRST, 0); |
| 554 | |
| 555 | return 0; |
| 556 | } |
| 557 | |
| 558 | static int ironlake_do_reset(struct drm_device *dev) |
| 559 | { |
| 560 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 561 | u32 gdrst; |
| 562 | int ret; |
| 563 | |
| 564 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); |
| 565 | gdrst &= ~GRDOM_MASK; |
| 566 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
| 567 | gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
| 568 | ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); |
| 569 | if (ret) |
| 570 | return ret; |
| 571 | |
| 572 | /* We can't reset render&media without also resetting display ... */ |
| 573 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); |
| 574 | gdrst &= ~GRDOM_MASK; |
| 575 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
| 576 | gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
| 577 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); |
| 578 | } |
| 579 | |
| 580 | static int gen6_do_reset(struct drm_device *dev) |
| 581 | { |
| 582 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 583 | int ret; |
| 584 | unsigned long irqflags; |
| 585 | |
| 586 | /* Hold uncore.lock across reset to prevent any register access |
| 587 | * with forcewake not set correctly |
| 588 | */ |
| 589 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 590 | |
| 591 | /* Reset the chip */ |
| 592 | |
| 593 | /* GEN6_GDRST is not in the gt power well, no need to check |
| 594 | * for fifo space for the write or forcewake the chip for |
| 595 | * the read |
| 596 | */ |
| 597 | __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL); |
| 598 | |
| 599 | /* Spin waiting for the device to ack the reset request */ |
| 600 | ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); |
| 601 | |
| 602 | intel_uncore_forcewake_reset(dev); |
| 603 | |
| 604 | /* If reset with a user forcewake, try to restore, otherwise turn it off */ |
| 605 | if (dev_priv->uncore.forcewake_count) |
| 606 | dev_priv->uncore.funcs.force_wake_get(dev_priv); |
| 607 | else |
| 608 | dev_priv->uncore.funcs.force_wake_put(dev_priv); |
| 609 | |
| 610 | /* Restore fifo count */ |
| 611 | dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); |
| 612 | |
| 613 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 614 | return ret; |
| 615 | } |
| 616 | |
| 617 | int intel_gpu_reset(struct drm_device *dev) |
| 618 | { |
| 619 | switch (INTEL_INFO(dev)->gen) { |
| 620 | case 7: |
| 621 | case 6: return gen6_do_reset(dev); |
| 622 | case 5: return ironlake_do_reset(dev); |
| 623 | case 4: return i965_do_reset(dev); |
| 624 | case 2: return i8xx_do_reset(dev); |
| 625 | default: return -ENODEV; |
| 626 | } |
| 627 | } |
| 628 | |
| 629 | void intel_uncore_clear_errors(struct drm_device *dev) |
| 630 | { |
| 631 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 632 | |
| 633 | /* XXX needs spinlock around caller's grouping */ |
| 634 | if (HAS_FPGA_DBG_UNCLAIMED(dev)) |
| 635 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
| 636 | } |
| 637 | |
| 638 | void intel_uncore_check_errors(struct drm_device *dev) |
| 639 | { |
| 640 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 641 | |
| 642 | if (HAS_FPGA_DBG_UNCLAIMED(dev) && |
| 643 | (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
| 644 | DRM_ERROR("Unclaimed register before interrupt\n"); |
| 645 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
| 646 | } |
| 647 | } |