| 1 | /* |
| 2 | * Copyright © 2013 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | */ |
| 23 | |
| 24 | #include "i915_drv.h" |
| 25 | #include "intel_drv.h" |
| 26 | |
| 27 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 |
| 28 | |
| 29 | #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__)) |
| 30 | #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__)) |
| 31 | |
| 32 | #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__)) |
| 33 | #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__)) |
| 34 | |
| 35 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) |
| 36 | #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__)) |
| 37 | |
| 38 | #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__)) |
| 39 | #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__)) |
| 40 | |
| 41 | #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__) |
| 42 | |
| 43 | static void |
| 44 | assert_device_not_suspended(struct drm_i915_private *dev_priv) |
| 45 | { |
| 46 | WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended, |
| 47 | "Device suspended\n"); |
| 48 | } |
| 49 | |
| 50 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) |
| 51 | { |
| 52 | /* w/a for a sporadic read returning 0 by waiting for the GT |
| 53 | * thread to wake up. |
| 54 | */ |
| 55 | if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & |
| 56 | GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500)) |
| 57 | DRM_ERROR("GT thread status wait timed out\n"); |
| 58 | } |
| 59 | |
| 60 | static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) |
| 61 | { |
| 62 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
| 63 | /* something from same cacheline, but !FORCEWAKE */ |
| 64 | __raw_posting_read(dev_priv, ECOBUS); |
| 65 | } |
| 66 | |
| 67 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, |
| 68 | int fw_engine) |
| 69 | { |
| 70 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0, |
| 71 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 72 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
| 73 | |
| 74 | __raw_i915_write32(dev_priv, FORCEWAKE, 1); |
| 75 | /* something from same cacheline, but !FORCEWAKE */ |
| 76 | __raw_posting_read(dev_priv, ECOBUS); |
| 77 | |
| 78 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1), |
| 79 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 80 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
| 81 | |
| 82 | /* WaRsForcewakeWaitTC0:snb */ |
| 83 | __gen6_gt_wait_for_thread_c0(dev_priv); |
| 84 | } |
| 85 | |
| 86 | static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) |
| 87 | { |
| 88 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); |
| 89 | /* something from same cacheline, but !FORCEWAKE_MT */ |
| 90 | __raw_posting_read(dev_priv, ECOBUS); |
| 91 | } |
| 92 | |
| 93 | static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv, |
| 94 | int fw_engine) |
| 95 | { |
| 96 | u32 forcewake_ack; |
| 97 | |
| 98 | if (IS_HASWELL(dev_priv->dev) || IS_BROADWELL(dev_priv->dev)) |
| 99 | forcewake_ack = FORCEWAKE_ACK_HSW; |
| 100 | else |
| 101 | forcewake_ack = FORCEWAKE_MT_ACK; |
| 102 | |
| 103 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0, |
| 104 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 105 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
| 106 | |
| 107 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
| 108 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
| 109 | /* something from same cacheline, but !FORCEWAKE_MT */ |
| 110 | __raw_posting_read(dev_priv, ECOBUS); |
| 111 | |
| 112 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL), |
| 113 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 114 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
| 115 | |
| 116 | /* WaRsForcewakeWaitTC0:ivb,hsw */ |
| 117 | __gen6_gt_wait_for_thread_c0(dev_priv); |
| 118 | } |
| 119 | |
| 120 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) |
| 121 | { |
| 122 | u32 gtfifodbg; |
| 123 | |
| 124 | gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); |
| 125 | if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) |
| 126 | __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg); |
| 127 | } |
| 128 | |
| 129 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, |
| 130 | int fw_engine) |
| 131 | { |
| 132 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
| 133 | /* something from same cacheline, but !FORCEWAKE */ |
| 134 | __raw_posting_read(dev_priv, ECOBUS); |
| 135 | gen6_gt_check_fifodbg(dev_priv); |
| 136 | } |
| 137 | |
| 138 | static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv, |
| 139 | int fw_engine) |
| 140 | { |
| 141 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
| 142 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
| 143 | /* something from same cacheline, but !FORCEWAKE_MT */ |
| 144 | __raw_posting_read(dev_priv, ECOBUS); |
| 145 | |
| 146 | if (IS_GEN7(dev_priv->dev)) |
| 147 | gen6_gt_check_fifodbg(dev_priv); |
| 148 | } |
| 149 | |
| 150 | static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
| 151 | { |
| 152 | int ret = 0; |
| 153 | |
| 154 | /* On VLV, FIFO will be shared by both SW and HW. |
| 155 | * So, we need to read the FREE_ENTRIES everytime */ |
| 156 | if (IS_VALLEYVIEW(dev_priv->dev)) |
| 157 | dev_priv->uncore.fifo_count = |
| 158 | __raw_i915_read32(dev_priv, GTFIFOCTL) & |
| 159 | GT_FIFO_FREE_ENTRIES_MASK; |
| 160 | |
| 161 | if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
| 162 | int loop = 500; |
| 163 | u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; |
| 164 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
| 165 | udelay(10); |
| 166 | fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; |
| 167 | } |
| 168 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) |
| 169 | ++ret; |
| 170 | dev_priv->uncore.fifo_count = fifo; |
| 171 | } |
| 172 | dev_priv->uncore.fifo_count--; |
| 173 | |
| 174 | return ret; |
| 175 | } |
| 176 | |
| 177 | static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) |
| 178 | { |
| 179 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
| 180 | _MASKED_BIT_DISABLE(0xffff)); |
| 181 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, |
| 182 | _MASKED_BIT_DISABLE(0xffff)); |
| 183 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
| 184 | __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); |
| 185 | } |
| 186 | |
| 187 | static void __vlv_force_wake_get(struct drm_i915_private *dev_priv, |
| 188 | int fw_engine) |
| 189 | { |
| 190 | /* Check for Render Engine */ |
| 191 | if (FORCEWAKE_RENDER & fw_engine) { |
| 192 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 193 | FORCEWAKE_ACK_VLV) & |
| 194 | FORCEWAKE_KERNEL) == 0, |
| 195 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 196 | DRM_ERROR("Timed out: Render forcewake old ack to clear.\n"); |
| 197 | |
| 198 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
| 199 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
| 200 | |
| 201 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 202 | FORCEWAKE_ACK_VLV) & |
| 203 | FORCEWAKE_KERNEL), |
| 204 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 205 | DRM_ERROR("Timed out: waiting for Render to ack.\n"); |
| 206 | } |
| 207 | |
| 208 | /* Check for Media Engine */ |
| 209 | if (FORCEWAKE_MEDIA & fw_engine) { |
| 210 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 211 | FORCEWAKE_ACK_MEDIA_VLV) & |
| 212 | FORCEWAKE_KERNEL) == 0, |
| 213 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 214 | DRM_ERROR("Timed out: Media forcewake old ack to clear.\n"); |
| 215 | |
| 216 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, |
| 217 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
| 218 | |
| 219 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 220 | FORCEWAKE_ACK_MEDIA_VLV) & |
| 221 | FORCEWAKE_KERNEL), |
| 222 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 223 | DRM_ERROR("Timed out: waiting for media to ack.\n"); |
| 224 | } |
| 225 | } |
| 226 | |
| 227 | static void __vlv_force_wake_put(struct drm_i915_private *dev_priv, |
| 228 | int fw_engine) |
| 229 | { |
| 230 | |
| 231 | /* Check for Render Engine */ |
| 232 | if (FORCEWAKE_RENDER & fw_engine) |
| 233 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
| 234 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
| 235 | |
| 236 | |
| 237 | /* Check for Media Engine */ |
| 238 | if (FORCEWAKE_MEDIA & fw_engine) |
| 239 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, |
| 240 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
| 241 | |
| 242 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
| 243 | __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); |
| 244 | if (!IS_CHERRYVIEW(dev_priv->dev)) |
| 245 | gen6_gt_check_fifodbg(dev_priv); |
| 246 | } |
| 247 | |
| 248 | static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) |
| 249 | { |
| 250 | unsigned long irqflags; |
| 251 | |
| 252 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 253 | |
| 254 | if (fw_engine & FORCEWAKE_RENDER && |
| 255 | dev_priv->uncore.fw_rendercount++ != 0) |
| 256 | fw_engine &= ~FORCEWAKE_RENDER; |
| 257 | if (fw_engine & FORCEWAKE_MEDIA && |
| 258 | dev_priv->uncore.fw_mediacount++ != 0) |
| 259 | fw_engine &= ~FORCEWAKE_MEDIA; |
| 260 | |
| 261 | if (fw_engine) |
| 262 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_engine); |
| 263 | |
| 264 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 265 | } |
| 266 | |
| 267 | static void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) |
| 268 | { |
| 269 | unsigned long irqflags; |
| 270 | |
| 271 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 272 | |
| 273 | if (fw_engine & FORCEWAKE_RENDER) { |
| 274 | WARN_ON(!dev_priv->uncore.fw_rendercount); |
| 275 | if (--dev_priv->uncore.fw_rendercount != 0) |
| 276 | fw_engine &= ~FORCEWAKE_RENDER; |
| 277 | } |
| 278 | |
| 279 | if (fw_engine & FORCEWAKE_MEDIA) { |
| 280 | WARN_ON(!dev_priv->uncore.fw_mediacount); |
| 281 | if (--dev_priv->uncore.fw_mediacount != 0) |
| 282 | fw_engine &= ~FORCEWAKE_MEDIA; |
| 283 | } |
| 284 | |
| 285 | if (fw_engine) |
| 286 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine); |
| 287 | |
| 288 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 289 | } |
| 290 | |
| 291 | static void __gen9_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) |
| 292 | { |
| 293 | __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9, |
| 294 | _MASKED_BIT_DISABLE(0xffff)); |
| 295 | |
| 296 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9, |
| 297 | _MASKED_BIT_DISABLE(0xffff)); |
| 298 | |
| 299 | __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9, |
| 300 | _MASKED_BIT_DISABLE(0xffff)); |
| 301 | } |
| 302 | |
| 303 | static void |
| 304 | __gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) |
| 305 | { |
| 306 | /* Check for Render Engine */ |
| 307 | if (FORCEWAKE_RENDER & fw_engine) { |
| 308 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 309 | FORCEWAKE_ACK_RENDER_GEN9) & |
| 310 | FORCEWAKE_KERNEL) == 0, |
| 311 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 312 | DRM_ERROR("Timed out: Render forcewake old ack to clear.\n"); |
| 313 | |
| 314 | __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9, |
| 315 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
| 316 | |
| 317 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 318 | FORCEWAKE_ACK_RENDER_GEN9) & |
| 319 | FORCEWAKE_KERNEL), |
| 320 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 321 | DRM_ERROR("Timed out: waiting for Render to ack.\n"); |
| 322 | } |
| 323 | |
| 324 | /* Check for Media Engine */ |
| 325 | if (FORCEWAKE_MEDIA & fw_engine) { |
| 326 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 327 | FORCEWAKE_ACK_MEDIA_GEN9) & |
| 328 | FORCEWAKE_KERNEL) == 0, |
| 329 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 330 | DRM_ERROR("Timed out: Media forcewake old ack to clear.\n"); |
| 331 | |
| 332 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9, |
| 333 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
| 334 | |
| 335 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 336 | FORCEWAKE_ACK_MEDIA_GEN9) & |
| 337 | FORCEWAKE_KERNEL), |
| 338 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 339 | DRM_ERROR("Timed out: waiting for Media to ack.\n"); |
| 340 | } |
| 341 | |
| 342 | /* Check for Blitter Engine */ |
| 343 | if (FORCEWAKE_BLITTER & fw_engine) { |
| 344 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 345 | FORCEWAKE_ACK_BLITTER_GEN9) & |
| 346 | FORCEWAKE_KERNEL) == 0, |
| 347 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 348 | DRM_ERROR("Timed out: Blitter forcewake old ack to clear.\n"); |
| 349 | |
| 350 | __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9, |
| 351 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
| 352 | |
| 353 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 354 | FORCEWAKE_ACK_BLITTER_GEN9) & |
| 355 | FORCEWAKE_KERNEL), |
| 356 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 357 | DRM_ERROR("Timed out: waiting for Blitter to ack.\n"); |
| 358 | } |
| 359 | } |
| 360 | |
| 361 | static void |
| 362 | __gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) |
| 363 | { |
| 364 | /* Check for Render Engine */ |
| 365 | if (FORCEWAKE_RENDER & fw_engine) |
| 366 | __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9, |
| 367 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
| 368 | |
| 369 | /* Check for Media Engine */ |
| 370 | if (FORCEWAKE_MEDIA & fw_engine) |
| 371 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9, |
| 372 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
| 373 | |
| 374 | /* Check for Blitter Engine */ |
| 375 | if (FORCEWAKE_BLITTER & fw_engine) |
| 376 | __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9, |
| 377 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
| 378 | } |
| 379 | |
| 380 | static void |
| 381 | gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) |
| 382 | { |
| 383 | unsigned long irqflags; |
| 384 | |
| 385 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 386 | |
| 387 | if (FORCEWAKE_RENDER & fw_engine) { |
| 388 | if (dev_priv->uncore.fw_rendercount++ == 0) |
| 389 | dev_priv->uncore.funcs.force_wake_get(dev_priv, |
| 390 | FORCEWAKE_RENDER); |
| 391 | } |
| 392 | |
| 393 | if (FORCEWAKE_MEDIA & fw_engine) { |
| 394 | if (dev_priv->uncore.fw_mediacount++ == 0) |
| 395 | dev_priv->uncore.funcs.force_wake_get(dev_priv, |
| 396 | FORCEWAKE_MEDIA); |
| 397 | } |
| 398 | |
| 399 | if (FORCEWAKE_BLITTER & fw_engine) { |
| 400 | if (dev_priv->uncore.fw_blittercount++ == 0) |
| 401 | dev_priv->uncore.funcs.force_wake_get(dev_priv, |
| 402 | FORCEWAKE_BLITTER); |
| 403 | } |
| 404 | |
| 405 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 406 | } |
| 407 | |
| 408 | static void |
| 409 | gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) |
| 410 | { |
| 411 | unsigned long irqflags; |
| 412 | |
| 413 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 414 | |
| 415 | if (FORCEWAKE_RENDER & fw_engine) { |
| 416 | WARN_ON(dev_priv->uncore.fw_rendercount == 0); |
| 417 | if (--dev_priv->uncore.fw_rendercount == 0) |
| 418 | dev_priv->uncore.funcs.force_wake_put(dev_priv, |
| 419 | FORCEWAKE_RENDER); |
| 420 | } |
| 421 | |
| 422 | if (FORCEWAKE_MEDIA & fw_engine) { |
| 423 | WARN_ON(dev_priv->uncore.fw_mediacount == 0); |
| 424 | if (--dev_priv->uncore.fw_mediacount == 0) |
| 425 | dev_priv->uncore.funcs.force_wake_put(dev_priv, |
| 426 | FORCEWAKE_MEDIA); |
| 427 | } |
| 428 | |
| 429 | if (FORCEWAKE_BLITTER & fw_engine) { |
| 430 | WARN_ON(dev_priv->uncore.fw_blittercount == 0); |
| 431 | if (--dev_priv->uncore.fw_blittercount == 0) |
| 432 | dev_priv->uncore.funcs.force_wake_put(dev_priv, |
| 433 | FORCEWAKE_BLITTER); |
| 434 | } |
| 435 | |
| 436 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 437 | } |
| 438 | |
| 439 | static void gen6_force_wake_timer(unsigned long arg) |
| 440 | { |
| 441 | struct drm_i915_private *dev_priv = (void *)arg; |
| 442 | unsigned long irqflags; |
| 443 | |
| 444 | assert_device_not_suspended(dev_priv); |
| 445 | |
| 446 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 447 | WARN_ON(!dev_priv->uncore.forcewake_count); |
| 448 | |
| 449 | if (--dev_priv->uncore.forcewake_count == 0) |
| 450 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); |
| 451 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 452 | |
| 453 | intel_runtime_pm_put(dev_priv); |
| 454 | } |
| 455 | |
| 456 | void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) |
| 457 | { |
| 458 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 459 | unsigned long irqflags; |
| 460 | |
| 461 | if (del_timer_sync(&dev_priv->uncore.force_wake_timer)) |
| 462 | gen6_force_wake_timer((unsigned long)dev_priv); |
| 463 | |
| 464 | /* Hold uncore.lock across reset to prevent any register access |
| 465 | * with forcewake not set correctly |
| 466 | */ |
| 467 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 468 | |
| 469 | if (IS_VALLEYVIEW(dev)) |
| 470 | vlv_force_wake_reset(dev_priv); |
| 471 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
| 472 | __gen6_gt_force_wake_reset(dev_priv); |
| 473 | |
| 474 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| 475 | __gen7_gt_force_wake_mt_reset(dev_priv); |
| 476 | |
| 477 | if (IS_GEN9(dev)) |
| 478 | __gen9_gt_force_wake_mt_reset(dev_priv); |
| 479 | |
| 480 | if (restore) { /* If reset with a user forcewake, try to restore */ |
| 481 | unsigned fw = 0; |
| 482 | |
| 483 | if (IS_VALLEYVIEW(dev)) { |
| 484 | if (dev_priv->uncore.fw_rendercount) |
| 485 | fw |= FORCEWAKE_RENDER; |
| 486 | |
| 487 | if (dev_priv->uncore.fw_mediacount) |
| 488 | fw |= FORCEWAKE_MEDIA; |
| 489 | } else if (IS_GEN9(dev)) { |
| 490 | if (dev_priv->uncore.fw_rendercount) |
| 491 | fw |= FORCEWAKE_RENDER; |
| 492 | |
| 493 | if (dev_priv->uncore.fw_mediacount) |
| 494 | fw |= FORCEWAKE_MEDIA; |
| 495 | |
| 496 | if (dev_priv->uncore.fw_blittercount) |
| 497 | fw |= FORCEWAKE_BLITTER; |
| 498 | } else { |
| 499 | if (dev_priv->uncore.forcewake_count) |
| 500 | fw = FORCEWAKE_ALL; |
| 501 | } |
| 502 | |
| 503 | if (fw) |
| 504 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw); |
| 505 | |
| 506 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
| 507 | dev_priv->uncore.fifo_count = |
| 508 | __raw_i915_read32(dev_priv, GTFIFOCTL) & |
| 509 | GT_FIFO_FREE_ENTRIES_MASK; |
| 510 | } |
| 511 | |
| 512 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 513 | } |
| 514 | |
| 515 | static void __intel_uncore_early_sanitize(struct drm_device *dev, |
| 516 | bool restore_forcewake) |
| 517 | { |
| 518 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 519 | |
| 520 | if (HAS_FPGA_DBG_UNCLAIMED(dev)) |
| 521 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
| 522 | |
| 523 | if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && |
| 524 | (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) { |
| 525 | /* The docs do not explain exactly how the calculation can be |
| 526 | * made. It is somewhat guessable, but for now, it's always |
| 527 | * 128MB. |
| 528 | * NB: We can't write IDICR yet because we do not have gt funcs |
| 529 | * set up */ |
| 530 | dev_priv->ellc_size = 128; |
| 531 | DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); |
| 532 | } |
| 533 | |
| 534 | /* clear out old GT FIFO errors */ |
| 535 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
| 536 | __raw_i915_write32(dev_priv, GTFIFODBG, |
| 537 | __raw_i915_read32(dev_priv, GTFIFODBG)); |
| 538 | |
| 539 | intel_uncore_forcewake_reset(dev, restore_forcewake); |
| 540 | } |
| 541 | |
| 542 | void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake) |
| 543 | { |
| 544 | __intel_uncore_early_sanitize(dev, restore_forcewake); |
| 545 | i915_check_and_clear_faults(dev); |
| 546 | } |
| 547 | |
| 548 | void intel_uncore_sanitize(struct drm_device *dev) |
| 549 | { |
| 550 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ |
| 551 | intel_disable_gt_powersave(dev); |
| 552 | } |
| 553 | |
| 554 | /* |
| 555 | * Generally this is called implicitly by the register read function. However, |
| 556 | * if some sequence requires the GT to not power down then this function should |
| 557 | * be called at the beginning of the sequence followed by a call to |
| 558 | * gen6_gt_force_wake_put() at the end of the sequence. |
| 559 | */ |
| 560 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) |
| 561 | { |
| 562 | unsigned long irqflags; |
| 563 | |
| 564 | if (!dev_priv->uncore.funcs.force_wake_get) |
| 565 | return; |
| 566 | |
| 567 | intel_runtime_pm_get(dev_priv); |
| 568 | |
| 569 | /* Redirect to Gen9 specific routine */ |
| 570 | if (IS_GEN9(dev_priv->dev)) |
| 571 | return gen9_force_wake_get(dev_priv, fw_engine); |
| 572 | |
| 573 | /* Redirect to VLV specific routine */ |
| 574 | if (IS_VALLEYVIEW(dev_priv->dev)) |
| 575 | return vlv_force_wake_get(dev_priv, fw_engine); |
| 576 | |
| 577 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 578 | if (dev_priv->uncore.forcewake_count++ == 0) |
| 579 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); |
| 580 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 581 | } |
| 582 | |
| 583 | /* |
| 584 | * see gen6_gt_force_wake_get() |
| 585 | */ |
| 586 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) |
| 587 | { |
| 588 | unsigned long irqflags; |
| 589 | bool delayed = false; |
| 590 | |
| 591 | if (!dev_priv->uncore.funcs.force_wake_put) |
| 592 | return; |
| 593 | |
| 594 | /* Redirect to Gen9 specific routine */ |
| 595 | if (IS_GEN9(dev_priv->dev)) { |
| 596 | gen9_force_wake_put(dev_priv, fw_engine); |
| 597 | goto out; |
| 598 | } |
| 599 | |
| 600 | /* Redirect to VLV specific routine */ |
| 601 | if (IS_VALLEYVIEW(dev_priv->dev)) { |
| 602 | vlv_force_wake_put(dev_priv, fw_engine); |
| 603 | goto out; |
| 604 | } |
| 605 | |
| 606 | |
| 607 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 608 | WARN_ON(!dev_priv->uncore.forcewake_count); |
| 609 | |
| 610 | if (--dev_priv->uncore.forcewake_count == 0) { |
| 611 | dev_priv->uncore.forcewake_count++; |
| 612 | delayed = true; |
| 613 | mod_timer_pinned(&dev_priv->uncore.force_wake_timer, |
| 614 | jiffies + 1); |
| 615 | } |
| 616 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 617 | |
| 618 | out: |
| 619 | if (!delayed) |
| 620 | intel_runtime_pm_put(dev_priv); |
| 621 | } |
| 622 | |
| 623 | void assert_force_wake_inactive(struct drm_i915_private *dev_priv) |
| 624 | { |
| 625 | if (!dev_priv->uncore.funcs.force_wake_get) |
| 626 | return; |
| 627 | |
| 628 | WARN_ON(dev_priv->uncore.forcewake_count > 0); |
| 629 | } |
| 630 | |
| 631 | /* We give fast paths for the really cool registers */ |
| 632 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
| 633 | ((reg) < 0x40000 && (reg) != FORCEWAKE) |
| 634 | |
| 635 | #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end)) |
| 636 | |
| 637 | #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \ |
| 638 | (REG_RANGE((reg), 0x2000, 0x4000) || \ |
| 639 | REG_RANGE((reg), 0x5000, 0x8000) || \ |
| 640 | REG_RANGE((reg), 0xB000, 0x12000) || \ |
| 641 | REG_RANGE((reg), 0x2E000, 0x30000)) |
| 642 | |
| 643 | #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \ |
| 644 | (REG_RANGE((reg), 0x12000, 0x14000) || \ |
| 645 | REG_RANGE((reg), 0x22000, 0x24000) || \ |
| 646 | REG_RANGE((reg), 0x30000, 0x40000)) |
| 647 | |
| 648 | #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \ |
| 649 | (REG_RANGE((reg), 0x2000, 0x4000) || \ |
| 650 | REG_RANGE((reg), 0x5000, 0x8000) || \ |
| 651 | REG_RANGE((reg), 0x8300, 0x8500) || \ |
| 652 | REG_RANGE((reg), 0xB000, 0xC000) || \ |
| 653 | REG_RANGE((reg), 0xE000, 0xE800)) |
| 654 | |
| 655 | #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \ |
| 656 | (REG_RANGE((reg), 0x8800, 0x8900) || \ |
| 657 | REG_RANGE((reg), 0xD000, 0xD800) || \ |
| 658 | REG_RANGE((reg), 0x12000, 0x14000) || \ |
| 659 | REG_RANGE((reg), 0x1A000, 0x1C000) || \ |
| 660 | REG_RANGE((reg), 0x1E800, 0x1EA00) || \ |
| 661 | REG_RANGE((reg), 0x30000, 0x40000)) |
| 662 | |
| 663 | #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \ |
| 664 | (REG_RANGE((reg), 0x4000, 0x5000) || \ |
| 665 | REG_RANGE((reg), 0x8000, 0x8300) || \ |
| 666 | REG_RANGE((reg), 0x8500, 0x8600) || \ |
| 667 | REG_RANGE((reg), 0x9000, 0xB000) || \ |
| 668 | REG_RANGE((reg), 0xC000, 0xC800) || \ |
| 669 | REG_RANGE((reg), 0xF000, 0x10000) || \ |
| 670 | REG_RANGE((reg), 0x14000, 0x14400) || \ |
| 671 | REG_RANGE((reg), 0x22000, 0x24000)) |
| 672 | |
| 673 | #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \ |
| 674 | REG_RANGE((reg), 0xC00, 0x2000) |
| 675 | |
| 676 | #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \ |
| 677 | (REG_RANGE((reg), 0x2000, 0x4000) || \ |
| 678 | REG_RANGE((reg), 0x5200, 0x8000) || \ |
| 679 | REG_RANGE((reg), 0x8300, 0x8500) || \ |
| 680 | REG_RANGE((reg), 0x8C00, 0x8D00) || \ |
| 681 | REG_RANGE((reg), 0xB000, 0xB480) || \ |
| 682 | REG_RANGE((reg), 0xE000, 0xE800)) |
| 683 | |
| 684 | #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \ |
| 685 | (REG_RANGE((reg), 0x8800, 0x8A00) || \ |
| 686 | REG_RANGE((reg), 0xD000, 0xD800) || \ |
| 687 | REG_RANGE((reg), 0x12000, 0x14000) || \ |
| 688 | REG_RANGE((reg), 0x1A000, 0x1EA00) || \ |
| 689 | REG_RANGE((reg), 0x30000, 0x40000)) |
| 690 | |
| 691 | #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \ |
| 692 | REG_RANGE((reg), 0x9400, 0x9800) |
| 693 | |
| 694 | #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \ |
| 695 | ((reg) < 0x40000 &&\ |
| 696 | !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \ |
| 697 | !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \ |
| 698 | !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \ |
| 699 | !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) |
| 700 | |
| 701 | static void |
| 702 | ilk_dummy_write(struct drm_i915_private *dev_priv) |
| 703 | { |
| 704 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up |
| 705 | * the chip from rc6 before touching it for real. MI_MODE is masked, |
| 706 | * hence harmless to write 0 into. */ |
| 707 | __raw_i915_write32(dev_priv, MI_MODE, 0); |
| 708 | } |
| 709 | |
| 710 | static void |
| 711 | hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read, |
| 712 | bool before) |
| 713 | { |
| 714 | const char *op = read ? "reading" : "writing to"; |
| 715 | const char *when = before ? "before" : "after"; |
| 716 | |
| 717 | if (!i915.mmio_debug) |
| 718 | return; |
| 719 | |
| 720 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
| 721 | WARN(1, "Unclaimed register detected %s %s register 0x%x\n", |
| 722 | when, op, reg); |
| 723 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
| 724 | } |
| 725 | } |
| 726 | |
| 727 | static void |
| 728 | hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv) |
| 729 | { |
| 730 | if (i915.mmio_debug) |
| 731 | return; |
| 732 | |
| 733 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
| 734 | DRM_ERROR("Unclaimed register detected. Please use the i915.mmio_debug=1 to debug this problem."); |
| 735 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
| 736 | } |
| 737 | } |
| 738 | |
| 739 | #define REG_READ_HEADER(x) \ |
| 740 | unsigned long irqflags; \ |
| 741 | u##x val = 0; \ |
| 742 | assert_device_not_suspended(dev_priv); \ |
| 743 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
| 744 | |
| 745 | #define REG_READ_FOOTER \ |
| 746 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ |
| 747 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ |
| 748 | return val |
| 749 | |
| 750 | #define __gen4_read(x) \ |
| 751 | static u##x \ |
| 752 | gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
| 753 | REG_READ_HEADER(x); \ |
| 754 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 755 | REG_READ_FOOTER; \ |
| 756 | } |
| 757 | |
| 758 | #define __gen5_read(x) \ |
| 759 | static u##x \ |
| 760 | gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
| 761 | REG_READ_HEADER(x); \ |
| 762 | ilk_dummy_write(dev_priv); \ |
| 763 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 764 | REG_READ_FOOTER; \ |
| 765 | } |
| 766 | |
| 767 | #define __gen6_read(x) \ |
| 768 | static u##x \ |
| 769 | gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
| 770 | REG_READ_HEADER(x); \ |
| 771 | hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \ |
| 772 | if (dev_priv->uncore.forcewake_count == 0 && \ |
| 773 | NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 774 | dev_priv->uncore.funcs.force_wake_get(dev_priv, \ |
| 775 | FORCEWAKE_ALL); \ |
| 776 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 777 | dev_priv->uncore.funcs.force_wake_put(dev_priv, \ |
| 778 | FORCEWAKE_ALL); \ |
| 779 | } else { \ |
| 780 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 781 | } \ |
| 782 | hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \ |
| 783 | REG_READ_FOOTER; \ |
| 784 | } |
| 785 | |
| 786 | #define __vlv_read(x) \ |
| 787 | static u##x \ |
| 788 | vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
| 789 | unsigned fwengine = 0; \ |
| 790 | REG_READ_HEADER(x); \ |
| 791 | if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \ |
| 792 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 793 | fwengine = FORCEWAKE_RENDER; \ |
| 794 | } else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \ |
| 795 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 796 | fwengine = FORCEWAKE_MEDIA; \ |
| 797 | } \ |
| 798 | if (fwengine) \ |
| 799 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ |
| 800 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 801 | if (fwengine) \ |
| 802 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ |
| 803 | REG_READ_FOOTER; \ |
| 804 | } |
| 805 | |
| 806 | #define __chv_read(x) \ |
| 807 | static u##x \ |
| 808 | chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
| 809 | unsigned fwengine = 0; \ |
| 810 | REG_READ_HEADER(x); \ |
| 811 | if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \ |
| 812 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 813 | fwengine = FORCEWAKE_RENDER; \ |
| 814 | } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ |
| 815 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 816 | fwengine = FORCEWAKE_MEDIA; \ |
| 817 | } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \ |
| 818 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 819 | fwengine |= FORCEWAKE_RENDER; \ |
| 820 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 821 | fwengine |= FORCEWAKE_MEDIA; \ |
| 822 | } \ |
| 823 | if (fwengine) \ |
| 824 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ |
| 825 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 826 | if (fwengine) \ |
| 827 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ |
| 828 | REG_READ_FOOTER; \ |
| 829 | } |
| 830 | |
| 831 | #define SKL_NEEDS_FORCE_WAKE(dev_priv, reg) \ |
| 832 | ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg)) |
| 833 | |
| 834 | #define __gen9_read(x) \ |
| 835 | static u##x \ |
| 836 | gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
| 837 | REG_READ_HEADER(x); \ |
| 838 | if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 839 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 840 | } else { \ |
| 841 | unsigned fwengine = 0; \ |
| 842 | if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) { \ |
| 843 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 844 | fwengine = FORCEWAKE_RENDER; \ |
| 845 | } else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) { \ |
| 846 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 847 | fwengine = FORCEWAKE_MEDIA; \ |
| 848 | } else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) { \ |
| 849 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 850 | fwengine |= FORCEWAKE_RENDER; \ |
| 851 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 852 | fwengine |= FORCEWAKE_MEDIA; \ |
| 853 | } else { \ |
| 854 | if (dev_priv->uncore.fw_blittercount == 0) \ |
| 855 | fwengine = FORCEWAKE_BLITTER; \ |
| 856 | } \ |
| 857 | if (fwengine) \ |
| 858 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ |
| 859 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 860 | if (fwengine) \ |
| 861 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ |
| 862 | } \ |
| 863 | REG_READ_FOOTER; \ |
| 864 | } |
| 865 | |
| 866 | __gen9_read(8) |
| 867 | __gen9_read(16) |
| 868 | __gen9_read(32) |
| 869 | __gen9_read(64) |
| 870 | __chv_read(8) |
| 871 | __chv_read(16) |
| 872 | __chv_read(32) |
| 873 | __chv_read(64) |
| 874 | __vlv_read(8) |
| 875 | __vlv_read(16) |
| 876 | __vlv_read(32) |
| 877 | __vlv_read(64) |
| 878 | __gen6_read(8) |
| 879 | __gen6_read(16) |
| 880 | __gen6_read(32) |
| 881 | __gen6_read(64) |
| 882 | __gen5_read(8) |
| 883 | __gen5_read(16) |
| 884 | __gen5_read(32) |
| 885 | __gen5_read(64) |
| 886 | __gen4_read(8) |
| 887 | __gen4_read(16) |
| 888 | __gen4_read(32) |
| 889 | __gen4_read(64) |
| 890 | |
| 891 | #undef __gen9_read |
| 892 | #undef __chv_read |
| 893 | #undef __vlv_read |
| 894 | #undef __gen6_read |
| 895 | #undef __gen5_read |
| 896 | #undef __gen4_read |
| 897 | #undef REG_READ_FOOTER |
| 898 | #undef REG_READ_HEADER |
| 899 | |
| 900 | #define REG_WRITE_HEADER \ |
| 901 | unsigned long irqflags; \ |
| 902 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ |
| 903 | assert_device_not_suspended(dev_priv); \ |
| 904 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
| 905 | |
| 906 | #define REG_WRITE_FOOTER \ |
| 907 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) |
| 908 | |
| 909 | #define __gen4_write(x) \ |
| 910 | static void \ |
| 911 | gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 912 | REG_WRITE_HEADER; \ |
| 913 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 914 | REG_WRITE_FOOTER; \ |
| 915 | } |
| 916 | |
| 917 | #define __gen5_write(x) \ |
| 918 | static void \ |
| 919 | gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 920 | REG_WRITE_HEADER; \ |
| 921 | ilk_dummy_write(dev_priv); \ |
| 922 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 923 | REG_WRITE_FOOTER; \ |
| 924 | } |
| 925 | |
| 926 | #define __gen6_write(x) \ |
| 927 | static void \ |
| 928 | gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 929 | u32 __fifo_ret = 0; \ |
| 930 | REG_WRITE_HEADER; \ |
| 931 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 932 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
| 933 | } \ |
| 934 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 935 | if (unlikely(__fifo_ret)) { \ |
| 936 | gen6_gt_check_fifodbg(dev_priv); \ |
| 937 | } \ |
| 938 | REG_WRITE_FOOTER; \ |
| 939 | } |
| 940 | |
| 941 | #define __hsw_write(x) \ |
| 942 | static void \ |
| 943 | hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 944 | u32 __fifo_ret = 0; \ |
| 945 | REG_WRITE_HEADER; \ |
| 946 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 947 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
| 948 | } \ |
| 949 | hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \ |
| 950 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 951 | if (unlikely(__fifo_ret)) { \ |
| 952 | gen6_gt_check_fifodbg(dev_priv); \ |
| 953 | } \ |
| 954 | hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ |
| 955 | hsw_unclaimed_reg_detect(dev_priv); \ |
| 956 | REG_WRITE_FOOTER; \ |
| 957 | } |
| 958 | |
| 959 | static const u32 gen8_shadowed_regs[] = { |
| 960 | FORCEWAKE_MT, |
| 961 | GEN6_RPNSWREQ, |
| 962 | GEN6_RC_VIDEO_FREQ, |
| 963 | RING_TAIL(RENDER_RING_BASE), |
| 964 | RING_TAIL(GEN6_BSD_RING_BASE), |
| 965 | RING_TAIL(VEBOX_RING_BASE), |
| 966 | RING_TAIL(BLT_RING_BASE), |
| 967 | /* TODO: Other registers are not yet used */ |
| 968 | }; |
| 969 | |
| 970 | static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg) |
| 971 | { |
| 972 | int i; |
| 973 | for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++) |
| 974 | if (reg == gen8_shadowed_regs[i]) |
| 975 | return true; |
| 976 | |
| 977 | return false; |
| 978 | } |
| 979 | |
| 980 | #define __gen8_write(x) \ |
| 981 | static void \ |
| 982 | gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 983 | REG_WRITE_HEADER; \ |
| 984 | hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \ |
| 985 | if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \ |
| 986 | if (dev_priv->uncore.forcewake_count == 0) \ |
| 987 | dev_priv->uncore.funcs.force_wake_get(dev_priv, \ |
| 988 | FORCEWAKE_ALL); \ |
| 989 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 990 | if (dev_priv->uncore.forcewake_count == 0) \ |
| 991 | dev_priv->uncore.funcs.force_wake_put(dev_priv, \ |
| 992 | FORCEWAKE_ALL); \ |
| 993 | } else { \ |
| 994 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 995 | } \ |
| 996 | hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ |
| 997 | hsw_unclaimed_reg_detect(dev_priv); \ |
| 998 | REG_WRITE_FOOTER; \ |
| 999 | } |
| 1000 | |
| 1001 | #define __chv_write(x) \ |
| 1002 | static void \ |
| 1003 | chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 1004 | unsigned fwengine = 0; \ |
| 1005 | bool shadowed = is_gen8_shadowed(dev_priv, reg); \ |
| 1006 | REG_WRITE_HEADER; \ |
| 1007 | if (!shadowed) { \ |
| 1008 | if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \ |
| 1009 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 1010 | fwengine = FORCEWAKE_RENDER; \ |
| 1011 | } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ |
| 1012 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 1013 | fwengine = FORCEWAKE_MEDIA; \ |
| 1014 | } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \ |
| 1015 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 1016 | fwengine |= FORCEWAKE_RENDER; \ |
| 1017 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 1018 | fwengine |= FORCEWAKE_MEDIA; \ |
| 1019 | } \ |
| 1020 | } \ |
| 1021 | if (fwengine) \ |
| 1022 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ |
| 1023 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 1024 | if (fwengine) \ |
| 1025 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ |
| 1026 | REG_WRITE_FOOTER; \ |
| 1027 | } |
| 1028 | |
| 1029 | static const u32 gen9_shadowed_regs[] = { |
| 1030 | RING_TAIL(RENDER_RING_BASE), |
| 1031 | RING_TAIL(GEN6_BSD_RING_BASE), |
| 1032 | RING_TAIL(VEBOX_RING_BASE), |
| 1033 | RING_TAIL(BLT_RING_BASE), |
| 1034 | FORCEWAKE_BLITTER_GEN9, |
| 1035 | FORCEWAKE_RENDER_GEN9, |
| 1036 | FORCEWAKE_MEDIA_GEN9, |
| 1037 | GEN6_RPNSWREQ, |
| 1038 | GEN6_RC_VIDEO_FREQ, |
| 1039 | /* TODO: Other registers are not yet used */ |
| 1040 | }; |
| 1041 | |
| 1042 | static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg) |
| 1043 | { |
| 1044 | int i; |
| 1045 | for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++) |
| 1046 | if (reg == gen9_shadowed_regs[i]) |
| 1047 | return true; |
| 1048 | |
| 1049 | return false; |
| 1050 | } |
| 1051 | |
| 1052 | #define __gen9_write(x) \ |
| 1053 | static void \ |
| 1054 | gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \ |
| 1055 | bool trace) { \ |
| 1056 | REG_WRITE_HEADER; \ |
| 1057 | if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \ |
| 1058 | is_gen9_shadowed(dev_priv, reg)) { \ |
| 1059 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 1060 | } else { \ |
| 1061 | unsigned fwengine = 0; \ |
| 1062 | if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) { \ |
| 1063 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 1064 | fwengine = FORCEWAKE_RENDER; \ |
| 1065 | } else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) { \ |
| 1066 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 1067 | fwengine = FORCEWAKE_MEDIA; \ |
| 1068 | } else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) { \ |
| 1069 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 1070 | fwengine |= FORCEWAKE_RENDER; \ |
| 1071 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 1072 | fwengine |= FORCEWAKE_MEDIA; \ |
| 1073 | } else { \ |
| 1074 | if (dev_priv->uncore.fw_blittercount == 0) \ |
| 1075 | fwengine = FORCEWAKE_BLITTER; \ |
| 1076 | } \ |
| 1077 | if (fwengine) \ |
| 1078 | dev_priv->uncore.funcs.force_wake_get(dev_priv, \ |
| 1079 | fwengine); \ |
| 1080 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 1081 | if (fwengine) \ |
| 1082 | dev_priv->uncore.funcs.force_wake_put(dev_priv, \ |
| 1083 | fwengine); \ |
| 1084 | } \ |
| 1085 | REG_WRITE_FOOTER; \ |
| 1086 | } |
| 1087 | |
| 1088 | __gen9_write(8) |
| 1089 | __gen9_write(16) |
| 1090 | __gen9_write(32) |
| 1091 | __gen9_write(64) |
| 1092 | __chv_write(8) |
| 1093 | __chv_write(16) |
| 1094 | __chv_write(32) |
| 1095 | __chv_write(64) |
| 1096 | __gen8_write(8) |
| 1097 | __gen8_write(16) |
| 1098 | __gen8_write(32) |
| 1099 | __gen8_write(64) |
| 1100 | __hsw_write(8) |
| 1101 | __hsw_write(16) |
| 1102 | __hsw_write(32) |
| 1103 | __hsw_write(64) |
| 1104 | __gen6_write(8) |
| 1105 | __gen6_write(16) |
| 1106 | __gen6_write(32) |
| 1107 | __gen6_write(64) |
| 1108 | __gen5_write(8) |
| 1109 | __gen5_write(16) |
| 1110 | __gen5_write(32) |
| 1111 | __gen5_write(64) |
| 1112 | __gen4_write(8) |
| 1113 | __gen4_write(16) |
| 1114 | __gen4_write(32) |
| 1115 | __gen4_write(64) |
| 1116 | |
| 1117 | #undef __gen9_write |
| 1118 | #undef __chv_write |
| 1119 | #undef __gen8_write |
| 1120 | #undef __hsw_write |
| 1121 | #undef __gen6_write |
| 1122 | #undef __gen5_write |
| 1123 | #undef __gen4_write |
| 1124 | #undef REG_WRITE_FOOTER |
| 1125 | #undef REG_WRITE_HEADER |
| 1126 | |
| 1127 | #define ASSIGN_WRITE_MMIO_VFUNCS(x) \ |
| 1128 | do { \ |
| 1129 | dev_priv->uncore.funcs.mmio_writeb = x##_write8; \ |
| 1130 | dev_priv->uncore.funcs.mmio_writew = x##_write16; \ |
| 1131 | dev_priv->uncore.funcs.mmio_writel = x##_write32; \ |
| 1132 | dev_priv->uncore.funcs.mmio_writeq = x##_write64; \ |
| 1133 | } while (0) |
| 1134 | |
| 1135 | #define ASSIGN_READ_MMIO_VFUNCS(x) \ |
| 1136 | do { \ |
| 1137 | dev_priv->uncore.funcs.mmio_readb = x##_read8; \ |
| 1138 | dev_priv->uncore.funcs.mmio_readw = x##_read16; \ |
| 1139 | dev_priv->uncore.funcs.mmio_readl = x##_read32; \ |
| 1140 | dev_priv->uncore.funcs.mmio_readq = x##_read64; \ |
| 1141 | } while (0) |
| 1142 | |
| 1143 | void intel_uncore_init(struct drm_device *dev) |
| 1144 | { |
| 1145 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1146 | |
| 1147 | setup_timer(&dev_priv->uncore.force_wake_timer, |
| 1148 | gen6_force_wake_timer, (unsigned long)dev_priv); |
| 1149 | |
| 1150 | __intel_uncore_early_sanitize(dev, false); |
| 1151 | |
| 1152 | if (IS_GEN9(dev)) { |
| 1153 | dev_priv->uncore.funcs.force_wake_get = __gen9_force_wake_get; |
| 1154 | dev_priv->uncore.funcs.force_wake_put = __gen9_force_wake_put; |
| 1155 | } else if (IS_VALLEYVIEW(dev)) { |
| 1156 | dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get; |
| 1157 | dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put; |
| 1158 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
| 1159 | dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get; |
| 1160 | dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put; |
| 1161 | } else if (IS_IVYBRIDGE(dev)) { |
| 1162 | u32 ecobus; |
| 1163 | |
| 1164 | /* IVB configs may use multi-threaded forcewake */ |
| 1165 | |
| 1166 | /* A small trick here - if the bios hasn't configured |
| 1167 | * MT forcewake, and if the device is in RC6, then |
| 1168 | * force_wake_mt_get will not wake the device and the |
| 1169 | * ECOBUS read will return zero. Which will be |
| 1170 | * (correctly) interpreted by the test below as MT |
| 1171 | * forcewake being disabled. |
| 1172 | */ |
| 1173 | mutex_lock(&dev->struct_mutex); |
| 1174 | __gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL); |
| 1175 | ecobus = __raw_i915_read32(dev_priv, ECOBUS); |
| 1176 | __gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL); |
| 1177 | mutex_unlock(&dev->struct_mutex); |
| 1178 | |
| 1179 | if (ecobus & FORCEWAKE_MT_ENABLE) { |
| 1180 | dev_priv->uncore.funcs.force_wake_get = |
| 1181 | __gen7_gt_force_wake_mt_get; |
| 1182 | dev_priv->uncore.funcs.force_wake_put = |
| 1183 | __gen7_gt_force_wake_mt_put; |
| 1184 | } else { |
| 1185 | DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); |
| 1186 | DRM_INFO("when using vblank-synced partial screen updates.\n"); |
| 1187 | dev_priv->uncore.funcs.force_wake_get = |
| 1188 | __gen6_gt_force_wake_get; |
| 1189 | dev_priv->uncore.funcs.force_wake_put = |
| 1190 | __gen6_gt_force_wake_put; |
| 1191 | } |
| 1192 | } else if (IS_GEN6(dev)) { |
| 1193 | dev_priv->uncore.funcs.force_wake_get = |
| 1194 | __gen6_gt_force_wake_get; |
| 1195 | dev_priv->uncore.funcs.force_wake_put = |
| 1196 | __gen6_gt_force_wake_put; |
| 1197 | } |
| 1198 | |
| 1199 | switch (INTEL_INFO(dev)->gen) { |
| 1200 | default: |
| 1201 | WARN_ON(1); |
| 1202 | return; |
| 1203 | case 9: |
| 1204 | ASSIGN_WRITE_MMIO_VFUNCS(gen9); |
| 1205 | ASSIGN_READ_MMIO_VFUNCS(gen9); |
| 1206 | break; |
| 1207 | case 8: |
| 1208 | if (IS_CHERRYVIEW(dev)) { |
| 1209 | ASSIGN_WRITE_MMIO_VFUNCS(chv); |
| 1210 | ASSIGN_READ_MMIO_VFUNCS(chv); |
| 1211 | |
| 1212 | } else { |
| 1213 | ASSIGN_WRITE_MMIO_VFUNCS(gen8); |
| 1214 | ASSIGN_READ_MMIO_VFUNCS(gen6); |
| 1215 | } |
| 1216 | break; |
| 1217 | case 7: |
| 1218 | case 6: |
| 1219 | if (IS_HASWELL(dev)) { |
| 1220 | ASSIGN_WRITE_MMIO_VFUNCS(hsw); |
| 1221 | } else { |
| 1222 | ASSIGN_WRITE_MMIO_VFUNCS(gen6); |
| 1223 | } |
| 1224 | |
| 1225 | if (IS_VALLEYVIEW(dev)) { |
| 1226 | ASSIGN_READ_MMIO_VFUNCS(vlv); |
| 1227 | } else { |
| 1228 | ASSIGN_READ_MMIO_VFUNCS(gen6); |
| 1229 | } |
| 1230 | break; |
| 1231 | case 5: |
| 1232 | ASSIGN_WRITE_MMIO_VFUNCS(gen5); |
| 1233 | ASSIGN_READ_MMIO_VFUNCS(gen5); |
| 1234 | break; |
| 1235 | case 4: |
| 1236 | case 3: |
| 1237 | case 2: |
| 1238 | ASSIGN_WRITE_MMIO_VFUNCS(gen4); |
| 1239 | ASSIGN_READ_MMIO_VFUNCS(gen4); |
| 1240 | break; |
| 1241 | } |
| 1242 | |
| 1243 | i915_check_and_clear_faults(dev); |
| 1244 | } |
| 1245 | #undef ASSIGN_WRITE_MMIO_VFUNCS |
| 1246 | #undef ASSIGN_READ_MMIO_VFUNCS |
| 1247 | |
| 1248 | void intel_uncore_fini(struct drm_device *dev) |
| 1249 | { |
| 1250 | /* Paranoia: make sure we have disabled everything before we exit. */ |
| 1251 | intel_uncore_sanitize(dev); |
| 1252 | intel_uncore_forcewake_reset(dev, false); |
| 1253 | } |
| 1254 | |
| 1255 | #define GEN_RANGE(l, h) GENMASK(h, l) |
| 1256 | |
| 1257 | static const struct register_whitelist { |
| 1258 | uint64_t offset; |
| 1259 | uint32_t size; |
| 1260 | /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ |
| 1261 | uint32_t gen_bitmask; |
| 1262 | } whitelist[] = { |
| 1263 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 9) }, |
| 1264 | }; |
| 1265 | |
| 1266 | int i915_reg_read_ioctl(struct drm_device *dev, |
| 1267 | void *data, struct drm_file *file) |
| 1268 | { |
| 1269 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1270 | struct drm_i915_reg_read *reg = data; |
| 1271 | struct register_whitelist const *entry = whitelist; |
| 1272 | int i, ret = 0; |
| 1273 | |
| 1274 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { |
| 1275 | if (entry->offset == reg->offset && |
| 1276 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) |
| 1277 | break; |
| 1278 | } |
| 1279 | |
| 1280 | if (i == ARRAY_SIZE(whitelist)) |
| 1281 | return -EINVAL; |
| 1282 | |
| 1283 | intel_runtime_pm_get(dev_priv); |
| 1284 | |
| 1285 | switch (entry->size) { |
| 1286 | case 8: |
| 1287 | reg->val = I915_READ64(reg->offset); |
| 1288 | break; |
| 1289 | case 4: |
| 1290 | reg->val = I915_READ(reg->offset); |
| 1291 | break; |
| 1292 | case 2: |
| 1293 | reg->val = I915_READ16(reg->offset); |
| 1294 | break; |
| 1295 | case 1: |
| 1296 | reg->val = I915_READ8(reg->offset); |
| 1297 | break; |
| 1298 | default: |
| 1299 | WARN_ON(1); |
| 1300 | ret = -EINVAL; |
| 1301 | goto out; |
| 1302 | } |
| 1303 | |
| 1304 | out: |
| 1305 | intel_runtime_pm_put(dev_priv); |
| 1306 | return ret; |
| 1307 | } |
| 1308 | |
| 1309 | int i915_get_reset_stats_ioctl(struct drm_device *dev, |
| 1310 | void *data, struct drm_file *file) |
| 1311 | { |
| 1312 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1313 | struct drm_i915_reset_stats *args = data; |
| 1314 | struct i915_ctx_hang_stats *hs; |
| 1315 | struct intel_context *ctx; |
| 1316 | int ret; |
| 1317 | |
| 1318 | if (args->flags || args->pad) |
| 1319 | return -EINVAL; |
| 1320 | |
| 1321 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN)) |
| 1322 | return -EPERM; |
| 1323 | |
| 1324 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1325 | if (ret) |
| 1326 | return ret; |
| 1327 | |
| 1328 | ctx = i915_gem_context_get(file->driver_priv, args->ctx_id); |
| 1329 | if (IS_ERR(ctx)) { |
| 1330 | mutex_unlock(&dev->struct_mutex); |
| 1331 | return PTR_ERR(ctx); |
| 1332 | } |
| 1333 | hs = &ctx->hang_stats; |
| 1334 | |
| 1335 | if (capable(CAP_SYS_ADMIN)) |
| 1336 | args->reset_count = i915_reset_count(&dev_priv->gpu_error); |
| 1337 | else |
| 1338 | args->reset_count = 0; |
| 1339 | |
| 1340 | args->batch_active = hs->batch_active; |
| 1341 | args->batch_pending = hs->batch_pending; |
| 1342 | |
| 1343 | mutex_unlock(&dev->struct_mutex); |
| 1344 | |
| 1345 | return 0; |
| 1346 | } |
| 1347 | |
| 1348 | static int i965_reset_complete(struct drm_device *dev) |
| 1349 | { |
| 1350 | u8 gdrst; |
| 1351 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
| 1352 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
| 1353 | } |
| 1354 | |
| 1355 | static int i965_do_reset(struct drm_device *dev) |
| 1356 | { |
| 1357 | int ret; |
| 1358 | |
| 1359 | /* FIXME: i965g/gm need a display save/restore for gpu reset. */ |
| 1360 | return -ENODEV; |
| 1361 | |
| 1362 | /* |
| 1363 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as |
| 1364 | * well as the reset bit (GR/bit 0). Setting the GR bit |
| 1365 | * triggers the reset; when done, the hardware will clear it. |
| 1366 | */ |
| 1367 | pci_write_config_byte(dev->pdev, I965_GDRST, |
| 1368 | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
| 1369 | ret = wait_for(i965_reset_complete(dev), 500); |
| 1370 | if (ret) |
| 1371 | return ret; |
| 1372 | |
| 1373 | pci_write_config_byte(dev->pdev, I965_GDRST, |
| 1374 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
| 1375 | |
| 1376 | ret = wait_for(i965_reset_complete(dev), 500); |
| 1377 | if (ret) |
| 1378 | return ret; |
| 1379 | |
| 1380 | pci_write_config_byte(dev->pdev, I965_GDRST, 0); |
| 1381 | |
| 1382 | return 0; |
| 1383 | } |
| 1384 | |
| 1385 | static int g4x_do_reset(struct drm_device *dev) |
| 1386 | { |
| 1387 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1388 | int ret; |
| 1389 | |
| 1390 | pci_write_config_byte(dev->pdev, I965_GDRST, |
| 1391 | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
| 1392 | ret = wait_for(i965_reset_complete(dev), 500); |
| 1393 | if (ret) |
| 1394 | return ret; |
| 1395 | |
| 1396 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ |
| 1397 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); |
| 1398 | POSTING_READ(VDECCLK_GATE_D); |
| 1399 | |
| 1400 | pci_write_config_byte(dev->pdev, I965_GDRST, |
| 1401 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
| 1402 | ret = wait_for(i965_reset_complete(dev), 500); |
| 1403 | if (ret) |
| 1404 | return ret; |
| 1405 | |
| 1406 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ |
| 1407 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE); |
| 1408 | POSTING_READ(VDECCLK_GATE_D); |
| 1409 | |
| 1410 | pci_write_config_byte(dev->pdev, I965_GDRST, 0); |
| 1411 | |
| 1412 | return 0; |
| 1413 | } |
| 1414 | |
| 1415 | static int ironlake_do_reset(struct drm_device *dev) |
| 1416 | { |
| 1417 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1418 | int ret; |
| 1419 | |
| 1420 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
| 1421 | ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE); |
| 1422 | ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & |
| 1423 | ILK_GRDOM_RESET_ENABLE) == 0, 500); |
| 1424 | if (ret) |
| 1425 | return ret; |
| 1426 | |
| 1427 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
| 1428 | ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE); |
| 1429 | ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & |
| 1430 | ILK_GRDOM_RESET_ENABLE) == 0, 500); |
| 1431 | if (ret) |
| 1432 | return ret; |
| 1433 | |
| 1434 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0); |
| 1435 | |
| 1436 | return 0; |
| 1437 | } |
| 1438 | |
| 1439 | static int gen6_do_reset(struct drm_device *dev) |
| 1440 | { |
| 1441 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1442 | int ret; |
| 1443 | |
| 1444 | /* Reset the chip */ |
| 1445 | |
| 1446 | /* GEN6_GDRST is not in the gt power well, no need to check |
| 1447 | * for fifo space for the write or forcewake the chip for |
| 1448 | * the read |
| 1449 | */ |
| 1450 | __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL); |
| 1451 | |
| 1452 | /* Spin waiting for the device to ack the reset request */ |
| 1453 | ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); |
| 1454 | |
| 1455 | intel_uncore_forcewake_reset(dev, true); |
| 1456 | |
| 1457 | return ret; |
| 1458 | } |
| 1459 | |
| 1460 | int intel_gpu_reset(struct drm_device *dev) |
| 1461 | { |
| 1462 | if (INTEL_INFO(dev)->gen >= 6) |
| 1463 | return gen6_do_reset(dev); |
| 1464 | else if (IS_GEN5(dev)) |
| 1465 | return ironlake_do_reset(dev); |
| 1466 | else if (IS_G4X(dev)) |
| 1467 | return g4x_do_reset(dev); |
| 1468 | else if (IS_GEN4(dev)) |
| 1469 | return i965_do_reset(dev); |
| 1470 | else |
| 1471 | return -ENODEV; |
| 1472 | } |
| 1473 | |
| 1474 | void intel_uncore_check_errors(struct drm_device *dev) |
| 1475 | { |
| 1476 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1477 | |
| 1478 | if (HAS_FPGA_DBG_UNCLAIMED(dev) && |
| 1479 | (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
| 1480 | DRM_ERROR("Unclaimed register before interrupt\n"); |
| 1481 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
| 1482 | } |
| 1483 | } |