| 1 | /* |
| 2 | * i.MX IPUv3 DP Overlay Planes |
| 3 | * |
| 4 | * Copyright (C) 2013 Philipp Zabel, Pengutronix |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version 2 |
| 9 | * of the License, or (at your option) any later version. |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <drm/drmP.h> |
| 17 | #include <drm/drm_fb_cma_helper.h> |
| 18 | #include <drm/drm_gem_cma_helper.h> |
| 19 | |
| 20 | #include "video/imx-ipu-v3.h" |
| 21 | #include "ipuv3-plane.h" |
| 22 | |
| 23 | #define to_ipu_plane(x) container_of(x, struct ipu_plane, base) |
| 24 | |
| 25 | static const uint32_t ipu_plane_formats[] = { |
| 26 | DRM_FORMAT_ARGB1555, |
| 27 | DRM_FORMAT_XRGB1555, |
| 28 | DRM_FORMAT_ABGR1555, |
| 29 | DRM_FORMAT_XBGR1555, |
| 30 | DRM_FORMAT_RGBA5551, |
| 31 | DRM_FORMAT_BGRA5551, |
| 32 | DRM_FORMAT_ARGB4444, |
| 33 | DRM_FORMAT_ARGB8888, |
| 34 | DRM_FORMAT_XRGB8888, |
| 35 | DRM_FORMAT_ABGR8888, |
| 36 | DRM_FORMAT_XBGR8888, |
| 37 | DRM_FORMAT_RGBA8888, |
| 38 | DRM_FORMAT_RGBX8888, |
| 39 | DRM_FORMAT_BGRA8888, |
| 40 | DRM_FORMAT_BGRA8888, |
| 41 | DRM_FORMAT_UYVY, |
| 42 | DRM_FORMAT_VYUY, |
| 43 | DRM_FORMAT_YUYV, |
| 44 | DRM_FORMAT_YVYU, |
| 45 | DRM_FORMAT_YUV420, |
| 46 | DRM_FORMAT_YVU420, |
| 47 | DRM_FORMAT_RGB565, |
| 48 | }; |
| 49 | |
| 50 | int ipu_plane_irq(struct ipu_plane *ipu_plane) |
| 51 | { |
| 52 | return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch, |
| 53 | IPU_IRQ_EOF); |
| 54 | } |
| 55 | |
| 56 | int ipu_plane_set_base(struct ipu_plane *ipu_plane, struct drm_framebuffer *fb, |
| 57 | int x, int y) |
| 58 | { |
| 59 | struct drm_gem_cma_object *cma_obj[3]; |
| 60 | unsigned long eba, ubo, vbo; |
| 61 | int active, i; |
| 62 | |
| 63 | for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) { |
| 64 | cma_obj[i] = drm_fb_cma_get_gem_obj(fb, i); |
| 65 | if (!cma_obj[i]) { |
| 66 | DRM_DEBUG_KMS("plane %d entry is null.\n", i); |
| 67 | return -EFAULT; |
| 68 | } |
| 69 | } |
| 70 | |
| 71 | eba = cma_obj[0]->paddr + fb->offsets[0] + |
| 72 | fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x; |
| 73 | |
| 74 | if (eba & 0x7) { |
| 75 | DRM_DEBUG_KMS("base address must be a multiple of 8.\n"); |
| 76 | return -EINVAL; |
| 77 | } |
| 78 | |
| 79 | if (fb->pitches[0] < 1 || fb->pitches[0] > 16384) { |
| 80 | DRM_DEBUG_KMS("pitches out of range.\n"); |
| 81 | return -EINVAL; |
| 82 | } |
| 83 | |
| 84 | if (ipu_plane->enabled && fb->pitches[0] != ipu_plane->stride[0]) { |
| 85 | DRM_DEBUG_KMS("pitches must not change while plane is enabled.\n"); |
| 86 | return -EINVAL; |
| 87 | } |
| 88 | |
| 89 | ipu_plane->stride[0] = fb->pitches[0]; |
| 90 | |
| 91 | switch (fb->pixel_format) { |
| 92 | case DRM_FORMAT_YUV420: |
| 93 | case DRM_FORMAT_YVU420: |
| 94 | /* |
| 95 | * Multiplanar formats have to meet the following restrictions: |
| 96 | * - The (up to) three plane addresses are EBA, EBA+UBO, EBA+VBO |
| 97 | * - EBA, UBO and VBO are a multiple of 8 |
| 98 | * - UBO and VBO are unsigned and not larger than 0xfffff8 |
| 99 | * - Only EBA may be changed while scanout is active |
| 100 | * - The strides of U and V planes must be identical. |
| 101 | */ |
| 102 | ubo = cma_obj[1]->paddr + fb->offsets[1] + |
| 103 | fb->pitches[1] * y / 2 + x / 2 - eba; |
| 104 | vbo = cma_obj[2]->paddr + fb->offsets[2] + |
| 105 | fb->pitches[2] * y / 2 + x / 2 - eba; |
| 106 | |
| 107 | if ((ubo & 0x7) || (vbo & 0x7)) { |
| 108 | DRM_DEBUG_KMS("U/V buffer offsets must be a multiple of 8.\n"); |
| 109 | return -EINVAL; |
| 110 | } |
| 111 | |
| 112 | if ((ubo > 0xfffff8) || (vbo > 0xfffff8)) { |
| 113 | DRM_DEBUG_KMS("U/V buffer offsets must be positive and not larger than 0xfffff8.\n"); |
| 114 | return -EINVAL; |
| 115 | } |
| 116 | |
| 117 | if (ipu_plane->enabled && ((ipu_plane->u_offset != ubo) || |
| 118 | (ipu_plane->v_offset != vbo))) { |
| 119 | DRM_DEBUG_KMS("U/V buffer offsets must not change while plane is enabled.\n"); |
| 120 | return -EINVAL; |
| 121 | } |
| 122 | |
| 123 | if (fb->pitches[1] != fb->pitches[2]) { |
| 124 | DRM_DEBUG_KMS("U/V pitches must be identical.\n"); |
| 125 | return -EINVAL; |
| 126 | } |
| 127 | |
| 128 | if (fb->pitches[1] < 1 || fb->pitches[1] > 16384) { |
| 129 | DRM_DEBUG_KMS("U/V pitches out of range.\n"); |
| 130 | return -EINVAL; |
| 131 | } |
| 132 | |
| 133 | if (ipu_plane->enabled && |
| 134 | (ipu_plane->stride[1] != fb->pitches[1])) { |
| 135 | DRM_DEBUG_KMS("U/V pitches must not change while plane is enabled.\n"); |
| 136 | return -EINVAL; |
| 137 | } |
| 138 | |
| 139 | ipu_plane->u_offset = ubo; |
| 140 | ipu_plane->v_offset = vbo; |
| 141 | ipu_plane->stride[1] = fb->pitches[1]; |
| 142 | |
| 143 | dev_dbg(ipu_plane->base.dev->dev, |
| 144 | "phys = %pad %pad %pad, x = %d, y = %d", |
| 145 | &cma_obj[0]->paddr, &cma_obj[1]->paddr, |
| 146 | &cma_obj[2]->paddr, x, y); |
| 147 | break; |
| 148 | default: |
| 149 | dev_dbg(ipu_plane->base.dev->dev, "phys = %pad, x = %d, y = %d", |
| 150 | &cma_obj[0]->paddr, x, y); |
| 151 | break; |
| 152 | } |
| 153 | |
| 154 | if (ipu_plane->enabled) { |
| 155 | active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch); |
| 156 | ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba); |
| 157 | ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active); |
| 158 | } else { |
| 159 | ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba); |
| 160 | ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba); |
| 161 | } |
| 162 | |
| 163 | /* cache offsets for subsequent pageflips */ |
| 164 | ipu_plane->x = x; |
| 165 | ipu_plane->y = y; |
| 166 | |
| 167 | return 0; |
| 168 | } |
| 169 | |
| 170 | int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc, |
| 171 | struct drm_display_mode *mode, |
| 172 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, |
| 173 | unsigned int crtc_w, unsigned int crtc_h, |
| 174 | uint32_t src_x, uint32_t src_y, |
| 175 | uint32_t src_w, uint32_t src_h, bool interlaced) |
| 176 | { |
| 177 | struct device *dev = ipu_plane->base.dev->dev; |
| 178 | int ret; |
| 179 | |
| 180 | /* no scaling */ |
| 181 | if (src_w != crtc_w || src_h != crtc_h) |
| 182 | return -EINVAL; |
| 183 | |
| 184 | if (ipu_plane->base.type == DRM_PLANE_TYPE_PRIMARY) { |
| 185 | /* full plane doesn't support partial off screen */ |
| 186 | if (crtc_x || crtc_y || crtc_w != mode->hdisplay || |
| 187 | crtc_h != mode->vdisplay) |
| 188 | return -EINVAL; |
| 189 | |
| 190 | /* full plane minimum width is 13 pixels */ |
| 191 | if (crtc_w < 13) |
| 192 | return -EINVAL; |
| 193 | } else if (ipu_plane->base.type == DRM_PLANE_TYPE_OVERLAY) { |
| 194 | /* clip to crtc bounds */ |
| 195 | if (crtc_x < 0) { |
| 196 | if (-crtc_x > crtc_w) |
| 197 | return -EINVAL; |
| 198 | src_x += -crtc_x; |
| 199 | src_w -= -crtc_x; |
| 200 | crtc_w -= -crtc_x; |
| 201 | crtc_x = 0; |
| 202 | } |
| 203 | if (crtc_y < 0) { |
| 204 | if (-crtc_y > crtc_h) |
| 205 | return -EINVAL; |
| 206 | src_y += -crtc_y; |
| 207 | src_h -= -crtc_y; |
| 208 | crtc_h -= -crtc_y; |
| 209 | crtc_y = 0; |
| 210 | } |
| 211 | if (crtc_x + crtc_w > mode->hdisplay) { |
| 212 | if (crtc_x > mode->hdisplay) |
| 213 | return -EINVAL; |
| 214 | crtc_w = mode->hdisplay - crtc_x; |
| 215 | src_w = crtc_w; |
| 216 | } |
| 217 | if (crtc_y + crtc_h > mode->vdisplay) { |
| 218 | if (crtc_y > mode->vdisplay) |
| 219 | return -EINVAL; |
| 220 | crtc_h = mode->vdisplay - crtc_y; |
| 221 | src_h = crtc_h; |
| 222 | } |
| 223 | } else |
| 224 | return -EINVAL; |
| 225 | if (crtc_h < 2) |
| 226 | return -EINVAL; |
| 227 | |
| 228 | /* |
| 229 | * since we cannot touch active IDMAC channels, we do not support |
| 230 | * resizing the enabled plane or changing its format |
| 231 | */ |
| 232 | if (ipu_plane->enabled) { |
| 233 | if (src_w != ipu_plane->w || src_h != ipu_plane->h || |
| 234 | fb->pixel_format != ipu_plane->base.fb->pixel_format) |
| 235 | return -EINVAL; |
| 236 | |
| 237 | return ipu_plane_set_base(ipu_plane, fb, src_x, src_y); |
| 238 | } |
| 239 | |
| 240 | switch (ipu_plane->dp_flow) { |
| 241 | case IPU_DP_FLOW_SYNC_BG: |
| 242 | ret = ipu_dp_setup_channel(ipu_plane->dp, |
| 243 | IPUV3_COLORSPACE_RGB, |
| 244 | IPUV3_COLORSPACE_RGB); |
| 245 | if (ret) { |
| 246 | dev_err(dev, |
| 247 | "initializing display processor failed with %d\n", |
| 248 | ret); |
| 249 | return ret; |
| 250 | } |
| 251 | ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true); |
| 252 | break; |
| 253 | case IPU_DP_FLOW_SYNC_FG: |
| 254 | ipu_dp_setup_channel(ipu_plane->dp, |
| 255 | ipu_drm_fourcc_to_colorspace(fb->pixel_format), |
| 256 | IPUV3_COLORSPACE_UNKNOWN); |
| 257 | ipu_dp_set_window_pos(ipu_plane->dp, crtc_x, crtc_y); |
| 258 | /* Enable local alpha on partial plane */ |
| 259 | switch (fb->pixel_format) { |
| 260 | case DRM_FORMAT_ARGB1555: |
| 261 | case DRM_FORMAT_ABGR1555: |
| 262 | case DRM_FORMAT_RGBA5551: |
| 263 | case DRM_FORMAT_BGRA5551: |
| 264 | case DRM_FORMAT_ARGB4444: |
| 265 | case DRM_FORMAT_ARGB8888: |
| 266 | case DRM_FORMAT_ABGR8888: |
| 267 | case DRM_FORMAT_RGBA8888: |
| 268 | case DRM_FORMAT_BGRA8888: |
| 269 | ipu_dp_set_global_alpha(ipu_plane->dp, false, 0, false); |
| 270 | break; |
| 271 | default: |
| 272 | break; |
| 273 | } |
| 274 | } |
| 275 | |
| 276 | ipu_dmfc_config_wait4eot(ipu_plane->dmfc, crtc_w); |
| 277 | |
| 278 | ipu_cpmem_zero(ipu_plane->ipu_ch); |
| 279 | ipu_cpmem_set_resolution(ipu_plane->ipu_ch, src_w, src_h); |
| 280 | ret = ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->pixel_format); |
| 281 | if (ret < 0) { |
| 282 | dev_err(dev, "unsupported pixel format 0x%08x\n", |
| 283 | fb->pixel_format); |
| 284 | return ret; |
| 285 | } |
| 286 | ipu_cpmem_set_high_priority(ipu_plane->ipu_ch); |
| 287 | ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1); |
| 288 | ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]); |
| 289 | |
| 290 | ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y); |
| 291 | if (ret < 0) |
| 292 | return ret; |
| 293 | if (interlaced) |
| 294 | ipu_cpmem_interlaced_scan(ipu_plane->ipu_ch, fb->pitches[0]); |
| 295 | |
| 296 | if (fb->pixel_format == DRM_FORMAT_YUV420) { |
| 297 | ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch, |
| 298 | ipu_plane->stride[1], |
| 299 | ipu_plane->u_offset, |
| 300 | ipu_plane->v_offset); |
| 301 | } else if (fb->pixel_format == DRM_FORMAT_YVU420) { |
| 302 | ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch, |
| 303 | ipu_plane->stride[1], |
| 304 | ipu_plane->v_offset, |
| 305 | ipu_plane->u_offset); |
| 306 | } |
| 307 | |
| 308 | ipu_plane->w = src_w; |
| 309 | ipu_plane->h = src_h; |
| 310 | |
| 311 | return 0; |
| 312 | } |
| 313 | |
| 314 | void ipu_plane_put_resources(struct ipu_plane *ipu_plane) |
| 315 | { |
| 316 | if (!IS_ERR_OR_NULL(ipu_plane->dp)) |
| 317 | ipu_dp_put(ipu_plane->dp); |
| 318 | if (!IS_ERR_OR_NULL(ipu_plane->dmfc)) |
| 319 | ipu_dmfc_put(ipu_plane->dmfc); |
| 320 | if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch)) |
| 321 | ipu_idmac_put(ipu_plane->ipu_ch); |
| 322 | } |
| 323 | |
| 324 | int ipu_plane_get_resources(struct ipu_plane *ipu_plane) |
| 325 | { |
| 326 | int ret; |
| 327 | |
| 328 | ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma); |
| 329 | if (IS_ERR(ipu_plane->ipu_ch)) { |
| 330 | ret = PTR_ERR(ipu_plane->ipu_ch); |
| 331 | DRM_ERROR("failed to get idmac channel: %d\n", ret); |
| 332 | return ret; |
| 333 | } |
| 334 | |
| 335 | ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma); |
| 336 | if (IS_ERR(ipu_plane->dmfc)) { |
| 337 | ret = PTR_ERR(ipu_plane->dmfc); |
| 338 | DRM_ERROR("failed to get dmfc: ret %d\n", ret); |
| 339 | goto err_out; |
| 340 | } |
| 341 | |
| 342 | if (ipu_plane->dp_flow >= 0) { |
| 343 | ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow); |
| 344 | if (IS_ERR(ipu_plane->dp)) { |
| 345 | ret = PTR_ERR(ipu_plane->dp); |
| 346 | DRM_ERROR("failed to get dp flow: %d\n", ret); |
| 347 | goto err_out; |
| 348 | } |
| 349 | } |
| 350 | |
| 351 | return 0; |
| 352 | err_out: |
| 353 | ipu_plane_put_resources(ipu_plane); |
| 354 | |
| 355 | return ret; |
| 356 | } |
| 357 | |
| 358 | void ipu_plane_enable(struct ipu_plane *ipu_plane) |
| 359 | { |
| 360 | if (ipu_plane->dp) |
| 361 | ipu_dp_enable(ipu_plane->ipu); |
| 362 | ipu_dmfc_enable_channel(ipu_plane->dmfc); |
| 363 | ipu_idmac_enable_channel(ipu_plane->ipu_ch); |
| 364 | if (ipu_plane->dp) |
| 365 | ipu_dp_enable_channel(ipu_plane->dp); |
| 366 | |
| 367 | ipu_plane->enabled = true; |
| 368 | } |
| 369 | |
| 370 | void ipu_plane_disable(struct ipu_plane *ipu_plane) |
| 371 | { |
| 372 | ipu_plane->enabled = false; |
| 373 | |
| 374 | ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50); |
| 375 | |
| 376 | if (ipu_plane->dp) |
| 377 | ipu_dp_disable_channel(ipu_plane->dp); |
| 378 | ipu_idmac_disable_channel(ipu_plane->ipu_ch); |
| 379 | ipu_dmfc_disable_channel(ipu_plane->dmfc); |
| 380 | if (ipu_plane->dp) |
| 381 | ipu_dp_disable(ipu_plane->ipu); |
| 382 | } |
| 383 | |
| 384 | /* |
| 385 | * drm_plane API |
| 386 | */ |
| 387 | |
| 388 | static int ipu_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
| 389 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, |
| 390 | unsigned int crtc_w, unsigned int crtc_h, |
| 391 | uint32_t src_x, uint32_t src_y, |
| 392 | uint32_t src_w, uint32_t src_h) |
| 393 | { |
| 394 | struct ipu_plane *ipu_plane = to_ipu_plane(plane); |
| 395 | int ret = 0; |
| 396 | |
| 397 | DRM_DEBUG_KMS("plane - %p\n", plane); |
| 398 | |
| 399 | if (!ipu_plane->enabled) |
| 400 | ret = ipu_plane_get_resources(ipu_plane); |
| 401 | if (ret < 0) |
| 402 | return ret; |
| 403 | |
| 404 | ret = ipu_plane_mode_set(ipu_plane, crtc, &crtc->hwmode, fb, |
| 405 | crtc_x, crtc_y, crtc_w, crtc_h, |
| 406 | src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16, |
| 407 | false); |
| 408 | if (ret < 0) { |
| 409 | ipu_plane_put_resources(ipu_plane); |
| 410 | return ret; |
| 411 | } |
| 412 | |
| 413 | if (crtc != plane->crtc) |
| 414 | dev_dbg(plane->dev->dev, "crtc change: %p -> %p\n", |
| 415 | plane->crtc, crtc); |
| 416 | |
| 417 | if (!ipu_plane->enabled) |
| 418 | ipu_plane_enable(ipu_plane); |
| 419 | |
| 420 | return 0; |
| 421 | } |
| 422 | |
| 423 | static int ipu_disable_plane(struct drm_plane *plane) |
| 424 | { |
| 425 | struct ipu_plane *ipu_plane = to_ipu_plane(plane); |
| 426 | |
| 427 | DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__); |
| 428 | |
| 429 | if (ipu_plane->enabled) |
| 430 | ipu_plane_disable(ipu_plane); |
| 431 | |
| 432 | ipu_plane_put_resources(ipu_plane); |
| 433 | |
| 434 | return 0; |
| 435 | } |
| 436 | |
| 437 | static void ipu_plane_destroy(struct drm_plane *plane) |
| 438 | { |
| 439 | struct ipu_plane *ipu_plane = to_ipu_plane(plane); |
| 440 | |
| 441 | DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__); |
| 442 | |
| 443 | ipu_disable_plane(plane); |
| 444 | drm_plane_cleanup(plane); |
| 445 | kfree(ipu_plane); |
| 446 | } |
| 447 | |
| 448 | static const struct drm_plane_funcs ipu_plane_funcs = { |
| 449 | .update_plane = ipu_update_plane, |
| 450 | .disable_plane = ipu_disable_plane, |
| 451 | .destroy = ipu_plane_destroy, |
| 452 | }; |
| 453 | |
| 454 | struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu, |
| 455 | int dma, int dp, unsigned int possible_crtcs, |
| 456 | enum drm_plane_type type) |
| 457 | { |
| 458 | struct ipu_plane *ipu_plane; |
| 459 | int ret; |
| 460 | |
| 461 | DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n", |
| 462 | dma, dp, possible_crtcs); |
| 463 | |
| 464 | ipu_plane = kzalloc(sizeof(*ipu_plane), GFP_KERNEL); |
| 465 | if (!ipu_plane) { |
| 466 | DRM_ERROR("failed to allocate plane\n"); |
| 467 | return ERR_PTR(-ENOMEM); |
| 468 | } |
| 469 | |
| 470 | ipu_plane->ipu = ipu; |
| 471 | ipu_plane->dma = dma; |
| 472 | ipu_plane->dp_flow = dp; |
| 473 | |
| 474 | ret = drm_universal_plane_init(dev, &ipu_plane->base, possible_crtcs, |
| 475 | &ipu_plane_funcs, ipu_plane_formats, |
| 476 | ARRAY_SIZE(ipu_plane_formats), type, |
| 477 | NULL); |
| 478 | if (ret) { |
| 479 | DRM_ERROR("failed to initialize plane\n"); |
| 480 | kfree(ipu_plane); |
| 481 | return ERR_PTR(ret); |
| 482 | } |
| 483 | |
| 484 | return ipu_plane; |
| 485 | } |