| 1 | #include "nv20.h" |
| 2 | #include "regs.h" |
| 3 | |
| 4 | #include <core/gpuobj.h> |
| 5 | #include <engine/fifo.h> |
| 6 | #include <engine/fifo/chan.h> |
| 7 | #include <subdev/fb.h> |
| 8 | |
| 9 | /******************************************************************************* |
| 10 | * PGRAPH context |
| 11 | ******************************************************************************/ |
| 12 | |
| 13 | static const struct nvkm_object_func |
| 14 | nv30_gr_chan = { |
| 15 | .dtor = nv20_gr_chan_dtor, |
| 16 | .init = nv20_gr_chan_init, |
| 17 | .fini = nv20_gr_chan_fini, |
| 18 | }; |
| 19 | |
| 20 | static int |
| 21 | nv30_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, |
| 22 | const struct nvkm_oclass *oclass, struct nvkm_object **pobject) |
| 23 | { |
| 24 | struct nv20_gr *gr = nv20_gr(base); |
| 25 | struct nv20_gr_chan *chan; |
| 26 | int ret, i; |
| 27 | |
| 28 | if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) |
| 29 | return -ENOMEM; |
| 30 | nvkm_object_ctor(&nv30_gr_chan, oclass, &chan->object); |
| 31 | chan->gr = gr; |
| 32 | chan->chid = fifoch->chid; |
| 33 | *pobject = &chan->object; |
| 34 | |
| 35 | ret = nvkm_memory_new(gr->base.engine.subdev.device, |
| 36 | NVKM_MEM_TARGET_INST, 0x5f48, 16, true, |
| 37 | &chan->inst); |
| 38 | if (ret) |
| 39 | return ret; |
| 40 | |
| 41 | nvkm_kmap(chan->inst); |
| 42 | nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); |
| 43 | nvkm_wo32(chan->inst, 0x0410, 0x00000101); |
| 44 | nvkm_wo32(chan->inst, 0x0424, 0x00000111); |
| 45 | nvkm_wo32(chan->inst, 0x0428, 0x00000060); |
| 46 | nvkm_wo32(chan->inst, 0x0444, 0x00000080); |
| 47 | nvkm_wo32(chan->inst, 0x0448, 0xffff0000); |
| 48 | nvkm_wo32(chan->inst, 0x044c, 0x00000001); |
| 49 | nvkm_wo32(chan->inst, 0x0460, 0x44400000); |
| 50 | nvkm_wo32(chan->inst, 0x048c, 0xffff0000); |
| 51 | for (i = 0x04e0; i < 0x04e8; i += 4) |
| 52 | nvkm_wo32(chan->inst, i, 0x0fff0000); |
| 53 | nvkm_wo32(chan->inst, 0x04ec, 0x00011100); |
| 54 | for (i = 0x0508; i < 0x0548; i += 4) |
| 55 | nvkm_wo32(chan->inst, i, 0x07ff0000); |
| 56 | nvkm_wo32(chan->inst, 0x0550, 0x4b7fffff); |
| 57 | nvkm_wo32(chan->inst, 0x058c, 0x00000080); |
| 58 | nvkm_wo32(chan->inst, 0x0590, 0x30201000); |
| 59 | nvkm_wo32(chan->inst, 0x0594, 0x70605040); |
| 60 | nvkm_wo32(chan->inst, 0x0598, 0xb8a89888); |
| 61 | nvkm_wo32(chan->inst, 0x059c, 0xf8e8d8c8); |
| 62 | nvkm_wo32(chan->inst, 0x05b0, 0xb0000000); |
| 63 | for (i = 0x0600; i < 0x0640; i += 4) |
| 64 | nvkm_wo32(chan->inst, i, 0x00010588); |
| 65 | for (i = 0x0640; i < 0x0680; i += 4) |
| 66 | nvkm_wo32(chan->inst, i, 0x00030303); |
| 67 | for (i = 0x06c0; i < 0x0700; i += 4) |
| 68 | nvkm_wo32(chan->inst, i, 0x0008aae4); |
| 69 | for (i = 0x0700; i < 0x0740; i += 4) |
| 70 | nvkm_wo32(chan->inst, i, 0x01012000); |
| 71 | for (i = 0x0740; i < 0x0780; i += 4) |
| 72 | nvkm_wo32(chan->inst, i, 0x00080008); |
| 73 | nvkm_wo32(chan->inst, 0x085c, 0x00040000); |
| 74 | nvkm_wo32(chan->inst, 0x0860, 0x00010000); |
| 75 | for (i = 0x0864; i < 0x0874; i += 4) |
| 76 | nvkm_wo32(chan->inst, i, 0x00040004); |
| 77 | for (i = 0x1f18; i <= 0x3088 ; i += 16) { |
| 78 | nvkm_wo32(chan->inst, i + 0, 0x10700ff9); |
| 79 | nvkm_wo32(chan->inst, i + 4, 0x0436086c); |
| 80 | nvkm_wo32(chan->inst, i + 8, 0x000c001b); |
| 81 | } |
| 82 | for (i = 0x30b8; i < 0x30c8; i += 4) |
| 83 | nvkm_wo32(chan->inst, i, 0x0000ffff); |
| 84 | nvkm_wo32(chan->inst, 0x344c, 0x3f800000); |
| 85 | nvkm_wo32(chan->inst, 0x3808, 0x3f800000); |
| 86 | nvkm_wo32(chan->inst, 0x381c, 0x3f800000); |
| 87 | nvkm_wo32(chan->inst, 0x3848, 0x40000000); |
| 88 | nvkm_wo32(chan->inst, 0x384c, 0x3f800000); |
| 89 | nvkm_wo32(chan->inst, 0x3850, 0x3f000000); |
| 90 | nvkm_wo32(chan->inst, 0x3858, 0x40000000); |
| 91 | nvkm_wo32(chan->inst, 0x385c, 0x3f800000); |
| 92 | nvkm_wo32(chan->inst, 0x3864, 0xbf800000); |
| 93 | nvkm_wo32(chan->inst, 0x386c, 0xbf800000); |
| 94 | nvkm_done(chan->inst); |
| 95 | return 0; |
| 96 | } |
| 97 | |
| 98 | /******************************************************************************* |
| 99 | * PGRAPH engine/subdev functions |
| 100 | ******************************************************************************/ |
| 101 | |
| 102 | int |
| 103 | nv30_gr_init(struct nvkm_gr *base) |
| 104 | { |
| 105 | struct nv20_gr *gr = nv20_gr(base); |
| 106 | struct nvkm_device *device = gr->base.engine.subdev.device; |
| 107 | |
| 108 | nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE, |
| 109 | nvkm_memory_addr(gr->ctxtab) >> 4); |
| 110 | |
| 111 | nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF); |
| 112 | nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); |
| 113 | |
| 114 | nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); |
| 115 | nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000); |
| 116 | nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x401287c0); |
| 117 | nvkm_wr32(device, 0x400890, 0x01b463ff); |
| 118 | nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xf2de0475); |
| 119 | nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00008000); |
| 120 | nvkm_wr32(device, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); |
| 121 | nvkm_wr32(device, 0x400B80, 0x1003d888); |
| 122 | nvkm_wr32(device, 0x400B84, 0x0c000000); |
| 123 | nvkm_wr32(device, 0x400098, 0x00000000); |
| 124 | nvkm_wr32(device, 0x40009C, 0x0005ad00); |
| 125 | nvkm_wr32(device, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */ |
| 126 | nvkm_wr32(device, 0x4000a0, 0x00000000); |
| 127 | nvkm_wr32(device, 0x4000a4, 0x00000008); |
| 128 | nvkm_wr32(device, 0x4008a8, 0xb784a400); |
| 129 | nvkm_wr32(device, 0x400ba0, 0x002f8685); |
| 130 | nvkm_wr32(device, 0x400ba4, 0x00231f3f); |
| 131 | nvkm_wr32(device, 0x4008a4, 0x40000020); |
| 132 | |
| 133 | if (device->chipset == 0x34) { |
| 134 | nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); |
| 135 | nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00200201); |
| 136 | nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0008); |
| 137 | nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000008); |
| 138 | nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); |
| 139 | nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000032); |
| 140 | nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00004); |
| 141 | nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000002); |
| 142 | } |
| 143 | |
| 144 | nvkm_wr32(device, 0x4000c0, 0x00000016); |
| 145 | |
| 146 | nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100); |
| 147 | nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF); |
| 148 | nvkm_wr32(device, 0x0040075c , 0x00000001); |
| 149 | |
| 150 | /* begin RAM config */ |
| 151 | /* vramsz = pci_resource_len(gr->dev->pdev, 1) - 1; */ |
| 152 | nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200)); |
| 153 | nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204)); |
| 154 | if (device->chipset != 0x34) { |
| 155 | nvkm_wr32(device, 0x400750, 0x00EA0000); |
| 156 | nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100200)); |
| 157 | nvkm_wr32(device, 0x400750, 0x00EA0004); |
| 158 | nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100204)); |
| 159 | } |
| 160 | |
| 161 | return 0; |
| 162 | } |
| 163 | |
| 164 | static const struct nvkm_gr_func |
| 165 | nv30_gr = { |
| 166 | .dtor = nv20_gr_dtor, |
| 167 | .oneinit = nv20_gr_oneinit, |
| 168 | .init = nv30_gr_init, |
| 169 | .intr = nv20_gr_intr, |
| 170 | .tile = nv20_gr_tile, |
| 171 | .chan_new = nv30_gr_chan_new, |
| 172 | .sclass = { |
| 173 | { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ |
| 174 | { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ |
| 175 | { -1, -1, 0x0030, &nv04_gr_object }, /* null */ |
| 176 | { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ |
| 177 | { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ |
| 178 | { -1, -1, 0x0044, &nv04_gr_object }, /* patt */ |
| 179 | { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ |
| 180 | { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ |
| 181 | { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ |
| 182 | { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ |
| 183 | { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ |
| 184 | { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */ |
| 185 | { -1, -1, 0x0362, &nv04_gr_object }, /* surf2d (nv30) */ |
| 186 | { -1, -1, 0x0389, &nv04_gr_object }, /* sifm (nv30) */ |
| 187 | { -1, -1, 0x038a, &nv04_gr_object }, /* ifc (nv30) */ |
| 188 | { -1, -1, 0x039e, &nv04_gr_object }, /* swzsurf (nv30) */ |
| 189 | { -1, -1, 0x0397, &nv04_gr_object }, /* rankine */ |
| 190 | {} |
| 191 | } |
| 192 | }; |
| 193 | |
| 194 | int |
| 195 | nv30_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) |
| 196 | { |
| 197 | return nv20_gr_new_(&nv30_gr, device, index, pgr); |
| 198 | } |