| 1 | /* |
| 2 | * OMAP5 HDMI CORE IP driver library |
| 3 | * |
| 4 | * Copyright (C) 2014 Texas Instruments Incorporated |
| 5 | * |
| 6 | * Authors: |
| 7 | * Yong Zhi |
| 8 | * Mythri pk |
| 9 | * Archit Taneja <archit@ti.com> |
| 10 | * Tomi Valkeinen <tomi.valkeinen@ti.com> |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify it |
| 13 | * under the terms of the GNU General Public License version 2 as published by |
| 14 | * the Free Software Foundation. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 17 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 19 | * more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License along with |
| 22 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 23 | */ |
| 24 | |
| 25 | #include <linux/kernel.h> |
| 26 | #include <linux/module.h> |
| 27 | #include <linux/err.h> |
| 28 | #include <linux/io.h> |
| 29 | #include <linux/delay.h> |
| 30 | #include <linux/string.h> |
| 31 | #include <linux/seq_file.h> |
| 32 | #include <drm/drm_edid.h> |
| 33 | #include <sound/asound.h> |
| 34 | #include <sound/asoundef.h> |
| 35 | |
| 36 | #include "hdmi5_core.h" |
| 37 | |
| 38 | /* only 24 bit color depth used for now */ |
| 39 | static const struct csc_table csc_table_deepcolor[] = { |
| 40 | /* HDMI_DEEP_COLOR_24BIT */ |
| 41 | [0] = { 7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32, }, |
| 42 | /* HDMI_DEEP_COLOR_30BIT */ |
| 43 | [1] = { 7015, 0, 0, 128, 0, 7015, 0, 128, 0, 0, 7015, 128, }, |
| 44 | /* HDMI_DEEP_COLOR_36BIT */ |
| 45 | [2] = { 7010, 0, 0, 512, 0, 7010, 0, 512, 0, 0, 7010, 512, }, |
| 46 | /* FULL RANGE */ |
| 47 | [3] = { 8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0, }, |
| 48 | }; |
| 49 | |
| 50 | static void hdmi_core_ddc_init(struct hdmi_core_data *core) |
| 51 | { |
| 52 | void __iomem *base = core->base; |
| 53 | const unsigned long long iclk = 266000000; /* DSS L3 ICLK */ |
| 54 | const unsigned ss_scl_high = 4000; /* ns */ |
| 55 | const unsigned ss_scl_low = 4700; /* ns */ |
| 56 | const unsigned fs_scl_high = 600; /* ns */ |
| 57 | const unsigned fs_scl_low = 1300; /* ns */ |
| 58 | const unsigned sda_hold = 1000; /* ns */ |
| 59 | const unsigned sfr_div = 10; |
| 60 | unsigned long long sfr; |
| 61 | unsigned v; |
| 62 | |
| 63 | sfr = iclk / sfr_div; /* SFR_DIV */ |
| 64 | sfr /= 1000; /* SFR clock in kHz */ |
| 65 | |
| 66 | /* Reset */ |
| 67 | REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); |
| 68 | if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ, |
| 69 | 0, 0, 1) != 1) |
| 70 | DSSERR("HDMI I2CM reset failed\n"); |
| 71 | |
| 72 | /* Standard (0) or Fast (1) Mode */ |
| 73 | REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); |
| 74 | |
| 75 | /* Standard Mode SCL High counter */ |
| 76 | v = DIV_ROUND_UP_ULL(ss_scl_high * sfr, 1000000); |
| 77 | REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, |
| 78 | (v >> 8) & 0xff, 7, 0); |
| 79 | REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, |
| 80 | v & 0xff, 7, 0); |
| 81 | |
| 82 | /* Standard Mode SCL Low counter */ |
| 83 | v = DIV_ROUND_UP_ULL(ss_scl_low * sfr, 1000000); |
| 84 | REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, |
| 85 | (v >> 8) & 0xff, 7, 0); |
| 86 | REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, |
| 87 | v & 0xff, 7, 0); |
| 88 | |
| 89 | /* Fast Mode SCL High Counter */ |
| 90 | v = DIV_ROUND_UP_ULL(fs_scl_high * sfr, 1000000); |
| 91 | REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR, |
| 92 | (v >> 8) & 0xff, 7, 0); |
| 93 | REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR, |
| 94 | v & 0xff, 7, 0); |
| 95 | |
| 96 | /* Fast Mode SCL Low Counter */ |
| 97 | v = DIV_ROUND_UP_ULL(fs_scl_low * sfr, 1000000); |
| 98 | REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR, |
| 99 | (v >> 8) & 0xff, 7, 0); |
| 100 | REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR, |
| 101 | v & 0xff, 7, 0); |
| 102 | |
| 103 | /* SDA Hold Time */ |
| 104 | v = DIV_ROUND_UP_ULL(sda_hold * sfr, 1000000); |
| 105 | REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0); |
| 106 | |
| 107 | REG_FLD_MOD(base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0); |
| 108 | REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0); |
| 109 | |
| 110 | /* NACK_POL to high */ |
| 111 | REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 7, 7); |
| 112 | |
| 113 | /* NACK_MASK to unmasked */ |
| 114 | REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6); |
| 115 | |
| 116 | /* ARBITRATION_POL to high */ |
| 117 | REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 3, 3); |
| 118 | |
| 119 | /* ARBITRATION_MASK to unmasked */ |
| 120 | REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2); |
| 121 | |
| 122 | /* DONE_POL to high */ |
| 123 | REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3); |
| 124 | |
| 125 | /* DONE_MASK to unmasked */ |
| 126 | REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2); |
| 127 | } |
| 128 | |
| 129 | static void hdmi_core_ddc_uninit(struct hdmi_core_data *core) |
| 130 | { |
| 131 | void __iomem *base = core->base; |
| 132 | |
| 133 | /* Mask I2C interrupts */ |
| 134 | REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6); |
| 135 | REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2); |
| 136 | REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2); |
| 137 | } |
| 138 | |
| 139 | static int hdmi_core_ddc_edid(struct hdmi_core_data *core, u8 *pedid, u8 ext) |
| 140 | { |
| 141 | void __iomem *base = core->base; |
| 142 | u8 cur_addr; |
| 143 | char checksum = 0; |
| 144 | const int retries = 1000; |
| 145 | u8 seg_ptr = ext / 2; |
| 146 | u8 edidbase = ((ext % 2) * 0x80); |
| 147 | |
| 148 | REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0); |
| 149 | |
| 150 | /* |
| 151 | * TODO: We use polling here, although we probably should use proper |
| 152 | * interrupts. |
| 153 | */ |
| 154 | for (cur_addr = 0; cur_addr < 128; ++cur_addr) { |
| 155 | int i; |
| 156 | |
| 157 | /* clear ERROR and DONE */ |
| 158 | REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0); |
| 159 | |
| 160 | REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS, |
| 161 | edidbase + cur_addr, 7, 0); |
| 162 | |
| 163 | if (seg_ptr) |
| 164 | REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 1, 1); |
| 165 | else |
| 166 | REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0); |
| 167 | |
| 168 | for (i = 0; i < retries; ++i) { |
| 169 | u32 stat; |
| 170 | |
| 171 | stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0); |
| 172 | |
| 173 | /* I2CM_ERROR */ |
| 174 | if (stat & 1) { |
| 175 | DSSERR("HDMI I2C Master Error\n"); |
| 176 | return -EIO; |
| 177 | } |
| 178 | |
| 179 | /* I2CM_DONE */ |
| 180 | if (stat & (1 << 1)) |
| 181 | break; |
| 182 | |
| 183 | usleep_range(250, 1000); |
| 184 | } |
| 185 | |
| 186 | if (i == retries) { |
| 187 | DSSERR("HDMI I2C timeout reading EDID\n"); |
| 188 | return -EIO; |
| 189 | } |
| 190 | |
| 191 | pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0); |
| 192 | checksum += pedid[cur_addr]; |
| 193 | } |
| 194 | |
| 195 | return 0; |
| 196 | |
| 197 | } |
| 198 | |
| 199 | int hdmi5_read_edid(struct hdmi_core_data *core, u8 *edid, int len) |
| 200 | { |
| 201 | int r, n, i; |
| 202 | int max_ext_blocks = (len / 128) - 1; |
| 203 | |
| 204 | if (len < 128) |
| 205 | return -EINVAL; |
| 206 | |
| 207 | hdmi_core_ddc_init(core); |
| 208 | |
| 209 | r = hdmi_core_ddc_edid(core, edid, 0); |
| 210 | if (r) |
| 211 | goto out; |
| 212 | |
| 213 | n = edid[0x7e]; |
| 214 | |
| 215 | if (n > max_ext_blocks) |
| 216 | n = max_ext_blocks; |
| 217 | |
| 218 | for (i = 1; i <= n; i++) { |
| 219 | r = hdmi_core_ddc_edid(core, edid + i * EDID_LENGTH, i); |
| 220 | if (r) |
| 221 | goto out; |
| 222 | } |
| 223 | |
| 224 | out: |
| 225 | hdmi_core_ddc_uninit(core); |
| 226 | |
| 227 | return r ? r : len; |
| 228 | } |
| 229 | |
| 230 | void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s) |
| 231 | { |
| 232 | |
| 233 | #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\ |
| 234 | hdmi_read_reg(core->base, r)) |
| 235 | |
| 236 | DUMPCORE(HDMI_CORE_FC_INVIDCONF); |
| 237 | DUMPCORE(HDMI_CORE_FC_INHACTIV0); |
| 238 | DUMPCORE(HDMI_CORE_FC_INHACTIV1); |
| 239 | DUMPCORE(HDMI_CORE_FC_INHBLANK0); |
| 240 | DUMPCORE(HDMI_CORE_FC_INHBLANK1); |
| 241 | DUMPCORE(HDMI_CORE_FC_INVACTIV0); |
| 242 | DUMPCORE(HDMI_CORE_FC_INVACTIV1); |
| 243 | DUMPCORE(HDMI_CORE_FC_INVBLANK); |
| 244 | DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY0); |
| 245 | DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY1); |
| 246 | DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH0); |
| 247 | DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH1); |
| 248 | DUMPCORE(HDMI_CORE_FC_VSYNCINDELAY); |
| 249 | DUMPCORE(HDMI_CORE_FC_VSYNCINWIDTH); |
| 250 | DUMPCORE(HDMI_CORE_FC_CTRLDUR); |
| 251 | DUMPCORE(HDMI_CORE_FC_EXCTRLDUR); |
| 252 | DUMPCORE(HDMI_CORE_FC_EXCTRLSPAC); |
| 253 | DUMPCORE(HDMI_CORE_FC_CH0PREAM); |
| 254 | DUMPCORE(HDMI_CORE_FC_CH1PREAM); |
| 255 | DUMPCORE(HDMI_CORE_FC_CH2PREAM); |
| 256 | DUMPCORE(HDMI_CORE_FC_AVICONF0); |
| 257 | DUMPCORE(HDMI_CORE_FC_AVICONF1); |
| 258 | DUMPCORE(HDMI_CORE_FC_AVICONF2); |
| 259 | DUMPCORE(HDMI_CORE_FC_AVIVID); |
| 260 | DUMPCORE(HDMI_CORE_FC_PRCONF); |
| 261 | |
| 262 | DUMPCORE(HDMI_CORE_MC_CLKDIS); |
| 263 | DUMPCORE(HDMI_CORE_MC_SWRSTZREQ); |
| 264 | DUMPCORE(HDMI_CORE_MC_FLOWCTRL); |
| 265 | DUMPCORE(HDMI_CORE_MC_PHYRSTZ); |
| 266 | DUMPCORE(HDMI_CORE_MC_LOCKONCLOCK); |
| 267 | |
| 268 | DUMPCORE(HDMI_CORE_I2CM_SLAVE); |
| 269 | DUMPCORE(HDMI_CORE_I2CM_ADDRESS); |
| 270 | DUMPCORE(HDMI_CORE_I2CM_DATAO); |
| 271 | DUMPCORE(HDMI_CORE_I2CM_DATAI); |
| 272 | DUMPCORE(HDMI_CORE_I2CM_OPERATION); |
| 273 | DUMPCORE(HDMI_CORE_I2CM_INT); |
| 274 | DUMPCORE(HDMI_CORE_I2CM_CTLINT); |
| 275 | DUMPCORE(HDMI_CORE_I2CM_DIV); |
| 276 | DUMPCORE(HDMI_CORE_I2CM_SEGADDR); |
| 277 | DUMPCORE(HDMI_CORE_I2CM_SOFTRSTZ); |
| 278 | DUMPCORE(HDMI_CORE_I2CM_SEGPTR); |
| 279 | DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR); |
| 280 | DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR); |
| 281 | DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR); |
| 282 | DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR); |
| 283 | DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR); |
| 284 | DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR); |
| 285 | DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR); |
| 286 | DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR); |
| 287 | DUMPCORE(HDMI_CORE_I2CM_SDA_HOLD_ADDR); |
| 288 | } |
| 289 | |
| 290 | static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg, |
| 291 | struct hdmi_config *cfg) |
| 292 | { |
| 293 | DSSDBG("hdmi_core_init\n"); |
| 294 | |
| 295 | video_cfg->v_fc_config.timings = cfg->timings; |
| 296 | |
| 297 | /* video core */ |
| 298 | video_cfg->data_enable_pol = 1; /* It is always 1*/ |
| 299 | video_cfg->hblank = cfg->timings.hfp + |
| 300 | cfg->timings.hbp + cfg->timings.hsw; |
| 301 | video_cfg->vblank_osc = 0; |
| 302 | video_cfg->vblank = cfg->timings.vsw + |
| 303 | cfg->timings.vfp + cfg->timings.vbp; |
| 304 | video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode; |
| 305 | |
| 306 | if (cfg->timings.interlace) { |
| 307 | /* set vblank_osc if vblank is fractional */ |
| 308 | if (video_cfg->vblank % 2 != 0) |
| 309 | video_cfg->vblank_osc = 1; |
| 310 | |
| 311 | video_cfg->v_fc_config.timings.y_res /= 2; |
| 312 | video_cfg->vblank /= 2; |
| 313 | video_cfg->v_fc_config.timings.vfp /= 2; |
| 314 | video_cfg->v_fc_config.timings.vsw /= 2; |
| 315 | video_cfg->v_fc_config.timings.vbp /= 2; |
| 316 | } |
| 317 | |
| 318 | if (cfg->timings.double_pixel) { |
| 319 | video_cfg->v_fc_config.timings.x_res *= 2; |
| 320 | video_cfg->hblank *= 2; |
| 321 | video_cfg->v_fc_config.timings.hfp *= 2; |
| 322 | video_cfg->v_fc_config.timings.hsw *= 2; |
| 323 | video_cfg->v_fc_config.timings.hbp *= 2; |
| 324 | } |
| 325 | } |
| 326 | |
| 327 | /* DSS_HDMI_CORE_VIDEO_CONFIG */ |
| 328 | static void hdmi_core_video_config(struct hdmi_core_data *core, |
| 329 | struct hdmi_core_vid_config *cfg) |
| 330 | { |
| 331 | void __iomem *base = core->base; |
| 332 | unsigned char r = 0; |
| 333 | bool vsync_pol, hsync_pol; |
| 334 | |
| 335 | vsync_pol = |
| 336 | cfg->v_fc_config.timings.vsync_level == OMAPDSS_SIG_ACTIVE_HIGH; |
| 337 | hsync_pol = |
| 338 | cfg->v_fc_config.timings.hsync_level == OMAPDSS_SIG_ACTIVE_HIGH; |
| 339 | |
| 340 | /* Set hsync, vsync and data-enable polarity */ |
| 341 | r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF); |
| 342 | r = FLD_MOD(r, vsync_pol, 6, 6); |
| 343 | r = FLD_MOD(r, hsync_pol, 5, 5); |
| 344 | r = FLD_MOD(r, cfg->data_enable_pol, 4, 4); |
| 345 | r = FLD_MOD(r, cfg->vblank_osc, 1, 1); |
| 346 | r = FLD_MOD(r, cfg->v_fc_config.timings.interlace, 0, 0); |
| 347 | hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r); |
| 348 | |
| 349 | /* set x resolution */ |
| 350 | REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1, |
| 351 | cfg->v_fc_config.timings.x_res >> 8, 4, 0); |
| 352 | REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0, |
| 353 | cfg->v_fc_config.timings.x_res & 0xFF, 7, 0); |
| 354 | |
| 355 | /* set y resolution */ |
| 356 | REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1, |
| 357 | cfg->v_fc_config.timings.y_res >> 8, 4, 0); |
| 358 | REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0, |
| 359 | cfg->v_fc_config.timings.y_res & 0xFF, 7, 0); |
| 360 | |
| 361 | /* set horizontal blanking pixels */ |
| 362 | REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0); |
| 363 | REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK0, cfg->hblank & 0xFF, 7, 0); |
| 364 | |
| 365 | /* set vertial blanking pixels */ |
| 366 | REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0); |
| 367 | |
| 368 | /* set horizontal sync offset */ |
| 369 | REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1, |
| 370 | cfg->v_fc_config.timings.hfp >> 8, 4, 0); |
| 371 | REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0, |
| 372 | cfg->v_fc_config.timings.hfp & 0xFF, 7, 0); |
| 373 | |
| 374 | /* set vertical sync offset */ |
| 375 | REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY, |
| 376 | cfg->v_fc_config.timings.vfp, 7, 0); |
| 377 | |
| 378 | /* set horizontal sync pulse width */ |
| 379 | REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1, |
| 380 | (cfg->v_fc_config.timings.hsw >> 8), 1, 0); |
| 381 | REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0, |
| 382 | cfg->v_fc_config.timings.hsw & 0xFF, 7, 0); |
| 383 | |
| 384 | /* set vertical sync pulse width */ |
| 385 | REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH, |
| 386 | cfg->v_fc_config.timings.vsw, 5, 0); |
| 387 | |
| 388 | /* select DVI mode */ |
| 389 | REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF, |
| 390 | cfg->v_fc_config.hdmi_dvi_mode, 3, 3); |
| 391 | |
| 392 | if (cfg->v_fc_config.timings.double_pixel) |
| 393 | REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 2, 7, 4); |
| 394 | else |
| 395 | REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 1, 7, 4); |
| 396 | } |
| 397 | |
| 398 | static void hdmi_core_config_video_packetizer(struct hdmi_core_data *core) |
| 399 | { |
| 400 | void __iomem *base = core->base; |
| 401 | int clr_depth = 0; /* 24 bit color depth */ |
| 402 | |
| 403 | /* COLOR_DEPTH */ |
| 404 | REG_FLD_MOD(base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4); |
| 405 | /* BYPASS_EN */ |
| 406 | REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6); |
| 407 | /* PP_EN */ |
| 408 | REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5); |
| 409 | /* YCC422_EN */ |
| 410 | REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3); |
| 411 | /* PP_STUFFING */ |
| 412 | REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1); |
| 413 | /* YCC422_STUFFING */ |
| 414 | REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2); |
| 415 | /* OUTPUT_SELECTOR */ |
| 416 | REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0); |
| 417 | } |
| 418 | |
| 419 | static void hdmi_core_config_csc(struct hdmi_core_data *core) |
| 420 | { |
| 421 | int clr_depth = 0; /* 24 bit color depth */ |
| 422 | |
| 423 | /* CSC_COLORDEPTH */ |
| 424 | REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4); |
| 425 | } |
| 426 | |
| 427 | static void hdmi_core_config_video_sampler(struct hdmi_core_data *core) |
| 428 | { |
| 429 | int video_mapping = 1; /* for 24 bit color depth */ |
| 430 | |
| 431 | /* VIDEO_MAPPING */ |
| 432 | REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0); |
| 433 | } |
| 434 | |
| 435 | static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core, |
| 436 | struct hdmi_avi_infoframe *frame) |
| 437 | { |
| 438 | void __iomem *base = core->base; |
| 439 | u8 data[HDMI_INFOFRAME_SIZE(AVI)]; |
| 440 | u8 *ptr; |
| 441 | unsigned y, a, b, s; |
| 442 | unsigned c, m, r; |
| 443 | unsigned itc, ec, q, sc; |
| 444 | unsigned vic; |
| 445 | unsigned yq, cn, pr; |
| 446 | |
| 447 | hdmi_avi_infoframe_pack(frame, data, sizeof(data)); |
| 448 | |
| 449 | print_hex_dump_debug("AVI: ", DUMP_PREFIX_NONE, 16, 1, data, |
| 450 | HDMI_INFOFRAME_SIZE(AVI), false); |
| 451 | |
| 452 | ptr = data + HDMI_INFOFRAME_HEADER_SIZE; |
| 453 | |
| 454 | y = (ptr[0] >> 5) & 0x3; |
| 455 | a = (ptr[0] >> 4) & 0x1; |
| 456 | b = (ptr[0] >> 2) & 0x3; |
| 457 | s = (ptr[0] >> 0) & 0x3; |
| 458 | |
| 459 | c = (ptr[1] >> 6) & 0x3; |
| 460 | m = (ptr[1] >> 4) & 0x3; |
| 461 | r = (ptr[1] >> 0) & 0xf; |
| 462 | |
| 463 | itc = (ptr[2] >> 7) & 0x1; |
| 464 | ec = (ptr[2] >> 4) & 0x7; |
| 465 | q = (ptr[2] >> 2) & 0x3; |
| 466 | sc = (ptr[2] >> 0) & 0x3; |
| 467 | |
| 468 | vic = ptr[3]; |
| 469 | |
| 470 | yq = (ptr[4] >> 6) & 0x3; |
| 471 | cn = (ptr[4] >> 4) & 0x3; |
| 472 | pr = (ptr[4] >> 0) & 0xf; |
| 473 | |
| 474 | hdmi_write_reg(base, HDMI_CORE_FC_AVICONF0, |
| 475 | (a << 6) | (s << 4) | (b << 2) | (y << 0)); |
| 476 | |
| 477 | hdmi_write_reg(base, HDMI_CORE_FC_AVICONF1, |
| 478 | (c << 6) | (m << 4) | (r << 0)); |
| 479 | |
| 480 | hdmi_write_reg(base, HDMI_CORE_FC_AVICONF2, |
| 481 | (itc << 7) | (ec << 4) | (q << 2) | (sc << 0)); |
| 482 | |
| 483 | hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic); |
| 484 | |
| 485 | hdmi_write_reg(base, HDMI_CORE_FC_AVICONF3, |
| 486 | (yq << 2) | (cn << 0)); |
| 487 | |
| 488 | REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0); |
| 489 | } |
| 490 | |
| 491 | static void hdmi_core_csc_config(struct hdmi_core_data *core, |
| 492 | struct csc_table csc_coeff) |
| 493 | { |
| 494 | void __iomem *base = core->base; |
| 495 | |
| 496 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff.a1 >> 8 , 6, 0); |
| 497 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff.a1, 7, 0); |
| 498 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff.a2 >> 8, 6, 0); |
| 499 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff.a2, 7, 0); |
| 500 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff.a3 >> 8, 6, 0); |
| 501 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff.a3, 7, 0); |
| 502 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff.a4 >> 8, 6, 0); |
| 503 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff.a4, 7, 0); |
| 504 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff.b1 >> 8, 6, 0); |
| 505 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff.b1, 7, 0); |
| 506 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff.b2 >> 8, 6, 0); |
| 507 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff.b2, 7, 0); |
| 508 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff.b3 >> 8, 6, 0); |
| 509 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff.b3, 7, 0); |
| 510 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff.b4 >> 8, 6, 0); |
| 511 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff.b4, 7, 0); |
| 512 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff.c1 >> 8, 6, 0); |
| 513 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff.c1, 7, 0); |
| 514 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff.c2 >> 8, 6, 0); |
| 515 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff.c2, 7, 0); |
| 516 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff.c3 >> 8, 6, 0); |
| 517 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff.c3, 7, 0); |
| 518 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0); |
| 519 | REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0); |
| 520 | |
| 521 | REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0); |
| 522 | } |
| 523 | |
| 524 | static void hdmi_core_configure_range(struct hdmi_core_data *core) |
| 525 | { |
| 526 | struct csc_table csc_coeff = { 0 }; |
| 527 | |
| 528 | /* support limited range with 24 bit color depth for now */ |
| 529 | csc_coeff = csc_table_deepcolor[0]; |
| 530 | |
| 531 | hdmi_core_csc_config(core, csc_coeff); |
| 532 | } |
| 533 | |
| 534 | static void hdmi_core_enable_video_path(struct hdmi_core_data *core) |
| 535 | { |
| 536 | void __iomem *base = core->base; |
| 537 | |
| 538 | DSSDBG("hdmi_core_enable_video_path\n"); |
| 539 | |
| 540 | REG_FLD_MOD(base, HDMI_CORE_FC_CTRLDUR, 0x0C, 7, 0); |
| 541 | REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLDUR, 0x20, 7, 0); |
| 542 | REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLSPAC, 0x01, 7, 0); |
| 543 | REG_FLD_MOD(base, HDMI_CORE_FC_CH0PREAM, 0x0B, 7, 0); |
| 544 | REG_FLD_MOD(base, HDMI_CORE_FC_CH1PREAM, 0x16, 5, 0); |
| 545 | REG_FLD_MOD(base, HDMI_CORE_FC_CH2PREAM, 0x21, 5, 0); |
| 546 | REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 0, 0); |
| 547 | REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 1, 1); |
| 548 | } |
| 549 | |
| 550 | static void hdmi_core_mask_interrupts(struct hdmi_core_data *core) |
| 551 | { |
| 552 | void __iomem *base = core->base; |
| 553 | |
| 554 | /* Master IRQ mask */ |
| 555 | REG_FLD_MOD(base, HDMI_CORE_IH_MUTE, 0x3, 1, 0); |
| 556 | |
| 557 | /* Mask all the interrupts in HDMI core */ |
| 558 | |
| 559 | REG_FLD_MOD(base, HDMI_CORE_VP_MASK, 0xff, 7, 0); |
| 560 | REG_FLD_MOD(base, HDMI_CORE_FC_MASK0, 0xe7, 7, 0); |
| 561 | REG_FLD_MOD(base, HDMI_CORE_FC_MASK1, 0xfb, 7, 0); |
| 562 | REG_FLD_MOD(base, HDMI_CORE_FC_MASK2, 0x3, 1, 0); |
| 563 | |
| 564 | REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 0x3, 3, 2); |
| 565 | REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 0x3, 1, 0); |
| 566 | |
| 567 | REG_FLD_MOD(base, HDMI_CORE_CEC_MASK, 0x7f, 6, 0); |
| 568 | |
| 569 | REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6); |
| 570 | REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2); |
| 571 | REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2); |
| 572 | |
| 573 | REG_FLD_MOD(base, HDMI_CORE_PHY_MASK0, 0xf3, 7, 0); |
| 574 | |
| 575 | REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); |
| 576 | |
| 577 | /* Clear all the current interrupt bits */ |
| 578 | |
| 579 | REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0); |
| 580 | REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xe7, 7, 0); |
| 581 | REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xfb, 7, 0); |
| 582 | REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0x3, 1, 0); |
| 583 | |
| 584 | REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0x7, 2, 0); |
| 585 | |
| 586 | REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0x7f, 6, 0); |
| 587 | |
| 588 | REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0); |
| 589 | |
| 590 | REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); |
| 591 | } |
| 592 | |
| 593 | static void hdmi_core_enable_interrupts(struct hdmi_core_data *core) |
| 594 | { |
| 595 | /* Unmute interrupts */ |
| 596 | REG_FLD_MOD(core->base, HDMI_CORE_IH_MUTE, 0x0, 1, 0); |
| 597 | } |
| 598 | |
| 599 | int hdmi5_core_handle_irqs(struct hdmi_core_data *core) |
| 600 | { |
| 601 | void __iomem *base = core->base; |
| 602 | |
| 603 | REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xff, 7, 0); |
| 604 | REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xff, 7, 0); |
| 605 | REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0xff, 7, 0); |
| 606 | REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0xff, 7, 0); |
| 607 | REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); |
| 608 | REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0xff, 7, 0); |
| 609 | REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0xff, 7, 0); |
| 610 | REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0); |
| 611 | REG_FLD_MOD(base, HDMI_CORE_IH_I2CMPHY_STAT0, 0xff, 7, 0); |
| 612 | |
| 613 | return 0; |
| 614 | } |
| 615 | |
| 616 | void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, |
| 617 | struct hdmi_config *cfg) |
| 618 | { |
| 619 | struct omap_video_timings video_timing; |
| 620 | struct hdmi_video_format video_format; |
| 621 | struct hdmi_core_vid_config v_core_cfg; |
| 622 | |
| 623 | hdmi_core_mask_interrupts(core); |
| 624 | |
| 625 | hdmi_core_init(&v_core_cfg, cfg); |
| 626 | |
| 627 | hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg); |
| 628 | |
| 629 | hdmi_wp_video_config_timing(wp, &video_timing); |
| 630 | |
| 631 | /* video config */ |
| 632 | video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; |
| 633 | |
| 634 | hdmi_wp_video_config_format(wp, &video_format); |
| 635 | |
| 636 | hdmi_wp_video_config_interface(wp, &video_timing); |
| 637 | |
| 638 | /* support limited range with 24 bit color depth for now */ |
| 639 | hdmi_core_configure_range(core); |
| 640 | cfg->infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_LIMITED; |
| 641 | |
| 642 | /* |
| 643 | * configure core video part, set software reset in the core |
| 644 | */ |
| 645 | v_core_cfg.packet_mode = HDMI_PACKETMODE24BITPERPIXEL; |
| 646 | |
| 647 | hdmi_core_video_config(core, &v_core_cfg); |
| 648 | |
| 649 | hdmi_core_config_video_packetizer(core); |
| 650 | hdmi_core_config_csc(core); |
| 651 | hdmi_core_config_video_sampler(core); |
| 652 | |
| 653 | if (cfg->hdmi_dvi_mode == HDMI_HDMI) |
| 654 | hdmi_core_write_avi_infoframe(core, &cfg->infoframe); |
| 655 | |
| 656 | hdmi_core_enable_video_path(core); |
| 657 | |
| 658 | hdmi_core_enable_interrupts(core); |
| 659 | } |
| 660 | |
| 661 | static void hdmi5_core_audio_config(struct hdmi_core_data *core, |
| 662 | struct hdmi_core_audio_config *cfg) |
| 663 | { |
| 664 | void __iomem *base = core->base; |
| 665 | u8 val; |
| 666 | |
| 667 | /* Mute audio before configuring */ |
| 668 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0xf, 7, 4); |
| 669 | |
| 670 | /* Set the N parameter */ |
| 671 | REG_FLD_MOD(base, HDMI_CORE_AUD_N1, cfg->n, 7, 0); |
| 672 | REG_FLD_MOD(base, HDMI_CORE_AUD_N2, cfg->n >> 8, 7, 0); |
| 673 | REG_FLD_MOD(base, HDMI_CORE_AUD_N3, cfg->n >> 16, 3, 0); |
| 674 | |
| 675 | /* |
| 676 | * CTS manual mode. Automatic mode is not supported when using audio |
| 677 | * parallel interface. |
| 678 | */ |
| 679 | REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, 1, 4, 4); |
| 680 | REG_FLD_MOD(base, HDMI_CORE_AUD_CTS1, cfg->cts, 7, 0); |
| 681 | REG_FLD_MOD(base, HDMI_CORE_AUD_CTS2, cfg->cts >> 8, 7, 0); |
| 682 | REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, cfg->cts >> 16, 3, 0); |
| 683 | |
| 684 | /* Layout of Audio Sample Packets: 2-channel or multichannels */ |
| 685 | if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) |
| 686 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 0, 0); |
| 687 | else |
| 688 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 1, 0, 0); |
| 689 | |
| 690 | /* Configure IEC-609580 Validity bits */ |
| 691 | /* Channel 0 is valid */ |
| 692 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 0, 0); |
| 693 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 4, 4); |
| 694 | |
| 695 | if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) |
| 696 | val = 1; |
| 697 | else |
| 698 | val = 0; |
| 699 | |
| 700 | /* Channels 1, 2 setting */ |
| 701 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1); |
| 702 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5); |
| 703 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2); |
| 704 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6); |
| 705 | /* Channel 3 setting */ |
| 706 | if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH) |
| 707 | val = 1; |
| 708 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3); |
| 709 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7); |
| 710 | |
| 711 | /* Configure IEC-60958 User bits */ |
| 712 | /* TODO: should be set by user. */ |
| 713 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSU, 0, 7, 0); |
| 714 | |
| 715 | /* Configure IEC-60958 Channel Status word */ |
| 716 | /* CGMSA */ |
| 717 | val = cfg->iec60958_cfg->status[5] & IEC958_AES5_CON_CGMSA; |
| 718 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4); |
| 719 | |
| 720 | /* Copyright */ |
| 721 | val = (cfg->iec60958_cfg->status[0] & |
| 722 | IEC958_AES0_CON_NOT_COPYRIGHT) >> 2; |
| 723 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0); |
| 724 | |
| 725 | /* Category */ |
| 726 | hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(1), |
| 727 | cfg->iec60958_cfg->status[1]); |
| 728 | |
| 729 | /* PCM audio mode */ |
| 730 | val = (cfg->iec60958_cfg->status[0] & IEC958_AES0_CON_MODE) >> 6; |
| 731 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4); |
| 732 | |
| 733 | /* Source number */ |
| 734 | val = cfg->iec60958_cfg->status[2] & IEC958_AES2_CON_SOURCE; |
| 735 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 0); |
| 736 | |
| 737 | /* Channel number right 0 */ |
| 738 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0); |
| 739 | /* Channel number right 1*/ |
| 740 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 4, 7, 4); |
| 741 | /* Channel number right 2 */ |
| 742 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 6, 3, 0); |
| 743 | /* Channel number right 3*/ |
| 744 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 8, 7, 4); |
| 745 | /* Channel number left 0 */ |
| 746 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 1, 3, 0); |
| 747 | /* Channel number left 1*/ |
| 748 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 3, 7, 4); |
| 749 | /* Channel number left 2 */ |
| 750 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 5, 3, 0); |
| 751 | /* Channel number left 3*/ |
| 752 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 7, 7, 4); |
| 753 | |
| 754 | /* Clock accuracy and sample rate */ |
| 755 | hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(7), |
| 756 | cfg->iec60958_cfg->status[3]); |
| 757 | |
| 758 | /* Original sample rate and word length */ |
| 759 | hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(8), |
| 760 | cfg->iec60958_cfg->status[4]); |
| 761 | |
| 762 | /* Enable FIFO empty and full interrupts */ |
| 763 | REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 3, 3, 2); |
| 764 | |
| 765 | /* Configure GPA */ |
| 766 | /* select HBR/SPDIF interfaces */ |
| 767 | if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) { |
| 768 | /* select HBR/SPDIF interfaces */ |
| 769 | REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); |
| 770 | /* enable two channels in GPA */ |
| 771 | REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 3, 7, 0); |
| 772 | } else if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH) { |
| 773 | /* select HBR/SPDIF interfaces */ |
| 774 | REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); |
| 775 | /* enable six channels in GPA */ |
| 776 | REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0x3F, 7, 0); |
| 777 | } else { |
| 778 | /* select HBR/SPDIF interfaces */ |
| 779 | REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); |
| 780 | /* enable eight channels in GPA */ |
| 781 | REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0xFF, 7, 0); |
| 782 | } |
| 783 | |
| 784 | /* disable HBR */ |
| 785 | REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 0, 0, 0); |
| 786 | /* enable PCUV */ |
| 787 | REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 1, 1, 1); |
| 788 | /* enable GPA FIFO full and empty mask */ |
| 789 | REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 3, 1, 0); |
| 790 | /* set polarity of GPA FIFO empty interrupts */ |
| 791 | REG_FLD_MOD(base, HDMI_CORE_AUD_GP_POL, 1, 0, 0); |
| 792 | |
| 793 | /* unmute audio */ |
| 794 | REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 7, 4); |
| 795 | } |
| 796 | |
| 797 | static void hdmi5_core_audio_infoframe_cfg(struct hdmi_core_data *core, |
| 798 | struct snd_cea_861_aud_if *info_aud) |
| 799 | { |
| 800 | void __iomem *base = core->base; |
| 801 | |
| 802 | /* channel count and coding type fields in AUDICONF0 are swapped */ |
| 803 | hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF0, |
| 804 | (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC) << 4 | |
| 805 | (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CT) >> 4); |
| 806 | |
| 807 | hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF1, info_aud->db2_sf_ss); |
| 808 | hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF2, info_aud->db4_ca); |
| 809 | hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF3, |
| 810 | (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_DM_INH) >> 3 | |
| 811 | (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_LSV)); |
| 812 | } |
| 813 | |
| 814 | int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, |
| 815 | struct omap_dss_audio *audio, u32 pclk) |
| 816 | { |
| 817 | struct hdmi_audio_format audio_format; |
| 818 | struct hdmi_audio_dma audio_dma; |
| 819 | struct hdmi_core_audio_config core_cfg; |
| 820 | int err, n, cts, channel_count; |
| 821 | unsigned int fs_nr; |
| 822 | bool word_length_16b = false; |
| 823 | |
| 824 | if (!audio || !audio->iec || !audio->cea || !core) |
| 825 | return -EINVAL; |
| 826 | |
| 827 | core_cfg.iec60958_cfg = audio->iec; |
| 828 | |
| 829 | if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) && |
| 830 | (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16)) |
| 831 | word_length_16b = true; |
| 832 | |
| 833 | /* only 16-bit word length supported atm */ |
| 834 | if (!word_length_16b) |
| 835 | return -EINVAL; |
| 836 | |
| 837 | switch (audio->iec->status[3] & IEC958_AES3_CON_FS) { |
| 838 | case IEC958_AES3_CON_FS_32000: |
| 839 | fs_nr = 32000; |
| 840 | break; |
| 841 | case IEC958_AES3_CON_FS_44100: |
| 842 | fs_nr = 44100; |
| 843 | break; |
| 844 | case IEC958_AES3_CON_FS_48000: |
| 845 | fs_nr = 48000; |
| 846 | break; |
| 847 | case IEC958_AES3_CON_FS_88200: |
| 848 | fs_nr = 88200; |
| 849 | break; |
| 850 | case IEC958_AES3_CON_FS_96000: |
| 851 | fs_nr = 96000; |
| 852 | break; |
| 853 | case IEC958_AES3_CON_FS_176400: |
| 854 | fs_nr = 176400; |
| 855 | break; |
| 856 | case IEC958_AES3_CON_FS_192000: |
| 857 | fs_nr = 192000; |
| 858 | break; |
| 859 | default: |
| 860 | return -EINVAL; |
| 861 | } |
| 862 | |
| 863 | err = hdmi_compute_acr(pclk, fs_nr, &n, &cts); |
| 864 | core_cfg.n = n; |
| 865 | core_cfg.cts = cts; |
| 866 | |
| 867 | /* Audio channels settings */ |
| 868 | channel_count = (audio->cea->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC) |
| 869 | + 1; |
| 870 | |
| 871 | if (channel_count == 2) |
| 872 | core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH; |
| 873 | else if (channel_count == 6) |
| 874 | core_cfg.layout = HDMI_AUDIO_LAYOUT_6CH; |
| 875 | else |
| 876 | core_cfg.layout = HDMI_AUDIO_LAYOUT_8CH; |
| 877 | |
| 878 | /* DMA settings */ |
| 879 | if (word_length_16b) |
| 880 | audio_dma.transfer_size = 0x10; |
| 881 | else |
| 882 | audio_dma.transfer_size = 0x20; |
| 883 | audio_dma.block_size = 0xC0; |
| 884 | audio_dma.mode = HDMI_AUDIO_TRANSF_DMA; |
| 885 | audio_dma.fifo_threshold = 0x20; /* in number of samples */ |
| 886 | |
| 887 | /* audio FIFO format settings for 16-bit samples*/ |
| 888 | audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES; |
| 889 | audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS; |
| 890 | audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT; |
| 891 | audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST; |
| 892 | |
| 893 | /* only LPCM atm */ |
| 894 | audio_format.type = HDMI_AUDIO_TYPE_LPCM; |
| 895 | |
| 896 | /* only allowed option */ |
| 897 | audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST; |
| 898 | |
| 899 | /* disable start/stop signals of IEC 60958 blocks */ |
| 900 | audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON; |
| 901 | |
| 902 | /* configure DMA and audio FIFO format*/ |
| 903 | hdmi_wp_audio_config_dma(wp, &audio_dma); |
| 904 | hdmi_wp_audio_config_format(wp, &audio_format); |
| 905 | |
| 906 | /* configure the core */ |
| 907 | hdmi5_core_audio_config(core, &core_cfg); |
| 908 | |
| 909 | /* configure CEA 861 audio infoframe */ |
| 910 | hdmi5_core_audio_infoframe_cfg(core, audio->cea); |
| 911 | |
| 912 | return 0; |
| 913 | } |
| 914 | |
| 915 | int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core) |
| 916 | { |
| 917 | struct resource *res; |
| 918 | |
| 919 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); |
| 920 | if (!res) { |
| 921 | DSSERR("can't get CORE IORESOURCE_MEM HDMI\n"); |
| 922 | return -EINVAL; |
| 923 | } |
| 924 | |
| 925 | core->base = devm_ioremap_resource(&pdev->dev, res); |
| 926 | if (IS_ERR(core->base)) { |
| 927 | DSSERR("can't ioremap HDMI core\n"); |
| 928 | return PTR_ERR(core->base); |
| 929 | } |
| 930 | |
| 931 | return 0; |
| 932 | } |