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[deliverable/linux.git] / drivers / gpu / drm / radeon / atombios_dp.c
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1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 * Jerome Glisse
26 */
27#include <drm/drmP.h>
28#include <drm/radeon_drm.h>
29#include "radeon.h"
30
31#include "atom.h"
32#include "atom-bits.h"
33#include <drm/drm_dp_helper.h>
34
35/* move these to drm_dp_helper.c/h */
36#define DP_LINK_CONFIGURATION_SIZE 9
37#define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
38
39static char *voltage_names[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
41};
42static char *pre_emph_names[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
44};
45
46/***** radeon AUX functions *****/
47
48/* Atom needs data in little endian format
49 * so swap as appropriate when copying data to
50 * or from atom. Note that atom operates on
51 * dw units.
52 */
53void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
54{
55#ifdef __BIG_ENDIAN
56 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
57 u32 *dst32, *src32;
58 int i;
59
60 memcpy(src_tmp, src, num_bytes);
61 src32 = (u32 *)src_tmp;
62 dst32 = (u32 *)dst_tmp;
63 if (to_le) {
64 for (i = 0; i < ((num_bytes + 3) / 4); i++)
65 dst32[i] = cpu_to_le32(src32[i]);
66 memcpy(dst, dst_tmp, num_bytes);
67 } else {
68 u8 dws = num_bytes & ~3;
69 for (i = 0; i < ((num_bytes + 3) / 4); i++)
70 dst32[i] = le32_to_cpu(src32[i]);
71 memcpy(dst, dst_tmp, dws);
72 if (num_bytes % 4) {
73 for (i = 0; i < (num_bytes % 4); i++)
74 dst[dws+i] = dst_tmp[dws+i];
75 }
76 }
77#else
78 memcpy(dst, src, num_bytes);
79#endif
80}
81
82union aux_channel_transaction {
83 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
84 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
85};
86
87static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
88 u8 *send, int send_bytes,
89 u8 *recv, int recv_size,
90 u8 delay, u8 *ack)
91{
92 struct drm_device *dev = chan->dev;
93 struct radeon_device *rdev = dev->dev_private;
94 union aux_channel_transaction args;
95 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
96 unsigned char *base;
97 int recv_bytes;
98
99 memset(&args, 0, sizeof(args));
100
101 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
102
103 radeon_atom_copy_swap(base, send, send_bytes, true);
104
105 args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
106 args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
107 args.v1.ucDataOutLen = 0;
108 args.v1.ucChannelID = chan->rec.i2c_id;
109 args.v1.ucDelay = delay / 10;
110 if (ASIC_IS_DCE4(rdev))
111 args.v2.ucHPD_ID = chan->rec.hpd;
112
113 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
114
115 *ack = args.v1.ucReplyStatus;
116
117 /* timeout */
118 if (args.v1.ucReplyStatus == 1) {
119 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
120 return -ETIMEDOUT;
121 }
122
123 /* flags not zero */
124 if (args.v1.ucReplyStatus == 2) {
125 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
126 return -EBUSY;
127 }
128
129 /* error */
130 if (args.v1.ucReplyStatus == 3) {
131 DRM_DEBUG_KMS("dp_aux_ch error\n");
132 return -EIO;
133 }
134
135 recv_bytes = args.v1.ucDataOutLen;
136 if (recv_bytes > recv_size)
137 recv_bytes = recv_size;
138
139 if (recv && recv_size)
140 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false);
141
142 return recv_bytes;
143}
144
145#define HEADER_SIZE 4
146
147static ssize_t
148radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
149{
150 struct radeon_i2c_chan *chan =
151 container_of(aux, struct radeon_i2c_chan, aux);
152 int ret;
153 u8 tx_buf[20];
154 size_t tx_size;
155 u8 ack, delay = 0;
156
157 if (WARN_ON(msg->size > 16))
158 return -E2BIG;
159
160 tx_buf[0] = msg->address & 0xff;
161 tx_buf[1] = msg->address >> 8;
162 tx_buf[2] = msg->request << 4;
163 tx_buf[3] = msg->size - 1;
164
165 switch (msg->request & ~DP_AUX_I2C_MOT) {
166 case DP_AUX_NATIVE_WRITE:
167 case DP_AUX_I2C_WRITE:
168 tx_size = HEADER_SIZE + msg->size;
169 tx_buf[3] |= tx_size << 4;
170 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
171 ret = radeon_process_aux_ch(chan,
172 tx_buf, tx_size, NULL, 0, delay, &ack);
173 if (ret >= 0)
174 /* Return payload size. */
175 ret = msg->size;
176 break;
177 case DP_AUX_NATIVE_READ:
178 case DP_AUX_I2C_READ:
179 tx_size = HEADER_SIZE;
180 tx_buf[3] |= tx_size << 4;
181 ret = radeon_process_aux_ch(chan,
182 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
183 break;
184 default:
185 ret = -EINVAL;
186 break;
187 }
188
189 if (ret > 0)
190 msg->reply = ack >> 4;
191
192 return ret;
193}
194
195void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
196{
197 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
198
199 dig_connector->dp_i2c_bus->aux.dev = radeon_connector->base.kdev;
200 dig_connector->dp_i2c_bus->aux.transfer = radeon_dp_aux_transfer;
201}
202
203int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
204 u8 write_byte, u8 *read_byte)
205{
206 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
207 struct radeon_i2c_chan *auxch = i2c_get_adapdata(adapter);
208 u16 address = algo_data->address;
209 u8 msg[5];
210 u8 reply[2];
211 unsigned retry;
212 int msg_bytes;
213 int reply_bytes = 1;
214 int ret;
215 u8 ack;
216
217 /* Set up the address */
218 msg[0] = address;
219 msg[1] = address >> 8;
220
221 /* Set up the command byte */
222 if (mode & MODE_I2C_READ) {
223 msg[2] = DP_AUX_I2C_READ << 4;
224 msg_bytes = 4;
225 msg[3] = msg_bytes << 4;
226 } else {
227 msg[2] = DP_AUX_I2C_WRITE << 4;
228 msg_bytes = 5;
229 msg[3] = msg_bytes << 4;
230 msg[4] = write_byte;
231 }
232
233 /* special handling for start/stop */
234 if (mode & (MODE_I2C_START | MODE_I2C_STOP))
235 msg[3] = 3 << 4;
236
237 /* Set MOT bit for all but stop */
238 if ((mode & MODE_I2C_STOP) == 0)
239 msg[2] |= DP_AUX_I2C_MOT << 4;
240
241 for (retry = 0; retry < 7; retry++) {
242 ret = radeon_process_aux_ch(auxch,
243 msg, msg_bytes, reply, reply_bytes, 0, &ack);
244 if (ret == -EBUSY)
245 continue;
246 else if (ret < 0) {
247 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
248 return ret;
249 }
250
251 switch ((ack >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
252 case DP_AUX_NATIVE_REPLY_ACK:
253 /* I2C-over-AUX Reply field is only valid
254 * when paired with AUX ACK.
255 */
256 break;
257 case DP_AUX_NATIVE_REPLY_NACK:
258 DRM_DEBUG_KMS("aux_ch native nack\n");
259 return -EREMOTEIO;
260 case DP_AUX_NATIVE_REPLY_DEFER:
261 DRM_DEBUG_KMS("aux_ch native defer\n");
262 usleep_range(500, 600);
263 continue;
264 default:
265 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
266 return -EREMOTEIO;
267 }
268
269 switch ((ack >> 4) & DP_AUX_I2C_REPLY_MASK) {
270 case DP_AUX_I2C_REPLY_ACK:
271 if (mode == MODE_I2C_READ)
272 *read_byte = reply[0];
273 return ret;
274 case DP_AUX_I2C_REPLY_NACK:
275 DRM_DEBUG_KMS("aux_i2c nack\n");
276 return -EREMOTEIO;
277 case DP_AUX_I2C_REPLY_DEFER:
278 DRM_DEBUG_KMS("aux_i2c defer\n");
279 usleep_range(400, 500);
280 break;
281 default:
282 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
283 return -EREMOTEIO;
284 }
285 }
286
287 DRM_DEBUG_KMS("aux i2c too many retries, giving up\n");
288 return -EREMOTEIO;
289}
290
291/***** general DP utility functions *****/
292
293#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
294#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
295
296static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
297 int lane_count,
298 u8 train_set[4])
299{
300 u8 v = 0;
301 u8 p = 0;
302 int lane;
303
304 for (lane = 0; lane < lane_count; lane++) {
305 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
306 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
307
308 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
309 lane,
310 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
311 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
312
313 if (this_v > v)
314 v = this_v;
315 if (this_p > p)
316 p = this_p;
317 }
318
319 if (v >= DP_VOLTAGE_MAX)
320 v |= DP_TRAIN_MAX_SWING_REACHED;
321
322 if (p >= DP_PRE_EMPHASIS_MAX)
323 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
324
325 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
326 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
327 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
328
329 for (lane = 0; lane < 4; lane++)
330 train_set[lane] = v | p;
331}
332
333/* convert bits per color to bits per pixel */
334/* get bpc from the EDID */
335static int convert_bpc_to_bpp(int bpc)
336{
337 if (bpc == 0)
338 return 24;
339 else
340 return bpc * 3;
341}
342
343/* get the max pix clock supported by the link rate and lane num */
344static int dp_get_max_dp_pix_clock(int link_rate,
345 int lane_num,
346 int bpp)
347{
348 return (link_rate * lane_num * 8) / bpp;
349}
350
351/***** radeon specific DP functions *****/
352
353/* First get the min lane# when low rate is used according to pixel clock
354 * (prefer low rate), second check max lane# supported by DP panel,
355 * if the max lane# < low rate lane# then use max lane# instead.
356 */
357static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
358 u8 dpcd[DP_DPCD_SIZE],
359 int pix_clock)
360{
361 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
362 int max_link_rate = drm_dp_max_link_rate(dpcd);
363 int max_lane_num = drm_dp_max_lane_count(dpcd);
364 int lane_num;
365 int max_dp_pix_clock;
366
367 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
368 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
369 if (pix_clock <= max_dp_pix_clock)
370 break;
371 }
372
373 return lane_num;
374}
375
376static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
377 u8 dpcd[DP_DPCD_SIZE],
378 int pix_clock)
379{
380 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
381 int lane_num, max_pix_clock;
382
383 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
384 ENCODER_OBJECT_ID_NUTMEG)
385 return 270000;
386
387 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
388 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
389 if (pix_clock <= max_pix_clock)
390 return 162000;
391 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
392 if (pix_clock <= max_pix_clock)
393 return 270000;
394 if (radeon_connector_is_dp12_capable(connector)) {
395 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
396 if (pix_clock <= max_pix_clock)
397 return 540000;
398 }
399
400 return drm_dp_max_link_rate(dpcd);
401}
402
403static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
404 int action, int dp_clock,
405 u8 ucconfig, u8 lane_num)
406{
407 DP_ENCODER_SERVICE_PARAMETERS args;
408 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
409
410 memset(&args, 0, sizeof(args));
411 args.ucLinkClock = dp_clock / 10;
412 args.ucConfig = ucconfig;
413 args.ucAction = action;
414 args.ucLaneNum = lane_num;
415 args.ucStatus = 0;
416
417 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
418 return args.ucStatus;
419}
420
421u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
422{
423 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
424 struct drm_device *dev = radeon_connector->base.dev;
425 struct radeon_device *rdev = dev->dev_private;
426
427 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
428 dig_connector->dp_i2c_bus->rec.i2c_id, 0);
429}
430
431static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
432{
433 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
434 u8 buf[3];
435
436 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
437 return;
438
439 if (drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_SINK_OUI, buf, 3))
440 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
441 buf[0], buf[1], buf[2]);
442
443 if (drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_BRANCH_OUI, buf, 3))
444 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
445 buf[0], buf[1], buf[2]);
446}
447
448bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
449{
450 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
451 u8 msg[DP_DPCD_SIZE];
452 int ret, i;
453
454 ret = drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_DPCD_REV, msg,
455 DP_DPCD_SIZE);
456 if (ret > 0) {
457 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
458 DRM_DEBUG_KMS("DPCD: ");
459 for (i = 0; i < DP_DPCD_SIZE; i++)
460 DRM_DEBUG_KMS("%02x ", msg[i]);
461 DRM_DEBUG_KMS("\n");
462
463 radeon_dp_probe_oui(radeon_connector);
464
465 return true;
466 }
467 dig_connector->dpcd[0] = 0;
468 return false;
469}
470
471int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
472 struct drm_connector *connector)
473{
474 struct drm_device *dev = encoder->dev;
475 struct radeon_device *rdev = dev->dev_private;
476 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
477 struct radeon_connector_atom_dig *dig_connector;
478 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
479 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
480 u8 tmp;
481
482 if (!ASIC_IS_DCE4(rdev))
483 return panel_mode;
484
485 if (!radeon_connector->con_priv)
486 return panel_mode;
487
488 dig_connector = radeon_connector->con_priv;
489
490 if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
491 /* DP bridge chips */
492 drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux,
493 DP_EDP_CONFIGURATION_CAP, &tmp);
494 if (tmp & 1)
495 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
496 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
497 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
498 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
499 else
500 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
501 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
502 /* eDP */
503 drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux,
504 DP_EDP_CONFIGURATION_CAP, &tmp);
505 if (tmp & 1)
506 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
507 }
508
509 return panel_mode;
510}
511
512void radeon_dp_set_link_config(struct drm_connector *connector,
513 const struct drm_display_mode *mode)
514{
515 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
516 struct radeon_connector_atom_dig *dig_connector;
517
518 if (!radeon_connector->con_priv)
519 return;
520 dig_connector = radeon_connector->con_priv;
521
522 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
523 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
524 dig_connector->dp_clock =
525 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
526 dig_connector->dp_lane_count =
527 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
528 }
529}
530
531int radeon_dp_mode_valid_helper(struct drm_connector *connector,
532 struct drm_display_mode *mode)
533{
534 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
535 struct radeon_connector_atom_dig *dig_connector;
536 int dp_clock;
537
538 if (!radeon_connector->con_priv)
539 return MODE_CLOCK_HIGH;
540 dig_connector = radeon_connector->con_priv;
541
542 dp_clock =
543 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
544
545 if ((dp_clock == 540000) &&
546 (!radeon_connector_is_dp12_capable(connector)))
547 return MODE_CLOCK_HIGH;
548
549 return MODE_OK;
550}
551
552bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
553{
554 u8 link_status[DP_LINK_STATUS_SIZE];
555 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
556
557 if (drm_dp_dpcd_read_link_status(&dig->dp_i2c_bus->aux, link_status) <= 0)
558 return false;
559 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
560 return false;
561 return true;
562}
563
564void radeon_dp_set_rx_power_state(struct drm_connector *connector,
565 u8 power_state)
566{
567 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
568 struct radeon_connector_atom_dig *dig_connector;
569
570 if (!radeon_connector->con_priv)
571 return;
572
573 dig_connector = radeon_connector->con_priv;
574
575 /* power up/down the sink */
576 if (dig_connector->dpcd[0] >= 0x11) {
577 drm_dp_dpcd_writeb(&dig_connector->dp_i2c_bus->aux,
578 DP_SET_POWER, power_state);
579 usleep_range(1000, 2000);
580 }
581}
582
583
584struct radeon_dp_link_train_info {
585 struct radeon_device *rdev;
586 struct drm_encoder *encoder;
587 struct drm_connector *connector;
588 int enc_id;
589 int dp_clock;
590 int dp_lane_count;
591 bool tp3_supported;
592 u8 dpcd[DP_RECEIVER_CAP_SIZE];
593 u8 train_set[4];
594 u8 link_status[DP_LINK_STATUS_SIZE];
595 u8 tries;
596 bool use_dpencoder;
597 struct drm_dp_aux *aux;
598};
599
600static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
601{
602 /* set the initial vs/emph on the source */
603 atombios_dig_transmitter_setup(dp_info->encoder,
604 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
605 0, dp_info->train_set[0]); /* sets all lanes at once */
606
607 /* set the vs/emph on the sink */
608 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
609 dp_info->train_set, dp_info->dp_lane_count);
610}
611
612static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
613{
614 int rtp = 0;
615
616 /* set training pattern on the source */
617 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
618 switch (tp) {
619 case DP_TRAINING_PATTERN_1:
620 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
621 break;
622 case DP_TRAINING_PATTERN_2:
623 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
624 break;
625 case DP_TRAINING_PATTERN_3:
626 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
627 break;
628 }
629 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
630 } else {
631 switch (tp) {
632 case DP_TRAINING_PATTERN_1:
633 rtp = 0;
634 break;
635 case DP_TRAINING_PATTERN_2:
636 rtp = 1;
637 break;
638 }
639 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
640 dp_info->dp_clock, dp_info->enc_id, rtp);
641 }
642
643 /* enable training pattern on the sink */
644 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
645}
646
647static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
648{
649 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
650 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
651 u8 tmp;
652
653 /* power up the sink */
654 radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
655
656 /* possibly enable downspread on the sink */
657 if (dp_info->dpcd[3] & 0x1)
658 drm_dp_dpcd_writeb(dp_info->aux,
659 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
660 else
661 drm_dp_dpcd_writeb(dp_info->aux,
662 DP_DOWNSPREAD_CTRL, 0);
663
664 if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
665 (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
666 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
667 }
668
669 /* set the lane count on the sink */
670 tmp = dp_info->dp_lane_count;
671 if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
672 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
673 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
674
675 /* set the link rate on the sink */
676 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
677 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
678
679 /* start training on the source */
680 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
681 atombios_dig_encoder_setup(dp_info->encoder,
682 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
683 else
684 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
685 dp_info->dp_clock, dp_info->enc_id, 0);
686
687 /* disable the training pattern on the sink */
688 drm_dp_dpcd_writeb(dp_info->aux,
689 DP_TRAINING_PATTERN_SET,
690 DP_TRAINING_PATTERN_DISABLE);
691
692 return 0;
693}
694
695static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
696{
697 udelay(400);
698
699 /* disable the training pattern on the sink */
700 drm_dp_dpcd_writeb(dp_info->aux,
701 DP_TRAINING_PATTERN_SET,
702 DP_TRAINING_PATTERN_DISABLE);
703
704 /* disable the training pattern on the source */
705 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
706 atombios_dig_encoder_setup(dp_info->encoder,
707 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
708 else
709 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
710 dp_info->dp_clock, dp_info->enc_id, 0);
711
712 return 0;
713}
714
715static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
716{
717 bool clock_recovery;
718 u8 voltage;
719 int i;
720
721 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
722 memset(dp_info->train_set, 0, 4);
723 radeon_dp_update_vs_emph(dp_info);
724
725 udelay(400);
726
727 /* clock recovery loop */
728 clock_recovery = false;
729 dp_info->tries = 0;
730 voltage = 0xff;
731 while (1) {
732 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
733
734 if (drm_dp_dpcd_read_link_status(dp_info->aux,
735 dp_info->link_status) <= 0) {
736 DRM_ERROR("displayport link status failed\n");
737 break;
738 }
739
740 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
741 clock_recovery = true;
742 break;
743 }
744
745 for (i = 0; i < dp_info->dp_lane_count; i++) {
746 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
747 break;
748 }
749 if (i == dp_info->dp_lane_count) {
750 DRM_ERROR("clock recovery reached max voltage\n");
751 break;
752 }
753
754 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
755 ++dp_info->tries;
756 if (dp_info->tries == 5) {
757 DRM_ERROR("clock recovery tried 5 times\n");
758 break;
759 }
760 } else
761 dp_info->tries = 0;
762
763 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
764
765 /* Compute new train_set as requested by sink */
766 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
767
768 radeon_dp_update_vs_emph(dp_info);
769 }
770 if (!clock_recovery) {
771 DRM_ERROR("clock recovery failed\n");
772 return -1;
773 } else {
774 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
775 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
776 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
777 DP_TRAIN_PRE_EMPHASIS_SHIFT);
778 return 0;
779 }
780}
781
782static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
783{
784 bool channel_eq;
785
786 if (dp_info->tp3_supported)
787 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
788 else
789 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
790
791 /* channel equalization loop */
792 dp_info->tries = 0;
793 channel_eq = false;
794 while (1) {
795 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
796
797 if (drm_dp_dpcd_read_link_status(dp_info->aux,
798 dp_info->link_status) <= 0) {
799 DRM_ERROR("displayport link status failed\n");
800 break;
801 }
802
803 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
804 channel_eq = true;
805 break;
806 }
807
808 /* Try 5 times */
809 if (dp_info->tries > 5) {
810 DRM_ERROR("channel eq failed: 5 tries\n");
811 break;
812 }
813
814 /* Compute new train_set as requested by sink */
815 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
816
817 radeon_dp_update_vs_emph(dp_info);
818 dp_info->tries++;
819 }
820
821 if (!channel_eq) {
822 DRM_ERROR("channel eq failed\n");
823 return -1;
824 } else {
825 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
826 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
827 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
828 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
829 return 0;
830 }
831}
832
833void radeon_dp_link_train(struct drm_encoder *encoder,
834 struct drm_connector *connector)
835{
836 struct drm_device *dev = encoder->dev;
837 struct radeon_device *rdev = dev->dev_private;
838 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
839 struct radeon_encoder_atom_dig *dig;
840 struct radeon_connector *radeon_connector;
841 struct radeon_connector_atom_dig *dig_connector;
842 struct radeon_dp_link_train_info dp_info;
843 int index;
844 u8 tmp, frev, crev;
845
846 if (!radeon_encoder->enc_priv)
847 return;
848 dig = radeon_encoder->enc_priv;
849
850 radeon_connector = to_radeon_connector(connector);
851 if (!radeon_connector->con_priv)
852 return;
853 dig_connector = radeon_connector->con_priv;
854
855 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
856 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
857 return;
858
859 /* DPEncoderService newer than 1.1 can't program properly the
860 * training pattern. When facing such version use the
861 * DIGXEncoderControl (X== 1 | 2)
862 */
863 dp_info.use_dpencoder = true;
864 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
865 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
866 if (crev > 1) {
867 dp_info.use_dpencoder = false;
868 }
869 }
870
871 dp_info.enc_id = 0;
872 if (dig->dig_encoder)
873 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
874 else
875 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
876 if (dig->linkb)
877 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
878 else
879 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
880
881 drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux, DP_MAX_LANE_COUNT, &tmp);
882 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
883 dp_info.tp3_supported = true;
884 else
885 dp_info.tp3_supported = false;
886
887 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
888 dp_info.rdev = rdev;
889 dp_info.encoder = encoder;
890 dp_info.connector = connector;
891 dp_info.dp_lane_count = dig_connector->dp_lane_count;
892 dp_info.dp_clock = dig_connector->dp_clock;
893 dp_info.aux = &dig_connector->dp_i2c_bus->aux;
894
895 if (radeon_dp_link_train_init(&dp_info))
896 goto done;
897 if (radeon_dp_link_train_cr(&dp_info))
898 goto done;
899 if (radeon_dp_link_train_ce(&dp_info))
900 goto done;
901done:
902 if (radeon_dp_link_train_finish(&dp_info))
903 return;
904}
Linux kernel - Deliverables
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