| 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #ifndef __RADEON_H__ |
| 29 | #define __RADEON_H__ |
| 30 | |
| 31 | /* TODO: Here are things that needs to be done : |
| 32 | * - surface allocator & initializer : (bit like scratch reg) should |
| 33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
| 34 | * related to surface |
| 35 | * - WB : write back stuff (do it bit like scratch reg things) |
| 36 | * - Vblank : look at Jesse's rework and what we should do |
| 37 | * - r600/r700: gart & cp |
| 38 | * - cs : clean cs ioctl use bitmap & things like that. |
| 39 | * - power management stuff |
| 40 | * - Barrier in gart code |
| 41 | * - Unmappabled vram ? |
| 42 | * - TESTING, TESTING, TESTING |
| 43 | */ |
| 44 | |
| 45 | /* Initialization path: |
| 46 | * We expect that acceleration initialization might fail for various |
| 47 | * reasons even thought we work hard to make it works on most |
| 48 | * configurations. In order to still have a working userspace in such |
| 49 | * situation the init path must succeed up to the memory controller |
| 50 | * initialization point. Failure before this point are considered as |
| 51 | * fatal error. Here is the init callchain : |
| 52 | * radeon_device_init perform common structure, mutex initialization |
| 53 | * asic_init setup the GPU memory layout and perform all |
| 54 | * one time initialization (failure in this |
| 55 | * function are considered fatal) |
| 56 | * asic_startup setup the GPU acceleration, in order to |
| 57 | * follow guideline the first thing this |
| 58 | * function should do is setting the GPU |
| 59 | * memory controller (only MC setup failure |
| 60 | * are considered as fatal) |
| 61 | */ |
| 62 | |
| 63 | #include <asm/atomic.h> |
| 64 | #include <linux/wait.h> |
| 65 | #include <linux/list.h> |
| 66 | #include <linux/kref.h> |
| 67 | |
| 68 | #include <ttm/ttm_bo_api.h> |
| 69 | #include <ttm/ttm_bo_driver.h> |
| 70 | #include <ttm/ttm_placement.h> |
| 71 | #include <ttm/ttm_module.h> |
| 72 | #include <ttm/ttm_execbuf_util.h> |
| 73 | |
| 74 | #include "radeon_family.h" |
| 75 | #include "radeon_mode.h" |
| 76 | #include "radeon_reg.h" |
| 77 | |
| 78 | /* |
| 79 | * Modules parameters. |
| 80 | */ |
| 81 | extern int radeon_no_wb; |
| 82 | extern int radeon_modeset; |
| 83 | extern int radeon_dynclks; |
| 84 | extern int radeon_r4xx_atom; |
| 85 | extern int radeon_agpmode; |
| 86 | extern int radeon_vram_limit; |
| 87 | extern int radeon_gart_size; |
| 88 | extern int radeon_benchmarking; |
| 89 | extern int radeon_testing; |
| 90 | extern int radeon_connector_table; |
| 91 | extern int radeon_tv; |
| 92 | extern int radeon_audio; |
| 93 | extern int radeon_disp_priority; |
| 94 | extern int radeon_hw_i2c; |
| 95 | extern int radeon_pcie_gen2; |
| 96 | |
| 97 | /* |
| 98 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
| 99 | * symbol; |
| 100 | */ |
| 101 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
| 102 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
| 103 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
| 104 | #define RADEON_IB_POOL_SIZE 16 |
| 105 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 |
| 106 | #define RADEONFB_CONN_LIMIT 4 |
| 107 | #define RADEON_BIOS_NUM_SCRATCH 8 |
| 108 | |
| 109 | /* |
| 110 | * Errata workarounds. |
| 111 | */ |
| 112 | enum radeon_pll_errata { |
| 113 | CHIP_ERRATA_R300_CG = 0x00000001, |
| 114 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
| 115 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
| 116 | }; |
| 117 | |
| 118 | |
| 119 | struct radeon_device; |
| 120 | |
| 121 | |
| 122 | /* |
| 123 | * BIOS. |
| 124 | */ |
| 125 | #define ATRM_BIOS_PAGE 4096 |
| 126 | |
| 127 | #if defined(CONFIG_VGA_SWITCHEROO) |
| 128 | bool radeon_atrm_supported(struct pci_dev *pdev); |
| 129 | int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len); |
| 130 | #else |
| 131 | static inline bool radeon_atrm_supported(struct pci_dev *pdev) |
| 132 | { |
| 133 | return false; |
| 134 | } |
| 135 | |
| 136 | static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){ |
| 137 | return -EINVAL; |
| 138 | } |
| 139 | #endif |
| 140 | bool radeon_get_bios(struct radeon_device *rdev); |
| 141 | |
| 142 | |
| 143 | /* |
| 144 | * Dummy page |
| 145 | */ |
| 146 | struct radeon_dummy_page { |
| 147 | struct page *page; |
| 148 | dma_addr_t addr; |
| 149 | }; |
| 150 | int radeon_dummy_page_init(struct radeon_device *rdev); |
| 151 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
| 152 | |
| 153 | |
| 154 | /* |
| 155 | * Clocks |
| 156 | */ |
| 157 | struct radeon_clock { |
| 158 | struct radeon_pll p1pll; |
| 159 | struct radeon_pll p2pll; |
| 160 | struct radeon_pll dcpll; |
| 161 | struct radeon_pll spll; |
| 162 | struct radeon_pll mpll; |
| 163 | /* 10 Khz units */ |
| 164 | uint32_t default_mclk; |
| 165 | uint32_t default_sclk; |
| 166 | uint32_t default_dispclk; |
| 167 | uint32_t dp_extclk; |
| 168 | }; |
| 169 | |
| 170 | /* |
| 171 | * Power management |
| 172 | */ |
| 173 | int radeon_pm_init(struct radeon_device *rdev); |
| 174 | void radeon_pm_fini(struct radeon_device *rdev); |
| 175 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
| 176 | void radeon_pm_suspend(struct radeon_device *rdev); |
| 177 | void radeon_pm_resume(struct radeon_device *rdev); |
| 178 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
| 179 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
| 180 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
| 181 | void rs690_pm_info(struct radeon_device *rdev); |
| 182 | extern int rv6xx_get_temp(struct radeon_device *rdev); |
| 183 | extern int rv770_get_temp(struct radeon_device *rdev); |
| 184 | extern int evergreen_get_temp(struct radeon_device *rdev); |
| 185 | extern int sumo_get_temp(struct radeon_device *rdev); |
| 186 | |
| 187 | /* |
| 188 | * Fences. |
| 189 | */ |
| 190 | struct radeon_fence_driver { |
| 191 | uint32_t scratch_reg; |
| 192 | atomic_t seq; |
| 193 | uint32_t last_seq; |
| 194 | unsigned long last_jiffies; |
| 195 | unsigned long last_timeout; |
| 196 | wait_queue_head_t queue; |
| 197 | rwlock_t lock; |
| 198 | struct list_head created; |
| 199 | struct list_head emited; |
| 200 | struct list_head signaled; |
| 201 | bool initialized; |
| 202 | }; |
| 203 | |
| 204 | struct radeon_fence { |
| 205 | struct radeon_device *rdev; |
| 206 | struct kref kref; |
| 207 | struct list_head list; |
| 208 | /* protected by radeon_fence.lock */ |
| 209 | uint32_t seq; |
| 210 | bool emited; |
| 211 | bool signaled; |
| 212 | }; |
| 213 | |
| 214 | int radeon_fence_driver_init(struct radeon_device *rdev); |
| 215 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
| 216 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); |
| 217 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); |
| 218 | void radeon_fence_process(struct radeon_device *rdev); |
| 219 | bool radeon_fence_signaled(struct radeon_fence *fence); |
| 220 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
| 221 | int radeon_fence_wait_next(struct radeon_device *rdev); |
| 222 | int radeon_fence_wait_last(struct radeon_device *rdev); |
| 223 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
| 224 | void radeon_fence_unref(struct radeon_fence **fence); |
| 225 | |
| 226 | /* |
| 227 | * Tiling registers |
| 228 | */ |
| 229 | struct radeon_surface_reg { |
| 230 | struct radeon_bo *bo; |
| 231 | }; |
| 232 | |
| 233 | #define RADEON_GEM_MAX_SURFACES 8 |
| 234 | |
| 235 | /* |
| 236 | * TTM. |
| 237 | */ |
| 238 | struct radeon_mman { |
| 239 | struct ttm_bo_global_ref bo_global_ref; |
| 240 | struct drm_global_reference mem_global_ref; |
| 241 | struct ttm_bo_device bdev; |
| 242 | bool mem_global_referenced; |
| 243 | bool initialized; |
| 244 | }; |
| 245 | |
| 246 | struct radeon_bo { |
| 247 | /* Protected by gem.mutex */ |
| 248 | struct list_head list; |
| 249 | /* Protected by tbo.reserved */ |
| 250 | u32 placements[3]; |
| 251 | struct ttm_placement placement; |
| 252 | struct ttm_buffer_object tbo; |
| 253 | struct ttm_bo_kmap_obj kmap; |
| 254 | unsigned pin_count; |
| 255 | void *kptr; |
| 256 | u32 tiling_flags; |
| 257 | u32 pitch; |
| 258 | int surface_reg; |
| 259 | /* Constant after initialization */ |
| 260 | struct radeon_device *rdev; |
| 261 | struct drm_gem_object gem_base; |
| 262 | }; |
| 263 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
| 264 | |
| 265 | struct radeon_bo_list { |
| 266 | struct ttm_validate_buffer tv; |
| 267 | struct radeon_bo *bo; |
| 268 | uint64_t gpu_offset; |
| 269 | unsigned rdomain; |
| 270 | unsigned wdomain; |
| 271 | u32 tiling_flags; |
| 272 | }; |
| 273 | |
| 274 | /* |
| 275 | * GEM objects. |
| 276 | */ |
| 277 | struct radeon_gem { |
| 278 | struct mutex mutex; |
| 279 | struct list_head objects; |
| 280 | }; |
| 281 | |
| 282 | int radeon_gem_init(struct radeon_device *rdev); |
| 283 | void radeon_gem_fini(struct radeon_device *rdev); |
| 284 | int radeon_gem_object_create(struct radeon_device *rdev, int size, |
| 285 | int alignment, int initial_domain, |
| 286 | bool discardable, bool kernel, |
| 287 | struct drm_gem_object **obj); |
| 288 | int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, |
| 289 | uint64_t *gpu_addr); |
| 290 | void radeon_gem_object_unpin(struct drm_gem_object *obj); |
| 291 | |
| 292 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
| 293 | struct drm_device *dev, |
| 294 | struct drm_mode_create_dumb *args); |
| 295 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
| 296 | struct drm_device *dev, |
| 297 | uint32_t handle, uint64_t *offset_p); |
| 298 | int radeon_mode_dumb_destroy(struct drm_file *file_priv, |
| 299 | struct drm_device *dev, |
| 300 | uint32_t handle); |
| 301 | |
| 302 | /* |
| 303 | * GART structures, functions & helpers |
| 304 | */ |
| 305 | struct radeon_mc; |
| 306 | |
| 307 | struct radeon_gart_table_ram { |
| 308 | volatile uint32_t *ptr; |
| 309 | }; |
| 310 | |
| 311 | struct radeon_gart_table_vram { |
| 312 | struct radeon_bo *robj; |
| 313 | volatile uint32_t *ptr; |
| 314 | }; |
| 315 | |
| 316 | union radeon_gart_table { |
| 317 | struct radeon_gart_table_ram ram; |
| 318 | struct radeon_gart_table_vram vram; |
| 319 | }; |
| 320 | |
| 321 | #define RADEON_GPU_PAGE_SIZE 4096 |
| 322 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
| 323 | |
| 324 | struct radeon_gart { |
| 325 | dma_addr_t table_addr; |
| 326 | unsigned num_gpu_pages; |
| 327 | unsigned num_cpu_pages; |
| 328 | unsigned table_size; |
| 329 | union radeon_gart_table table; |
| 330 | struct page **pages; |
| 331 | dma_addr_t *pages_addr; |
| 332 | bool *ttm_alloced; |
| 333 | bool ready; |
| 334 | }; |
| 335 | |
| 336 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
| 337 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
| 338 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
| 339 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
| 340 | int radeon_gart_init(struct radeon_device *rdev); |
| 341 | void radeon_gart_fini(struct radeon_device *rdev); |
| 342 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
| 343 | int pages); |
| 344 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
| 345 | int pages, struct page **pagelist, |
| 346 | dma_addr_t *dma_addr); |
| 347 | |
| 348 | |
| 349 | /* |
| 350 | * GPU MC structures, functions & helpers |
| 351 | */ |
| 352 | struct radeon_mc { |
| 353 | resource_size_t aper_size; |
| 354 | resource_size_t aper_base; |
| 355 | resource_size_t agp_base; |
| 356 | /* for some chips with <= 32MB we need to lie |
| 357 | * about vram size near mc fb location */ |
| 358 | u64 mc_vram_size; |
| 359 | u64 visible_vram_size; |
| 360 | u64 gtt_size; |
| 361 | u64 gtt_start; |
| 362 | u64 gtt_end; |
| 363 | u64 vram_start; |
| 364 | u64 vram_end; |
| 365 | unsigned vram_width; |
| 366 | u64 real_vram_size; |
| 367 | int vram_mtrr; |
| 368 | bool vram_is_ddr; |
| 369 | bool igp_sideport_enabled; |
| 370 | u64 gtt_base_align; |
| 371 | }; |
| 372 | |
| 373 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
| 374 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
| 375 | |
| 376 | /* |
| 377 | * GPU scratch registers structures, functions & helpers |
| 378 | */ |
| 379 | struct radeon_scratch { |
| 380 | unsigned num_reg; |
| 381 | uint32_t reg_base; |
| 382 | bool free[32]; |
| 383 | uint32_t reg[32]; |
| 384 | }; |
| 385 | |
| 386 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
| 387 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
| 388 | |
| 389 | |
| 390 | /* |
| 391 | * IRQS. |
| 392 | */ |
| 393 | |
| 394 | struct radeon_unpin_work { |
| 395 | struct work_struct work; |
| 396 | struct radeon_device *rdev; |
| 397 | int crtc_id; |
| 398 | struct radeon_fence *fence; |
| 399 | struct drm_pending_vblank_event *event; |
| 400 | struct radeon_bo *old_rbo; |
| 401 | u64 new_crtc_base; |
| 402 | }; |
| 403 | |
| 404 | struct r500_irq_stat_regs { |
| 405 | u32 disp_int; |
| 406 | }; |
| 407 | |
| 408 | struct r600_irq_stat_regs { |
| 409 | u32 disp_int; |
| 410 | u32 disp_int_cont; |
| 411 | u32 disp_int_cont2; |
| 412 | u32 d1grph_int; |
| 413 | u32 d2grph_int; |
| 414 | }; |
| 415 | |
| 416 | struct evergreen_irq_stat_regs { |
| 417 | u32 disp_int; |
| 418 | u32 disp_int_cont; |
| 419 | u32 disp_int_cont2; |
| 420 | u32 disp_int_cont3; |
| 421 | u32 disp_int_cont4; |
| 422 | u32 disp_int_cont5; |
| 423 | u32 d1grph_int; |
| 424 | u32 d2grph_int; |
| 425 | u32 d3grph_int; |
| 426 | u32 d4grph_int; |
| 427 | u32 d5grph_int; |
| 428 | u32 d6grph_int; |
| 429 | }; |
| 430 | |
| 431 | union radeon_irq_stat_regs { |
| 432 | struct r500_irq_stat_regs r500; |
| 433 | struct r600_irq_stat_regs r600; |
| 434 | struct evergreen_irq_stat_regs evergreen; |
| 435 | }; |
| 436 | |
| 437 | struct radeon_irq { |
| 438 | bool installed; |
| 439 | bool sw_int; |
| 440 | /* FIXME: use a define max crtc rather than hardcode it */ |
| 441 | bool crtc_vblank_int[6]; |
| 442 | bool pflip[6]; |
| 443 | wait_queue_head_t vblank_queue; |
| 444 | /* FIXME: use defines for max hpd/dacs */ |
| 445 | bool hpd[6]; |
| 446 | bool gui_idle; |
| 447 | bool gui_idle_acked; |
| 448 | wait_queue_head_t idle_queue; |
| 449 | /* FIXME: use defines for max HDMI blocks */ |
| 450 | bool hdmi[2]; |
| 451 | spinlock_t sw_lock; |
| 452 | int sw_refcount; |
| 453 | union radeon_irq_stat_regs stat_regs; |
| 454 | spinlock_t pflip_lock[6]; |
| 455 | int pflip_refcount[6]; |
| 456 | }; |
| 457 | |
| 458 | int radeon_irq_kms_init(struct radeon_device *rdev); |
| 459 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
| 460 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev); |
| 461 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); |
| 462 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
| 463 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); |
| 464 | |
| 465 | /* |
| 466 | * CP & ring. |
| 467 | */ |
| 468 | struct radeon_ib { |
| 469 | struct list_head list; |
| 470 | unsigned idx; |
| 471 | uint64_t gpu_addr; |
| 472 | struct radeon_fence *fence; |
| 473 | uint32_t *ptr; |
| 474 | uint32_t length_dw; |
| 475 | bool free; |
| 476 | }; |
| 477 | |
| 478 | /* |
| 479 | * locking - |
| 480 | * mutex protects scheduled_ibs, ready, alloc_bm |
| 481 | */ |
| 482 | struct radeon_ib_pool { |
| 483 | struct mutex mutex; |
| 484 | struct radeon_bo *robj; |
| 485 | struct list_head bogus_ib; |
| 486 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
| 487 | bool ready; |
| 488 | unsigned head_id; |
| 489 | }; |
| 490 | |
| 491 | struct radeon_cp { |
| 492 | struct radeon_bo *ring_obj; |
| 493 | volatile uint32_t *ring; |
| 494 | unsigned rptr; |
| 495 | unsigned wptr; |
| 496 | unsigned wptr_old; |
| 497 | unsigned ring_size; |
| 498 | unsigned ring_free_dw; |
| 499 | int count_dw; |
| 500 | uint64_t gpu_addr; |
| 501 | uint32_t align_mask; |
| 502 | uint32_t ptr_mask; |
| 503 | struct mutex mutex; |
| 504 | bool ready; |
| 505 | }; |
| 506 | |
| 507 | /* |
| 508 | * R6xx+ IH ring |
| 509 | */ |
| 510 | struct r600_ih { |
| 511 | struct radeon_bo *ring_obj; |
| 512 | volatile uint32_t *ring; |
| 513 | unsigned rptr; |
| 514 | unsigned wptr; |
| 515 | unsigned wptr_old; |
| 516 | unsigned ring_size; |
| 517 | uint64_t gpu_addr; |
| 518 | uint32_t ptr_mask; |
| 519 | spinlock_t lock; |
| 520 | bool enabled; |
| 521 | }; |
| 522 | |
| 523 | struct r600_blit { |
| 524 | struct mutex mutex; |
| 525 | struct radeon_bo *shader_obj; |
| 526 | u64 shader_gpu_addr; |
| 527 | u32 vs_offset, ps_offset; |
| 528 | u32 state_offset; |
| 529 | u32 state_len; |
| 530 | u32 vb_used, vb_total; |
| 531 | struct radeon_ib *vb_ib; |
| 532 | }; |
| 533 | |
| 534 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
| 535 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); |
| 536 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); |
| 537 | int radeon_ib_pool_init(struct radeon_device *rdev); |
| 538 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
| 539 | int radeon_ib_test(struct radeon_device *rdev); |
| 540 | extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib); |
| 541 | /* Ring access between begin & end cannot sleep */ |
| 542 | void radeon_ring_free_size(struct radeon_device *rdev); |
| 543 | int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw); |
| 544 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
| 545 | void radeon_ring_commit(struct radeon_device *rdev); |
| 546 | void radeon_ring_unlock_commit(struct radeon_device *rdev); |
| 547 | void radeon_ring_unlock_undo(struct radeon_device *rdev); |
| 548 | int radeon_ring_test(struct radeon_device *rdev); |
| 549 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); |
| 550 | void radeon_ring_fini(struct radeon_device *rdev); |
| 551 | |
| 552 | |
| 553 | /* |
| 554 | * CS. |
| 555 | */ |
| 556 | struct radeon_cs_reloc { |
| 557 | struct drm_gem_object *gobj; |
| 558 | struct radeon_bo *robj; |
| 559 | struct radeon_bo_list lobj; |
| 560 | uint32_t handle; |
| 561 | uint32_t flags; |
| 562 | }; |
| 563 | |
| 564 | struct radeon_cs_chunk { |
| 565 | uint32_t chunk_id; |
| 566 | uint32_t length_dw; |
| 567 | int kpage_idx[2]; |
| 568 | uint32_t *kpage[2]; |
| 569 | uint32_t *kdata; |
| 570 | void __user *user_ptr; |
| 571 | int last_copied_page; |
| 572 | int last_page_index; |
| 573 | }; |
| 574 | |
| 575 | struct radeon_cs_parser { |
| 576 | struct device *dev; |
| 577 | struct radeon_device *rdev; |
| 578 | struct drm_file *filp; |
| 579 | /* chunks */ |
| 580 | unsigned nchunks; |
| 581 | struct radeon_cs_chunk *chunks; |
| 582 | uint64_t *chunks_array; |
| 583 | /* IB */ |
| 584 | unsigned idx; |
| 585 | /* relocations */ |
| 586 | unsigned nrelocs; |
| 587 | struct radeon_cs_reloc *relocs; |
| 588 | struct radeon_cs_reloc **relocs_ptr; |
| 589 | struct list_head validated; |
| 590 | /* indices of various chunks */ |
| 591 | int chunk_ib_idx; |
| 592 | int chunk_relocs_idx; |
| 593 | struct radeon_ib *ib; |
| 594 | void *track; |
| 595 | unsigned family; |
| 596 | int parser_error; |
| 597 | }; |
| 598 | |
| 599 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
| 600 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
| 601 | |
| 602 | |
| 603 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
| 604 | { |
| 605 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; |
| 606 | u32 pg_idx, pg_offset; |
| 607 | u32 idx_value = 0; |
| 608 | int new_page; |
| 609 | |
| 610 | pg_idx = (idx * 4) / PAGE_SIZE; |
| 611 | pg_offset = (idx * 4) % PAGE_SIZE; |
| 612 | |
| 613 | if (ibc->kpage_idx[0] == pg_idx) |
| 614 | return ibc->kpage[0][pg_offset/4]; |
| 615 | if (ibc->kpage_idx[1] == pg_idx) |
| 616 | return ibc->kpage[1][pg_offset/4]; |
| 617 | |
| 618 | new_page = radeon_cs_update_pages(p, pg_idx); |
| 619 | if (new_page < 0) { |
| 620 | p->parser_error = new_page; |
| 621 | return 0; |
| 622 | } |
| 623 | |
| 624 | idx_value = ibc->kpage[new_page][pg_offset/4]; |
| 625 | return idx_value; |
| 626 | } |
| 627 | |
| 628 | struct radeon_cs_packet { |
| 629 | unsigned idx; |
| 630 | unsigned type; |
| 631 | unsigned reg; |
| 632 | unsigned opcode; |
| 633 | int count; |
| 634 | unsigned one_reg_wr; |
| 635 | }; |
| 636 | |
| 637 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
| 638 | struct radeon_cs_packet *pkt, |
| 639 | unsigned idx, unsigned reg); |
| 640 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
| 641 | struct radeon_cs_packet *pkt); |
| 642 | |
| 643 | |
| 644 | /* |
| 645 | * AGP |
| 646 | */ |
| 647 | int radeon_agp_init(struct radeon_device *rdev); |
| 648 | void radeon_agp_resume(struct radeon_device *rdev); |
| 649 | void radeon_agp_suspend(struct radeon_device *rdev); |
| 650 | void radeon_agp_fini(struct radeon_device *rdev); |
| 651 | |
| 652 | |
| 653 | /* |
| 654 | * Writeback |
| 655 | */ |
| 656 | struct radeon_wb { |
| 657 | struct radeon_bo *wb_obj; |
| 658 | volatile uint32_t *wb; |
| 659 | uint64_t gpu_addr; |
| 660 | bool enabled; |
| 661 | bool use_event; |
| 662 | }; |
| 663 | |
| 664 | #define RADEON_WB_SCRATCH_OFFSET 0 |
| 665 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
| 666 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
| 667 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 |
| 668 | #define R600_WB_IH_WPTR_OFFSET 2048 |
| 669 | #define R600_WB_EVENT_OFFSET 3072 |
| 670 | |
| 671 | /** |
| 672 | * struct radeon_pm - power management datas |
| 673 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
| 674 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
| 675 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
| 676 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
| 677 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
| 678 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
| 679 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
| 680 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
| 681 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
| 682 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
| 683 | * @needed_bandwidth: current bandwidth needs |
| 684 | * |
| 685 | * It keeps track of various data needed to take powermanagement decision. |
| 686 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
| 687 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
| 688 | * (type of memory, bus size, efficiency, ...) |
| 689 | */ |
| 690 | |
| 691 | enum radeon_pm_method { |
| 692 | PM_METHOD_PROFILE, |
| 693 | PM_METHOD_DYNPM, |
| 694 | }; |
| 695 | |
| 696 | enum radeon_dynpm_state { |
| 697 | DYNPM_STATE_DISABLED, |
| 698 | DYNPM_STATE_MINIMUM, |
| 699 | DYNPM_STATE_PAUSED, |
| 700 | DYNPM_STATE_ACTIVE, |
| 701 | DYNPM_STATE_SUSPENDED, |
| 702 | }; |
| 703 | enum radeon_dynpm_action { |
| 704 | DYNPM_ACTION_NONE, |
| 705 | DYNPM_ACTION_MINIMUM, |
| 706 | DYNPM_ACTION_DOWNCLOCK, |
| 707 | DYNPM_ACTION_UPCLOCK, |
| 708 | DYNPM_ACTION_DEFAULT |
| 709 | }; |
| 710 | |
| 711 | enum radeon_voltage_type { |
| 712 | VOLTAGE_NONE = 0, |
| 713 | VOLTAGE_GPIO, |
| 714 | VOLTAGE_VDDC, |
| 715 | VOLTAGE_SW |
| 716 | }; |
| 717 | |
| 718 | enum radeon_pm_state_type { |
| 719 | POWER_STATE_TYPE_DEFAULT, |
| 720 | POWER_STATE_TYPE_POWERSAVE, |
| 721 | POWER_STATE_TYPE_BATTERY, |
| 722 | POWER_STATE_TYPE_BALANCED, |
| 723 | POWER_STATE_TYPE_PERFORMANCE, |
| 724 | }; |
| 725 | |
| 726 | enum radeon_pm_profile_type { |
| 727 | PM_PROFILE_DEFAULT, |
| 728 | PM_PROFILE_AUTO, |
| 729 | PM_PROFILE_LOW, |
| 730 | PM_PROFILE_MID, |
| 731 | PM_PROFILE_HIGH, |
| 732 | }; |
| 733 | |
| 734 | #define PM_PROFILE_DEFAULT_IDX 0 |
| 735 | #define PM_PROFILE_LOW_SH_IDX 1 |
| 736 | #define PM_PROFILE_MID_SH_IDX 2 |
| 737 | #define PM_PROFILE_HIGH_SH_IDX 3 |
| 738 | #define PM_PROFILE_LOW_MH_IDX 4 |
| 739 | #define PM_PROFILE_MID_MH_IDX 5 |
| 740 | #define PM_PROFILE_HIGH_MH_IDX 6 |
| 741 | #define PM_PROFILE_MAX 7 |
| 742 | |
| 743 | struct radeon_pm_profile { |
| 744 | int dpms_off_ps_idx; |
| 745 | int dpms_on_ps_idx; |
| 746 | int dpms_off_cm_idx; |
| 747 | int dpms_on_cm_idx; |
| 748 | }; |
| 749 | |
| 750 | enum radeon_int_thermal_type { |
| 751 | THERMAL_TYPE_NONE, |
| 752 | THERMAL_TYPE_RV6XX, |
| 753 | THERMAL_TYPE_RV770, |
| 754 | THERMAL_TYPE_EVERGREEN, |
| 755 | THERMAL_TYPE_SUMO, |
| 756 | THERMAL_TYPE_NI, |
| 757 | }; |
| 758 | |
| 759 | struct radeon_voltage { |
| 760 | enum radeon_voltage_type type; |
| 761 | /* gpio voltage */ |
| 762 | struct radeon_gpio_rec gpio; |
| 763 | u32 delay; /* delay in usec from voltage drop to sclk change */ |
| 764 | bool active_high; /* voltage drop is active when bit is high */ |
| 765 | /* VDDC voltage */ |
| 766 | u8 vddc_id; /* index into vddc voltage table */ |
| 767 | u8 vddci_id; /* index into vddci voltage table */ |
| 768 | bool vddci_enabled; |
| 769 | /* r6xx+ sw */ |
| 770 | u16 voltage; |
| 771 | /* evergreen+ vddci */ |
| 772 | u16 vddci; |
| 773 | }; |
| 774 | |
| 775 | /* clock mode flags */ |
| 776 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) |
| 777 | |
| 778 | struct radeon_pm_clock_info { |
| 779 | /* memory clock */ |
| 780 | u32 mclk; |
| 781 | /* engine clock */ |
| 782 | u32 sclk; |
| 783 | /* voltage info */ |
| 784 | struct radeon_voltage voltage; |
| 785 | /* standardized clock flags */ |
| 786 | u32 flags; |
| 787 | }; |
| 788 | |
| 789 | /* state flags */ |
| 790 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
| 791 | |
| 792 | struct radeon_power_state { |
| 793 | enum radeon_pm_state_type type; |
| 794 | /* XXX: use a define for num clock modes */ |
| 795 | struct radeon_pm_clock_info clock_info[8]; |
| 796 | /* number of valid clock modes in this power state */ |
| 797 | int num_clock_modes; |
| 798 | struct radeon_pm_clock_info *default_clock_mode; |
| 799 | /* standardized state flags */ |
| 800 | u32 flags; |
| 801 | u32 misc; /* vbios specific flags */ |
| 802 | u32 misc2; /* vbios specific flags */ |
| 803 | int pcie_lanes; /* pcie lanes */ |
| 804 | }; |
| 805 | |
| 806 | /* |
| 807 | * Some modes are overclocked by very low value, accept them |
| 808 | */ |
| 809 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ |
| 810 | |
| 811 | struct radeon_pm { |
| 812 | struct mutex mutex; |
| 813 | u32 active_crtcs; |
| 814 | int active_crtc_count; |
| 815 | int req_vblank; |
| 816 | bool vblank_sync; |
| 817 | bool gui_idle; |
| 818 | fixed20_12 max_bandwidth; |
| 819 | fixed20_12 igp_sideport_mclk; |
| 820 | fixed20_12 igp_system_mclk; |
| 821 | fixed20_12 igp_ht_link_clk; |
| 822 | fixed20_12 igp_ht_link_width; |
| 823 | fixed20_12 k8_bandwidth; |
| 824 | fixed20_12 sideport_bandwidth; |
| 825 | fixed20_12 ht_bandwidth; |
| 826 | fixed20_12 core_bandwidth; |
| 827 | fixed20_12 sclk; |
| 828 | fixed20_12 mclk; |
| 829 | fixed20_12 needed_bandwidth; |
| 830 | struct radeon_power_state *power_state; |
| 831 | /* number of valid power states */ |
| 832 | int num_power_states; |
| 833 | int current_power_state_index; |
| 834 | int current_clock_mode_index; |
| 835 | int requested_power_state_index; |
| 836 | int requested_clock_mode_index; |
| 837 | int default_power_state_index; |
| 838 | u32 current_sclk; |
| 839 | u32 current_mclk; |
| 840 | u16 current_vddc; |
| 841 | u16 current_vddci; |
| 842 | u32 default_sclk; |
| 843 | u32 default_mclk; |
| 844 | u16 default_vddc; |
| 845 | u16 default_vddci; |
| 846 | struct radeon_i2c_chan *i2c_bus; |
| 847 | /* selected pm method */ |
| 848 | enum radeon_pm_method pm_method; |
| 849 | /* dynpm power management */ |
| 850 | struct delayed_work dynpm_idle_work; |
| 851 | enum radeon_dynpm_state dynpm_state; |
| 852 | enum radeon_dynpm_action dynpm_planned_action; |
| 853 | unsigned long dynpm_action_timeout; |
| 854 | bool dynpm_can_upclock; |
| 855 | bool dynpm_can_downclock; |
| 856 | /* profile-based power management */ |
| 857 | enum radeon_pm_profile_type profile; |
| 858 | int profile_index; |
| 859 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; |
| 860 | /* internal thermal controller on rv6xx+ */ |
| 861 | enum radeon_int_thermal_type int_thermal_type; |
| 862 | struct device *int_hwmon_dev; |
| 863 | }; |
| 864 | |
| 865 | |
| 866 | /* |
| 867 | * Benchmarking |
| 868 | */ |
| 869 | void radeon_benchmark(struct radeon_device *rdev); |
| 870 | |
| 871 | |
| 872 | /* |
| 873 | * Testing |
| 874 | */ |
| 875 | void radeon_test_moves(struct radeon_device *rdev); |
| 876 | |
| 877 | |
| 878 | /* |
| 879 | * Debugfs |
| 880 | */ |
| 881 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
| 882 | struct drm_info_list *files, |
| 883 | unsigned nfiles); |
| 884 | int radeon_debugfs_fence_init(struct radeon_device *rdev); |
| 885 | |
| 886 | |
| 887 | /* |
| 888 | * ASIC specific functions. |
| 889 | */ |
| 890 | struct radeon_asic { |
| 891 | int (*init)(struct radeon_device *rdev); |
| 892 | void (*fini)(struct radeon_device *rdev); |
| 893 | int (*resume)(struct radeon_device *rdev); |
| 894 | int (*suspend)(struct radeon_device *rdev); |
| 895 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
| 896 | bool (*gpu_is_lockup)(struct radeon_device *rdev); |
| 897 | int (*asic_reset)(struct radeon_device *rdev); |
| 898 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
| 899 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
| 900 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); |
| 901 | void (*cp_fini)(struct radeon_device *rdev); |
| 902 | void (*cp_disable)(struct radeon_device *rdev); |
| 903 | void (*cp_commit)(struct radeon_device *rdev); |
| 904 | void (*ring_start)(struct radeon_device *rdev); |
| 905 | int (*ring_test)(struct radeon_device *rdev); |
| 906 | void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
| 907 | int (*irq_set)(struct radeon_device *rdev); |
| 908 | int (*irq_process)(struct radeon_device *rdev); |
| 909 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
| 910 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
| 911 | int (*cs_parse)(struct radeon_cs_parser *p); |
| 912 | int (*copy_blit)(struct radeon_device *rdev, |
| 913 | uint64_t src_offset, |
| 914 | uint64_t dst_offset, |
| 915 | unsigned num_pages, |
| 916 | struct radeon_fence *fence); |
| 917 | int (*copy_dma)(struct radeon_device *rdev, |
| 918 | uint64_t src_offset, |
| 919 | uint64_t dst_offset, |
| 920 | unsigned num_pages, |
| 921 | struct radeon_fence *fence); |
| 922 | int (*copy)(struct radeon_device *rdev, |
| 923 | uint64_t src_offset, |
| 924 | uint64_t dst_offset, |
| 925 | unsigned num_pages, |
| 926 | struct radeon_fence *fence); |
| 927 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
| 928 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
| 929 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
| 930 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
| 931 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
| 932 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
| 933 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
| 934 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
| 935 | uint32_t tiling_flags, uint32_t pitch, |
| 936 | uint32_t offset, uint32_t obj_size); |
| 937 | void (*clear_surface_reg)(struct radeon_device *rdev, int reg); |
| 938 | void (*bandwidth_update)(struct radeon_device *rdev); |
| 939 | void (*hpd_init)(struct radeon_device *rdev); |
| 940 | void (*hpd_fini)(struct radeon_device *rdev); |
| 941 | bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
| 942 | void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
| 943 | /* ioctl hw specific callback. Some hw might want to perform special |
| 944 | * operation on specific ioctl. For instance on wait idle some hw |
| 945 | * might want to perform and HDP flush through MMIO as it seems that |
| 946 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed |
| 947 | * through ring. |
| 948 | */ |
| 949 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); |
| 950 | bool (*gui_idle)(struct radeon_device *rdev); |
| 951 | /* power management */ |
| 952 | void (*pm_misc)(struct radeon_device *rdev); |
| 953 | void (*pm_prepare)(struct radeon_device *rdev); |
| 954 | void (*pm_finish)(struct radeon_device *rdev); |
| 955 | void (*pm_init_profile)(struct radeon_device *rdev); |
| 956 | void (*pm_get_dynpm_state)(struct radeon_device *rdev); |
| 957 | /* pageflipping */ |
| 958 | void (*pre_page_flip)(struct radeon_device *rdev, int crtc); |
| 959 | u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); |
| 960 | void (*post_page_flip)(struct radeon_device *rdev, int crtc); |
| 961 | }; |
| 962 | |
| 963 | /* |
| 964 | * Asic structures |
| 965 | */ |
| 966 | struct r100_gpu_lockup { |
| 967 | unsigned long last_jiffies; |
| 968 | u32 last_cp_rptr; |
| 969 | }; |
| 970 | |
| 971 | struct r100_asic { |
| 972 | const unsigned *reg_safe_bm; |
| 973 | unsigned reg_safe_bm_size; |
| 974 | u32 hdp_cntl; |
| 975 | struct r100_gpu_lockup lockup; |
| 976 | }; |
| 977 | |
| 978 | struct r300_asic { |
| 979 | const unsigned *reg_safe_bm; |
| 980 | unsigned reg_safe_bm_size; |
| 981 | u32 resync_scratch; |
| 982 | u32 hdp_cntl; |
| 983 | struct r100_gpu_lockup lockup; |
| 984 | }; |
| 985 | |
| 986 | struct r600_asic { |
| 987 | unsigned max_pipes; |
| 988 | unsigned max_tile_pipes; |
| 989 | unsigned max_simds; |
| 990 | unsigned max_backends; |
| 991 | unsigned max_gprs; |
| 992 | unsigned max_threads; |
| 993 | unsigned max_stack_entries; |
| 994 | unsigned max_hw_contexts; |
| 995 | unsigned max_gs_threads; |
| 996 | unsigned sx_max_export_size; |
| 997 | unsigned sx_max_export_pos_size; |
| 998 | unsigned sx_max_export_smx_size; |
| 999 | unsigned sq_num_cf_insts; |
| 1000 | unsigned tiling_nbanks; |
| 1001 | unsigned tiling_npipes; |
| 1002 | unsigned tiling_group_size; |
| 1003 | unsigned tile_config; |
| 1004 | struct r100_gpu_lockup lockup; |
| 1005 | }; |
| 1006 | |
| 1007 | struct rv770_asic { |
| 1008 | unsigned max_pipes; |
| 1009 | unsigned max_tile_pipes; |
| 1010 | unsigned max_simds; |
| 1011 | unsigned max_backends; |
| 1012 | unsigned max_gprs; |
| 1013 | unsigned max_threads; |
| 1014 | unsigned max_stack_entries; |
| 1015 | unsigned max_hw_contexts; |
| 1016 | unsigned max_gs_threads; |
| 1017 | unsigned sx_max_export_size; |
| 1018 | unsigned sx_max_export_pos_size; |
| 1019 | unsigned sx_max_export_smx_size; |
| 1020 | unsigned sq_num_cf_insts; |
| 1021 | unsigned sx_num_of_sets; |
| 1022 | unsigned sc_prim_fifo_size; |
| 1023 | unsigned sc_hiz_tile_fifo_size; |
| 1024 | unsigned sc_earlyz_tile_fifo_fize; |
| 1025 | unsigned tiling_nbanks; |
| 1026 | unsigned tiling_npipes; |
| 1027 | unsigned tiling_group_size; |
| 1028 | unsigned tile_config; |
| 1029 | struct r100_gpu_lockup lockup; |
| 1030 | }; |
| 1031 | |
| 1032 | struct evergreen_asic { |
| 1033 | unsigned num_ses; |
| 1034 | unsigned max_pipes; |
| 1035 | unsigned max_tile_pipes; |
| 1036 | unsigned max_simds; |
| 1037 | unsigned max_backends; |
| 1038 | unsigned max_gprs; |
| 1039 | unsigned max_threads; |
| 1040 | unsigned max_stack_entries; |
| 1041 | unsigned max_hw_contexts; |
| 1042 | unsigned max_gs_threads; |
| 1043 | unsigned sx_max_export_size; |
| 1044 | unsigned sx_max_export_pos_size; |
| 1045 | unsigned sx_max_export_smx_size; |
| 1046 | unsigned sq_num_cf_insts; |
| 1047 | unsigned sx_num_of_sets; |
| 1048 | unsigned sc_prim_fifo_size; |
| 1049 | unsigned sc_hiz_tile_fifo_size; |
| 1050 | unsigned sc_earlyz_tile_fifo_size; |
| 1051 | unsigned tiling_nbanks; |
| 1052 | unsigned tiling_npipes; |
| 1053 | unsigned tiling_group_size; |
| 1054 | unsigned tile_config; |
| 1055 | struct r100_gpu_lockup lockup; |
| 1056 | }; |
| 1057 | |
| 1058 | struct cayman_asic { |
| 1059 | unsigned max_shader_engines; |
| 1060 | unsigned max_pipes_per_simd; |
| 1061 | unsigned max_tile_pipes; |
| 1062 | unsigned max_simds_per_se; |
| 1063 | unsigned max_backends_per_se; |
| 1064 | unsigned max_texture_channel_caches; |
| 1065 | unsigned max_gprs; |
| 1066 | unsigned max_threads; |
| 1067 | unsigned max_gs_threads; |
| 1068 | unsigned max_stack_entries; |
| 1069 | unsigned sx_num_of_sets; |
| 1070 | unsigned sx_max_export_size; |
| 1071 | unsigned sx_max_export_pos_size; |
| 1072 | unsigned sx_max_export_smx_size; |
| 1073 | unsigned max_hw_contexts; |
| 1074 | unsigned sq_num_cf_insts; |
| 1075 | unsigned sc_prim_fifo_size; |
| 1076 | unsigned sc_hiz_tile_fifo_size; |
| 1077 | unsigned sc_earlyz_tile_fifo_size; |
| 1078 | |
| 1079 | unsigned num_shader_engines; |
| 1080 | unsigned num_shader_pipes_per_simd; |
| 1081 | unsigned num_tile_pipes; |
| 1082 | unsigned num_simds_per_se; |
| 1083 | unsigned num_backends_per_se; |
| 1084 | unsigned backend_disable_mask_per_asic; |
| 1085 | unsigned backend_map; |
| 1086 | unsigned num_texture_channel_caches; |
| 1087 | unsigned mem_max_burst_length_bytes; |
| 1088 | unsigned mem_row_size_in_kb; |
| 1089 | unsigned shader_engine_tile_size; |
| 1090 | unsigned num_gpus; |
| 1091 | unsigned multi_gpu_tile_size; |
| 1092 | |
| 1093 | unsigned tile_config; |
| 1094 | struct r100_gpu_lockup lockup; |
| 1095 | }; |
| 1096 | |
| 1097 | union radeon_asic_config { |
| 1098 | struct r300_asic r300; |
| 1099 | struct r100_asic r100; |
| 1100 | struct r600_asic r600; |
| 1101 | struct rv770_asic rv770; |
| 1102 | struct evergreen_asic evergreen; |
| 1103 | struct cayman_asic cayman; |
| 1104 | }; |
| 1105 | |
| 1106 | /* |
| 1107 | * asic initizalization from radeon_asic.c |
| 1108 | */ |
| 1109 | void radeon_agp_disable(struct radeon_device *rdev); |
| 1110 | int radeon_asic_init(struct radeon_device *rdev); |
| 1111 | |
| 1112 | |
| 1113 | /* |
| 1114 | * IOCTL. |
| 1115 | */ |
| 1116 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, |
| 1117 | struct drm_file *filp); |
| 1118 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, |
| 1119 | struct drm_file *filp); |
| 1120 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 1121 | struct drm_file *file_priv); |
| 1122 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 1123 | struct drm_file *file_priv); |
| 1124 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 1125 | struct drm_file *file_priv); |
| 1126 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 1127 | struct drm_file *file_priv); |
| 1128 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 1129 | struct drm_file *filp); |
| 1130 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1131 | struct drm_file *filp); |
| 1132 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 1133 | struct drm_file *filp); |
| 1134 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, |
| 1135 | struct drm_file *filp); |
| 1136 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
| 1137 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
| 1138 | struct drm_file *filp); |
| 1139 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, |
| 1140 | struct drm_file *filp); |
| 1141 | |
| 1142 | /* VRAM scratch page for HDP bug */ |
| 1143 | struct r700_vram_scratch { |
| 1144 | struct radeon_bo *robj; |
| 1145 | volatile uint32_t *ptr; |
| 1146 | }; |
| 1147 | |
| 1148 | /* |
| 1149 | * Core structure, functions and helpers. |
| 1150 | */ |
| 1151 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
| 1152 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
| 1153 | |
| 1154 | struct radeon_device { |
| 1155 | struct device *dev; |
| 1156 | struct drm_device *ddev; |
| 1157 | struct pci_dev *pdev; |
| 1158 | /* ASIC */ |
| 1159 | union radeon_asic_config config; |
| 1160 | enum radeon_family family; |
| 1161 | unsigned long flags; |
| 1162 | int usec_timeout; |
| 1163 | enum radeon_pll_errata pll_errata; |
| 1164 | int num_gb_pipes; |
| 1165 | int num_z_pipes; |
| 1166 | int disp_priority; |
| 1167 | /* BIOS */ |
| 1168 | uint8_t *bios; |
| 1169 | bool is_atom_bios; |
| 1170 | uint16_t bios_header_start; |
| 1171 | struct radeon_bo *stollen_vga_memory; |
| 1172 | /* Register mmio */ |
| 1173 | resource_size_t rmmio_base; |
| 1174 | resource_size_t rmmio_size; |
| 1175 | void *rmmio; |
| 1176 | radeon_rreg_t mc_rreg; |
| 1177 | radeon_wreg_t mc_wreg; |
| 1178 | radeon_rreg_t pll_rreg; |
| 1179 | radeon_wreg_t pll_wreg; |
| 1180 | uint32_t pcie_reg_mask; |
| 1181 | radeon_rreg_t pciep_rreg; |
| 1182 | radeon_wreg_t pciep_wreg; |
| 1183 | /* io port */ |
| 1184 | void __iomem *rio_mem; |
| 1185 | resource_size_t rio_mem_size; |
| 1186 | struct radeon_clock clock; |
| 1187 | struct radeon_mc mc; |
| 1188 | struct radeon_gart gart; |
| 1189 | struct radeon_mode_info mode_info; |
| 1190 | struct radeon_scratch scratch; |
| 1191 | struct radeon_mman mman; |
| 1192 | struct radeon_fence_driver fence_drv; |
| 1193 | struct radeon_cp cp; |
| 1194 | /* cayman compute rings */ |
| 1195 | struct radeon_cp cp1; |
| 1196 | struct radeon_cp cp2; |
| 1197 | struct radeon_ib_pool ib_pool; |
| 1198 | struct radeon_irq irq; |
| 1199 | struct radeon_asic *asic; |
| 1200 | struct radeon_gem gem; |
| 1201 | struct radeon_pm pm; |
| 1202 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
| 1203 | struct mutex cs_mutex; |
| 1204 | struct radeon_wb wb; |
| 1205 | struct radeon_dummy_page dummy_page; |
| 1206 | bool gpu_lockup; |
| 1207 | bool shutdown; |
| 1208 | bool suspend; |
| 1209 | bool need_dma32; |
| 1210 | bool accel_working; |
| 1211 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
| 1212 | const struct firmware *me_fw; /* all family ME firmware */ |
| 1213 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
| 1214 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
| 1215 | const struct firmware *mc_fw; /* NI MC firmware */ |
| 1216 | struct r600_blit r600_blit; |
| 1217 | struct r700_vram_scratch vram_scratch; |
| 1218 | int msi_enabled; /* msi enabled */ |
| 1219 | struct r600_ih ih; /* r6/700 interrupt ring */ |
| 1220 | struct work_struct hotplug_work; |
| 1221 | int num_crtc; /* number of crtcs */ |
| 1222 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
| 1223 | struct mutex vram_mutex; |
| 1224 | |
| 1225 | /* audio stuff */ |
| 1226 | bool audio_enabled; |
| 1227 | struct timer_list audio_timer; |
| 1228 | int audio_channels; |
| 1229 | int audio_rate; |
| 1230 | int audio_bits_per_sample; |
| 1231 | uint8_t audio_status_bits; |
| 1232 | uint8_t audio_category_code; |
| 1233 | |
| 1234 | struct notifier_block acpi_nb; |
| 1235 | /* only one userspace can use Hyperz features or CMASK at a time */ |
| 1236 | struct drm_file *hyperz_filp; |
| 1237 | struct drm_file *cmask_filp; |
| 1238 | /* i2c buses */ |
| 1239 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; |
| 1240 | }; |
| 1241 | |
| 1242 | int radeon_device_init(struct radeon_device *rdev, |
| 1243 | struct drm_device *ddev, |
| 1244 | struct pci_dev *pdev, |
| 1245 | uint32_t flags); |
| 1246 | void radeon_device_fini(struct radeon_device *rdev); |
| 1247 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
| 1248 | |
| 1249 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
| 1250 | { |
| 1251 | if (reg < rdev->rmmio_size) |
| 1252 | return readl(((void __iomem *)rdev->rmmio) + reg); |
| 1253 | else { |
| 1254 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
| 1255 | return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
| 1256 | } |
| 1257 | } |
| 1258 | |
| 1259 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| 1260 | { |
| 1261 | if (reg < rdev->rmmio_size) |
| 1262 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
| 1263 | else { |
| 1264 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
| 1265 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
| 1266 | } |
| 1267 | } |
| 1268 | |
| 1269 | static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) |
| 1270 | { |
| 1271 | if (reg < rdev->rio_mem_size) |
| 1272 | return ioread32(rdev->rio_mem + reg); |
| 1273 | else { |
| 1274 | iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); |
| 1275 | return ioread32(rdev->rio_mem + RADEON_MM_DATA); |
| 1276 | } |
| 1277 | } |
| 1278 | |
| 1279 | static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
| 1280 | { |
| 1281 | if (reg < rdev->rio_mem_size) |
| 1282 | iowrite32(v, rdev->rio_mem + reg); |
| 1283 | else { |
| 1284 | iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); |
| 1285 | iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); |
| 1286 | } |
| 1287 | } |
| 1288 | |
| 1289 | /* |
| 1290 | * Cast helper |
| 1291 | */ |
| 1292 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) |
| 1293 | |
| 1294 | /* |
| 1295 | * Registers read & write functions. |
| 1296 | */ |
| 1297 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) |
| 1298 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) |
| 1299 | #define RREG16(reg) readw(((void __iomem *)rdev->rmmio) + (reg)) |
| 1300 | #define WREG16(reg, v) writew(v, ((void __iomem *)rdev->rmmio) + (reg)) |
| 1301 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
| 1302 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) |
| 1303 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
| 1304 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| 1305 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| 1306 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
| 1307 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
| 1308 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
| 1309 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
| 1310 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
| 1311 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
| 1312 | #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) |
| 1313 | #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) |
| 1314 | #define WREG32_P(reg, val, mask) \ |
| 1315 | do { \ |
| 1316 | uint32_t tmp_ = RREG32(reg); \ |
| 1317 | tmp_ &= (mask); \ |
| 1318 | tmp_ |= ((val) & ~(mask)); \ |
| 1319 | WREG32(reg, tmp_); \ |
| 1320 | } while (0) |
| 1321 | #define WREG32_PLL_P(reg, val, mask) \ |
| 1322 | do { \ |
| 1323 | uint32_t tmp_ = RREG32_PLL(reg); \ |
| 1324 | tmp_ &= (mask); \ |
| 1325 | tmp_ |= ((val) & ~(mask)); \ |
| 1326 | WREG32_PLL(reg, tmp_); \ |
| 1327 | } while (0) |
| 1328 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) |
| 1329 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
| 1330 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) |
| 1331 | |
| 1332 | /* |
| 1333 | * Indirect registers accessor |
| 1334 | */ |
| 1335 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
| 1336 | { |
| 1337 | uint32_t r; |
| 1338 | |
| 1339 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
| 1340 | r = RREG32(RADEON_PCIE_DATA); |
| 1341 | return r; |
| 1342 | } |
| 1343 | |
| 1344 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| 1345 | { |
| 1346 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
| 1347 | WREG32(RADEON_PCIE_DATA, (v)); |
| 1348 | } |
| 1349 | |
| 1350 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
| 1351 | |
| 1352 | |
| 1353 | /* |
| 1354 | * ASICs helpers. |
| 1355 | */ |
| 1356 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
| 1357 | (rdev->pdev->device == 0x5969)) |
| 1358 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
| 1359 | (rdev->family == CHIP_RV200) || \ |
| 1360 | (rdev->family == CHIP_RS100) || \ |
| 1361 | (rdev->family == CHIP_RS200) || \ |
| 1362 | (rdev->family == CHIP_RV250) || \ |
| 1363 | (rdev->family == CHIP_RV280) || \ |
| 1364 | (rdev->family == CHIP_RS300)) |
| 1365 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
| 1366 | (rdev->family == CHIP_RV350) || \ |
| 1367 | (rdev->family == CHIP_R350) || \ |
| 1368 | (rdev->family == CHIP_RV380) || \ |
| 1369 | (rdev->family == CHIP_R420) || \ |
| 1370 | (rdev->family == CHIP_R423) || \ |
| 1371 | (rdev->family == CHIP_RV410) || \ |
| 1372 | (rdev->family == CHIP_RS400) || \ |
| 1373 | (rdev->family == CHIP_RS480)) |
| 1374 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
| 1375 | (rdev->ddev->pdev->device == 0x9443) || \ |
| 1376 | (rdev->ddev->pdev->device == 0x944B) || \ |
| 1377 | (rdev->ddev->pdev->device == 0x9506) || \ |
| 1378 | (rdev->ddev->pdev->device == 0x9509) || \ |
| 1379 | (rdev->ddev->pdev->device == 0x950F) || \ |
| 1380 | (rdev->ddev->pdev->device == 0x689C) || \ |
| 1381 | (rdev->ddev->pdev->device == 0x689D)) |
| 1382 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
| 1383 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
| 1384 | (rdev->family == CHIP_RS690) || \ |
| 1385 | (rdev->family == CHIP_RS740) || \ |
| 1386 | (rdev->family >= CHIP_R600)) |
| 1387 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
| 1388 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
| 1389 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
| 1390 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
| 1391 | (rdev->flags & RADEON_IS_IGP)) |
| 1392 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
| 1393 | |
| 1394 | /* |
| 1395 | * BIOS helpers. |
| 1396 | */ |
| 1397 | #define RBIOS8(i) (rdev->bios[i]) |
| 1398 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
| 1399 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
| 1400 | |
| 1401 | int radeon_combios_init(struct radeon_device *rdev); |
| 1402 | void radeon_combios_fini(struct radeon_device *rdev); |
| 1403 | int radeon_atombios_init(struct radeon_device *rdev); |
| 1404 | void radeon_atombios_fini(struct radeon_device *rdev); |
| 1405 | |
| 1406 | |
| 1407 | /* |
| 1408 | * RING helpers. |
| 1409 | */ |
| 1410 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
| 1411 | { |
| 1412 | #if DRM_DEBUG_CODE |
| 1413 | if (rdev->cp.count_dw <= 0) { |
| 1414 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); |
| 1415 | } |
| 1416 | #endif |
| 1417 | rdev->cp.ring[rdev->cp.wptr++] = v; |
| 1418 | rdev->cp.wptr &= rdev->cp.ptr_mask; |
| 1419 | rdev->cp.count_dw--; |
| 1420 | rdev->cp.ring_free_dw--; |
| 1421 | } |
| 1422 | |
| 1423 | |
| 1424 | /* |
| 1425 | * ASICs macro. |
| 1426 | */ |
| 1427 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
| 1428 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
| 1429 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
| 1430 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
| 1431 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
| 1432 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
| 1433 | #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev)) |
| 1434 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
| 1435 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
| 1436 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
| 1437 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
| 1438 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
| 1439 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
| 1440 | #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) |
| 1441 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
| 1442 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) |
| 1443 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
| 1444 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
| 1445 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) |
| 1446 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) |
| 1447 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) |
| 1448 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) |
| 1449 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
| 1450 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) |
| 1451 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) |
| 1452 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev)) |
| 1453 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
| 1454 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) |
| 1455 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
| 1456 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) |
| 1457 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
| 1458 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) |
| 1459 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) |
| 1460 | #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) |
| 1461 | #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) |
| 1462 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
| 1463 | #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev)) |
| 1464 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev)) |
| 1465 | #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev)) |
| 1466 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev)) |
| 1467 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev)) |
| 1468 | #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc)) |
| 1469 | #define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base)) |
| 1470 | #define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc)) |
| 1471 | |
| 1472 | /* Common functions */ |
| 1473 | /* AGP */ |
| 1474 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
| 1475 | extern void radeon_agp_disable(struct radeon_device *rdev); |
| 1476 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
| 1477 | extern void radeon_gart_restore(struct radeon_device *rdev); |
| 1478 | extern int radeon_modeset_init(struct radeon_device *rdev); |
| 1479 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
| 1480 | extern bool radeon_card_posted(struct radeon_device *rdev); |
| 1481 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
| 1482 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
| 1483 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
| 1484 | extern void radeon_scratch_init(struct radeon_device *rdev); |
| 1485 | extern void radeon_wb_fini(struct radeon_device *rdev); |
| 1486 | extern int radeon_wb_init(struct radeon_device *rdev); |
| 1487 | extern void radeon_wb_disable(struct radeon_device *rdev); |
| 1488 | extern void radeon_surface_init(struct radeon_device *rdev); |
| 1489 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
| 1490 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
| 1491 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
| 1492 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
| 1493 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
| 1494 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
| 1495 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
| 1496 | extern int radeon_resume_kms(struct drm_device *dev); |
| 1497 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); |
| 1498 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
| 1499 | |
| 1500 | /* |
| 1501 | * r600 functions used by radeon_encoder.c |
| 1502 | */ |
| 1503 | extern void r600_hdmi_enable(struct drm_encoder *encoder); |
| 1504 | extern void r600_hdmi_disable(struct drm_encoder *encoder); |
| 1505 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
| 1506 | |
| 1507 | extern int ni_init_microcode(struct radeon_device *rdev); |
| 1508 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
| 1509 | |
| 1510 | /* radeon_acpi.c */ |
| 1511 | #if defined(CONFIG_ACPI) |
| 1512 | extern int radeon_acpi_init(struct radeon_device *rdev); |
| 1513 | #else |
| 1514 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } |
| 1515 | #endif |
| 1516 | |
| 1517 | #include "radeon_object.h" |
| 1518 | |
| 1519 | #endif |