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drm/radeon: fix IB debugfs files for multiple cards
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_asic.c
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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/console.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
33#include <linux/vgaarb.h>
34#include <linux/vga_switcheroo.h>
35#include "radeon_reg.h"
36#include "radeon.h"
37#include "radeon_asic.h"
38#include "atom.h"
39
40/*
41 * Registers accessors functions.
42 */
43static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
44{
45 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
46 BUG_ON(1);
47 return 0;
48}
49
50static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
51{
52 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
53 reg, v);
54 BUG_ON(1);
55}
56
57static void radeon_register_accessor_init(struct radeon_device *rdev)
58{
59 rdev->mc_rreg = &radeon_invalid_rreg;
60 rdev->mc_wreg = &radeon_invalid_wreg;
61 rdev->pll_rreg = &radeon_invalid_rreg;
62 rdev->pll_wreg = &radeon_invalid_wreg;
63 rdev->pciep_rreg = &radeon_invalid_rreg;
64 rdev->pciep_wreg = &radeon_invalid_wreg;
65
66 /* Don't change order as we are overridding accessor. */
67 if (rdev->family < CHIP_RV515) {
68 rdev->pcie_reg_mask = 0xff;
69 } else {
70 rdev->pcie_reg_mask = 0x7ff;
71 }
72 /* FIXME: not sure here */
73 if (rdev->family <= CHIP_R580) {
74 rdev->pll_rreg = &r100_pll_rreg;
75 rdev->pll_wreg = &r100_pll_wreg;
76 }
77 if (rdev->family >= CHIP_R420) {
78 rdev->mc_rreg = &r420_mc_rreg;
79 rdev->mc_wreg = &r420_mc_wreg;
80 }
81 if (rdev->family >= CHIP_RV515) {
82 rdev->mc_rreg = &rv515_mc_rreg;
83 rdev->mc_wreg = &rv515_mc_wreg;
84 }
85 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
86 rdev->mc_rreg = &rs400_mc_rreg;
87 rdev->mc_wreg = &rs400_mc_wreg;
88 }
89 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
90 rdev->mc_rreg = &rs690_mc_rreg;
91 rdev->mc_wreg = &rs690_mc_wreg;
92 }
93 if (rdev->family == CHIP_RS600) {
94 rdev->mc_rreg = &rs600_mc_rreg;
95 rdev->mc_wreg = &rs600_mc_wreg;
96 }
97 if (rdev->family >= CHIP_R600) {
98 rdev->pciep_rreg = &r600_pciep_rreg;
99 rdev->pciep_wreg = &r600_pciep_wreg;
100 }
101}
102
103
104/* helper to disable agp */
105void radeon_agp_disable(struct radeon_device *rdev)
106{
107 rdev->flags &= ~RADEON_IS_AGP;
108 if (rdev->family >= CHIP_R600) {
109 DRM_INFO("Forcing AGP to PCIE mode\n");
110 rdev->flags |= RADEON_IS_PCIE;
111 } else if (rdev->family >= CHIP_RV515 ||
112 rdev->family == CHIP_RV380 ||
113 rdev->family == CHIP_RV410 ||
114 rdev->family == CHIP_R423) {
115 DRM_INFO("Forcing AGP to PCIE mode\n");
116 rdev->flags |= RADEON_IS_PCIE;
117 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
118 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
119 } else {
120 DRM_INFO("Forcing AGP to PCI mode\n");
121 rdev->flags |= RADEON_IS_PCI;
122 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
123 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
124 }
125 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
126}
127
128/*
129 * ASIC
130 */
131static struct radeon_asic r100_asic = {
132 .init = &r100_init,
133 .fini = &r100_fini,
134 .suspend = &r100_suspend,
135 .resume = &r100_resume,
136 .vga_set_state = &r100_vga_set_state,
137 .gpu_is_lockup = &r100_gpu_is_lockup,
138 .asic_reset = &r100_asic_reset,
139 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
140 .gart_set_page = &r100_pci_gart_set_page,
141 .ring_start = &r100_ring_start,
142 .ring_test = &r100_ring_test,
143 .ring = {
144 [RADEON_RING_TYPE_GFX_INDEX] = {
145 .ib_execute = &r100_ring_ib_execute,
146 .emit_fence = &r100_fence_ring_emit,
147 .emit_semaphore = &r100_semaphore_ring_emit,
148 .cs_parse = &r100_cs_parse,
149 }
150 },
151 .irq_set = &r100_irq_set,
152 .irq_process = &r100_irq_process,
153 .get_vblank_counter = &r100_get_vblank_counter,
154 .copy_blit = &r100_copy_blit,
155 .copy_dma = NULL,
156 .copy = &r100_copy_blit,
157 .get_engine_clock = &radeon_legacy_get_engine_clock,
158 .set_engine_clock = &radeon_legacy_set_engine_clock,
159 .get_memory_clock = &radeon_legacy_get_memory_clock,
160 .set_memory_clock = NULL,
161 .get_pcie_lanes = NULL,
162 .set_pcie_lanes = NULL,
163 .set_clock_gating = &radeon_legacy_set_clock_gating,
164 .set_surface_reg = r100_set_surface_reg,
165 .clear_surface_reg = r100_clear_surface_reg,
166 .bandwidth_update = &r100_bandwidth_update,
167 .hpd = {
168 .init = &r100_hpd_init,
169 .fini = &r100_hpd_fini,
170 .sense = &r100_hpd_sense,
171 .set_polarity = &r100_hpd_set_polarity,
172 },
173 .ioctl_wait_idle = NULL,
174 .gui_idle = &r100_gui_idle,
175 .pm = {
176 .misc = &r100_pm_misc,
177 .prepare = &r100_pm_prepare,
178 .finish = &r100_pm_finish,
179 .init_profile = &r100_pm_init_profile,
180 .get_dynpm_state = &r100_pm_get_dynpm_state,
181 },
182 .pflip = {
183 .pre_page_flip = &r100_pre_page_flip,
184 .page_flip = &r100_page_flip,
185 .post_page_flip = &r100_post_page_flip,
186 },
187 .wait_for_vblank = &r100_wait_for_vblank,
188 .mc_wait_for_idle = &r100_mc_wait_for_idle,
189};
190
191static struct radeon_asic r200_asic = {
192 .init = &r100_init,
193 .fini = &r100_fini,
194 .suspend = &r100_suspend,
195 .resume = &r100_resume,
196 .vga_set_state = &r100_vga_set_state,
197 .gpu_is_lockup = &r100_gpu_is_lockup,
198 .asic_reset = &r100_asic_reset,
199 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
200 .gart_set_page = &r100_pci_gart_set_page,
201 .ring_start = &r100_ring_start,
202 .ring_test = &r100_ring_test,
203 .ring = {
204 [RADEON_RING_TYPE_GFX_INDEX] = {
205 .ib_execute = &r100_ring_ib_execute,
206 .emit_fence = &r100_fence_ring_emit,
207 .emit_semaphore = &r100_semaphore_ring_emit,
208 .cs_parse = &r100_cs_parse,
209 }
210 },
211 .irq_set = &r100_irq_set,
212 .irq_process = &r100_irq_process,
213 .get_vblank_counter = &r100_get_vblank_counter,
214 .copy_blit = &r100_copy_blit,
215 .copy_dma = &r200_copy_dma,
216 .copy = &r100_copy_blit,
217 .get_engine_clock = &radeon_legacy_get_engine_clock,
218 .set_engine_clock = &radeon_legacy_set_engine_clock,
219 .get_memory_clock = &radeon_legacy_get_memory_clock,
220 .set_memory_clock = NULL,
221 .set_pcie_lanes = NULL,
222 .set_clock_gating = &radeon_legacy_set_clock_gating,
223 .set_surface_reg = r100_set_surface_reg,
224 .clear_surface_reg = r100_clear_surface_reg,
225 .bandwidth_update = &r100_bandwidth_update,
226 .hpd = {
227 .init = &r100_hpd_init,
228 .fini = &r100_hpd_fini,
229 .sense = &r100_hpd_sense,
230 .set_polarity = &r100_hpd_set_polarity,
231 },
232 .ioctl_wait_idle = NULL,
233 .gui_idle = &r100_gui_idle,
234 .pm = {
235 .misc = &r100_pm_misc,
236 .prepare = &r100_pm_prepare,
237 .finish = &r100_pm_finish,
238 .init_profile = &r100_pm_init_profile,
239 .get_dynpm_state = &r100_pm_get_dynpm_state,
240 },
241 .pflip = {
242 .pre_page_flip = &r100_pre_page_flip,
243 .page_flip = &r100_page_flip,
244 .post_page_flip = &r100_post_page_flip,
245 },
246 .wait_for_vblank = &r100_wait_for_vblank,
247 .mc_wait_for_idle = &r100_mc_wait_for_idle,
248};
249
250static struct radeon_asic r300_asic = {
251 .init = &r300_init,
252 .fini = &r300_fini,
253 .suspend = &r300_suspend,
254 .resume = &r300_resume,
255 .vga_set_state = &r100_vga_set_state,
256 .gpu_is_lockup = &r300_gpu_is_lockup,
257 .asic_reset = &r300_asic_reset,
258 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
259 .gart_set_page = &r100_pci_gart_set_page,
260 .ring_start = &r300_ring_start,
261 .ring_test = &r100_ring_test,
262 .ring = {
263 [RADEON_RING_TYPE_GFX_INDEX] = {
264 .ib_execute = &r100_ring_ib_execute,
265 .emit_fence = &r300_fence_ring_emit,
266 .emit_semaphore = &r100_semaphore_ring_emit,
267 .cs_parse = &r300_cs_parse,
268 }
269 },
270 .irq_set = &r100_irq_set,
271 .irq_process = &r100_irq_process,
272 .get_vblank_counter = &r100_get_vblank_counter,
273 .copy_blit = &r100_copy_blit,
274 .copy_dma = &r200_copy_dma,
275 .copy = &r100_copy_blit,
276 .get_engine_clock = &radeon_legacy_get_engine_clock,
277 .set_engine_clock = &radeon_legacy_set_engine_clock,
278 .get_memory_clock = &radeon_legacy_get_memory_clock,
279 .set_memory_clock = NULL,
280 .get_pcie_lanes = &rv370_get_pcie_lanes,
281 .set_pcie_lanes = &rv370_set_pcie_lanes,
282 .set_clock_gating = &radeon_legacy_set_clock_gating,
283 .set_surface_reg = r100_set_surface_reg,
284 .clear_surface_reg = r100_clear_surface_reg,
285 .bandwidth_update = &r100_bandwidth_update,
286 .hpd = {
287 .init = &r100_hpd_init,
288 .fini = &r100_hpd_fini,
289 .sense = &r100_hpd_sense,
290 .set_polarity = &r100_hpd_set_polarity,
291 },
292 .ioctl_wait_idle = NULL,
293 .gui_idle = &r100_gui_idle,
294 .pm = {
295 .misc = &r100_pm_misc,
296 .prepare = &r100_pm_prepare,
297 .finish = &r100_pm_finish,
298 .init_profile = &r100_pm_init_profile,
299 .get_dynpm_state = &r100_pm_get_dynpm_state,
300 },
301 .pflip = {
302 .pre_page_flip = &r100_pre_page_flip,
303 .page_flip = &r100_page_flip,
304 .post_page_flip = &r100_post_page_flip,
305 },
306 .wait_for_vblank = &r100_wait_for_vblank,
307 .mc_wait_for_idle = &r300_mc_wait_for_idle,
308};
309
310static struct radeon_asic r300_asic_pcie = {
311 .init = &r300_init,
312 .fini = &r300_fini,
313 .suspend = &r300_suspend,
314 .resume = &r300_resume,
315 .vga_set_state = &r100_vga_set_state,
316 .gpu_is_lockup = &r300_gpu_is_lockup,
317 .asic_reset = &r300_asic_reset,
318 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
319 .gart_set_page = &rv370_pcie_gart_set_page,
320 .ring_start = &r300_ring_start,
321 .ring_test = &r100_ring_test,
322 .ring = {
323 [RADEON_RING_TYPE_GFX_INDEX] = {
324 .ib_execute = &r100_ring_ib_execute,
325 .emit_fence = &r300_fence_ring_emit,
326 .emit_semaphore = &r100_semaphore_ring_emit,
327 .cs_parse = &r300_cs_parse,
328 }
329 },
330 .irq_set = &r100_irq_set,
331 .irq_process = &r100_irq_process,
332 .get_vblank_counter = &r100_get_vblank_counter,
333 .copy_blit = &r100_copy_blit,
334 .copy_dma = &r200_copy_dma,
335 .copy = &r100_copy_blit,
336 .get_engine_clock = &radeon_legacy_get_engine_clock,
337 .set_engine_clock = &radeon_legacy_set_engine_clock,
338 .get_memory_clock = &radeon_legacy_get_memory_clock,
339 .set_memory_clock = NULL,
340 .set_pcie_lanes = &rv370_set_pcie_lanes,
341 .set_clock_gating = &radeon_legacy_set_clock_gating,
342 .set_surface_reg = r100_set_surface_reg,
343 .clear_surface_reg = r100_clear_surface_reg,
344 .bandwidth_update = &r100_bandwidth_update,
345 .hpd = {
346 .init = &r100_hpd_init,
347 .fini = &r100_hpd_fini,
348 .sense = &r100_hpd_sense,
349 .set_polarity = &r100_hpd_set_polarity,
350 },
351 .ioctl_wait_idle = NULL,
352 .gui_idle = &r100_gui_idle,
353 .pm = {
354 .misc = &r100_pm_misc,
355 .prepare = &r100_pm_prepare,
356 .finish = &r100_pm_finish,
357 .init_profile = &r100_pm_init_profile,
358 .get_dynpm_state = &r100_pm_get_dynpm_state,
359 },
360 .pflip = {
361 .pre_page_flip = &r100_pre_page_flip,
362 .page_flip = &r100_page_flip,
363 .post_page_flip = &r100_post_page_flip,
364 },
365 .wait_for_vblank = &r100_wait_for_vblank,
366 .mc_wait_for_idle = &r300_mc_wait_for_idle,
367};
368
369static struct radeon_asic r420_asic = {
370 .init = &r420_init,
371 .fini = &r420_fini,
372 .suspend = &r420_suspend,
373 .resume = &r420_resume,
374 .vga_set_state = &r100_vga_set_state,
375 .gpu_is_lockup = &r300_gpu_is_lockup,
376 .asic_reset = &r300_asic_reset,
377 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
378 .gart_set_page = &rv370_pcie_gart_set_page,
379 .ring_start = &r300_ring_start,
380 .ring_test = &r100_ring_test,
381 .ring = {
382 [RADEON_RING_TYPE_GFX_INDEX] = {
383 .ib_execute = &r100_ring_ib_execute,
384 .emit_fence = &r300_fence_ring_emit,
385 .emit_semaphore = &r100_semaphore_ring_emit,
386 .cs_parse = &r300_cs_parse,
387 }
388 },
389 .irq_set = &r100_irq_set,
390 .irq_process = &r100_irq_process,
391 .get_vblank_counter = &r100_get_vblank_counter,
392 .copy_blit = &r100_copy_blit,
393 .copy_dma = &r200_copy_dma,
394 .copy = &r100_copy_blit,
395 .get_engine_clock = &radeon_atom_get_engine_clock,
396 .set_engine_clock = &radeon_atom_set_engine_clock,
397 .get_memory_clock = &radeon_atom_get_memory_clock,
398 .set_memory_clock = &radeon_atom_set_memory_clock,
399 .get_pcie_lanes = &rv370_get_pcie_lanes,
400 .set_pcie_lanes = &rv370_set_pcie_lanes,
401 .set_clock_gating = &radeon_atom_set_clock_gating,
402 .set_surface_reg = r100_set_surface_reg,
403 .clear_surface_reg = r100_clear_surface_reg,
404 .bandwidth_update = &r100_bandwidth_update,
405 .hpd = {
406 .init = &r100_hpd_init,
407 .fini = &r100_hpd_fini,
408 .sense = &r100_hpd_sense,
409 .set_polarity = &r100_hpd_set_polarity,
410 },
411 .ioctl_wait_idle = NULL,
412 .gui_idle = &r100_gui_idle,
413 .pm = {
414 .misc = &r100_pm_misc,
415 .prepare = &r100_pm_prepare,
416 .finish = &r100_pm_finish,
417 .init_profile = &r420_pm_init_profile,
418 .get_dynpm_state = &r100_pm_get_dynpm_state,
419 },
420 .pflip = {
421 .pre_page_flip = &r100_pre_page_flip,
422 .page_flip = &r100_page_flip,
423 .post_page_flip = &r100_post_page_flip,
424 },
425 .wait_for_vblank = &r100_wait_for_vblank,
426 .mc_wait_for_idle = &r300_mc_wait_for_idle,
427};
428
429static struct radeon_asic rs400_asic = {
430 .init = &rs400_init,
431 .fini = &rs400_fini,
432 .suspend = &rs400_suspend,
433 .resume = &rs400_resume,
434 .vga_set_state = &r100_vga_set_state,
435 .gpu_is_lockup = &r300_gpu_is_lockup,
436 .asic_reset = &r300_asic_reset,
437 .gart_tlb_flush = &rs400_gart_tlb_flush,
438 .gart_set_page = &rs400_gart_set_page,
439 .ring_start = &r300_ring_start,
440 .ring_test = &r100_ring_test,
441 .ring = {
442 [RADEON_RING_TYPE_GFX_INDEX] = {
443 .ib_execute = &r100_ring_ib_execute,
444 .emit_fence = &r300_fence_ring_emit,
445 .emit_semaphore = &r100_semaphore_ring_emit,
446 .cs_parse = &r300_cs_parse,
447 }
448 },
449 .irq_set = &r100_irq_set,
450 .irq_process = &r100_irq_process,
451 .get_vblank_counter = &r100_get_vblank_counter,
452 .copy_blit = &r100_copy_blit,
453 .copy_dma = &r200_copy_dma,
454 .copy = &r100_copy_blit,
455 .get_engine_clock = &radeon_legacy_get_engine_clock,
456 .set_engine_clock = &radeon_legacy_set_engine_clock,
457 .get_memory_clock = &radeon_legacy_get_memory_clock,
458 .set_memory_clock = NULL,
459 .get_pcie_lanes = NULL,
460 .set_pcie_lanes = NULL,
461 .set_clock_gating = &radeon_legacy_set_clock_gating,
462 .set_surface_reg = r100_set_surface_reg,
463 .clear_surface_reg = r100_clear_surface_reg,
464 .bandwidth_update = &r100_bandwidth_update,
465 .hpd = {
466 .init = &r100_hpd_init,
467 .fini = &r100_hpd_fini,
468 .sense = &r100_hpd_sense,
469 .set_polarity = &r100_hpd_set_polarity,
470 },
471 .ioctl_wait_idle = NULL,
472 .gui_idle = &r100_gui_idle,
473 .pm = {
474 .misc = &r100_pm_misc,
475 .prepare = &r100_pm_prepare,
476 .finish = &r100_pm_finish,
477 .init_profile = &r100_pm_init_profile,
478 .get_dynpm_state = &r100_pm_get_dynpm_state,
479 },
480 .pflip = {
481 .pre_page_flip = &r100_pre_page_flip,
482 .page_flip = &r100_page_flip,
483 .post_page_flip = &r100_post_page_flip,
484 },
485 .wait_for_vblank = &r100_wait_for_vblank,
486 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
487};
488
489static struct radeon_asic rs600_asic = {
490 .init = &rs600_init,
491 .fini = &rs600_fini,
492 .suspend = &rs600_suspend,
493 .resume = &rs600_resume,
494 .vga_set_state = &r100_vga_set_state,
495 .gpu_is_lockup = &r300_gpu_is_lockup,
496 .asic_reset = &rs600_asic_reset,
497 .gart_tlb_flush = &rs600_gart_tlb_flush,
498 .gart_set_page = &rs600_gart_set_page,
499 .ring_start = &r300_ring_start,
500 .ring_test = &r100_ring_test,
501 .ring = {
502 [RADEON_RING_TYPE_GFX_INDEX] = {
503 .ib_execute = &r100_ring_ib_execute,
504 .emit_fence = &r300_fence_ring_emit,
505 .emit_semaphore = &r100_semaphore_ring_emit,
506 .cs_parse = &r300_cs_parse,
507 }
508 },
509 .irq_set = &rs600_irq_set,
510 .irq_process = &rs600_irq_process,
511 .get_vblank_counter = &rs600_get_vblank_counter,
512 .copy_blit = &r100_copy_blit,
513 .copy_dma = &r200_copy_dma,
514 .copy = &r100_copy_blit,
515 .get_engine_clock = &radeon_atom_get_engine_clock,
516 .set_engine_clock = &radeon_atom_set_engine_clock,
517 .get_memory_clock = &radeon_atom_get_memory_clock,
518 .set_memory_clock = &radeon_atom_set_memory_clock,
519 .get_pcie_lanes = NULL,
520 .set_pcie_lanes = NULL,
521 .set_clock_gating = &radeon_atom_set_clock_gating,
522 .set_surface_reg = r100_set_surface_reg,
523 .clear_surface_reg = r100_clear_surface_reg,
524 .bandwidth_update = &rs600_bandwidth_update,
525 .hpd = {
526 .init = &rs600_hpd_init,
527 .fini = &rs600_hpd_fini,
528 .sense = &rs600_hpd_sense,
529 .set_polarity = &rs600_hpd_set_polarity,
530 },
531 .ioctl_wait_idle = NULL,
532 .gui_idle = &r100_gui_idle,
533 .pm = {
534 .misc = &rs600_pm_misc,
535 .prepare = &rs600_pm_prepare,
536 .finish = &rs600_pm_finish,
537 .init_profile = &r420_pm_init_profile,
538 .get_dynpm_state = &r100_pm_get_dynpm_state,
539 },
540 .pflip = {
541 .pre_page_flip = &rs600_pre_page_flip,
542 .page_flip = &rs600_page_flip,
543 .post_page_flip = &rs600_post_page_flip,
544 },
545 .wait_for_vblank = &avivo_wait_for_vblank,
546 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
547};
548
549static struct radeon_asic rs690_asic = {
550 .init = &rs690_init,
551 .fini = &rs690_fini,
552 .suspend = &rs690_suspend,
553 .resume = &rs690_resume,
554 .vga_set_state = &r100_vga_set_state,
555 .gpu_is_lockup = &r300_gpu_is_lockup,
556 .asic_reset = &rs600_asic_reset,
557 .gart_tlb_flush = &rs400_gart_tlb_flush,
558 .gart_set_page = &rs400_gart_set_page,
559 .ring_start = &r300_ring_start,
560 .ring_test = &r100_ring_test,
561 .ring = {
562 [RADEON_RING_TYPE_GFX_INDEX] = {
563 .ib_execute = &r100_ring_ib_execute,
564 .emit_fence = &r300_fence_ring_emit,
565 .emit_semaphore = &r100_semaphore_ring_emit,
566 .cs_parse = &r300_cs_parse,
567 }
568 },
569 .irq_set = &rs600_irq_set,
570 .irq_process = &rs600_irq_process,
571 .get_vblank_counter = &rs600_get_vblank_counter,
572 .copy_blit = &r100_copy_blit,
573 .copy_dma = &r200_copy_dma,
574 .copy = &r200_copy_dma,
575 .get_engine_clock = &radeon_atom_get_engine_clock,
576 .set_engine_clock = &radeon_atom_set_engine_clock,
577 .get_memory_clock = &radeon_atom_get_memory_clock,
578 .set_memory_clock = &radeon_atom_set_memory_clock,
579 .get_pcie_lanes = NULL,
580 .set_pcie_lanes = NULL,
581 .set_clock_gating = &radeon_atom_set_clock_gating,
582 .set_surface_reg = r100_set_surface_reg,
583 .clear_surface_reg = r100_clear_surface_reg,
584 .bandwidth_update = &rs690_bandwidth_update,
585 .hpd = {
586 .init = &rs600_hpd_init,
587 .fini = &rs600_hpd_fini,
588 .sense = &rs600_hpd_sense,
589 .set_polarity = &rs600_hpd_set_polarity,
590 },
591 .ioctl_wait_idle = NULL,
592 .gui_idle = &r100_gui_idle,
593 .pm = {
594 .misc = &rs600_pm_misc,
595 .prepare = &rs600_pm_prepare,
596 .finish = &rs600_pm_finish,
597 .init_profile = &r420_pm_init_profile,
598 .get_dynpm_state = &r100_pm_get_dynpm_state,
599 },
600 .pflip = {
601 .pre_page_flip = &rs600_pre_page_flip,
602 .page_flip = &rs600_page_flip,
603 .post_page_flip = &rs600_post_page_flip,
604 },
605 .wait_for_vblank = &avivo_wait_for_vblank,
606 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
607};
608
609static struct radeon_asic rv515_asic = {
610 .init = &rv515_init,
611 .fini = &rv515_fini,
612 .suspend = &rv515_suspend,
613 .resume = &rv515_resume,
614 .vga_set_state = &r100_vga_set_state,
615 .gpu_is_lockup = &r300_gpu_is_lockup,
616 .asic_reset = &rs600_asic_reset,
617 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
618 .gart_set_page = &rv370_pcie_gart_set_page,
619 .ring_start = &rv515_ring_start,
620 .ring_test = &r100_ring_test,
621 .ring = {
622 [RADEON_RING_TYPE_GFX_INDEX] = {
623 .ib_execute = &r100_ring_ib_execute,
624 .emit_fence = &r300_fence_ring_emit,
625 .emit_semaphore = &r100_semaphore_ring_emit,
626 .cs_parse = &r300_cs_parse,
627 }
628 },
629 .irq_set = &rs600_irq_set,
630 .irq_process = &rs600_irq_process,
631 .get_vblank_counter = &rs600_get_vblank_counter,
632 .copy_blit = &r100_copy_blit,
633 .copy_dma = &r200_copy_dma,
634 .copy = &r100_copy_blit,
635 .get_engine_clock = &radeon_atom_get_engine_clock,
636 .set_engine_clock = &radeon_atom_set_engine_clock,
637 .get_memory_clock = &radeon_atom_get_memory_clock,
638 .set_memory_clock = &radeon_atom_set_memory_clock,
639 .get_pcie_lanes = &rv370_get_pcie_lanes,
640 .set_pcie_lanes = &rv370_set_pcie_lanes,
641 .set_clock_gating = &radeon_atom_set_clock_gating,
642 .set_surface_reg = r100_set_surface_reg,
643 .clear_surface_reg = r100_clear_surface_reg,
644 .bandwidth_update = &rv515_bandwidth_update,
645 .hpd = {
646 .init = &rs600_hpd_init,
647 .fini = &rs600_hpd_fini,
648 .sense = &rs600_hpd_sense,
649 .set_polarity = &rs600_hpd_set_polarity,
650 },
651 .ioctl_wait_idle = NULL,
652 .gui_idle = &r100_gui_idle,
653 .pm = {
654 .misc = &rs600_pm_misc,
655 .prepare = &rs600_pm_prepare,
656 .finish = &rs600_pm_finish,
657 .init_profile = &r420_pm_init_profile,
658 .get_dynpm_state = &r100_pm_get_dynpm_state,
659 },
660 .pflip = {
661 .pre_page_flip = &rs600_pre_page_flip,
662 .page_flip = &rs600_page_flip,
663 .post_page_flip = &rs600_post_page_flip,
664 },
665 .wait_for_vblank = &avivo_wait_for_vblank,
666 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
667};
668
669static struct radeon_asic r520_asic = {
670 .init = &r520_init,
671 .fini = &rv515_fini,
672 .suspend = &rv515_suspend,
673 .resume = &r520_resume,
674 .vga_set_state = &r100_vga_set_state,
675 .gpu_is_lockup = &r300_gpu_is_lockup,
676 .asic_reset = &rs600_asic_reset,
677 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
678 .gart_set_page = &rv370_pcie_gart_set_page,
679 .ring_start = &rv515_ring_start,
680 .ring_test = &r100_ring_test,
681 .ring = {
682 [RADEON_RING_TYPE_GFX_INDEX] = {
683 .ib_execute = &r100_ring_ib_execute,
684 .emit_fence = &r300_fence_ring_emit,
685 .emit_semaphore = &r100_semaphore_ring_emit,
686 .cs_parse = &r300_cs_parse,
687 }
688 },
689 .irq_set = &rs600_irq_set,
690 .irq_process = &rs600_irq_process,
691 .get_vblank_counter = &rs600_get_vblank_counter,
692 .copy_blit = &r100_copy_blit,
693 .copy_dma = &r200_copy_dma,
694 .copy = &r100_copy_blit,
695 .get_engine_clock = &radeon_atom_get_engine_clock,
696 .set_engine_clock = &radeon_atom_set_engine_clock,
697 .get_memory_clock = &radeon_atom_get_memory_clock,
698 .set_memory_clock = &radeon_atom_set_memory_clock,
699 .get_pcie_lanes = &rv370_get_pcie_lanes,
700 .set_pcie_lanes = &rv370_set_pcie_lanes,
701 .set_clock_gating = &radeon_atom_set_clock_gating,
702 .set_surface_reg = r100_set_surface_reg,
703 .clear_surface_reg = r100_clear_surface_reg,
704 .bandwidth_update = &rv515_bandwidth_update,
705 .hpd = {
706 .init = &rs600_hpd_init,
707 .fini = &rs600_hpd_fini,
708 .sense = &rs600_hpd_sense,
709 .set_polarity = &rs600_hpd_set_polarity,
710 },
711 .ioctl_wait_idle = NULL,
712 .gui_idle = &r100_gui_idle,
713 .pm = {
714 .misc = &rs600_pm_misc,
715 .prepare = &rs600_pm_prepare,
716 .finish = &rs600_pm_finish,
717 .init_profile = &r420_pm_init_profile,
718 .get_dynpm_state = &r100_pm_get_dynpm_state,
719 },
720 .pflip = {
721 .pre_page_flip = &rs600_pre_page_flip,
722 .page_flip = &rs600_page_flip,
723 .post_page_flip = &rs600_post_page_flip,
724 },
725 .wait_for_vblank = &avivo_wait_for_vblank,
726 .mc_wait_for_idle = &r520_mc_wait_for_idle,
727};
728
729static struct radeon_asic r600_asic = {
730 .init = &r600_init,
731 .fini = &r600_fini,
732 .suspend = &r600_suspend,
733 .resume = &r600_resume,
734 .vga_set_state = &r600_vga_set_state,
735 .gpu_is_lockup = &r600_gpu_is_lockup,
736 .asic_reset = &r600_asic_reset,
737 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
738 .gart_set_page = &rs600_gart_set_page,
739 .ring_test = &r600_ring_test,
740 .ring = {
741 [RADEON_RING_TYPE_GFX_INDEX] = {
742 .ib_execute = &r600_ring_ib_execute,
743 .emit_fence = &r600_fence_ring_emit,
744 .emit_semaphore = &r600_semaphore_ring_emit,
745 .cs_parse = &r600_cs_parse,
746 }
747 },
748 .irq_set = &r600_irq_set,
749 .irq_process = &r600_irq_process,
750 .get_vblank_counter = &rs600_get_vblank_counter,
751 .copy_blit = &r600_copy_blit,
752 .copy_dma = NULL,
753 .copy = &r600_copy_blit,
754 .get_engine_clock = &radeon_atom_get_engine_clock,
755 .set_engine_clock = &radeon_atom_set_engine_clock,
756 .get_memory_clock = &radeon_atom_get_memory_clock,
757 .set_memory_clock = &radeon_atom_set_memory_clock,
758 .get_pcie_lanes = &r600_get_pcie_lanes,
759 .set_pcie_lanes = &r600_set_pcie_lanes,
760 .set_clock_gating = NULL,
761 .set_surface_reg = r600_set_surface_reg,
762 .clear_surface_reg = r600_clear_surface_reg,
763 .bandwidth_update = &rv515_bandwidth_update,
764 .hpd = {
765 .init = &r600_hpd_init,
766 .fini = &r600_hpd_fini,
767 .sense = &r600_hpd_sense,
768 .set_polarity = &r600_hpd_set_polarity,
769 },
770 .ioctl_wait_idle = r600_ioctl_wait_idle,
771 .gui_idle = &r600_gui_idle,
772 .pm = {
773 .misc = &r600_pm_misc,
774 .prepare = &rs600_pm_prepare,
775 .finish = &rs600_pm_finish,
776 .init_profile = &r600_pm_init_profile,
777 .get_dynpm_state = &r600_pm_get_dynpm_state,
778 },
779 .pflip = {
780 .pre_page_flip = &rs600_pre_page_flip,
781 .page_flip = &rs600_page_flip,
782 .post_page_flip = &rs600_post_page_flip,
783 },
784 .wait_for_vblank = &avivo_wait_for_vblank,
785 .mc_wait_for_idle = &r600_mc_wait_for_idle,
786};
787
788static struct radeon_asic rs780_asic = {
789 .init = &r600_init,
790 .fini = &r600_fini,
791 .suspend = &r600_suspend,
792 .resume = &r600_resume,
793 .gpu_is_lockup = &r600_gpu_is_lockup,
794 .vga_set_state = &r600_vga_set_state,
795 .asic_reset = &r600_asic_reset,
796 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
797 .gart_set_page = &rs600_gart_set_page,
798 .ring_test = &r600_ring_test,
799 .ring = {
800 [RADEON_RING_TYPE_GFX_INDEX] = {
801 .ib_execute = &r600_ring_ib_execute,
802 .emit_fence = &r600_fence_ring_emit,
803 .emit_semaphore = &r600_semaphore_ring_emit,
804 .cs_parse = &r600_cs_parse,
805 }
806 },
807 .irq_set = &r600_irq_set,
808 .irq_process = &r600_irq_process,
809 .get_vblank_counter = &rs600_get_vblank_counter,
810 .copy_blit = &r600_copy_blit,
811 .copy_dma = NULL,
812 .copy = &r600_copy_blit,
813 .get_engine_clock = &radeon_atom_get_engine_clock,
814 .set_engine_clock = &radeon_atom_set_engine_clock,
815 .get_memory_clock = NULL,
816 .set_memory_clock = NULL,
817 .get_pcie_lanes = NULL,
818 .set_pcie_lanes = NULL,
819 .set_clock_gating = NULL,
820 .set_surface_reg = r600_set_surface_reg,
821 .clear_surface_reg = r600_clear_surface_reg,
822 .bandwidth_update = &rs690_bandwidth_update,
823 .hpd = {
824 .init = &r600_hpd_init,
825 .fini = &r600_hpd_fini,
826 .sense = &r600_hpd_sense,
827 .set_polarity = &r600_hpd_set_polarity,
828 },
829 .ioctl_wait_idle = r600_ioctl_wait_idle,
830 .gui_idle = &r600_gui_idle,
831 .pm = {
832 .misc = &r600_pm_misc,
833 .prepare = &rs600_pm_prepare,
834 .finish = &rs600_pm_finish,
835 .init_profile = &rs780_pm_init_profile,
836 .get_dynpm_state = &r600_pm_get_dynpm_state,
837 },
838 .pflip = {
839 .pre_page_flip = &rs600_pre_page_flip,
840 .page_flip = &rs600_page_flip,
841 .post_page_flip = &rs600_post_page_flip,
842 },
843 .wait_for_vblank = &avivo_wait_for_vblank,
844 .mc_wait_for_idle = &r600_mc_wait_for_idle,
845};
846
847static struct radeon_asic rv770_asic = {
848 .init = &rv770_init,
849 .fini = &rv770_fini,
850 .suspend = &rv770_suspend,
851 .resume = &rv770_resume,
852 .asic_reset = &r600_asic_reset,
853 .gpu_is_lockup = &r600_gpu_is_lockup,
854 .vga_set_state = &r600_vga_set_state,
855 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
856 .gart_set_page = &rs600_gart_set_page,
857 .ring_test = &r600_ring_test,
858 .ring = {
859 [RADEON_RING_TYPE_GFX_INDEX] = {
860 .ib_execute = &r600_ring_ib_execute,
861 .emit_fence = &r600_fence_ring_emit,
862 .emit_semaphore = &r600_semaphore_ring_emit,
863 .cs_parse = &r600_cs_parse,
864 }
865 },
866 .irq_set = &r600_irq_set,
867 .irq_process = &r600_irq_process,
868 .get_vblank_counter = &rs600_get_vblank_counter,
869 .copy_blit = &r600_copy_blit,
870 .copy_dma = NULL,
871 .copy = &r600_copy_blit,
872 .get_engine_clock = &radeon_atom_get_engine_clock,
873 .set_engine_clock = &radeon_atom_set_engine_clock,
874 .get_memory_clock = &radeon_atom_get_memory_clock,
875 .set_memory_clock = &radeon_atom_set_memory_clock,
876 .get_pcie_lanes = &r600_get_pcie_lanes,
877 .set_pcie_lanes = &r600_set_pcie_lanes,
878 .set_clock_gating = &radeon_atom_set_clock_gating,
879 .set_surface_reg = r600_set_surface_reg,
880 .clear_surface_reg = r600_clear_surface_reg,
881 .bandwidth_update = &rv515_bandwidth_update,
882 .hpd = {
883 .init = &r600_hpd_init,
884 .fini = &r600_hpd_fini,
885 .sense = &r600_hpd_sense,
886 .set_polarity = &r600_hpd_set_polarity,
887 },
888 .ioctl_wait_idle = r600_ioctl_wait_idle,
889 .gui_idle = &r600_gui_idle,
890 .pm = {
891 .misc = &rv770_pm_misc,
892 .prepare = &rs600_pm_prepare,
893 .finish = &rs600_pm_finish,
894 .init_profile = &r600_pm_init_profile,
895 .get_dynpm_state = &r600_pm_get_dynpm_state,
896 },
897 .pflip = {
898 .pre_page_flip = &rs600_pre_page_flip,
899 .page_flip = &rv770_page_flip,
900 .post_page_flip = &rs600_post_page_flip,
901 },
902 .wait_for_vblank = &avivo_wait_for_vblank,
903 .mc_wait_for_idle = &r600_mc_wait_for_idle,
904};
905
906static struct radeon_asic evergreen_asic = {
907 .init = &evergreen_init,
908 .fini = &evergreen_fini,
909 .suspend = &evergreen_suspend,
910 .resume = &evergreen_resume,
911 .gpu_is_lockup = &evergreen_gpu_is_lockup,
912 .asic_reset = &evergreen_asic_reset,
913 .vga_set_state = &r600_vga_set_state,
914 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
915 .gart_set_page = &rs600_gart_set_page,
916 .ring_test = &r600_ring_test,
917 .ring = {
918 [RADEON_RING_TYPE_GFX_INDEX] = {
919 .ib_execute = &evergreen_ring_ib_execute,
920 .emit_fence = &r600_fence_ring_emit,
921 .emit_semaphore = &r600_semaphore_ring_emit,
922 .cs_parse = &evergreen_cs_parse,
923 }
924 },
925 .irq_set = &evergreen_irq_set,
926 .irq_process = &evergreen_irq_process,
927 .get_vblank_counter = &evergreen_get_vblank_counter,
928 .copy_blit = &r600_copy_blit,
929 .copy_dma = NULL,
930 .copy = &r600_copy_blit,
931 .get_engine_clock = &radeon_atom_get_engine_clock,
932 .set_engine_clock = &radeon_atom_set_engine_clock,
933 .get_memory_clock = &radeon_atom_get_memory_clock,
934 .set_memory_clock = &radeon_atom_set_memory_clock,
935 .get_pcie_lanes = &r600_get_pcie_lanes,
936 .set_pcie_lanes = &r600_set_pcie_lanes,
937 .set_clock_gating = NULL,
938 .set_surface_reg = r600_set_surface_reg,
939 .clear_surface_reg = r600_clear_surface_reg,
940 .bandwidth_update = &evergreen_bandwidth_update,
941 .hpd = {
942 .init = &evergreen_hpd_init,
943 .fini = &evergreen_hpd_fini,
944 .sense = &evergreen_hpd_sense,
945 .set_polarity = &evergreen_hpd_set_polarity,
946 },
947 .ioctl_wait_idle = r600_ioctl_wait_idle,
948 .gui_idle = &r600_gui_idle,
949 .pm = {
950 .misc = &evergreen_pm_misc,
951 .prepare = &evergreen_pm_prepare,
952 .finish = &evergreen_pm_finish,
953 .init_profile = &r600_pm_init_profile,
954 .get_dynpm_state = &r600_pm_get_dynpm_state,
955 },
956 .pflip = {
957 .pre_page_flip = &evergreen_pre_page_flip,
958 .page_flip = &evergreen_page_flip,
959 .post_page_flip = &evergreen_post_page_flip,
960 },
961 .wait_for_vblank = &dce4_wait_for_vblank,
962 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
963};
964
965static struct radeon_asic sumo_asic = {
966 .init = &evergreen_init,
967 .fini = &evergreen_fini,
968 .suspend = &evergreen_suspend,
969 .resume = &evergreen_resume,
970 .gpu_is_lockup = &evergreen_gpu_is_lockup,
971 .asic_reset = &evergreen_asic_reset,
972 .vga_set_state = &r600_vga_set_state,
973 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
974 .gart_set_page = &rs600_gart_set_page,
975 .ring_test = &r600_ring_test,
976 .ring = {
977 [RADEON_RING_TYPE_GFX_INDEX] = {
978 .ib_execute = &evergreen_ring_ib_execute,
979 .emit_fence = &r600_fence_ring_emit,
980 .emit_semaphore = &r600_semaphore_ring_emit,
981 .cs_parse = &evergreen_cs_parse,
982 },
983 },
984 .irq_set = &evergreen_irq_set,
985 .irq_process = &evergreen_irq_process,
986 .get_vblank_counter = &evergreen_get_vblank_counter,
987 .copy_blit = &r600_copy_blit,
988 .copy_dma = NULL,
989 .copy = &r600_copy_blit,
990 .get_engine_clock = &radeon_atom_get_engine_clock,
991 .set_engine_clock = &radeon_atom_set_engine_clock,
992 .get_memory_clock = NULL,
993 .set_memory_clock = NULL,
994 .get_pcie_lanes = NULL,
995 .set_pcie_lanes = NULL,
996 .set_clock_gating = NULL,
997 .set_surface_reg = r600_set_surface_reg,
998 .clear_surface_reg = r600_clear_surface_reg,
999 .bandwidth_update = &evergreen_bandwidth_update,
1000 .hpd = {
1001 .init = &evergreen_hpd_init,
1002 .fini = &evergreen_hpd_fini,
1003 .sense = &evergreen_hpd_sense,
1004 .set_polarity = &evergreen_hpd_set_polarity,
1005 },
1006 .ioctl_wait_idle = r600_ioctl_wait_idle,
1007 .gui_idle = &r600_gui_idle,
1008 .pm = {
1009 .misc = &evergreen_pm_misc,
1010 .prepare = &evergreen_pm_prepare,
1011 .finish = &evergreen_pm_finish,
1012 .init_profile = &sumo_pm_init_profile,
1013 .get_dynpm_state = &r600_pm_get_dynpm_state,
1014 },
1015 .pflip = {
1016 .pre_page_flip = &evergreen_pre_page_flip,
1017 .page_flip = &evergreen_page_flip,
1018 .post_page_flip = &evergreen_post_page_flip,
1019 },
1020 .wait_for_vblank = &dce4_wait_for_vblank,
1021 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1022};
1023
1024static struct radeon_asic btc_asic = {
1025 .init = &evergreen_init,
1026 .fini = &evergreen_fini,
1027 .suspend = &evergreen_suspend,
1028 .resume = &evergreen_resume,
1029 .gpu_is_lockup = &evergreen_gpu_is_lockup,
1030 .asic_reset = &evergreen_asic_reset,
1031 .vga_set_state = &r600_vga_set_state,
1032 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
1033 .gart_set_page = &rs600_gart_set_page,
1034 .ring_test = &r600_ring_test,
1035 .ring = {
1036 [RADEON_RING_TYPE_GFX_INDEX] = {
1037 .ib_execute = &evergreen_ring_ib_execute,
1038 .emit_fence = &r600_fence_ring_emit,
1039 .emit_semaphore = &r600_semaphore_ring_emit,
1040 .cs_parse = &evergreen_cs_parse,
1041 }
1042 },
1043 .irq_set = &evergreen_irq_set,
1044 .irq_process = &evergreen_irq_process,
1045 .get_vblank_counter = &evergreen_get_vblank_counter,
1046 .copy_blit = &r600_copy_blit,
1047 .copy_dma = NULL,
1048 .copy = &r600_copy_blit,
1049 .get_engine_clock = &radeon_atom_get_engine_clock,
1050 .set_engine_clock = &radeon_atom_set_engine_clock,
1051 .get_memory_clock = &radeon_atom_get_memory_clock,
1052 .set_memory_clock = &radeon_atom_set_memory_clock,
1053 .get_pcie_lanes = NULL,
1054 .set_pcie_lanes = NULL,
1055 .set_clock_gating = NULL,
1056 .set_surface_reg = r600_set_surface_reg,
1057 .clear_surface_reg = r600_clear_surface_reg,
1058 .bandwidth_update = &evergreen_bandwidth_update,
1059 .hpd = {
1060 .init = &evergreen_hpd_init,
1061 .fini = &evergreen_hpd_fini,
1062 .sense = &evergreen_hpd_sense,
1063 .set_polarity = &evergreen_hpd_set_polarity,
1064 },
1065 .ioctl_wait_idle = r600_ioctl_wait_idle,
1066 .gui_idle = &r600_gui_idle,
1067 .pm = {
1068 .misc = &evergreen_pm_misc,
1069 .prepare = &evergreen_pm_prepare,
1070 .finish = &evergreen_pm_finish,
1071 .init_profile = &r600_pm_init_profile,
1072 .get_dynpm_state = &r600_pm_get_dynpm_state,
1073 },
1074 .pflip = {
1075 .pre_page_flip = &evergreen_pre_page_flip,
1076 .page_flip = &evergreen_page_flip,
1077 .post_page_flip = &evergreen_post_page_flip,
1078 },
1079 .wait_for_vblank = &dce4_wait_for_vblank,
1080 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1081};
1082
1083static const struct radeon_vm_funcs cayman_vm_funcs = {
1084 .init = &cayman_vm_init,
1085 .fini = &cayman_vm_fini,
1086 .bind = &cayman_vm_bind,
1087 .unbind = &cayman_vm_unbind,
1088 .tlb_flush = &cayman_vm_tlb_flush,
1089 .page_flags = &cayman_vm_page_flags,
1090 .set_page = &cayman_vm_set_page,
1091};
1092
1093static struct radeon_asic cayman_asic = {
1094 .init = &cayman_init,
1095 .fini = &cayman_fini,
1096 .suspend = &cayman_suspend,
1097 .resume = &cayman_resume,
1098 .gpu_is_lockup = &cayman_gpu_is_lockup,
1099 .asic_reset = &cayman_asic_reset,
1100 .vga_set_state = &r600_vga_set_state,
1101 .gart_tlb_flush = &cayman_pcie_gart_tlb_flush,
1102 .gart_set_page = &rs600_gart_set_page,
1103 .ring_test = &r600_ring_test,
1104 .ring = {
1105 [RADEON_RING_TYPE_GFX_INDEX] = {
1106 .ib_execute = &cayman_ring_ib_execute,
1107 .ib_parse = &evergreen_ib_parse,
1108 .emit_fence = &cayman_fence_ring_emit,
1109 .emit_semaphore = &r600_semaphore_ring_emit,
1110 .cs_parse = &evergreen_cs_parse,
1111 },
1112 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1113 .ib_execute = &cayman_ring_ib_execute,
1114 .ib_parse = &evergreen_ib_parse,
1115 .emit_fence = &cayman_fence_ring_emit,
1116 .emit_semaphore = &r600_semaphore_ring_emit,
1117 .cs_parse = &evergreen_cs_parse,
1118 },
1119 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1120 .ib_execute = &cayman_ring_ib_execute,
1121 .ib_parse = &evergreen_ib_parse,
1122 .emit_fence = &cayman_fence_ring_emit,
1123 .emit_semaphore = &r600_semaphore_ring_emit,
1124 .cs_parse = &evergreen_cs_parse,
1125 }
1126 },
1127 .irq_set = &evergreen_irq_set,
1128 .irq_process = &evergreen_irq_process,
1129 .get_vblank_counter = &evergreen_get_vblank_counter,
1130 .copy_blit = &r600_copy_blit,
1131 .copy_dma = NULL,
1132 .copy = &r600_copy_blit,
1133 .get_engine_clock = &radeon_atom_get_engine_clock,
1134 .set_engine_clock = &radeon_atom_set_engine_clock,
1135 .get_memory_clock = &radeon_atom_get_memory_clock,
1136 .set_memory_clock = &radeon_atom_set_memory_clock,
1137 .get_pcie_lanes = NULL,
1138 .set_pcie_lanes = NULL,
1139 .set_clock_gating = NULL,
1140 .set_surface_reg = r600_set_surface_reg,
1141 .clear_surface_reg = r600_clear_surface_reg,
1142 .bandwidth_update = &evergreen_bandwidth_update,
1143 .hpd = {
1144 .init = &evergreen_hpd_init,
1145 .fini = &evergreen_hpd_fini,
1146 .sense = &evergreen_hpd_sense,
1147 .set_polarity = &evergreen_hpd_set_polarity,
1148 },
1149 .ioctl_wait_idle = r600_ioctl_wait_idle,
1150 .gui_idle = &r600_gui_idle,
1151 .pm = {
1152 .misc = &evergreen_pm_misc,
1153 .prepare = &evergreen_pm_prepare,
1154 .finish = &evergreen_pm_finish,
1155 .init_profile = &r600_pm_init_profile,
1156 .get_dynpm_state = &r600_pm_get_dynpm_state,
1157 },
1158 .pflip = {
1159 .pre_page_flip = &evergreen_pre_page_flip,
1160 .page_flip = &evergreen_page_flip,
1161 .post_page_flip = &evergreen_post_page_flip,
1162 },
1163 .wait_for_vblank = &dce4_wait_for_vblank,
1164 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1165};
1166
1167int radeon_asic_init(struct radeon_device *rdev)
1168{
1169 radeon_register_accessor_init(rdev);
1170
1171 /* set the number of crtcs */
1172 if (rdev->flags & RADEON_SINGLE_CRTC)
1173 rdev->num_crtc = 1;
1174 else
1175 rdev->num_crtc = 2;
1176
1177 /* set the ring used for bo copies */
1178 rdev->copy_ring = RADEON_RING_TYPE_GFX_INDEX;
1179
1180 switch (rdev->family) {
1181 case CHIP_R100:
1182 case CHIP_RV100:
1183 case CHIP_RS100:
1184 case CHIP_RV200:
1185 case CHIP_RS200:
1186 rdev->asic = &r100_asic;
1187 break;
1188 case CHIP_R200:
1189 case CHIP_RV250:
1190 case CHIP_RS300:
1191 case CHIP_RV280:
1192 rdev->asic = &r200_asic;
1193 break;
1194 case CHIP_R300:
1195 case CHIP_R350:
1196 case CHIP_RV350:
1197 case CHIP_RV380:
1198 if (rdev->flags & RADEON_IS_PCIE)
1199 rdev->asic = &r300_asic_pcie;
1200 else
1201 rdev->asic = &r300_asic;
1202 break;
1203 case CHIP_R420:
1204 case CHIP_R423:
1205 case CHIP_RV410:
1206 rdev->asic = &r420_asic;
1207 /* handle macs */
1208 if (rdev->bios == NULL) {
1209 rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock;
1210 rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock;
1211 rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock;
1212 rdev->asic->set_memory_clock = NULL;
1213 }
1214 break;
1215 case CHIP_RS400:
1216 case CHIP_RS480:
1217 rdev->asic = &rs400_asic;
1218 break;
1219 case CHIP_RS600:
1220 rdev->asic = &rs600_asic;
1221 break;
1222 case CHIP_RS690:
1223 case CHIP_RS740:
1224 rdev->asic = &rs690_asic;
1225 break;
1226 case CHIP_RV515:
1227 rdev->asic = &rv515_asic;
1228 break;
1229 case CHIP_R520:
1230 case CHIP_RV530:
1231 case CHIP_RV560:
1232 case CHIP_RV570:
1233 case CHIP_R580:
1234 rdev->asic = &r520_asic;
1235 break;
1236 case CHIP_R600:
1237 case CHIP_RV610:
1238 case CHIP_RV630:
1239 case CHIP_RV620:
1240 case CHIP_RV635:
1241 case CHIP_RV670:
1242 rdev->asic = &r600_asic;
1243 break;
1244 case CHIP_RS780:
1245 case CHIP_RS880:
1246 rdev->asic = &rs780_asic;
1247 break;
1248 case CHIP_RV770:
1249 case CHIP_RV730:
1250 case CHIP_RV710:
1251 case CHIP_RV740:
1252 rdev->asic = &rv770_asic;
1253 break;
1254 case CHIP_CEDAR:
1255 case CHIP_REDWOOD:
1256 case CHIP_JUNIPER:
1257 case CHIP_CYPRESS:
1258 case CHIP_HEMLOCK:
1259 /* set num crtcs */
1260 if (rdev->family == CHIP_CEDAR)
1261 rdev->num_crtc = 4;
1262 else
1263 rdev->num_crtc = 6;
1264 rdev->asic = &evergreen_asic;
1265 break;
1266 case CHIP_PALM:
1267 case CHIP_SUMO:
1268 case CHIP_SUMO2:
1269 rdev->asic = &sumo_asic;
1270 break;
1271 case CHIP_BARTS:
1272 case CHIP_TURKS:
1273 case CHIP_CAICOS:
1274 /* set num crtcs */
1275 if (rdev->family == CHIP_CAICOS)
1276 rdev->num_crtc = 4;
1277 else
1278 rdev->num_crtc = 6;
1279 rdev->asic = &btc_asic;
1280 break;
1281 case CHIP_CAYMAN:
1282 rdev->asic = &cayman_asic;
1283 /* set num crtcs */
1284 rdev->num_crtc = 6;
1285 rdev->vm_manager.funcs = &cayman_vm_funcs;
1286 break;
1287 default:
1288 /* FIXME: not supported yet */
1289 return -EINVAL;
1290 }
1291
1292 if (rdev->flags & RADEON_IS_IGP) {
1293 rdev->asic->get_memory_clock = NULL;
1294 rdev->asic->set_memory_clock = NULL;
1295 }
1296
1297 return 0;
1298}
1299
Linux kernel - Deliverables
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