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drm/radeon/dpm: implement force performance level for CI
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_asic.c
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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/console.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
33#include <linux/vgaarb.h>
34#include <linux/vga_switcheroo.h>
35#include "radeon_reg.h"
36#include "radeon.h"
37#include "radeon_asic.h"
38#include "atom.h"
39
40/*
41 * Registers accessors functions.
42 */
43/**
44 * radeon_invalid_rreg - dummy reg read function
45 *
46 * @rdev: radeon device pointer
47 * @reg: offset of register
48 *
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
52 */
53static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54{
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56 BUG_ON(1);
57 return 0;
58}
59
60/**
61 * radeon_invalid_wreg - dummy reg write function
62 *
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
66 *
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
69 */
70static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71{
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73 reg, v);
74 BUG_ON(1);
75}
76
77/**
78 * radeon_register_accessor_init - sets up the register accessor callbacks
79 *
80 * @rdev: radeon device pointer
81 *
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
84 */
85static void radeon_register_accessor_init(struct radeon_device *rdev)
86{
87 rdev->mc_rreg = &radeon_invalid_rreg;
88 rdev->mc_wreg = &radeon_invalid_wreg;
89 rdev->pll_rreg = &radeon_invalid_rreg;
90 rdev->pll_wreg = &radeon_invalid_wreg;
91 rdev->pciep_rreg = &radeon_invalid_rreg;
92 rdev->pciep_wreg = &radeon_invalid_wreg;
93
94 /* Don't change order as we are overridding accessor. */
95 if (rdev->family < CHIP_RV515) {
96 rdev->pcie_reg_mask = 0xff;
97 } else {
98 rdev->pcie_reg_mask = 0x7ff;
99 }
100 /* FIXME: not sure here */
101 if (rdev->family <= CHIP_R580) {
102 rdev->pll_rreg = &r100_pll_rreg;
103 rdev->pll_wreg = &r100_pll_wreg;
104 }
105 if (rdev->family >= CHIP_R420) {
106 rdev->mc_rreg = &r420_mc_rreg;
107 rdev->mc_wreg = &r420_mc_wreg;
108 }
109 if (rdev->family >= CHIP_RV515) {
110 rdev->mc_rreg = &rv515_mc_rreg;
111 rdev->mc_wreg = &rv515_mc_wreg;
112 }
113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 rdev->mc_rreg = &rs400_mc_rreg;
115 rdev->mc_wreg = &rs400_mc_wreg;
116 }
117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 rdev->mc_rreg = &rs690_mc_rreg;
119 rdev->mc_wreg = &rs690_mc_wreg;
120 }
121 if (rdev->family == CHIP_RS600) {
122 rdev->mc_rreg = &rs600_mc_rreg;
123 rdev->mc_wreg = &rs600_mc_wreg;
124 }
125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
126 rdev->mc_rreg = &rs780_mc_rreg;
127 rdev->mc_wreg = &rs780_mc_wreg;
128 }
129
130 if (rdev->family >= CHIP_BONAIRE) {
131 rdev->pciep_rreg = &cik_pciep_rreg;
132 rdev->pciep_wreg = &cik_pciep_wreg;
133 } else if (rdev->family >= CHIP_R600) {
134 rdev->pciep_rreg = &r600_pciep_rreg;
135 rdev->pciep_wreg = &r600_pciep_wreg;
136 }
137}
138
139
140/* helper to disable agp */
141/**
142 * radeon_agp_disable - AGP disable helper function
143 *
144 * @rdev: radeon device pointer
145 *
146 * Removes AGP flags and changes the gart callbacks on AGP
147 * cards when using the internal gart rather than AGP (all asics).
148 */
149void radeon_agp_disable(struct radeon_device *rdev)
150{
151 rdev->flags &= ~RADEON_IS_AGP;
152 if (rdev->family >= CHIP_R600) {
153 DRM_INFO("Forcing AGP to PCIE mode\n");
154 rdev->flags |= RADEON_IS_PCIE;
155 } else if (rdev->family >= CHIP_RV515 ||
156 rdev->family == CHIP_RV380 ||
157 rdev->family == CHIP_RV410 ||
158 rdev->family == CHIP_R423) {
159 DRM_INFO("Forcing AGP to PCIE mode\n");
160 rdev->flags |= RADEON_IS_PCIE;
161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
162 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
163 } else {
164 DRM_INFO("Forcing AGP to PCI mode\n");
165 rdev->flags |= RADEON_IS_PCI;
166 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
167 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
168 }
169 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
170}
171
172/*
173 * ASIC
174 */
175static struct radeon_asic r100_asic = {
176 .init = &r100_init,
177 .fini = &r100_fini,
178 .suspend = &r100_suspend,
179 .resume = &r100_resume,
180 .vga_set_state = &r100_vga_set_state,
181 .asic_reset = &r100_asic_reset,
182 .ioctl_wait_idle = NULL,
183 .gui_idle = &r100_gui_idle,
184 .mc_wait_for_idle = &r100_mc_wait_for_idle,
185 .gart = {
186 .tlb_flush = &r100_pci_gart_tlb_flush,
187 .set_page = &r100_pci_gart_set_page,
188 },
189 .ring = {
190 [RADEON_RING_TYPE_GFX_INDEX] = {
191 .ib_execute = &r100_ring_ib_execute,
192 .emit_fence = &r100_fence_ring_emit,
193 .emit_semaphore = &r100_semaphore_ring_emit,
194 .cs_parse = &r100_cs_parse,
195 .ring_start = &r100_ring_start,
196 .ring_test = &r100_ring_test,
197 .ib_test = &r100_ib_test,
198 .is_lockup = &r100_gpu_is_lockup,
199 .get_rptr = &radeon_ring_generic_get_rptr,
200 .get_wptr = &radeon_ring_generic_get_wptr,
201 .set_wptr = &radeon_ring_generic_set_wptr,
202 }
203 },
204 .irq = {
205 .set = &r100_irq_set,
206 .process = &r100_irq_process,
207 },
208 .display = {
209 .bandwidth_update = &r100_bandwidth_update,
210 .get_vblank_counter = &r100_get_vblank_counter,
211 .wait_for_vblank = &r100_wait_for_vblank,
212 .set_backlight_level = &radeon_legacy_set_backlight_level,
213 .get_backlight_level = &radeon_legacy_get_backlight_level,
214 },
215 .copy = {
216 .blit = &r100_copy_blit,
217 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
218 .dma = NULL,
219 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
220 .copy = &r100_copy_blit,
221 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
222 },
223 .surface = {
224 .set_reg = r100_set_surface_reg,
225 .clear_reg = r100_clear_surface_reg,
226 },
227 .hpd = {
228 .init = &r100_hpd_init,
229 .fini = &r100_hpd_fini,
230 .sense = &r100_hpd_sense,
231 .set_polarity = &r100_hpd_set_polarity,
232 },
233 .pm = {
234 .misc = &r100_pm_misc,
235 .prepare = &r100_pm_prepare,
236 .finish = &r100_pm_finish,
237 .init_profile = &r100_pm_init_profile,
238 .get_dynpm_state = &r100_pm_get_dynpm_state,
239 .get_engine_clock = &radeon_legacy_get_engine_clock,
240 .set_engine_clock = &radeon_legacy_set_engine_clock,
241 .get_memory_clock = &radeon_legacy_get_memory_clock,
242 .set_memory_clock = NULL,
243 .get_pcie_lanes = NULL,
244 .set_pcie_lanes = NULL,
245 .set_clock_gating = &radeon_legacy_set_clock_gating,
246 },
247 .pflip = {
248 .pre_page_flip = &r100_pre_page_flip,
249 .page_flip = &r100_page_flip,
250 .post_page_flip = &r100_post_page_flip,
251 },
252};
253
254static struct radeon_asic r200_asic = {
255 .init = &r100_init,
256 .fini = &r100_fini,
257 .suspend = &r100_suspend,
258 .resume = &r100_resume,
259 .vga_set_state = &r100_vga_set_state,
260 .asic_reset = &r100_asic_reset,
261 .ioctl_wait_idle = NULL,
262 .gui_idle = &r100_gui_idle,
263 .mc_wait_for_idle = &r100_mc_wait_for_idle,
264 .gart = {
265 .tlb_flush = &r100_pci_gart_tlb_flush,
266 .set_page = &r100_pci_gart_set_page,
267 },
268 .ring = {
269 [RADEON_RING_TYPE_GFX_INDEX] = {
270 .ib_execute = &r100_ring_ib_execute,
271 .emit_fence = &r100_fence_ring_emit,
272 .emit_semaphore = &r100_semaphore_ring_emit,
273 .cs_parse = &r100_cs_parse,
274 .ring_start = &r100_ring_start,
275 .ring_test = &r100_ring_test,
276 .ib_test = &r100_ib_test,
277 .is_lockup = &r100_gpu_is_lockup,
278 .get_rptr = &radeon_ring_generic_get_rptr,
279 .get_wptr = &radeon_ring_generic_get_wptr,
280 .set_wptr = &radeon_ring_generic_set_wptr,
281 }
282 },
283 .irq = {
284 .set = &r100_irq_set,
285 .process = &r100_irq_process,
286 },
287 .display = {
288 .bandwidth_update = &r100_bandwidth_update,
289 .get_vblank_counter = &r100_get_vblank_counter,
290 .wait_for_vblank = &r100_wait_for_vblank,
291 .set_backlight_level = &radeon_legacy_set_backlight_level,
292 .get_backlight_level = &radeon_legacy_get_backlight_level,
293 },
294 .copy = {
295 .blit = &r100_copy_blit,
296 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
297 .dma = &r200_copy_dma,
298 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
299 .copy = &r100_copy_blit,
300 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
301 },
302 .surface = {
303 .set_reg = r100_set_surface_reg,
304 .clear_reg = r100_clear_surface_reg,
305 },
306 .hpd = {
307 .init = &r100_hpd_init,
308 .fini = &r100_hpd_fini,
309 .sense = &r100_hpd_sense,
310 .set_polarity = &r100_hpd_set_polarity,
311 },
312 .pm = {
313 .misc = &r100_pm_misc,
314 .prepare = &r100_pm_prepare,
315 .finish = &r100_pm_finish,
316 .init_profile = &r100_pm_init_profile,
317 .get_dynpm_state = &r100_pm_get_dynpm_state,
318 .get_engine_clock = &radeon_legacy_get_engine_clock,
319 .set_engine_clock = &radeon_legacy_set_engine_clock,
320 .get_memory_clock = &radeon_legacy_get_memory_clock,
321 .set_memory_clock = NULL,
322 .get_pcie_lanes = NULL,
323 .set_pcie_lanes = NULL,
324 .set_clock_gating = &radeon_legacy_set_clock_gating,
325 },
326 .pflip = {
327 .pre_page_flip = &r100_pre_page_flip,
328 .page_flip = &r100_page_flip,
329 .post_page_flip = &r100_post_page_flip,
330 },
331};
332
333static struct radeon_asic r300_asic = {
334 .init = &r300_init,
335 .fini = &r300_fini,
336 .suspend = &r300_suspend,
337 .resume = &r300_resume,
338 .vga_set_state = &r100_vga_set_state,
339 .asic_reset = &r300_asic_reset,
340 .ioctl_wait_idle = NULL,
341 .gui_idle = &r100_gui_idle,
342 .mc_wait_for_idle = &r300_mc_wait_for_idle,
343 .gart = {
344 .tlb_flush = &r100_pci_gart_tlb_flush,
345 .set_page = &r100_pci_gart_set_page,
346 },
347 .ring = {
348 [RADEON_RING_TYPE_GFX_INDEX] = {
349 .ib_execute = &r100_ring_ib_execute,
350 .emit_fence = &r300_fence_ring_emit,
351 .emit_semaphore = &r100_semaphore_ring_emit,
352 .cs_parse = &r300_cs_parse,
353 .ring_start = &r300_ring_start,
354 .ring_test = &r100_ring_test,
355 .ib_test = &r100_ib_test,
356 .is_lockup = &r100_gpu_is_lockup,
357 .get_rptr = &radeon_ring_generic_get_rptr,
358 .get_wptr = &radeon_ring_generic_get_wptr,
359 .set_wptr = &radeon_ring_generic_set_wptr,
360 }
361 },
362 .irq = {
363 .set = &r100_irq_set,
364 .process = &r100_irq_process,
365 },
366 .display = {
367 .bandwidth_update = &r100_bandwidth_update,
368 .get_vblank_counter = &r100_get_vblank_counter,
369 .wait_for_vblank = &r100_wait_for_vblank,
370 .set_backlight_level = &radeon_legacy_set_backlight_level,
371 .get_backlight_level = &radeon_legacy_get_backlight_level,
372 },
373 .copy = {
374 .blit = &r100_copy_blit,
375 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
376 .dma = &r200_copy_dma,
377 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
378 .copy = &r100_copy_blit,
379 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
380 },
381 .surface = {
382 .set_reg = r100_set_surface_reg,
383 .clear_reg = r100_clear_surface_reg,
384 },
385 .hpd = {
386 .init = &r100_hpd_init,
387 .fini = &r100_hpd_fini,
388 .sense = &r100_hpd_sense,
389 .set_polarity = &r100_hpd_set_polarity,
390 },
391 .pm = {
392 .misc = &r100_pm_misc,
393 .prepare = &r100_pm_prepare,
394 .finish = &r100_pm_finish,
395 .init_profile = &r100_pm_init_profile,
396 .get_dynpm_state = &r100_pm_get_dynpm_state,
397 .get_engine_clock = &radeon_legacy_get_engine_clock,
398 .set_engine_clock = &radeon_legacy_set_engine_clock,
399 .get_memory_clock = &radeon_legacy_get_memory_clock,
400 .set_memory_clock = NULL,
401 .get_pcie_lanes = &rv370_get_pcie_lanes,
402 .set_pcie_lanes = &rv370_set_pcie_lanes,
403 .set_clock_gating = &radeon_legacy_set_clock_gating,
404 },
405 .pflip = {
406 .pre_page_flip = &r100_pre_page_flip,
407 .page_flip = &r100_page_flip,
408 .post_page_flip = &r100_post_page_flip,
409 },
410};
411
412static struct radeon_asic r300_asic_pcie = {
413 .init = &r300_init,
414 .fini = &r300_fini,
415 .suspend = &r300_suspend,
416 .resume = &r300_resume,
417 .vga_set_state = &r100_vga_set_state,
418 .asic_reset = &r300_asic_reset,
419 .ioctl_wait_idle = NULL,
420 .gui_idle = &r100_gui_idle,
421 .mc_wait_for_idle = &r300_mc_wait_for_idle,
422 .gart = {
423 .tlb_flush = &rv370_pcie_gart_tlb_flush,
424 .set_page = &rv370_pcie_gart_set_page,
425 },
426 .ring = {
427 [RADEON_RING_TYPE_GFX_INDEX] = {
428 .ib_execute = &r100_ring_ib_execute,
429 .emit_fence = &r300_fence_ring_emit,
430 .emit_semaphore = &r100_semaphore_ring_emit,
431 .cs_parse = &r300_cs_parse,
432 .ring_start = &r300_ring_start,
433 .ring_test = &r100_ring_test,
434 .ib_test = &r100_ib_test,
435 .is_lockup = &r100_gpu_is_lockup,
436 .get_rptr = &radeon_ring_generic_get_rptr,
437 .get_wptr = &radeon_ring_generic_get_wptr,
438 .set_wptr = &radeon_ring_generic_set_wptr,
439 }
440 },
441 .irq = {
442 .set = &r100_irq_set,
443 .process = &r100_irq_process,
444 },
445 .display = {
446 .bandwidth_update = &r100_bandwidth_update,
447 .get_vblank_counter = &r100_get_vblank_counter,
448 .wait_for_vblank = &r100_wait_for_vblank,
449 .set_backlight_level = &radeon_legacy_set_backlight_level,
450 .get_backlight_level = &radeon_legacy_get_backlight_level,
451 },
452 .copy = {
453 .blit = &r100_copy_blit,
454 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
455 .dma = &r200_copy_dma,
456 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
457 .copy = &r100_copy_blit,
458 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
459 },
460 .surface = {
461 .set_reg = r100_set_surface_reg,
462 .clear_reg = r100_clear_surface_reg,
463 },
464 .hpd = {
465 .init = &r100_hpd_init,
466 .fini = &r100_hpd_fini,
467 .sense = &r100_hpd_sense,
468 .set_polarity = &r100_hpd_set_polarity,
469 },
470 .pm = {
471 .misc = &r100_pm_misc,
472 .prepare = &r100_pm_prepare,
473 .finish = &r100_pm_finish,
474 .init_profile = &r100_pm_init_profile,
475 .get_dynpm_state = &r100_pm_get_dynpm_state,
476 .get_engine_clock = &radeon_legacy_get_engine_clock,
477 .set_engine_clock = &radeon_legacy_set_engine_clock,
478 .get_memory_clock = &radeon_legacy_get_memory_clock,
479 .set_memory_clock = NULL,
480 .get_pcie_lanes = &rv370_get_pcie_lanes,
481 .set_pcie_lanes = &rv370_set_pcie_lanes,
482 .set_clock_gating = &radeon_legacy_set_clock_gating,
483 },
484 .pflip = {
485 .pre_page_flip = &r100_pre_page_flip,
486 .page_flip = &r100_page_flip,
487 .post_page_flip = &r100_post_page_flip,
488 },
489};
490
491static struct radeon_asic r420_asic = {
492 .init = &r420_init,
493 .fini = &r420_fini,
494 .suspend = &r420_suspend,
495 .resume = &r420_resume,
496 .vga_set_state = &r100_vga_set_state,
497 .asic_reset = &r300_asic_reset,
498 .ioctl_wait_idle = NULL,
499 .gui_idle = &r100_gui_idle,
500 .mc_wait_for_idle = &r300_mc_wait_for_idle,
501 .gart = {
502 .tlb_flush = &rv370_pcie_gart_tlb_flush,
503 .set_page = &rv370_pcie_gart_set_page,
504 },
505 .ring = {
506 [RADEON_RING_TYPE_GFX_INDEX] = {
507 .ib_execute = &r100_ring_ib_execute,
508 .emit_fence = &r300_fence_ring_emit,
509 .emit_semaphore = &r100_semaphore_ring_emit,
510 .cs_parse = &r300_cs_parse,
511 .ring_start = &r300_ring_start,
512 .ring_test = &r100_ring_test,
513 .ib_test = &r100_ib_test,
514 .is_lockup = &r100_gpu_is_lockup,
515 .get_rptr = &radeon_ring_generic_get_rptr,
516 .get_wptr = &radeon_ring_generic_get_wptr,
517 .set_wptr = &radeon_ring_generic_set_wptr,
518 }
519 },
520 .irq = {
521 .set = &r100_irq_set,
522 .process = &r100_irq_process,
523 },
524 .display = {
525 .bandwidth_update = &r100_bandwidth_update,
526 .get_vblank_counter = &r100_get_vblank_counter,
527 .wait_for_vblank = &r100_wait_for_vblank,
528 .set_backlight_level = &atombios_set_backlight_level,
529 .get_backlight_level = &atombios_get_backlight_level,
530 },
531 .copy = {
532 .blit = &r100_copy_blit,
533 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
534 .dma = &r200_copy_dma,
535 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
536 .copy = &r100_copy_blit,
537 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
538 },
539 .surface = {
540 .set_reg = r100_set_surface_reg,
541 .clear_reg = r100_clear_surface_reg,
542 },
543 .hpd = {
544 .init = &r100_hpd_init,
545 .fini = &r100_hpd_fini,
546 .sense = &r100_hpd_sense,
547 .set_polarity = &r100_hpd_set_polarity,
548 },
549 .pm = {
550 .misc = &r100_pm_misc,
551 .prepare = &r100_pm_prepare,
552 .finish = &r100_pm_finish,
553 .init_profile = &r420_pm_init_profile,
554 .get_dynpm_state = &r100_pm_get_dynpm_state,
555 .get_engine_clock = &radeon_atom_get_engine_clock,
556 .set_engine_clock = &radeon_atom_set_engine_clock,
557 .get_memory_clock = &radeon_atom_get_memory_clock,
558 .set_memory_clock = &radeon_atom_set_memory_clock,
559 .get_pcie_lanes = &rv370_get_pcie_lanes,
560 .set_pcie_lanes = &rv370_set_pcie_lanes,
561 .set_clock_gating = &radeon_atom_set_clock_gating,
562 },
563 .pflip = {
564 .pre_page_flip = &r100_pre_page_flip,
565 .page_flip = &r100_page_flip,
566 .post_page_flip = &r100_post_page_flip,
567 },
568};
569
570static struct radeon_asic rs400_asic = {
571 .init = &rs400_init,
572 .fini = &rs400_fini,
573 .suspend = &rs400_suspend,
574 .resume = &rs400_resume,
575 .vga_set_state = &r100_vga_set_state,
576 .asic_reset = &r300_asic_reset,
577 .ioctl_wait_idle = NULL,
578 .gui_idle = &r100_gui_idle,
579 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
580 .gart = {
581 .tlb_flush = &rs400_gart_tlb_flush,
582 .set_page = &rs400_gart_set_page,
583 },
584 .ring = {
585 [RADEON_RING_TYPE_GFX_INDEX] = {
586 .ib_execute = &r100_ring_ib_execute,
587 .emit_fence = &r300_fence_ring_emit,
588 .emit_semaphore = &r100_semaphore_ring_emit,
589 .cs_parse = &r300_cs_parse,
590 .ring_start = &r300_ring_start,
591 .ring_test = &r100_ring_test,
592 .ib_test = &r100_ib_test,
593 .is_lockup = &r100_gpu_is_lockup,
594 .get_rptr = &radeon_ring_generic_get_rptr,
595 .get_wptr = &radeon_ring_generic_get_wptr,
596 .set_wptr = &radeon_ring_generic_set_wptr,
597 }
598 },
599 .irq = {
600 .set = &r100_irq_set,
601 .process = &r100_irq_process,
602 },
603 .display = {
604 .bandwidth_update = &r100_bandwidth_update,
605 .get_vblank_counter = &r100_get_vblank_counter,
606 .wait_for_vblank = &r100_wait_for_vblank,
607 .set_backlight_level = &radeon_legacy_set_backlight_level,
608 .get_backlight_level = &radeon_legacy_get_backlight_level,
609 },
610 .copy = {
611 .blit = &r100_copy_blit,
612 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
613 .dma = &r200_copy_dma,
614 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
615 .copy = &r100_copy_blit,
616 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
617 },
618 .surface = {
619 .set_reg = r100_set_surface_reg,
620 .clear_reg = r100_clear_surface_reg,
621 },
622 .hpd = {
623 .init = &r100_hpd_init,
624 .fini = &r100_hpd_fini,
625 .sense = &r100_hpd_sense,
626 .set_polarity = &r100_hpd_set_polarity,
627 },
628 .pm = {
629 .misc = &r100_pm_misc,
630 .prepare = &r100_pm_prepare,
631 .finish = &r100_pm_finish,
632 .init_profile = &r100_pm_init_profile,
633 .get_dynpm_state = &r100_pm_get_dynpm_state,
634 .get_engine_clock = &radeon_legacy_get_engine_clock,
635 .set_engine_clock = &radeon_legacy_set_engine_clock,
636 .get_memory_clock = &radeon_legacy_get_memory_clock,
637 .set_memory_clock = NULL,
638 .get_pcie_lanes = NULL,
639 .set_pcie_lanes = NULL,
640 .set_clock_gating = &radeon_legacy_set_clock_gating,
641 },
642 .pflip = {
643 .pre_page_flip = &r100_pre_page_flip,
644 .page_flip = &r100_page_flip,
645 .post_page_flip = &r100_post_page_flip,
646 },
647};
648
649static struct radeon_asic rs600_asic = {
650 .init = &rs600_init,
651 .fini = &rs600_fini,
652 .suspend = &rs600_suspend,
653 .resume = &rs600_resume,
654 .vga_set_state = &r100_vga_set_state,
655 .asic_reset = &rs600_asic_reset,
656 .ioctl_wait_idle = NULL,
657 .gui_idle = &r100_gui_idle,
658 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
659 .gart = {
660 .tlb_flush = &rs600_gart_tlb_flush,
661 .set_page = &rs600_gart_set_page,
662 },
663 .ring = {
664 [RADEON_RING_TYPE_GFX_INDEX] = {
665 .ib_execute = &r100_ring_ib_execute,
666 .emit_fence = &r300_fence_ring_emit,
667 .emit_semaphore = &r100_semaphore_ring_emit,
668 .cs_parse = &r300_cs_parse,
669 .ring_start = &r300_ring_start,
670 .ring_test = &r100_ring_test,
671 .ib_test = &r100_ib_test,
672 .is_lockup = &r100_gpu_is_lockup,
673 .get_rptr = &radeon_ring_generic_get_rptr,
674 .get_wptr = &radeon_ring_generic_get_wptr,
675 .set_wptr = &radeon_ring_generic_set_wptr,
676 }
677 },
678 .irq = {
679 .set = &rs600_irq_set,
680 .process = &rs600_irq_process,
681 },
682 .display = {
683 .bandwidth_update = &rs600_bandwidth_update,
684 .get_vblank_counter = &rs600_get_vblank_counter,
685 .wait_for_vblank = &avivo_wait_for_vblank,
686 .set_backlight_level = &atombios_set_backlight_level,
687 .get_backlight_level = &atombios_get_backlight_level,
688 .hdmi_enable = &r600_hdmi_enable,
689 .hdmi_setmode = &r600_hdmi_setmode,
690 },
691 .copy = {
692 .blit = &r100_copy_blit,
693 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
694 .dma = &r200_copy_dma,
695 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
696 .copy = &r100_copy_blit,
697 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
698 },
699 .surface = {
700 .set_reg = r100_set_surface_reg,
701 .clear_reg = r100_clear_surface_reg,
702 },
703 .hpd = {
704 .init = &rs600_hpd_init,
705 .fini = &rs600_hpd_fini,
706 .sense = &rs600_hpd_sense,
707 .set_polarity = &rs600_hpd_set_polarity,
708 },
709 .pm = {
710 .misc = &rs600_pm_misc,
711 .prepare = &rs600_pm_prepare,
712 .finish = &rs600_pm_finish,
713 .init_profile = &r420_pm_init_profile,
714 .get_dynpm_state = &r100_pm_get_dynpm_state,
715 .get_engine_clock = &radeon_atom_get_engine_clock,
716 .set_engine_clock = &radeon_atom_set_engine_clock,
717 .get_memory_clock = &radeon_atom_get_memory_clock,
718 .set_memory_clock = &radeon_atom_set_memory_clock,
719 .get_pcie_lanes = NULL,
720 .set_pcie_lanes = NULL,
721 .set_clock_gating = &radeon_atom_set_clock_gating,
722 },
723 .pflip = {
724 .pre_page_flip = &rs600_pre_page_flip,
725 .page_flip = &rs600_page_flip,
726 .post_page_flip = &rs600_post_page_flip,
727 },
728};
729
730static struct radeon_asic rs690_asic = {
731 .init = &rs690_init,
732 .fini = &rs690_fini,
733 .suspend = &rs690_suspend,
734 .resume = &rs690_resume,
735 .vga_set_state = &r100_vga_set_state,
736 .asic_reset = &rs600_asic_reset,
737 .ioctl_wait_idle = NULL,
738 .gui_idle = &r100_gui_idle,
739 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
740 .gart = {
741 .tlb_flush = &rs400_gart_tlb_flush,
742 .set_page = &rs400_gart_set_page,
743 },
744 .ring = {
745 [RADEON_RING_TYPE_GFX_INDEX] = {
746 .ib_execute = &r100_ring_ib_execute,
747 .emit_fence = &r300_fence_ring_emit,
748 .emit_semaphore = &r100_semaphore_ring_emit,
749 .cs_parse = &r300_cs_parse,
750 .ring_start = &r300_ring_start,
751 .ring_test = &r100_ring_test,
752 .ib_test = &r100_ib_test,
753 .is_lockup = &r100_gpu_is_lockup,
754 .get_rptr = &radeon_ring_generic_get_rptr,
755 .get_wptr = &radeon_ring_generic_get_wptr,
756 .set_wptr = &radeon_ring_generic_set_wptr,
757 }
758 },
759 .irq = {
760 .set = &rs600_irq_set,
761 .process = &rs600_irq_process,
762 },
763 .display = {
764 .get_vblank_counter = &rs600_get_vblank_counter,
765 .bandwidth_update = &rs690_bandwidth_update,
766 .wait_for_vblank = &avivo_wait_for_vblank,
767 .set_backlight_level = &atombios_set_backlight_level,
768 .get_backlight_level = &atombios_get_backlight_level,
769 .hdmi_enable = &r600_hdmi_enable,
770 .hdmi_setmode = &r600_hdmi_setmode,
771 },
772 .copy = {
773 .blit = &r100_copy_blit,
774 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
775 .dma = &r200_copy_dma,
776 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
777 .copy = &r200_copy_dma,
778 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
779 },
780 .surface = {
781 .set_reg = r100_set_surface_reg,
782 .clear_reg = r100_clear_surface_reg,
783 },
784 .hpd = {
785 .init = &rs600_hpd_init,
786 .fini = &rs600_hpd_fini,
787 .sense = &rs600_hpd_sense,
788 .set_polarity = &rs600_hpd_set_polarity,
789 },
790 .pm = {
791 .misc = &rs600_pm_misc,
792 .prepare = &rs600_pm_prepare,
793 .finish = &rs600_pm_finish,
794 .init_profile = &r420_pm_init_profile,
795 .get_dynpm_state = &r100_pm_get_dynpm_state,
796 .get_engine_clock = &radeon_atom_get_engine_clock,
797 .set_engine_clock = &radeon_atom_set_engine_clock,
798 .get_memory_clock = &radeon_atom_get_memory_clock,
799 .set_memory_clock = &radeon_atom_set_memory_clock,
800 .get_pcie_lanes = NULL,
801 .set_pcie_lanes = NULL,
802 .set_clock_gating = &radeon_atom_set_clock_gating,
803 },
804 .pflip = {
805 .pre_page_flip = &rs600_pre_page_flip,
806 .page_flip = &rs600_page_flip,
807 .post_page_flip = &rs600_post_page_flip,
808 },
809};
810
811static struct radeon_asic rv515_asic = {
812 .init = &rv515_init,
813 .fini = &rv515_fini,
814 .suspend = &rv515_suspend,
815 .resume = &rv515_resume,
816 .vga_set_state = &r100_vga_set_state,
817 .asic_reset = &rs600_asic_reset,
818 .ioctl_wait_idle = NULL,
819 .gui_idle = &r100_gui_idle,
820 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
821 .gart = {
822 .tlb_flush = &rv370_pcie_gart_tlb_flush,
823 .set_page = &rv370_pcie_gart_set_page,
824 },
825 .ring = {
826 [RADEON_RING_TYPE_GFX_INDEX] = {
827 .ib_execute = &r100_ring_ib_execute,
828 .emit_fence = &r300_fence_ring_emit,
829 .emit_semaphore = &r100_semaphore_ring_emit,
830 .cs_parse = &r300_cs_parse,
831 .ring_start = &rv515_ring_start,
832 .ring_test = &r100_ring_test,
833 .ib_test = &r100_ib_test,
834 .is_lockup = &r100_gpu_is_lockup,
835 .get_rptr = &radeon_ring_generic_get_rptr,
836 .get_wptr = &radeon_ring_generic_get_wptr,
837 .set_wptr = &radeon_ring_generic_set_wptr,
838 }
839 },
840 .irq = {
841 .set = &rs600_irq_set,
842 .process = &rs600_irq_process,
843 },
844 .display = {
845 .get_vblank_counter = &rs600_get_vblank_counter,
846 .bandwidth_update = &rv515_bandwidth_update,
847 .wait_for_vblank = &avivo_wait_for_vblank,
848 .set_backlight_level = &atombios_set_backlight_level,
849 .get_backlight_level = &atombios_get_backlight_level,
850 },
851 .copy = {
852 .blit = &r100_copy_blit,
853 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
854 .dma = &r200_copy_dma,
855 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
856 .copy = &r100_copy_blit,
857 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
858 },
859 .surface = {
860 .set_reg = r100_set_surface_reg,
861 .clear_reg = r100_clear_surface_reg,
862 },
863 .hpd = {
864 .init = &rs600_hpd_init,
865 .fini = &rs600_hpd_fini,
866 .sense = &rs600_hpd_sense,
867 .set_polarity = &rs600_hpd_set_polarity,
868 },
869 .pm = {
870 .misc = &rs600_pm_misc,
871 .prepare = &rs600_pm_prepare,
872 .finish = &rs600_pm_finish,
873 .init_profile = &r420_pm_init_profile,
874 .get_dynpm_state = &r100_pm_get_dynpm_state,
875 .get_engine_clock = &radeon_atom_get_engine_clock,
876 .set_engine_clock = &radeon_atom_set_engine_clock,
877 .get_memory_clock = &radeon_atom_get_memory_clock,
878 .set_memory_clock = &radeon_atom_set_memory_clock,
879 .get_pcie_lanes = &rv370_get_pcie_lanes,
880 .set_pcie_lanes = &rv370_set_pcie_lanes,
881 .set_clock_gating = &radeon_atom_set_clock_gating,
882 },
883 .pflip = {
884 .pre_page_flip = &rs600_pre_page_flip,
885 .page_flip = &rs600_page_flip,
886 .post_page_flip = &rs600_post_page_flip,
887 },
888};
889
890static struct radeon_asic r520_asic = {
891 .init = &r520_init,
892 .fini = &rv515_fini,
893 .suspend = &rv515_suspend,
894 .resume = &r520_resume,
895 .vga_set_state = &r100_vga_set_state,
896 .asic_reset = &rs600_asic_reset,
897 .ioctl_wait_idle = NULL,
898 .gui_idle = &r100_gui_idle,
899 .mc_wait_for_idle = &r520_mc_wait_for_idle,
900 .gart = {
901 .tlb_flush = &rv370_pcie_gart_tlb_flush,
902 .set_page = &rv370_pcie_gart_set_page,
903 },
904 .ring = {
905 [RADEON_RING_TYPE_GFX_INDEX] = {
906 .ib_execute = &r100_ring_ib_execute,
907 .emit_fence = &r300_fence_ring_emit,
908 .emit_semaphore = &r100_semaphore_ring_emit,
909 .cs_parse = &r300_cs_parse,
910 .ring_start = &rv515_ring_start,
911 .ring_test = &r100_ring_test,
912 .ib_test = &r100_ib_test,
913 .is_lockup = &r100_gpu_is_lockup,
914 .get_rptr = &radeon_ring_generic_get_rptr,
915 .get_wptr = &radeon_ring_generic_get_wptr,
916 .set_wptr = &radeon_ring_generic_set_wptr,
917 }
918 },
919 .irq = {
920 .set = &rs600_irq_set,
921 .process = &rs600_irq_process,
922 },
923 .display = {
924 .bandwidth_update = &rv515_bandwidth_update,
925 .get_vblank_counter = &rs600_get_vblank_counter,
926 .wait_for_vblank = &avivo_wait_for_vblank,
927 .set_backlight_level = &atombios_set_backlight_level,
928 .get_backlight_level = &atombios_get_backlight_level,
929 },
930 .copy = {
931 .blit = &r100_copy_blit,
932 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
933 .dma = &r200_copy_dma,
934 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
935 .copy = &r100_copy_blit,
936 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
937 },
938 .surface = {
939 .set_reg = r100_set_surface_reg,
940 .clear_reg = r100_clear_surface_reg,
941 },
942 .hpd = {
943 .init = &rs600_hpd_init,
944 .fini = &rs600_hpd_fini,
945 .sense = &rs600_hpd_sense,
946 .set_polarity = &rs600_hpd_set_polarity,
947 },
948 .pm = {
949 .misc = &rs600_pm_misc,
950 .prepare = &rs600_pm_prepare,
951 .finish = &rs600_pm_finish,
952 .init_profile = &r420_pm_init_profile,
953 .get_dynpm_state = &r100_pm_get_dynpm_state,
954 .get_engine_clock = &radeon_atom_get_engine_clock,
955 .set_engine_clock = &radeon_atom_set_engine_clock,
956 .get_memory_clock = &radeon_atom_get_memory_clock,
957 .set_memory_clock = &radeon_atom_set_memory_clock,
958 .get_pcie_lanes = &rv370_get_pcie_lanes,
959 .set_pcie_lanes = &rv370_set_pcie_lanes,
960 .set_clock_gating = &radeon_atom_set_clock_gating,
961 },
962 .pflip = {
963 .pre_page_flip = &rs600_pre_page_flip,
964 .page_flip = &rs600_page_flip,
965 .post_page_flip = &rs600_post_page_flip,
966 },
967};
968
969static struct radeon_asic r600_asic = {
970 .init = &r600_init,
971 .fini = &r600_fini,
972 .suspend = &r600_suspend,
973 .resume = &r600_resume,
974 .vga_set_state = &r600_vga_set_state,
975 .asic_reset = &r600_asic_reset,
976 .ioctl_wait_idle = r600_ioctl_wait_idle,
977 .gui_idle = &r600_gui_idle,
978 .mc_wait_for_idle = &r600_mc_wait_for_idle,
979 .get_xclk = &r600_get_xclk,
980 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
981 .gart = {
982 .tlb_flush = &r600_pcie_gart_tlb_flush,
983 .set_page = &rs600_gart_set_page,
984 },
985 .ring = {
986 [RADEON_RING_TYPE_GFX_INDEX] = {
987 .ib_execute = &r600_ring_ib_execute,
988 .emit_fence = &r600_fence_ring_emit,
989 .emit_semaphore = &r600_semaphore_ring_emit,
990 .cs_parse = &r600_cs_parse,
991 .ring_test = &r600_ring_test,
992 .ib_test = &r600_ib_test,
993 .is_lockup = &r600_gfx_is_lockup,
994 .get_rptr = &radeon_ring_generic_get_rptr,
995 .get_wptr = &radeon_ring_generic_get_wptr,
996 .set_wptr = &radeon_ring_generic_set_wptr,
997 },
998 [R600_RING_TYPE_DMA_INDEX] = {
999 .ib_execute = &r600_dma_ring_ib_execute,
1000 .emit_fence = &r600_dma_fence_ring_emit,
1001 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1002 .cs_parse = &r600_dma_cs_parse,
1003 .ring_test = &r600_dma_ring_test,
1004 .ib_test = &r600_dma_ib_test,
1005 .is_lockup = &r600_dma_is_lockup,
1006 .get_rptr = &radeon_ring_generic_get_rptr,
1007 .get_wptr = &radeon_ring_generic_get_wptr,
1008 .set_wptr = &radeon_ring_generic_set_wptr,
1009 }
1010 },
1011 .irq = {
1012 .set = &r600_irq_set,
1013 .process = &r600_irq_process,
1014 },
1015 .display = {
1016 .bandwidth_update = &rv515_bandwidth_update,
1017 .get_vblank_counter = &rs600_get_vblank_counter,
1018 .wait_for_vblank = &avivo_wait_for_vblank,
1019 .set_backlight_level = &atombios_set_backlight_level,
1020 .get_backlight_level = &atombios_get_backlight_level,
1021 .hdmi_enable = &r600_hdmi_enable,
1022 .hdmi_setmode = &r600_hdmi_setmode,
1023 },
1024 .copy = {
1025 .blit = &r600_copy_cpdma,
1026 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1027 .dma = &r600_copy_dma,
1028 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1029 .copy = &r600_copy_cpdma,
1030 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1031 },
1032 .surface = {
1033 .set_reg = r600_set_surface_reg,
1034 .clear_reg = r600_clear_surface_reg,
1035 },
1036 .hpd = {
1037 .init = &r600_hpd_init,
1038 .fini = &r600_hpd_fini,
1039 .sense = &r600_hpd_sense,
1040 .set_polarity = &r600_hpd_set_polarity,
1041 },
1042 .pm = {
1043 .misc = &r600_pm_misc,
1044 .prepare = &rs600_pm_prepare,
1045 .finish = &rs600_pm_finish,
1046 .init_profile = &r600_pm_init_profile,
1047 .get_dynpm_state = &r600_pm_get_dynpm_state,
1048 .get_engine_clock = &radeon_atom_get_engine_clock,
1049 .set_engine_clock = &radeon_atom_set_engine_clock,
1050 .get_memory_clock = &radeon_atom_get_memory_clock,
1051 .set_memory_clock = &radeon_atom_set_memory_clock,
1052 .get_pcie_lanes = &r600_get_pcie_lanes,
1053 .set_pcie_lanes = &r600_set_pcie_lanes,
1054 .set_clock_gating = NULL,
1055 .get_temperature = &rv6xx_get_temp,
1056 },
1057 .pflip = {
1058 .pre_page_flip = &rs600_pre_page_flip,
1059 .page_flip = &rs600_page_flip,
1060 .post_page_flip = &rs600_post_page_flip,
1061 },
1062};
1063
1064static struct radeon_asic rv6xx_asic = {
1065 .init = &r600_init,
1066 .fini = &r600_fini,
1067 .suspend = &r600_suspend,
1068 .resume = &r600_resume,
1069 .vga_set_state = &r600_vga_set_state,
1070 .asic_reset = &r600_asic_reset,
1071 .ioctl_wait_idle = r600_ioctl_wait_idle,
1072 .gui_idle = &r600_gui_idle,
1073 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1074 .get_xclk = &r600_get_xclk,
1075 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1076 .gart = {
1077 .tlb_flush = &r600_pcie_gart_tlb_flush,
1078 .set_page = &rs600_gart_set_page,
1079 },
1080 .ring = {
1081 [RADEON_RING_TYPE_GFX_INDEX] = {
1082 .ib_execute = &r600_ring_ib_execute,
1083 .emit_fence = &r600_fence_ring_emit,
1084 .emit_semaphore = &r600_semaphore_ring_emit,
1085 .cs_parse = &r600_cs_parse,
1086 .ring_test = &r600_ring_test,
1087 .ib_test = &r600_ib_test,
1088 .is_lockup = &r600_gfx_is_lockup,
1089 .get_rptr = &radeon_ring_generic_get_rptr,
1090 .get_wptr = &radeon_ring_generic_get_wptr,
1091 .set_wptr = &radeon_ring_generic_set_wptr,
1092 },
1093 [R600_RING_TYPE_DMA_INDEX] = {
1094 .ib_execute = &r600_dma_ring_ib_execute,
1095 .emit_fence = &r600_dma_fence_ring_emit,
1096 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1097 .cs_parse = &r600_dma_cs_parse,
1098 .ring_test = &r600_dma_ring_test,
1099 .ib_test = &r600_dma_ib_test,
1100 .is_lockup = &r600_dma_is_lockup,
1101 .get_rptr = &radeon_ring_generic_get_rptr,
1102 .get_wptr = &radeon_ring_generic_get_wptr,
1103 .set_wptr = &radeon_ring_generic_set_wptr,
1104 }
1105 },
1106 .irq = {
1107 .set = &r600_irq_set,
1108 .process = &r600_irq_process,
1109 },
1110 .display = {
1111 .bandwidth_update = &rv515_bandwidth_update,
1112 .get_vblank_counter = &rs600_get_vblank_counter,
1113 .wait_for_vblank = &avivo_wait_for_vblank,
1114 .set_backlight_level = &atombios_set_backlight_level,
1115 .get_backlight_level = &atombios_get_backlight_level,
1116 },
1117 .copy = {
1118 .blit = &r600_copy_cpdma,
1119 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1120 .dma = &r600_copy_dma,
1121 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1122 .copy = &r600_copy_cpdma,
1123 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1124 },
1125 .surface = {
1126 .set_reg = r600_set_surface_reg,
1127 .clear_reg = r600_clear_surface_reg,
1128 },
1129 .hpd = {
1130 .init = &r600_hpd_init,
1131 .fini = &r600_hpd_fini,
1132 .sense = &r600_hpd_sense,
1133 .set_polarity = &r600_hpd_set_polarity,
1134 },
1135 .pm = {
1136 .misc = &r600_pm_misc,
1137 .prepare = &rs600_pm_prepare,
1138 .finish = &rs600_pm_finish,
1139 .init_profile = &r600_pm_init_profile,
1140 .get_dynpm_state = &r600_pm_get_dynpm_state,
1141 .get_engine_clock = &radeon_atom_get_engine_clock,
1142 .set_engine_clock = &radeon_atom_set_engine_clock,
1143 .get_memory_clock = &radeon_atom_get_memory_clock,
1144 .set_memory_clock = &radeon_atom_set_memory_clock,
1145 .get_pcie_lanes = &r600_get_pcie_lanes,
1146 .set_pcie_lanes = &r600_set_pcie_lanes,
1147 .set_clock_gating = NULL,
1148 .get_temperature = &rv6xx_get_temp,
1149 },
1150 .dpm = {
1151 .init = &rv6xx_dpm_init,
1152 .setup_asic = &rv6xx_setup_asic,
1153 .enable = &rv6xx_dpm_enable,
1154 .disable = &rv6xx_dpm_disable,
1155 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1156 .set_power_state = &rv6xx_dpm_set_power_state,
1157 .post_set_power_state = &r600_dpm_post_set_power_state,
1158 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1159 .fini = &rv6xx_dpm_fini,
1160 .get_sclk = &rv6xx_dpm_get_sclk,
1161 .get_mclk = &rv6xx_dpm_get_mclk,
1162 .print_power_state = &rv6xx_dpm_print_power_state,
1163 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1164 .force_performance_level = &rv6xx_dpm_force_performance_level,
1165 },
1166 .pflip = {
1167 .pre_page_flip = &rs600_pre_page_flip,
1168 .page_flip = &rs600_page_flip,
1169 .post_page_flip = &rs600_post_page_flip,
1170 },
1171};
1172
1173static struct radeon_asic rs780_asic = {
1174 .init = &r600_init,
1175 .fini = &r600_fini,
1176 .suspend = &r600_suspend,
1177 .resume = &r600_resume,
1178 .vga_set_state = &r600_vga_set_state,
1179 .asic_reset = &r600_asic_reset,
1180 .ioctl_wait_idle = r600_ioctl_wait_idle,
1181 .gui_idle = &r600_gui_idle,
1182 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1183 .get_xclk = &r600_get_xclk,
1184 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1185 .gart = {
1186 .tlb_flush = &r600_pcie_gart_tlb_flush,
1187 .set_page = &rs600_gart_set_page,
1188 },
1189 .ring = {
1190 [RADEON_RING_TYPE_GFX_INDEX] = {
1191 .ib_execute = &r600_ring_ib_execute,
1192 .emit_fence = &r600_fence_ring_emit,
1193 .emit_semaphore = &r600_semaphore_ring_emit,
1194 .cs_parse = &r600_cs_parse,
1195 .ring_test = &r600_ring_test,
1196 .ib_test = &r600_ib_test,
1197 .is_lockup = &r600_gfx_is_lockup,
1198 .get_rptr = &radeon_ring_generic_get_rptr,
1199 .get_wptr = &radeon_ring_generic_get_wptr,
1200 .set_wptr = &radeon_ring_generic_set_wptr,
1201 },
1202 [R600_RING_TYPE_DMA_INDEX] = {
1203 .ib_execute = &r600_dma_ring_ib_execute,
1204 .emit_fence = &r600_dma_fence_ring_emit,
1205 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1206 .cs_parse = &r600_dma_cs_parse,
1207 .ring_test = &r600_dma_ring_test,
1208 .ib_test = &r600_dma_ib_test,
1209 .is_lockup = &r600_dma_is_lockup,
1210 .get_rptr = &radeon_ring_generic_get_rptr,
1211 .get_wptr = &radeon_ring_generic_get_wptr,
1212 .set_wptr = &radeon_ring_generic_set_wptr,
1213 }
1214 },
1215 .irq = {
1216 .set = &r600_irq_set,
1217 .process = &r600_irq_process,
1218 },
1219 .display = {
1220 .bandwidth_update = &rs690_bandwidth_update,
1221 .get_vblank_counter = &rs600_get_vblank_counter,
1222 .wait_for_vblank = &avivo_wait_for_vblank,
1223 .set_backlight_level = &atombios_set_backlight_level,
1224 .get_backlight_level = &atombios_get_backlight_level,
1225 .hdmi_enable = &r600_hdmi_enable,
1226 .hdmi_setmode = &r600_hdmi_setmode,
1227 },
1228 .copy = {
1229 .blit = &r600_copy_cpdma,
1230 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1231 .dma = &r600_copy_dma,
1232 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1233 .copy = &r600_copy_cpdma,
1234 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1235 },
1236 .surface = {
1237 .set_reg = r600_set_surface_reg,
1238 .clear_reg = r600_clear_surface_reg,
1239 },
1240 .hpd = {
1241 .init = &r600_hpd_init,
1242 .fini = &r600_hpd_fini,
1243 .sense = &r600_hpd_sense,
1244 .set_polarity = &r600_hpd_set_polarity,
1245 },
1246 .pm = {
1247 .misc = &r600_pm_misc,
1248 .prepare = &rs600_pm_prepare,
1249 .finish = &rs600_pm_finish,
1250 .init_profile = &rs780_pm_init_profile,
1251 .get_dynpm_state = &r600_pm_get_dynpm_state,
1252 .get_engine_clock = &radeon_atom_get_engine_clock,
1253 .set_engine_clock = &radeon_atom_set_engine_clock,
1254 .get_memory_clock = NULL,
1255 .set_memory_clock = NULL,
1256 .get_pcie_lanes = NULL,
1257 .set_pcie_lanes = NULL,
1258 .set_clock_gating = NULL,
1259 .get_temperature = &rv6xx_get_temp,
1260 },
1261 .dpm = {
1262 .init = &rs780_dpm_init,
1263 .setup_asic = &rs780_dpm_setup_asic,
1264 .enable = &rs780_dpm_enable,
1265 .disable = &rs780_dpm_disable,
1266 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1267 .set_power_state = &rs780_dpm_set_power_state,
1268 .post_set_power_state = &r600_dpm_post_set_power_state,
1269 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1270 .fini = &rs780_dpm_fini,
1271 .get_sclk = &rs780_dpm_get_sclk,
1272 .get_mclk = &rs780_dpm_get_mclk,
1273 .print_power_state = &rs780_dpm_print_power_state,
1274 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
1275 },
1276 .pflip = {
1277 .pre_page_flip = &rs600_pre_page_flip,
1278 .page_flip = &rs600_page_flip,
1279 .post_page_flip = &rs600_post_page_flip,
1280 },
1281};
1282
1283static struct radeon_asic rv770_asic = {
1284 .init = &rv770_init,
1285 .fini = &rv770_fini,
1286 .suspend = &rv770_suspend,
1287 .resume = &rv770_resume,
1288 .asic_reset = &r600_asic_reset,
1289 .vga_set_state = &r600_vga_set_state,
1290 .ioctl_wait_idle = r600_ioctl_wait_idle,
1291 .gui_idle = &r600_gui_idle,
1292 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1293 .get_xclk = &rv770_get_xclk,
1294 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1295 .gart = {
1296 .tlb_flush = &r600_pcie_gart_tlb_flush,
1297 .set_page = &rs600_gart_set_page,
1298 },
1299 .ring = {
1300 [RADEON_RING_TYPE_GFX_INDEX] = {
1301 .ib_execute = &r600_ring_ib_execute,
1302 .emit_fence = &r600_fence_ring_emit,
1303 .emit_semaphore = &r600_semaphore_ring_emit,
1304 .cs_parse = &r600_cs_parse,
1305 .ring_test = &r600_ring_test,
1306 .ib_test = &r600_ib_test,
1307 .is_lockup = &r600_gfx_is_lockup,
1308 .get_rptr = &radeon_ring_generic_get_rptr,
1309 .get_wptr = &radeon_ring_generic_get_wptr,
1310 .set_wptr = &radeon_ring_generic_set_wptr,
1311 },
1312 [R600_RING_TYPE_DMA_INDEX] = {
1313 .ib_execute = &r600_dma_ring_ib_execute,
1314 .emit_fence = &r600_dma_fence_ring_emit,
1315 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1316 .cs_parse = &r600_dma_cs_parse,
1317 .ring_test = &r600_dma_ring_test,
1318 .ib_test = &r600_dma_ib_test,
1319 .is_lockup = &r600_dma_is_lockup,
1320 .get_rptr = &radeon_ring_generic_get_rptr,
1321 .get_wptr = &radeon_ring_generic_get_wptr,
1322 .set_wptr = &radeon_ring_generic_set_wptr,
1323 },
1324 [R600_RING_TYPE_UVD_INDEX] = {
1325 .ib_execute = &r600_uvd_ib_execute,
1326 .emit_fence = &r600_uvd_fence_emit,
1327 .emit_semaphore = &r600_uvd_semaphore_emit,
1328 .cs_parse = &radeon_uvd_cs_parse,
1329 .ring_test = &r600_uvd_ring_test,
1330 .ib_test = &r600_uvd_ib_test,
1331 .is_lockup = &radeon_ring_test_lockup,
1332 .get_rptr = &radeon_ring_generic_get_rptr,
1333 .get_wptr = &radeon_ring_generic_get_wptr,
1334 .set_wptr = &radeon_ring_generic_set_wptr,
1335 }
1336 },
1337 .irq = {
1338 .set = &r600_irq_set,
1339 .process = &r600_irq_process,
1340 },
1341 .display = {
1342 .bandwidth_update = &rv515_bandwidth_update,
1343 .get_vblank_counter = &rs600_get_vblank_counter,
1344 .wait_for_vblank = &avivo_wait_for_vblank,
1345 .set_backlight_level = &atombios_set_backlight_level,
1346 .get_backlight_level = &atombios_get_backlight_level,
1347 .hdmi_enable = &r600_hdmi_enable,
1348 .hdmi_setmode = &r600_hdmi_setmode,
1349 },
1350 .copy = {
1351 .blit = &r600_copy_cpdma,
1352 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1353 .dma = &rv770_copy_dma,
1354 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1355 .copy = &rv770_copy_dma,
1356 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1357 },
1358 .surface = {
1359 .set_reg = r600_set_surface_reg,
1360 .clear_reg = r600_clear_surface_reg,
1361 },
1362 .hpd = {
1363 .init = &r600_hpd_init,
1364 .fini = &r600_hpd_fini,
1365 .sense = &r600_hpd_sense,
1366 .set_polarity = &r600_hpd_set_polarity,
1367 },
1368 .pm = {
1369 .misc = &rv770_pm_misc,
1370 .prepare = &rs600_pm_prepare,
1371 .finish = &rs600_pm_finish,
1372 .init_profile = &r600_pm_init_profile,
1373 .get_dynpm_state = &r600_pm_get_dynpm_state,
1374 .get_engine_clock = &radeon_atom_get_engine_clock,
1375 .set_engine_clock = &radeon_atom_set_engine_clock,
1376 .get_memory_clock = &radeon_atom_get_memory_clock,
1377 .set_memory_clock = &radeon_atom_set_memory_clock,
1378 .get_pcie_lanes = &r600_get_pcie_lanes,
1379 .set_pcie_lanes = &r600_set_pcie_lanes,
1380 .set_clock_gating = &radeon_atom_set_clock_gating,
1381 .set_uvd_clocks = &rv770_set_uvd_clocks,
1382 .get_temperature = &rv770_get_temp,
1383 },
1384 .dpm = {
1385 .init = &rv770_dpm_init,
1386 .setup_asic = &rv770_dpm_setup_asic,
1387 .enable = &rv770_dpm_enable,
1388 .disable = &rv770_dpm_disable,
1389 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1390 .set_power_state = &rv770_dpm_set_power_state,
1391 .post_set_power_state = &r600_dpm_post_set_power_state,
1392 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1393 .fini = &rv770_dpm_fini,
1394 .get_sclk = &rv770_dpm_get_sclk,
1395 .get_mclk = &rv770_dpm_get_mclk,
1396 .print_power_state = &rv770_dpm_print_power_state,
1397 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1398 .force_performance_level = &rv770_dpm_force_performance_level,
1399 .vblank_too_short = &rv770_dpm_vblank_too_short,
1400 },
1401 .pflip = {
1402 .pre_page_flip = &rs600_pre_page_flip,
1403 .page_flip = &rv770_page_flip,
1404 .post_page_flip = &rs600_post_page_flip,
1405 },
1406};
1407
1408static struct radeon_asic evergreen_asic = {
1409 .init = &evergreen_init,
1410 .fini = &evergreen_fini,
1411 .suspend = &evergreen_suspend,
1412 .resume = &evergreen_resume,
1413 .asic_reset = &evergreen_asic_reset,
1414 .vga_set_state = &r600_vga_set_state,
1415 .ioctl_wait_idle = r600_ioctl_wait_idle,
1416 .gui_idle = &r600_gui_idle,
1417 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1418 .get_xclk = &rv770_get_xclk,
1419 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1420 .gart = {
1421 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1422 .set_page = &rs600_gart_set_page,
1423 },
1424 .ring = {
1425 [RADEON_RING_TYPE_GFX_INDEX] = {
1426 .ib_execute = &evergreen_ring_ib_execute,
1427 .emit_fence = &r600_fence_ring_emit,
1428 .emit_semaphore = &r600_semaphore_ring_emit,
1429 .cs_parse = &evergreen_cs_parse,
1430 .ring_test = &r600_ring_test,
1431 .ib_test = &r600_ib_test,
1432 .is_lockup = &evergreen_gfx_is_lockup,
1433 .get_rptr = &radeon_ring_generic_get_rptr,
1434 .get_wptr = &radeon_ring_generic_get_wptr,
1435 .set_wptr = &radeon_ring_generic_set_wptr,
1436 },
1437 [R600_RING_TYPE_DMA_INDEX] = {
1438 .ib_execute = &evergreen_dma_ring_ib_execute,
1439 .emit_fence = &evergreen_dma_fence_ring_emit,
1440 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1441 .cs_parse = &evergreen_dma_cs_parse,
1442 .ring_test = &r600_dma_ring_test,
1443 .ib_test = &r600_dma_ib_test,
1444 .is_lockup = &evergreen_dma_is_lockup,
1445 .get_rptr = &radeon_ring_generic_get_rptr,
1446 .get_wptr = &radeon_ring_generic_get_wptr,
1447 .set_wptr = &radeon_ring_generic_set_wptr,
1448 },
1449 [R600_RING_TYPE_UVD_INDEX] = {
1450 .ib_execute = &r600_uvd_ib_execute,
1451 .emit_fence = &r600_uvd_fence_emit,
1452 .emit_semaphore = &r600_uvd_semaphore_emit,
1453 .cs_parse = &radeon_uvd_cs_parse,
1454 .ring_test = &r600_uvd_ring_test,
1455 .ib_test = &r600_uvd_ib_test,
1456 .is_lockup = &radeon_ring_test_lockup,
1457 .get_rptr = &radeon_ring_generic_get_rptr,
1458 .get_wptr = &radeon_ring_generic_get_wptr,
1459 .set_wptr = &radeon_ring_generic_set_wptr,
1460 }
1461 },
1462 .irq = {
1463 .set = &evergreen_irq_set,
1464 .process = &evergreen_irq_process,
1465 },
1466 .display = {
1467 .bandwidth_update = &evergreen_bandwidth_update,
1468 .get_vblank_counter = &evergreen_get_vblank_counter,
1469 .wait_for_vblank = &dce4_wait_for_vblank,
1470 .set_backlight_level = &atombios_set_backlight_level,
1471 .get_backlight_level = &atombios_get_backlight_level,
1472 .hdmi_enable = &evergreen_hdmi_enable,
1473 .hdmi_setmode = &evergreen_hdmi_setmode,
1474 },
1475 .copy = {
1476 .blit = &r600_copy_cpdma,
1477 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1478 .dma = &evergreen_copy_dma,
1479 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1480 .copy = &evergreen_copy_dma,
1481 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1482 },
1483 .surface = {
1484 .set_reg = r600_set_surface_reg,
1485 .clear_reg = r600_clear_surface_reg,
1486 },
1487 .hpd = {
1488 .init = &evergreen_hpd_init,
1489 .fini = &evergreen_hpd_fini,
1490 .sense = &evergreen_hpd_sense,
1491 .set_polarity = &evergreen_hpd_set_polarity,
1492 },
1493 .pm = {
1494 .misc = &evergreen_pm_misc,
1495 .prepare = &evergreen_pm_prepare,
1496 .finish = &evergreen_pm_finish,
1497 .init_profile = &r600_pm_init_profile,
1498 .get_dynpm_state = &r600_pm_get_dynpm_state,
1499 .get_engine_clock = &radeon_atom_get_engine_clock,
1500 .set_engine_clock = &radeon_atom_set_engine_clock,
1501 .get_memory_clock = &radeon_atom_get_memory_clock,
1502 .set_memory_clock = &radeon_atom_set_memory_clock,
1503 .get_pcie_lanes = &r600_get_pcie_lanes,
1504 .set_pcie_lanes = &r600_set_pcie_lanes,
1505 .set_clock_gating = NULL,
1506 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1507 .get_temperature = &evergreen_get_temp,
1508 },
1509 .dpm = {
1510 .init = &cypress_dpm_init,
1511 .setup_asic = &cypress_dpm_setup_asic,
1512 .enable = &cypress_dpm_enable,
1513 .disable = &cypress_dpm_disable,
1514 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1515 .set_power_state = &cypress_dpm_set_power_state,
1516 .post_set_power_state = &r600_dpm_post_set_power_state,
1517 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1518 .fini = &cypress_dpm_fini,
1519 .get_sclk = &rv770_dpm_get_sclk,
1520 .get_mclk = &rv770_dpm_get_mclk,
1521 .print_power_state = &rv770_dpm_print_power_state,
1522 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1523 .force_performance_level = &rv770_dpm_force_performance_level,
1524 .vblank_too_short = &cypress_dpm_vblank_too_short,
1525 },
1526 .pflip = {
1527 .pre_page_flip = &evergreen_pre_page_flip,
1528 .page_flip = &evergreen_page_flip,
1529 .post_page_flip = &evergreen_post_page_flip,
1530 },
1531};
1532
1533static struct radeon_asic sumo_asic = {
1534 .init = &evergreen_init,
1535 .fini = &evergreen_fini,
1536 .suspend = &evergreen_suspend,
1537 .resume = &evergreen_resume,
1538 .asic_reset = &evergreen_asic_reset,
1539 .vga_set_state = &r600_vga_set_state,
1540 .ioctl_wait_idle = r600_ioctl_wait_idle,
1541 .gui_idle = &r600_gui_idle,
1542 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1543 .get_xclk = &r600_get_xclk,
1544 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1545 .gart = {
1546 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1547 .set_page = &rs600_gart_set_page,
1548 },
1549 .ring = {
1550 [RADEON_RING_TYPE_GFX_INDEX] = {
1551 .ib_execute = &evergreen_ring_ib_execute,
1552 .emit_fence = &r600_fence_ring_emit,
1553 .emit_semaphore = &r600_semaphore_ring_emit,
1554 .cs_parse = &evergreen_cs_parse,
1555 .ring_test = &r600_ring_test,
1556 .ib_test = &r600_ib_test,
1557 .is_lockup = &evergreen_gfx_is_lockup,
1558 .get_rptr = &radeon_ring_generic_get_rptr,
1559 .get_wptr = &radeon_ring_generic_get_wptr,
1560 .set_wptr = &radeon_ring_generic_set_wptr,
1561 },
1562 [R600_RING_TYPE_DMA_INDEX] = {
1563 .ib_execute = &evergreen_dma_ring_ib_execute,
1564 .emit_fence = &evergreen_dma_fence_ring_emit,
1565 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1566 .cs_parse = &evergreen_dma_cs_parse,
1567 .ring_test = &r600_dma_ring_test,
1568 .ib_test = &r600_dma_ib_test,
1569 .is_lockup = &evergreen_dma_is_lockup,
1570 .get_rptr = &radeon_ring_generic_get_rptr,
1571 .get_wptr = &radeon_ring_generic_get_wptr,
1572 .set_wptr = &radeon_ring_generic_set_wptr,
1573 },
1574 [R600_RING_TYPE_UVD_INDEX] = {
1575 .ib_execute = &r600_uvd_ib_execute,
1576 .emit_fence = &r600_uvd_fence_emit,
1577 .emit_semaphore = &r600_uvd_semaphore_emit,
1578 .cs_parse = &radeon_uvd_cs_parse,
1579 .ring_test = &r600_uvd_ring_test,
1580 .ib_test = &r600_uvd_ib_test,
1581 .is_lockup = &radeon_ring_test_lockup,
1582 .get_rptr = &radeon_ring_generic_get_rptr,
1583 .get_wptr = &radeon_ring_generic_get_wptr,
1584 .set_wptr = &radeon_ring_generic_set_wptr,
1585 }
1586 },
1587 .irq = {
1588 .set = &evergreen_irq_set,
1589 .process = &evergreen_irq_process,
1590 },
1591 .display = {
1592 .bandwidth_update = &evergreen_bandwidth_update,
1593 .get_vblank_counter = &evergreen_get_vblank_counter,
1594 .wait_for_vblank = &dce4_wait_for_vblank,
1595 .set_backlight_level = &atombios_set_backlight_level,
1596 .get_backlight_level = &atombios_get_backlight_level,
1597 .hdmi_enable = &evergreen_hdmi_enable,
1598 .hdmi_setmode = &evergreen_hdmi_setmode,
1599 },
1600 .copy = {
1601 .blit = &r600_copy_cpdma,
1602 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1603 .dma = &evergreen_copy_dma,
1604 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1605 .copy = &evergreen_copy_dma,
1606 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1607 },
1608 .surface = {
1609 .set_reg = r600_set_surface_reg,
1610 .clear_reg = r600_clear_surface_reg,
1611 },
1612 .hpd = {
1613 .init = &evergreen_hpd_init,
1614 .fini = &evergreen_hpd_fini,
1615 .sense = &evergreen_hpd_sense,
1616 .set_polarity = &evergreen_hpd_set_polarity,
1617 },
1618 .pm = {
1619 .misc = &evergreen_pm_misc,
1620 .prepare = &evergreen_pm_prepare,
1621 .finish = &evergreen_pm_finish,
1622 .init_profile = &sumo_pm_init_profile,
1623 .get_dynpm_state = &r600_pm_get_dynpm_state,
1624 .get_engine_clock = &radeon_atom_get_engine_clock,
1625 .set_engine_clock = &radeon_atom_set_engine_clock,
1626 .get_memory_clock = NULL,
1627 .set_memory_clock = NULL,
1628 .get_pcie_lanes = NULL,
1629 .set_pcie_lanes = NULL,
1630 .set_clock_gating = NULL,
1631 .set_uvd_clocks = &sumo_set_uvd_clocks,
1632 .get_temperature = &sumo_get_temp,
1633 },
1634 .dpm = {
1635 .init = &sumo_dpm_init,
1636 .setup_asic = &sumo_dpm_setup_asic,
1637 .enable = &sumo_dpm_enable,
1638 .disable = &sumo_dpm_disable,
1639 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
1640 .set_power_state = &sumo_dpm_set_power_state,
1641 .post_set_power_state = &sumo_dpm_post_set_power_state,
1642 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1643 .fini = &sumo_dpm_fini,
1644 .get_sclk = &sumo_dpm_get_sclk,
1645 .get_mclk = &sumo_dpm_get_mclk,
1646 .print_power_state = &sumo_dpm_print_power_state,
1647 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
1648 .force_performance_level = &sumo_dpm_force_performance_level,
1649 },
1650 .pflip = {
1651 .pre_page_flip = &evergreen_pre_page_flip,
1652 .page_flip = &evergreen_page_flip,
1653 .post_page_flip = &evergreen_post_page_flip,
1654 },
1655};
1656
1657static struct radeon_asic btc_asic = {
1658 .init = &evergreen_init,
1659 .fini = &evergreen_fini,
1660 .suspend = &evergreen_suspend,
1661 .resume = &evergreen_resume,
1662 .asic_reset = &evergreen_asic_reset,
1663 .vga_set_state = &r600_vga_set_state,
1664 .ioctl_wait_idle = r600_ioctl_wait_idle,
1665 .gui_idle = &r600_gui_idle,
1666 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1667 .get_xclk = &rv770_get_xclk,
1668 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1669 .gart = {
1670 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1671 .set_page = &rs600_gart_set_page,
1672 },
1673 .ring = {
1674 [RADEON_RING_TYPE_GFX_INDEX] = {
1675 .ib_execute = &evergreen_ring_ib_execute,
1676 .emit_fence = &r600_fence_ring_emit,
1677 .emit_semaphore = &r600_semaphore_ring_emit,
1678 .cs_parse = &evergreen_cs_parse,
1679 .ring_test = &r600_ring_test,
1680 .ib_test = &r600_ib_test,
1681 .is_lockup = &evergreen_gfx_is_lockup,
1682 .get_rptr = &radeon_ring_generic_get_rptr,
1683 .get_wptr = &radeon_ring_generic_get_wptr,
1684 .set_wptr = &radeon_ring_generic_set_wptr,
1685 },
1686 [R600_RING_TYPE_DMA_INDEX] = {
1687 .ib_execute = &evergreen_dma_ring_ib_execute,
1688 .emit_fence = &evergreen_dma_fence_ring_emit,
1689 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1690 .cs_parse = &evergreen_dma_cs_parse,
1691 .ring_test = &r600_dma_ring_test,
1692 .ib_test = &r600_dma_ib_test,
1693 .is_lockup = &evergreen_dma_is_lockup,
1694 .get_rptr = &radeon_ring_generic_get_rptr,
1695 .get_wptr = &radeon_ring_generic_get_wptr,
1696 .set_wptr = &radeon_ring_generic_set_wptr,
1697 },
1698 [R600_RING_TYPE_UVD_INDEX] = {
1699 .ib_execute = &r600_uvd_ib_execute,
1700 .emit_fence = &r600_uvd_fence_emit,
1701 .emit_semaphore = &r600_uvd_semaphore_emit,
1702 .cs_parse = &radeon_uvd_cs_parse,
1703 .ring_test = &r600_uvd_ring_test,
1704 .ib_test = &r600_uvd_ib_test,
1705 .is_lockup = &radeon_ring_test_lockup,
1706 .get_rptr = &radeon_ring_generic_get_rptr,
1707 .get_wptr = &radeon_ring_generic_get_wptr,
1708 .set_wptr = &radeon_ring_generic_set_wptr,
1709 }
1710 },
1711 .irq = {
1712 .set = &evergreen_irq_set,
1713 .process = &evergreen_irq_process,
1714 },
1715 .display = {
1716 .bandwidth_update = &evergreen_bandwidth_update,
1717 .get_vblank_counter = &evergreen_get_vblank_counter,
1718 .wait_for_vblank = &dce4_wait_for_vblank,
1719 .set_backlight_level = &atombios_set_backlight_level,
1720 .get_backlight_level = &atombios_get_backlight_level,
1721 .hdmi_enable = &evergreen_hdmi_enable,
1722 .hdmi_setmode = &evergreen_hdmi_setmode,
1723 },
1724 .copy = {
1725 .blit = &r600_copy_cpdma,
1726 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1727 .dma = &evergreen_copy_dma,
1728 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1729 .copy = &evergreen_copy_dma,
1730 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1731 },
1732 .surface = {
1733 .set_reg = r600_set_surface_reg,
1734 .clear_reg = r600_clear_surface_reg,
1735 },
1736 .hpd = {
1737 .init = &evergreen_hpd_init,
1738 .fini = &evergreen_hpd_fini,
1739 .sense = &evergreen_hpd_sense,
1740 .set_polarity = &evergreen_hpd_set_polarity,
1741 },
1742 .pm = {
1743 .misc = &evergreen_pm_misc,
1744 .prepare = &evergreen_pm_prepare,
1745 .finish = &evergreen_pm_finish,
1746 .init_profile = &btc_pm_init_profile,
1747 .get_dynpm_state = &r600_pm_get_dynpm_state,
1748 .get_engine_clock = &radeon_atom_get_engine_clock,
1749 .set_engine_clock = &radeon_atom_set_engine_clock,
1750 .get_memory_clock = &radeon_atom_get_memory_clock,
1751 .set_memory_clock = &radeon_atom_set_memory_clock,
1752 .get_pcie_lanes = &r600_get_pcie_lanes,
1753 .set_pcie_lanes = &r600_set_pcie_lanes,
1754 .set_clock_gating = NULL,
1755 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1756 .get_temperature = &evergreen_get_temp,
1757 },
1758 .dpm = {
1759 .init = &btc_dpm_init,
1760 .setup_asic = &btc_dpm_setup_asic,
1761 .enable = &btc_dpm_enable,
1762 .disable = &btc_dpm_disable,
1763 .pre_set_power_state = &btc_dpm_pre_set_power_state,
1764 .set_power_state = &btc_dpm_set_power_state,
1765 .post_set_power_state = &btc_dpm_post_set_power_state,
1766 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1767 .fini = &btc_dpm_fini,
1768 .get_sclk = &btc_dpm_get_sclk,
1769 .get_mclk = &btc_dpm_get_mclk,
1770 .print_power_state = &rv770_dpm_print_power_state,
1771 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1772 .force_performance_level = &rv770_dpm_force_performance_level,
1773 .vblank_too_short = &btc_dpm_vblank_too_short,
1774 },
1775 .pflip = {
1776 .pre_page_flip = &evergreen_pre_page_flip,
1777 .page_flip = &evergreen_page_flip,
1778 .post_page_flip = &evergreen_post_page_flip,
1779 },
1780};
1781
1782static struct radeon_asic cayman_asic = {
1783 .init = &cayman_init,
1784 .fini = &cayman_fini,
1785 .suspend = &cayman_suspend,
1786 .resume = &cayman_resume,
1787 .asic_reset = &cayman_asic_reset,
1788 .vga_set_state = &r600_vga_set_state,
1789 .ioctl_wait_idle = r600_ioctl_wait_idle,
1790 .gui_idle = &r600_gui_idle,
1791 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1792 .get_xclk = &rv770_get_xclk,
1793 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1794 .gart = {
1795 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1796 .set_page = &rs600_gart_set_page,
1797 },
1798 .vm = {
1799 .init = &cayman_vm_init,
1800 .fini = &cayman_vm_fini,
1801 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1802 .set_page = &cayman_vm_set_page,
1803 },
1804 .ring = {
1805 [RADEON_RING_TYPE_GFX_INDEX] = {
1806 .ib_execute = &cayman_ring_ib_execute,
1807 .ib_parse = &evergreen_ib_parse,
1808 .emit_fence = &cayman_fence_ring_emit,
1809 .emit_semaphore = &r600_semaphore_ring_emit,
1810 .cs_parse = &evergreen_cs_parse,
1811 .ring_test = &r600_ring_test,
1812 .ib_test = &r600_ib_test,
1813 .is_lockup = &cayman_gfx_is_lockup,
1814 .vm_flush = &cayman_vm_flush,
1815 .get_rptr = &radeon_ring_generic_get_rptr,
1816 .get_wptr = &radeon_ring_generic_get_wptr,
1817 .set_wptr = &radeon_ring_generic_set_wptr,
1818 },
1819 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1820 .ib_execute = &cayman_ring_ib_execute,
1821 .ib_parse = &evergreen_ib_parse,
1822 .emit_fence = &cayman_fence_ring_emit,
1823 .emit_semaphore = &r600_semaphore_ring_emit,
1824 .cs_parse = &evergreen_cs_parse,
1825 .ring_test = &r600_ring_test,
1826 .ib_test = &r600_ib_test,
1827 .is_lockup = &cayman_gfx_is_lockup,
1828 .vm_flush = &cayman_vm_flush,
1829 .get_rptr = &radeon_ring_generic_get_rptr,
1830 .get_wptr = &radeon_ring_generic_get_wptr,
1831 .set_wptr = &radeon_ring_generic_set_wptr,
1832 },
1833 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1834 .ib_execute = &cayman_ring_ib_execute,
1835 .ib_parse = &evergreen_ib_parse,
1836 .emit_fence = &cayman_fence_ring_emit,
1837 .emit_semaphore = &r600_semaphore_ring_emit,
1838 .cs_parse = &evergreen_cs_parse,
1839 .ring_test = &r600_ring_test,
1840 .ib_test = &r600_ib_test,
1841 .is_lockup = &cayman_gfx_is_lockup,
1842 .vm_flush = &cayman_vm_flush,
1843 .get_rptr = &radeon_ring_generic_get_rptr,
1844 .get_wptr = &radeon_ring_generic_get_wptr,
1845 .set_wptr = &radeon_ring_generic_set_wptr,
1846 },
1847 [R600_RING_TYPE_DMA_INDEX] = {
1848 .ib_execute = &cayman_dma_ring_ib_execute,
1849 .ib_parse = &evergreen_dma_ib_parse,
1850 .emit_fence = &evergreen_dma_fence_ring_emit,
1851 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1852 .cs_parse = &evergreen_dma_cs_parse,
1853 .ring_test = &r600_dma_ring_test,
1854 .ib_test = &r600_dma_ib_test,
1855 .is_lockup = &cayman_dma_is_lockup,
1856 .vm_flush = &cayman_dma_vm_flush,
1857 .get_rptr = &radeon_ring_generic_get_rptr,
1858 .get_wptr = &radeon_ring_generic_get_wptr,
1859 .set_wptr = &radeon_ring_generic_set_wptr,
1860 },
1861 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1862 .ib_execute = &cayman_dma_ring_ib_execute,
1863 .ib_parse = &evergreen_dma_ib_parse,
1864 .emit_fence = &evergreen_dma_fence_ring_emit,
1865 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1866 .cs_parse = &evergreen_dma_cs_parse,
1867 .ring_test = &r600_dma_ring_test,
1868 .ib_test = &r600_dma_ib_test,
1869 .is_lockup = &cayman_dma_is_lockup,
1870 .vm_flush = &cayman_dma_vm_flush,
1871 .get_rptr = &radeon_ring_generic_get_rptr,
1872 .get_wptr = &radeon_ring_generic_get_wptr,
1873 .set_wptr = &radeon_ring_generic_set_wptr,
1874 },
1875 [R600_RING_TYPE_UVD_INDEX] = {
1876 .ib_execute = &r600_uvd_ib_execute,
1877 .emit_fence = &r600_uvd_fence_emit,
1878 .emit_semaphore = &cayman_uvd_semaphore_emit,
1879 .cs_parse = &radeon_uvd_cs_parse,
1880 .ring_test = &r600_uvd_ring_test,
1881 .ib_test = &r600_uvd_ib_test,
1882 .is_lockup = &radeon_ring_test_lockup,
1883 .get_rptr = &radeon_ring_generic_get_rptr,
1884 .get_wptr = &radeon_ring_generic_get_wptr,
1885 .set_wptr = &radeon_ring_generic_set_wptr,
1886 }
1887 },
1888 .irq = {
1889 .set = &evergreen_irq_set,
1890 .process = &evergreen_irq_process,
1891 },
1892 .display = {
1893 .bandwidth_update = &evergreen_bandwidth_update,
1894 .get_vblank_counter = &evergreen_get_vblank_counter,
1895 .wait_for_vblank = &dce4_wait_for_vblank,
1896 .set_backlight_level = &atombios_set_backlight_level,
1897 .get_backlight_level = &atombios_get_backlight_level,
1898 .hdmi_enable = &evergreen_hdmi_enable,
1899 .hdmi_setmode = &evergreen_hdmi_setmode,
1900 },
1901 .copy = {
1902 .blit = &r600_copy_cpdma,
1903 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1904 .dma = &evergreen_copy_dma,
1905 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1906 .copy = &evergreen_copy_dma,
1907 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1908 },
1909 .surface = {
1910 .set_reg = r600_set_surface_reg,
1911 .clear_reg = r600_clear_surface_reg,
1912 },
1913 .hpd = {
1914 .init = &evergreen_hpd_init,
1915 .fini = &evergreen_hpd_fini,
1916 .sense = &evergreen_hpd_sense,
1917 .set_polarity = &evergreen_hpd_set_polarity,
1918 },
1919 .pm = {
1920 .misc = &evergreen_pm_misc,
1921 .prepare = &evergreen_pm_prepare,
1922 .finish = &evergreen_pm_finish,
1923 .init_profile = &btc_pm_init_profile,
1924 .get_dynpm_state = &r600_pm_get_dynpm_state,
1925 .get_engine_clock = &radeon_atom_get_engine_clock,
1926 .set_engine_clock = &radeon_atom_set_engine_clock,
1927 .get_memory_clock = &radeon_atom_get_memory_clock,
1928 .set_memory_clock = &radeon_atom_set_memory_clock,
1929 .get_pcie_lanes = &r600_get_pcie_lanes,
1930 .set_pcie_lanes = &r600_set_pcie_lanes,
1931 .set_clock_gating = NULL,
1932 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1933 .get_temperature = &evergreen_get_temp,
1934 },
1935 .dpm = {
1936 .init = &ni_dpm_init,
1937 .setup_asic = &ni_dpm_setup_asic,
1938 .enable = &ni_dpm_enable,
1939 .disable = &ni_dpm_disable,
1940 .pre_set_power_state = &ni_dpm_pre_set_power_state,
1941 .set_power_state = &ni_dpm_set_power_state,
1942 .post_set_power_state = &ni_dpm_post_set_power_state,
1943 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1944 .fini = &ni_dpm_fini,
1945 .get_sclk = &ni_dpm_get_sclk,
1946 .get_mclk = &ni_dpm_get_mclk,
1947 .print_power_state = &ni_dpm_print_power_state,
1948 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
1949 .force_performance_level = &ni_dpm_force_performance_level,
1950 .vblank_too_short = &ni_dpm_vblank_too_short,
1951 },
1952 .pflip = {
1953 .pre_page_flip = &evergreen_pre_page_flip,
1954 .page_flip = &evergreen_page_flip,
1955 .post_page_flip = &evergreen_post_page_flip,
1956 },
1957};
1958
1959static struct radeon_asic trinity_asic = {
1960 .init = &cayman_init,
1961 .fini = &cayman_fini,
1962 .suspend = &cayman_suspend,
1963 .resume = &cayman_resume,
1964 .asic_reset = &cayman_asic_reset,
1965 .vga_set_state = &r600_vga_set_state,
1966 .ioctl_wait_idle = r600_ioctl_wait_idle,
1967 .gui_idle = &r600_gui_idle,
1968 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1969 .get_xclk = &r600_get_xclk,
1970 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1971 .gart = {
1972 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1973 .set_page = &rs600_gart_set_page,
1974 },
1975 .vm = {
1976 .init = &cayman_vm_init,
1977 .fini = &cayman_vm_fini,
1978 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1979 .set_page = &cayman_vm_set_page,
1980 },
1981 .ring = {
1982 [RADEON_RING_TYPE_GFX_INDEX] = {
1983 .ib_execute = &cayman_ring_ib_execute,
1984 .ib_parse = &evergreen_ib_parse,
1985 .emit_fence = &cayman_fence_ring_emit,
1986 .emit_semaphore = &r600_semaphore_ring_emit,
1987 .cs_parse = &evergreen_cs_parse,
1988 .ring_test = &r600_ring_test,
1989 .ib_test = &r600_ib_test,
1990 .is_lockup = &cayman_gfx_is_lockup,
1991 .vm_flush = &cayman_vm_flush,
1992 .get_rptr = &radeon_ring_generic_get_rptr,
1993 .get_wptr = &radeon_ring_generic_get_wptr,
1994 .set_wptr = &radeon_ring_generic_set_wptr,
1995 },
1996 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1997 .ib_execute = &cayman_ring_ib_execute,
1998 .ib_parse = &evergreen_ib_parse,
1999 .emit_fence = &cayman_fence_ring_emit,
2000 .emit_semaphore = &r600_semaphore_ring_emit,
2001 .cs_parse = &evergreen_cs_parse,
2002 .ring_test = &r600_ring_test,
2003 .ib_test = &r600_ib_test,
2004 .is_lockup = &cayman_gfx_is_lockup,
2005 .vm_flush = &cayman_vm_flush,
2006 .get_rptr = &radeon_ring_generic_get_rptr,
2007 .get_wptr = &radeon_ring_generic_get_wptr,
2008 .set_wptr = &radeon_ring_generic_set_wptr,
2009 },
2010 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2011 .ib_execute = &cayman_ring_ib_execute,
2012 .ib_parse = &evergreen_ib_parse,
2013 .emit_fence = &cayman_fence_ring_emit,
2014 .emit_semaphore = &r600_semaphore_ring_emit,
2015 .cs_parse = &evergreen_cs_parse,
2016 .ring_test = &r600_ring_test,
2017 .ib_test = &r600_ib_test,
2018 .is_lockup = &cayman_gfx_is_lockup,
2019 .vm_flush = &cayman_vm_flush,
2020 .get_rptr = &radeon_ring_generic_get_rptr,
2021 .get_wptr = &radeon_ring_generic_get_wptr,
2022 .set_wptr = &radeon_ring_generic_set_wptr,
2023 },
2024 [R600_RING_TYPE_DMA_INDEX] = {
2025 .ib_execute = &cayman_dma_ring_ib_execute,
2026 .ib_parse = &evergreen_dma_ib_parse,
2027 .emit_fence = &evergreen_dma_fence_ring_emit,
2028 .emit_semaphore = &r600_dma_semaphore_ring_emit,
2029 .cs_parse = &evergreen_dma_cs_parse,
2030 .ring_test = &r600_dma_ring_test,
2031 .ib_test = &r600_dma_ib_test,
2032 .is_lockup = &cayman_dma_is_lockup,
2033 .vm_flush = &cayman_dma_vm_flush,
2034 .get_rptr = &radeon_ring_generic_get_rptr,
2035 .get_wptr = &radeon_ring_generic_get_wptr,
2036 .set_wptr = &radeon_ring_generic_set_wptr,
2037 },
2038 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2039 .ib_execute = &cayman_dma_ring_ib_execute,
2040 .ib_parse = &evergreen_dma_ib_parse,
2041 .emit_fence = &evergreen_dma_fence_ring_emit,
2042 .emit_semaphore = &r600_dma_semaphore_ring_emit,
2043 .cs_parse = &evergreen_dma_cs_parse,
2044 .ring_test = &r600_dma_ring_test,
2045 .ib_test = &r600_dma_ib_test,
2046 .is_lockup = &cayman_dma_is_lockup,
2047 .vm_flush = &cayman_dma_vm_flush,
2048 .get_rptr = &radeon_ring_generic_get_rptr,
2049 .get_wptr = &radeon_ring_generic_get_wptr,
2050 .set_wptr = &radeon_ring_generic_set_wptr,
2051 },
2052 [R600_RING_TYPE_UVD_INDEX] = {
2053 .ib_execute = &r600_uvd_ib_execute,
2054 .emit_fence = &r600_uvd_fence_emit,
2055 .emit_semaphore = &cayman_uvd_semaphore_emit,
2056 .cs_parse = &radeon_uvd_cs_parse,
2057 .ring_test = &r600_uvd_ring_test,
2058 .ib_test = &r600_uvd_ib_test,
2059 .is_lockup = &radeon_ring_test_lockup,
2060 .get_rptr = &radeon_ring_generic_get_rptr,
2061 .get_wptr = &radeon_ring_generic_get_wptr,
2062 .set_wptr = &radeon_ring_generic_set_wptr,
2063 }
2064 },
2065 .irq = {
2066 .set = &evergreen_irq_set,
2067 .process = &evergreen_irq_process,
2068 },
2069 .display = {
2070 .bandwidth_update = &dce6_bandwidth_update,
2071 .get_vblank_counter = &evergreen_get_vblank_counter,
2072 .wait_for_vblank = &dce4_wait_for_vblank,
2073 .set_backlight_level = &atombios_set_backlight_level,
2074 .get_backlight_level = &atombios_get_backlight_level,
2075 },
2076 .copy = {
2077 .blit = &r600_copy_cpdma,
2078 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2079 .dma = &evergreen_copy_dma,
2080 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2081 .copy = &evergreen_copy_dma,
2082 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2083 },
2084 .surface = {
2085 .set_reg = r600_set_surface_reg,
2086 .clear_reg = r600_clear_surface_reg,
2087 },
2088 .hpd = {
2089 .init = &evergreen_hpd_init,
2090 .fini = &evergreen_hpd_fini,
2091 .sense = &evergreen_hpd_sense,
2092 .set_polarity = &evergreen_hpd_set_polarity,
2093 },
2094 .pm = {
2095 .misc = &evergreen_pm_misc,
2096 .prepare = &evergreen_pm_prepare,
2097 .finish = &evergreen_pm_finish,
2098 .init_profile = &sumo_pm_init_profile,
2099 .get_dynpm_state = &r600_pm_get_dynpm_state,
2100 .get_engine_clock = &radeon_atom_get_engine_clock,
2101 .set_engine_clock = &radeon_atom_set_engine_clock,
2102 .get_memory_clock = NULL,
2103 .set_memory_clock = NULL,
2104 .get_pcie_lanes = NULL,
2105 .set_pcie_lanes = NULL,
2106 .set_clock_gating = NULL,
2107 .set_uvd_clocks = &sumo_set_uvd_clocks,
2108 .get_temperature = &tn_get_temp,
2109 },
2110 .dpm = {
2111 .init = &trinity_dpm_init,
2112 .setup_asic = &trinity_dpm_setup_asic,
2113 .enable = &trinity_dpm_enable,
2114 .disable = &trinity_dpm_disable,
2115 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
2116 .set_power_state = &trinity_dpm_set_power_state,
2117 .post_set_power_state = &trinity_dpm_post_set_power_state,
2118 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
2119 .fini = &trinity_dpm_fini,
2120 .get_sclk = &trinity_dpm_get_sclk,
2121 .get_mclk = &trinity_dpm_get_mclk,
2122 .print_power_state = &trinity_dpm_print_power_state,
2123 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
2124 .force_performance_level = &trinity_dpm_force_performance_level,
2125 },
2126 .pflip = {
2127 .pre_page_flip = &evergreen_pre_page_flip,
2128 .page_flip = &evergreen_page_flip,
2129 .post_page_flip = &evergreen_post_page_flip,
2130 },
2131};
2132
2133static struct radeon_asic si_asic = {
2134 .init = &si_init,
2135 .fini = &si_fini,
2136 .suspend = &si_suspend,
2137 .resume = &si_resume,
2138 .asic_reset = &si_asic_reset,
2139 .vga_set_state = &r600_vga_set_state,
2140 .ioctl_wait_idle = r600_ioctl_wait_idle,
2141 .gui_idle = &r600_gui_idle,
2142 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2143 .get_xclk = &si_get_xclk,
2144 .get_gpu_clock_counter = &si_get_gpu_clock_counter,
2145 .gart = {
2146 .tlb_flush = &si_pcie_gart_tlb_flush,
2147 .set_page = &rs600_gart_set_page,
2148 },
2149 .vm = {
2150 .init = &si_vm_init,
2151 .fini = &si_vm_fini,
2152 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2153 .set_page = &si_vm_set_page,
2154 },
2155 .ring = {
2156 [RADEON_RING_TYPE_GFX_INDEX] = {
2157 .ib_execute = &si_ring_ib_execute,
2158 .ib_parse = &si_ib_parse,
2159 .emit_fence = &si_fence_ring_emit,
2160 .emit_semaphore = &r600_semaphore_ring_emit,
2161 .cs_parse = NULL,
2162 .ring_test = &r600_ring_test,
2163 .ib_test = &r600_ib_test,
2164 .is_lockup = &si_gfx_is_lockup,
2165 .vm_flush = &si_vm_flush,
2166 .get_rptr = &radeon_ring_generic_get_rptr,
2167 .get_wptr = &radeon_ring_generic_get_wptr,
2168 .set_wptr = &radeon_ring_generic_set_wptr,
2169 },
2170 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2171 .ib_execute = &si_ring_ib_execute,
2172 .ib_parse = &si_ib_parse,
2173 .emit_fence = &si_fence_ring_emit,
2174 .emit_semaphore = &r600_semaphore_ring_emit,
2175 .cs_parse = NULL,
2176 .ring_test = &r600_ring_test,
2177 .ib_test = &r600_ib_test,
2178 .is_lockup = &si_gfx_is_lockup,
2179 .vm_flush = &si_vm_flush,
2180 .get_rptr = &radeon_ring_generic_get_rptr,
2181 .get_wptr = &radeon_ring_generic_get_wptr,
2182 .set_wptr = &radeon_ring_generic_set_wptr,
2183 },
2184 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2185 .ib_execute = &si_ring_ib_execute,
2186 .ib_parse = &si_ib_parse,
2187 .emit_fence = &si_fence_ring_emit,
2188 .emit_semaphore = &r600_semaphore_ring_emit,
2189 .cs_parse = NULL,
2190 .ring_test = &r600_ring_test,
2191 .ib_test = &r600_ib_test,
2192 .is_lockup = &si_gfx_is_lockup,
2193 .vm_flush = &si_vm_flush,
2194 .get_rptr = &radeon_ring_generic_get_rptr,
2195 .get_wptr = &radeon_ring_generic_get_wptr,
2196 .set_wptr = &radeon_ring_generic_set_wptr,
2197 },
2198 [R600_RING_TYPE_DMA_INDEX] = {
2199 .ib_execute = &cayman_dma_ring_ib_execute,
2200 .ib_parse = &evergreen_dma_ib_parse,
2201 .emit_fence = &evergreen_dma_fence_ring_emit,
2202 .emit_semaphore = &r600_dma_semaphore_ring_emit,
2203 .cs_parse = NULL,
2204 .ring_test = &r600_dma_ring_test,
2205 .ib_test = &r600_dma_ib_test,
2206 .is_lockup = &si_dma_is_lockup,
2207 .vm_flush = &si_dma_vm_flush,
2208 .get_rptr = &radeon_ring_generic_get_rptr,
2209 .get_wptr = &radeon_ring_generic_get_wptr,
2210 .set_wptr = &radeon_ring_generic_set_wptr,
2211 },
2212 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2213 .ib_execute = &cayman_dma_ring_ib_execute,
2214 .ib_parse = &evergreen_dma_ib_parse,
2215 .emit_fence = &evergreen_dma_fence_ring_emit,
2216 .emit_semaphore = &r600_dma_semaphore_ring_emit,
2217 .cs_parse = NULL,
2218 .ring_test = &r600_dma_ring_test,
2219 .ib_test = &r600_dma_ib_test,
2220 .is_lockup = &si_dma_is_lockup,
2221 .vm_flush = &si_dma_vm_flush,
2222 .get_rptr = &radeon_ring_generic_get_rptr,
2223 .get_wptr = &radeon_ring_generic_get_wptr,
2224 .set_wptr = &radeon_ring_generic_set_wptr,
2225 },
2226 [R600_RING_TYPE_UVD_INDEX] = {
2227 .ib_execute = &r600_uvd_ib_execute,
2228 .emit_fence = &r600_uvd_fence_emit,
2229 .emit_semaphore = &cayman_uvd_semaphore_emit,
2230 .cs_parse = &radeon_uvd_cs_parse,
2231 .ring_test = &r600_uvd_ring_test,
2232 .ib_test = &r600_uvd_ib_test,
2233 .is_lockup = &radeon_ring_test_lockup,
2234 .get_rptr = &radeon_ring_generic_get_rptr,
2235 .get_wptr = &radeon_ring_generic_get_wptr,
2236 .set_wptr = &radeon_ring_generic_set_wptr,
2237 }
2238 },
2239 .irq = {
2240 .set = &si_irq_set,
2241 .process = &si_irq_process,
2242 },
2243 .display = {
2244 .bandwidth_update = &dce6_bandwidth_update,
2245 .get_vblank_counter = &evergreen_get_vblank_counter,
2246 .wait_for_vblank = &dce4_wait_for_vblank,
2247 .set_backlight_level = &atombios_set_backlight_level,
2248 .get_backlight_level = &atombios_get_backlight_level,
2249 },
2250 .copy = {
2251 .blit = NULL,
2252 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2253 .dma = &si_copy_dma,
2254 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2255 .copy = &si_copy_dma,
2256 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2257 },
2258 .surface = {
2259 .set_reg = r600_set_surface_reg,
2260 .clear_reg = r600_clear_surface_reg,
2261 },
2262 .hpd = {
2263 .init = &evergreen_hpd_init,
2264 .fini = &evergreen_hpd_fini,
2265 .sense = &evergreen_hpd_sense,
2266 .set_polarity = &evergreen_hpd_set_polarity,
2267 },
2268 .pm = {
2269 .misc = &evergreen_pm_misc,
2270 .prepare = &evergreen_pm_prepare,
2271 .finish = &evergreen_pm_finish,
2272 .init_profile = &sumo_pm_init_profile,
2273 .get_dynpm_state = &r600_pm_get_dynpm_state,
2274 .get_engine_clock = &radeon_atom_get_engine_clock,
2275 .set_engine_clock = &radeon_atom_set_engine_clock,
2276 .get_memory_clock = &radeon_atom_get_memory_clock,
2277 .set_memory_clock = &radeon_atom_set_memory_clock,
2278 .get_pcie_lanes = &r600_get_pcie_lanes,
2279 .set_pcie_lanes = &r600_set_pcie_lanes,
2280 .set_clock_gating = NULL,
2281 .set_uvd_clocks = &si_set_uvd_clocks,
2282 .get_temperature = &si_get_temp,
2283 },
2284 .dpm = {
2285 .init = &si_dpm_init,
2286 .setup_asic = &si_dpm_setup_asic,
2287 .enable = &si_dpm_enable,
2288 .disable = &si_dpm_disable,
2289 .pre_set_power_state = &si_dpm_pre_set_power_state,
2290 .set_power_state = &si_dpm_set_power_state,
2291 .post_set_power_state = &si_dpm_post_set_power_state,
2292 .display_configuration_changed = &si_dpm_display_configuration_changed,
2293 .fini = &si_dpm_fini,
2294 .get_sclk = &ni_dpm_get_sclk,
2295 .get_mclk = &ni_dpm_get_mclk,
2296 .print_power_state = &ni_dpm_print_power_state,
2297 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
2298 .force_performance_level = &si_dpm_force_performance_level,
2299 .vblank_too_short = &ni_dpm_vblank_too_short,
2300 },
2301 .pflip = {
2302 .pre_page_flip = &evergreen_pre_page_flip,
2303 .page_flip = &evergreen_page_flip,
2304 .post_page_flip = &evergreen_post_page_flip,
2305 },
2306};
2307
2308static struct radeon_asic ci_asic = {
2309 .init = &cik_init,
2310 .fini = &cik_fini,
2311 .suspend = &cik_suspend,
2312 .resume = &cik_resume,
2313 .asic_reset = &cik_asic_reset,
2314 .vga_set_state = &r600_vga_set_state,
2315 .ioctl_wait_idle = NULL,
2316 .gui_idle = &r600_gui_idle,
2317 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2318 .get_xclk = &cik_get_xclk,
2319 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2320 .gart = {
2321 .tlb_flush = &cik_pcie_gart_tlb_flush,
2322 .set_page = &rs600_gart_set_page,
2323 },
2324 .vm = {
2325 .init = &cik_vm_init,
2326 .fini = &cik_vm_fini,
2327 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2328 .set_page = &cik_vm_set_page,
2329 },
2330 .ring = {
2331 [RADEON_RING_TYPE_GFX_INDEX] = {
2332 .ib_execute = &cik_ring_ib_execute,
2333 .ib_parse = &cik_ib_parse,
2334 .emit_fence = &cik_fence_gfx_ring_emit,
2335 .emit_semaphore = &cik_semaphore_ring_emit,
2336 .cs_parse = NULL,
2337 .ring_test = &cik_ring_test,
2338 .ib_test = &cik_ib_test,
2339 .is_lockup = &cik_gfx_is_lockup,
2340 .vm_flush = &cik_vm_flush,
2341 .get_rptr = &radeon_ring_generic_get_rptr,
2342 .get_wptr = &radeon_ring_generic_get_wptr,
2343 .set_wptr = &radeon_ring_generic_set_wptr,
2344 },
2345 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2346 .ib_execute = &cik_ring_ib_execute,
2347 .ib_parse = &cik_ib_parse,
2348 .emit_fence = &cik_fence_compute_ring_emit,
2349 .emit_semaphore = &cik_semaphore_ring_emit,
2350 .cs_parse = NULL,
2351 .ring_test = &cik_ring_test,
2352 .ib_test = &cik_ib_test,
2353 .is_lockup = &cik_gfx_is_lockup,
2354 .vm_flush = &cik_vm_flush,
2355 .get_rptr = &cik_compute_ring_get_rptr,
2356 .get_wptr = &cik_compute_ring_get_wptr,
2357 .set_wptr = &cik_compute_ring_set_wptr,
2358 },
2359 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2360 .ib_execute = &cik_ring_ib_execute,
2361 .ib_parse = &cik_ib_parse,
2362 .emit_fence = &cik_fence_compute_ring_emit,
2363 .emit_semaphore = &cik_semaphore_ring_emit,
2364 .cs_parse = NULL,
2365 .ring_test = &cik_ring_test,
2366 .ib_test = &cik_ib_test,
2367 .is_lockup = &cik_gfx_is_lockup,
2368 .vm_flush = &cik_vm_flush,
2369 .get_rptr = &cik_compute_ring_get_rptr,
2370 .get_wptr = &cik_compute_ring_get_wptr,
2371 .set_wptr = &cik_compute_ring_set_wptr,
2372 },
2373 [R600_RING_TYPE_DMA_INDEX] = {
2374 .ib_execute = &cik_sdma_ring_ib_execute,
2375 .ib_parse = &cik_ib_parse,
2376 .emit_fence = &cik_sdma_fence_ring_emit,
2377 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2378 .cs_parse = NULL,
2379 .ring_test = &cik_sdma_ring_test,
2380 .ib_test = &cik_sdma_ib_test,
2381 .is_lockup = &cik_sdma_is_lockup,
2382 .vm_flush = &cik_dma_vm_flush,
2383 .get_rptr = &radeon_ring_generic_get_rptr,
2384 .get_wptr = &radeon_ring_generic_get_wptr,
2385 .set_wptr = &radeon_ring_generic_set_wptr,
2386 },
2387 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2388 .ib_execute = &cik_sdma_ring_ib_execute,
2389 .ib_parse = &cik_ib_parse,
2390 .emit_fence = &cik_sdma_fence_ring_emit,
2391 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2392 .cs_parse = NULL,
2393 .ring_test = &cik_sdma_ring_test,
2394 .ib_test = &cik_sdma_ib_test,
2395 .is_lockup = &cik_sdma_is_lockup,
2396 .vm_flush = &cik_dma_vm_flush,
2397 .get_rptr = &radeon_ring_generic_get_rptr,
2398 .get_wptr = &radeon_ring_generic_get_wptr,
2399 .set_wptr = &radeon_ring_generic_set_wptr,
2400 },
2401 [R600_RING_TYPE_UVD_INDEX] = {
2402 .ib_execute = &r600_uvd_ib_execute,
2403 .emit_fence = &r600_uvd_fence_emit,
2404 .emit_semaphore = &cayman_uvd_semaphore_emit,
2405 .cs_parse = &radeon_uvd_cs_parse,
2406 .ring_test = &r600_uvd_ring_test,
2407 .ib_test = &r600_uvd_ib_test,
2408 .is_lockup = &radeon_ring_test_lockup,
2409 .get_rptr = &radeon_ring_generic_get_rptr,
2410 .get_wptr = &radeon_ring_generic_get_wptr,
2411 .set_wptr = &radeon_ring_generic_set_wptr,
2412 }
2413 },
2414 .irq = {
2415 .set = &cik_irq_set,
2416 .process = &cik_irq_process,
2417 },
2418 .display = {
2419 .bandwidth_update = &dce8_bandwidth_update,
2420 .get_vblank_counter = &evergreen_get_vblank_counter,
2421 .wait_for_vblank = &dce4_wait_for_vblank,
2422 },
2423 .copy = {
2424 .blit = NULL,
2425 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2426 .dma = &cik_copy_dma,
2427 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2428 .copy = &cik_copy_dma,
2429 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2430 },
2431 .surface = {
2432 .set_reg = r600_set_surface_reg,
2433 .clear_reg = r600_clear_surface_reg,
2434 },
2435 .hpd = {
2436 .init = &evergreen_hpd_init,
2437 .fini = &evergreen_hpd_fini,
2438 .sense = &evergreen_hpd_sense,
2439 .set_polarity = &evergreen_hpd_set_polarity,
2440 },
2441 .pm = {
2442 .misc = &evergreen_pm_misc,
2443 .prepare = &evergreen_pm_prepare,
2444 .finish = &evergreen_pm_finish,
2445 .init_profile = &sumo_pm_init_profile,
2446 .get_dynpm_state = &r600_pm_get_dynpm_state,
2447 .get_engine_clock = &radeon_atom_get_engine_clock,
2448 .set_engine_clock = &radeon_atom_set_engine_clock,
2449 .get_memory_clock = &radeon_atom_get_memory_clock,
2450 .set_memory_clock = &radeon_atom_set_memory_clock,
2451 .get_pcie_lanes = NULL,
2452 .set_pcie_lanes = NULL,
2453 .set_clock_gating = NULL,
2454 .set_uvd_clocks = &cik_set_uvd_clocks,
2455 .get_temperature = &ci_get_temp,
2456 },
2457 .dpm = {
2458 .init = &ci_dpm_init,
2459 .setup_asic = &ci_dpm_setup_asic,
2460 .enable = &ci_dpm_enable,
2461 .disable = &ci_dpm_disable,
2462 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2463 .set_power_state = &ci_dpm_set_power_state,
2464 .post_set_power_state = &ci_dpm_post_set_power_state,
2465 .display_configuration_changed = &ci_dpm_display_configuration_changed,
2466 .fini = &ci_dpm_fini,
2467 .get_sclk = &ci_dpm_get_sclk,
2468 .get_mclk = &ci_dpm_get_mclk,
2469 .print_power_state = &ci_dpm_print_power_state,
2470 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
2471 .force_performance_level = &ci_dpm_force_performance_level,
2472 },
2473 .pflip = {
2474 .pre_page_flip = &evergreen_pre_page_flip,
2475 .page_flip = &evergreen_page_flip,
2476 .post_page_flip = &evergreen_post_page_flip,
2477 },
2478};
2479
2480static struct radeon_asic kv_asic = {
2481 .init = &cik_init,
2482 .fini = &cik_fini,
2483 .suspend = &cik_suspend,
2484 .resume = &cik_resume,
2485 .asic_reset = &cik_asic_reset,
2486 .vga_set_state = &r600_vga_set_state,
2487 .ioctl_wait_idle = NULL,
2488 .gui_idle = &r600_gui_idle,
2489 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2490 .get_xclk = &cik_get_xclk,
2491 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2492 .gart = {
2493 .tlb_flush = &cik_pcie_gart_tlb_flush,
2494 .set_page = &rs600_gart_set_page,
2495 },
2496 .vm = {
2497 .init = &cik_vm_init,
2498 .fini = &cik_vm_fini,
2499 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2500 .set_page = &cik_vm_set_page,
2501 },
2502 .ring = {
2503 [RADEON_RING_TYPE_GFX_INDEX] = {
2504 .ib_execute = &cik_ring_ib_execute,
2505 .ib_parse = &cik_ib_parse,
2506 .emit_fence = &cik_fence_gfx_ring_emit,
2507 .emit_semaphore = &cik_semaphore_ring_emit,
2508 .cs_parse = NULL,
2509 .ring_test = &cik_ring_test,
2510 .ib_test = &cik_ib_test,
2511 .is_lockup = &cik_gfx_is_lockup,
2512 .vm_flush = &cik_vm_flush,
2513 .get_rptr = &radeon_ring_generic_get_rptr,
2514 .get_wptr = &radeon_ring_generic_get_wptr,
2515 .set_wptr = &radeon_ring_generic_set_wptr,
2516 },
2517 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2518 .ib_execute = &cik_ring_ib_execute,
2519 .ib_parse = &cik_ib_parse,
2520 .emit_fence = &cik_fence_compute_ring_emit,
2521 .emit_semaphore = &cik_semaphore_ring_emit,
2522 .cs_parse = NULL,
2523 .ring_test = &cik_ring_test,
2524 .ib_test = &cik_ib_test,
2525 .is_lockup = &cik_gfx_is_lockup,
2526 .vm_flush = &cik_vm_flush,
2527 .get_rptr = &cik_compute_ring_get_rptr,
2528 .get_wptr = &cik_compute_ring_get_wptr,
2529 .set_wptr = &cik_compute_ring_set_wptr,
2530 },
2531 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2532 .ib_execute = &cik_ring_ib_execute,
2533 .ib_parse = &cik_ib_parse,
2534 .emit_fence = &cik_fence_compute_ring_emit,
2535 .emit_semaphore = &cik_semaphore_ring_emit,
2536 .cs_parse = NULL,
2537 .ring_test = &cik_ring_test,
2538 .ib_test = &cik_ib_test,
2539 .is_lockup = &cik_gfx_is_lockup,
2540 .vm_flush = &cik_vm_flush,
2541 .get_rptr = &cik_compute_ring_get_rptr,
2542 .get_wptr = &cik_compute_ring_get_wptr,
2543 .set_wptr = &cik_compute_ring_set_wptr,
2544 },
2545 [R600_RING_TYPE_DMA_INDEX] = {
2546 .ib_execute = &cik_sdma_ring_ib_execute,
2547 .ib_parse = &cik_ib_parse,
2548 .emit_fence = &cik_sdma_fence_ring_emit,
2549 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2550 .cs_parse = NULL,
2551 .ring_test = &cik_sdma_ring_test,
2552 .ib_test = &cik_sdma_ib_test,
2553 .is_lockup = &cik_sdma_is_lockup,
2554 .vm_flush = &cik_dma_vm_flush,
2555 .get_rptr = &radeon_ring_generic_get_rptr,
2556 .get_wptr = &radeon_ring_generic_get_wptr,
2557 .set_wptr = &radeon_ring_generic_set_wptr,
2558 },
2559 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2560 .ib_execute = &cik_sdma_ring_ib_execute,
2561 .ib_parse = &cik_ib_parse,
2562 .emit_fence = &cik_sdma_fence_ring_emit,
2563 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2564 .cs_parse = NULL,
2565 .ring_test = &cik_sdma_ring_test,
2566 .ib_test = &cik_sdma_ib_test,
2567 .is_lockup = &cik_sdma_is_lockup,
2568 .vm_flush = &cik_dma_vm_flush,
2569 .get_rptr = &radeon_ring_generic_get_rptr,
2570 .get_wptr = &radeon_ring_generic_get_wptr,
2571 .set_wptr = &radeon_ring_generic_set_wptr,
2572 },
2573 [R600_RING_TYPE_UVD_INDEX] = {
2574 .ib_execute = &r600_uvd_ib_execute,
2575 .emit_fence = &r600_uvd_fence_emit,
2576 .emit_semaphore = &cayman_uvd_semaphore_emit,
2577 .cs_parse = &radeon_uvd_cs_parse,
2578 .ring_test = &r600_uvd_ring_test,
2579 .ib_test = &r600_uvd_ib_test,
2580 .is_lockup = &radeon_ring_test_lockup,
2581 .get_rptr = &radeon_ring_generic_get_rptr,
2582 .get_wptr = &radeon_ring_generic_get_wptr,
2583 .set_wptr = &radeon_ring_generic_set_wptr,
2584 }
2585 },
2586 .irq = {
2587 .set = &cik_irq_set,
2588 .process = &cik_irq_process,
2589 },
2590 .display = {
2591 .bandwidth_update = &dce8_bandwidth_update,
2592 .get_vblank_counter = &evergreen_get_vblank_counter,
2593 .wait_for_vblank = &dce4_wait_for_vblank,
2594 },
2595 .copy = {
2596 .blit = NULL,
2597 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2598 .dma = &cik_copy_dma,
2599 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2600 .copy = &cik_copy_dma,
2601 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2602 },
2603 .surface = {
2604 .set_reg = r600_set_surface_reg,
2605 .clear_reg = r600_clear_surface_reg,
2606 },
2607 .hpd = {
2608 .init = &evergreen_hpd_init,
2609 .fini = &evergreen_hpd_fini,
2610 .sense = &evergreen_hpd_sense,
2611 .set_polarity = &evergreen_hpd_set_polarity,
2612 },
2613 .pm = {
2614 .misc = &evergreen_pm_misc,
2615 .prepare = &evergreen_pm_prepare,
2616 .finish = &evergreen_pm_finish,
2617 .init_profile = &sumo_pm_init_profile,
2618 .get_dynpm_state = &r600_pm_get_dynpm_state,
2619 .get_engine_clock = &radeon_atom_get_engine_clock,
2620 .set_engine_clock = &radeon_atom_set_engine_clock,
2621 .get_memory_clock = &radeon_atom_get_memory_clock,
2622 .set_memory_clock = &radeon_atom_set_memory_clock,
2623 .get_pcie_lanes = NULL,
2624 .set_pcie_lanes = NULL,
2625 .set_clock_gating = NULL,
2626 .set_uvd_clocks = &cik_set_uvd_clocks,
2627 .get_temperature = &kv_get_temp,
2628 },
2629 .dpm = {
2630 .init = &kv_dpm_init,
2631 .setup_asic = &kv_dpm_setup_asic,
2632 .enable = &kv_dpm_enable,
2633 .disable = &kv_dpm_disable,
2634 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2635 .set_power_state = &kv_dpm_set_power_state,
2636 .post_set_power_state = &kv_dpm_post_set_power_state,
2637 .display_configuration_changed = &kv_dpm_display_configuration_changed,
2638 .fini = &kv_dpm_fini,
2639 .get_sclk = &kv_dpm_get_sclk,
2640 .get_mclk = &kv_dpm_get_mclk,
2641 .print_power_state = &kv_dpm_print_power_state,
2642 },
2643 .pflip = {
2644 .pre_page_flip = &evergreen_pre_page_flip,
2645 .page_flip = &evergreen_page_flip,
2646 .post_page_flip = &evergreen_post_page_flip,
2647 },
2648};
2649
2650/**
2651 * radeon_asic_init - register asic specific callbacks
2652 *
2653 * @rdev: radeon device pointer
2654 *
2655 * Registers the appropriate asic specific callbacks for each
2656 * chip family. Also sets other asics specific info like the number
2657 * of crtcs and the register aperture accessors (all asics).
2658 * Returns 0 for success.
2659 */
2660int radeon_asic_init(struct radeon_device *rdev)
2661{
2662 radeon_register_accessor_init(rdev);
2663
2664 /* set the number of crtcs */
2665 if (rdev->flags & RADEON_SINGLE_CRTC)
2666 rdev->num_crtc = 1;
2667 else
2668 rdev->num_crtc = 2;
2669
2670 rdev->has_uvd = false;
2671
2672 switch (rdev->family) {
2673 case CHIP_R100:
2674 case CHIP_RV100:
2675 case CHIP_RS100:
2676 case CHIP_RV200:
2677 case CHIP_RS200:
2678 rdev->asic = &r100_asic;
2679 break;
2680 case CHIP_R200:
2681 case CHIP_RV250:
2682 case CHIP_RS300:
2683 case CHIP_RV280:
2684 rdev->asic = &r200_asic;
2685 break;
2686 case CHIP_R300:
2687 case CHIP_R350:
2688 case CHIP_RV350:
2689 case CHIP_RV380:
2690 if (rdev->flags & RADEON_IS_PCIE)
2691 rdev->asic = &r300_asic_pcie;
2692 else
2693 rdev->asic = &r300_asic;
2694 break;
2695 case CHIP_R420:
2696 case CHIP_R423:
2697 case CHIP_RV410:
2698 rdev->asic = &r420_asic;
2699 /* handle macs */
2700 if (rdev->bios == NULL) {
2701 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2702 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2703 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2704 rdev->asic->pm.set_memory_clock = NULL;
2705 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2706 }
2707 break;
2708 case CHIP_RS400:
2709 case CHIP_RS480:
2710 rdev->asic = &rs400_asic;
2711 break;
2712 case CHIP_RS600:
2713 rdev->asic = &rs600_asic;
2714 break;
2715 case CHIP_RS690:
2716 case CHIP_RS740:
2717 rdev->asic = &rs690_asic;
2718 break;
2719 case CHIP_RV515:
2720 rdev->asic = &rv515_asic;
2721 break;
2722 case CHIP_R520:
2723 case CHIP_RV530:
2724 case CHIP_RV560:
2725 case CHIP_RV570:
2726 case CHIP_R580:
2727 rdev->asic = &r520_asic;
2728 break;
2729 case CHIP_R600:
2730 rdev->asic = &r600_asic;
2731 break;
2732 case CHIP_RV610:
2733 case CHIP_RV630:
2734 case CHIP_RV620:
2735 case CHIP_RV635:
2736 case CHIP_RV670:
2737 rdev->asic = &rv6xx_asic;
2738 rdev->has_uvd = true;
2739 break;
2740 case CHIP_RS780:
2741 case CHIP_RS880:
2742 rdev->asic = &rs780_asic;
2743 rdev->has_uvd = true;
2744 break;
2745 case CHIP_RV770:
2746 case CHIP_RV730:
2747 case CHIP_RV710:
2748 case CHIP_RV740:
2749 rdev->asic = &rv770_asic;
2750 rdev->has_uvd = true;
2751 break;
2752 case CHIP_CEDAR:
2753 case CHIP_REDWOOD:
2754 case CHIP_JUNIPER:
2755 case CHIP_CYPRESS:
2756 case CHIP_HEMLOCK:
2757 /* set num crtcs */
2758 if (rdev->family == CHIP_CEDAR)
2759 rdev->num_crtc = 4;
2760 else
2761 rdev->num_crtc = 6;
2762 rdev->asic = &evergreen_asic;
2763 rdev->has_uvd = true;
2764 break;
2765 case CHIP_PALM:
2766 case CHIP_SUMO:
2767 case CHIP_SUMO2:
2768 rdev->asic = &sumo_asic;
2769 rdev->has_uvd = true;
2770 break;
2771 case CHIP_BARTS:
2772 case CHIP_TURKS:
2773 case CHIP_CAICOS:
2774 /* set num crtcs */
2775 if (rdev->family == CHIP_CAICOS)
2776 rdev->num_crtc = 4;
2777 else
2778 rdev->num_crtc = 6;
2779 rdev->asic = &btc_asic;
2780 rdev->has_uvd = true;
2781 break;
2782 case CHIP_CAYMAN:
2783 rdev->asic = &cayman_asic;
2784 /* set num crtcs */
2785 rdev->num_crtc = 6;
2786 rdev->has_uvd = true;
2787 break;
2788 case CHIP_ARUBA:
2789 rdev->asic = &trinity_asic;
2790 /* set num crtcs */
2791 rdev->num_crtc = 4;
2792 rdev->has_uvd = true;
2793 break;
2794 case CHIP_TAHITI:
2795 case CHIP_PITCAIRN:
2796 case CHIP_VERDE:
2797 case CHIP_OLAND:
2798 case CHIP_HAINAN:
2799 rdev->asic = &si_asic;
2800 /* set num crtcs */
2801 if (rdev->family == CHIP_HAINAN)
2802 rdev->num_crtc = 0;
2803 else if (rdev->family == CHIP_OLAND)
2804 rdev->num_crtc = 2;
2805 else
2806 rdev->num_crtc = 6;
2807 if (rdev->family == CHIP_HAINAN)
2808 rdev->has_uvd = false;
2809 else
2810 rdev->has_uvd = true;
2811 break;
2812 case CHIP_BONAIRE:
2813 rdev->asic = &ci_asic;
2814 rdev->num_crtc = 6;
2815 rdev->has_uvd = true;
2816 break;
2817 case CHIP_KAVERI:
2818 case CHIP_KABINI:
2819 rdev->asic = &kv_asic;
2820 /* set num crtcs */
2821 if (rdev->family == CHIP_KAVERI)
2822 rdev->num_crtc = 4;
2823 else
2824 rdev->num_crtc = 2;
2825 rdev->has_uvd = true;
2826 break;
2827 default:
2828 /* FIXME: not supported yet */
2829 return -EINVAL;
2830 }
2831
2832 if (rdev->flags & RADEON_IS_IGP) {
2833 rdev->asic->pm.get_memory_clock = NULL;
2834 rdev->asic->pm.set_memory_clock = NULL;
2835 }
2836
2837 return 0;
2838}
2839
Linux kernel - Deliverables
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