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drm/radeon: enable dpm by default on CI APUs
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_asic.c
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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/console.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
33#include <linux/vgaarb.h>
34#include <linux/vga_switcheroo.h>
35#include "radeon_reg.h"
36#include "radeon.h"
37#include "radeon_asic.h"
38#include "atom.h"
39
40/*
41 * Registers accessors functions.
42 */
43/**
44 * radeon_invalid_rreg - dummy reg read function
45 *
46 * @rdev: radeon device pointer
47 * @reg: offset of register
48 *
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
52 */
53static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54{
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56 BUG_ON(1);
57 return 0;
58}
59
60/**
61 * radeon_invalid_wreg - dummy reg write function
62 *
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
66 *
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
69 */
70static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71{
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73 reg, v);
74 BUG_ON(1);
75}
76
77/**
78 * radeon_register_accessor_init - sets up the register accessor callbacks
79 *
80 * @rdev: radeon device pointer
81 *
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
84 */
85static void radeon_register_accessor_init(struct radeon_device *rdev)
86{
87 rdev->mc_rreg = &radeon_invalid_rreg;
88 rdev->mc_wreg = &radeon_invalid_wreg;
89 rdev->pll_rreg = &radeon_invalid_rreg;
90 rdev->pll_wreg = &radeon_invalid_wreg;
91 rdev->pciep_rreg = &radeon_invalid_rreg;
92 rdev->pciep_wreg = &radeon_invalid_wreg;
93
94 /* Don't change order as we are overridding accessor. */
95 if (rdev->family < CHIP_RV515) {
96 rdev->pcie_reg_mask = 0xff;
97 } else {
98 rdev->pcie_reg_mask = 0x7ff;
99 }
100 /* FIXME: not sure here */
101 if (rdev->family <= CHIP_R580) {
102 rdev->pll_rreg = &r100_pll_rreg;
103 rdev->pll_wreg = &r100_pll_wreg;
104 }
105 if (rdev->family >= CHIP_R420) {
106 rdev->mc_rreg = &r420_mc_rreg;
107 rdev->mc_wreg = &r420_mc_wreg;
108 }
109 if (rdev->family >= CHIP_RV515) {
110 rdev->mc_rreg = &rv515_mc_rreg;
111 rdev->mc_wreg = &rv515_mc_wreg;
112 }
113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 rdev->mc_rreg = &rs400_mc_rreg;
115 rdev->mc_wreg = &rs400_mc_wreg;
116 }
117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 rdev->mc_rreg = &rs690_mc_rreg;
119 rdev->mc_wreg = &rs690_mc_wreg;
120 }
121 if (rdev->family == CHIP_RS600) {
122 rdev->mc_rreg = &rs600_mc_rreg;
123 rdev->mc_wreg = &rs600_mc_wreg;
124 }
125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
126 rdev->mc_rreg = &rs780_mc_rreg;
127 rdev->mc_wreg = &rs780_mc_wreg;
128 }
129
130 if (rdev->family >= CHIP_BONAIRE) {
131 rdev->pciep_rreg = &cik_pciep_rreg;
132 rdev->pciep_wreg = &cik_pciep_wreg;
133 } else if (rdev->family >= CHIP_R600) {
134 rdev->pciep_rreg = &r600_pciep_rreg;
135 rdev->pciep_wreg = &r600_pciep_wreg;
136 }
137}
138
139
140/* helper to disable agp */
141/**
142 * radeon_agp_disable - AGP disable helper function
143 *
144 * @rdev: radeon device pointer
145 *
146 * Removes AGP flags and changes the gart callbacks on AGP
147 * cards when using the internal gart rather than AGP (all asics).
148 */
149void radeon_agp_disable(struct radeon_device *rdev)
150{
151 rdev->flags &= ~RADEON_IS_AGP;
152 if (rdev->family >= CHIP_R600) {
153 DRM_INFO("Forcing AGP to PCIE mode\n");
154 rdev->flags |= RADEON_IS_PCIE;
155 } else if (rdev->family >= CHIP_RV515 ||
156 rdev->family == CHIP_RV380 ||
157 rdev->family == CHIP_RV410 ||
158 rdev->family == CHIP_R423) {
159 DRM_INFO("Forcing AGP to PCIE mode\n");
160 rdev->flags |= RADEON_IS_PCIE;
161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
162 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
163 } else {
164 DRM_INFO("Forcing AGP to PCI mode\n");
165 rdev->flags |= RADEON_IS_PCI;
166 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
167 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
168 }
169 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
170}
171
172/*
173 * ASIC
174 */
175
176static struct radeon_asic_ring r100_gfx_ring = {
177 .ib_execute = &r100_ring_ib_execute,
178 .emit_fence = &r100_fence_ring_emit,
179 .emit_semaphore = &r100_semaphore_ring_emit,
180 .cs_parse = &r100_cs_parse,
181 .ring_start = &r100_ring_start,
182 .ring_test = &r100_ring_test,
183 .ib_test = &r100_ib_test,
184 .is_lockup = &r100_gpu_is_lockup,
185 .get_rptr = &radeon_ring_generic_get_rptr,
186 .get_wptr = &radeon_ring_generic_get_wptr,
187 .set_wptr = &radeon_ring_generic_set_wptr,
188};
189
190static struct radeon_asic r100_asic = {
191 .init = &r100_init,
192 .fini = &r100_fini,
193 .suspend = &r100_suspend,
194 .resume = &r100_resume,
195 .vga_set_state = &r100_vga_set_state,
196 .asic_reset = &r100_asic_reset,
197 .ioctl_wait_idle = NULL,
198 .gui_idle = &r100_gui_idle,
199 .mc_wait_for_idle = &r100_mc_wait_for_idle,
200 .gart = {
201 .tlb_flush = &r100_pci_gart_tlb_flush,
202 .set_page = &r100_pci_gart_set_page,
203 },
204 .ring = {
205 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
206 },
207 .irq = {
208 .set = &r100_irq_set,
209 .process = &r100_irq_process,
210 },
211 .display = {
212 .bandwidth_update = &r100_bandwidth_update,
213 .get_vblank_counter = &r100_get_vblank_counter,
214 .wait_for_vblank = &r100_wait_for_vblank,
215 .set_backlight_level = &radeon_legacy_set_backlight_level,
216 .get_backlight_level = &radeon_legacy_get_backlight_level,
217 },
218 .copy = {
219 .blit = &r100_copy_blit,
220 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
221 .dma = NULL,
222 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
223 .copy = &r100_copy_blit,
224 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
225 },
226 .surface = {
227 .set_reg = r100_set_surface_reg,
228 .clear_reg = r100_clear_surface_reg,
229 },
230 .hpd = {
231 .init = &r100_hpd_init,
232 .fini = &r100_hpd_fini,
233 .sense = &r100_hpd_sense,
234 .set_polarity = &r100_hpd_set_polarity,
235 },
236 .pm = {
237 .misc = &r100_pm_misc,
238 .prepare = &r100_pm_prepare,
239 .finish = &r100_pm_finish,
240 .init_profile = &r100_pm_init_profile,
241 .get_dynpm_state = &r100_pm_get_dynpm_state,
242 .get_engine_clock = &radeon_legacy_get_engine_clock,
243 .set_engine_clock = &radeon_legacy_set_engine_clock,
244 .get_memory_clock = &radeon_legacy_get_memory_clock,
245 .set_memory_clock = NULL,
246 .get_pcie_lanes = NULL,
247 .set_pcie_lanes = NULL,
248 .set_clock_gating = &radeon_legacy_set_clock_gating,
249 },
250 .pflip = {
251 .pre_page_flip = &r100_pre_page_flip,
252 .page_flip = &r100_page_flip,
253 .post_page_flip = &r100_post_page_flip,
254 },
255};
256
257static struct radeon_asic r200_asic = {
258 .init = &r100_init,
259 .fini = &r100_fini,
260 .suspend = &r100_suspend,
261 .resume = &r100_resume,
262 .vga_set_state = &r100_vga_set_state,
263 .asic_reset = &r100_asic_reset,
264 .ioctl_wait_idle = NULL,
265 .gui_idle = &r100_gui_idle,
266 .mc_wait_for_idle = &r100_mc_wait_for_idle,
267 .gart = {
268 .tlb_flush = &r100_pci_gart_tlb_flush,
269 .set_page = &r100_pci_gart_set_page,
270 },
271 .ring = {
272 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
273 },
274 .irq = {
275 .set = &r100_irq_set,
276 .process = &r100_irq_process,
277 },
278 .display = {
279 .bandwidth_update = &r100_bandwidth_update,
280 .get_vblank_counter = &r100_get_vblank_counter,
281 .wait_for_vblank = &r100_wait_for_vblank,
282 .set_backlight_level = &radeon_legacy_set_backlight_level,
283 .get_backlight_level = &radeon_legacy_get_backlight_level,
284 },
285 .copy = {
286 .blit = &r100_copy_blit,
287 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
288 .dma = &r200_copy_dma,
289 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
290 .copy = &r100_copy_blit,
291 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
292 },
293 .surface = {
294 .set_reg = r100_set_surface_reg,
295 .clear_reg = r100_clear_surface_reg,
296 },
297 .hpd = {
298 .init = &r100_hpd_init,
299 .fini = &r100_hpd_fini,
300 .sense = &r100_hpd_sense,
301 .set_polarity = &r100_hpd_set_polarity,
302 },
303 .pm = {
304 .misc = &r100_pm_misc,
305 .prepare = &r100_pm_prepare,
306 .finish = &r100_pm_finish,
307 .init_profile = &r100_pm_init_profile,
308 .get_dynpm_state = &r100_pm_get_dynpm_state,
309 .get_engine_clock = &radeon_legacy_get_engine_clock,
310 .set_engine_clock = &radeon_legacy_set_engine_clock,
311 .get_memory_clock = &radeon_legacy_get_memory_clock,
312 .set_memory_clock = NULL,
313 .get_pcie_lanes = NULL,
314 .set_pcie_lanes = NULL,
315 .set_clock_gating = &radeon_legacy_set_clock_gating,
316 },
317 .pflip = {
318 .pre_page_flip = &r100_pre_page_flip,
319 .page_flip = &r100_page_flip,
320 .post_page_flip = &r100_post_page_flip,
321 },
322};
323
324static struct radeon_asic_ring r300_gfx_ring = {
325 .ib_execute = &r100_ring_ib_execute,
326 .emit_fence = &r300_fence_ring_emit,
327 .emit_semaphore = &r100_semaphore_ring_emit,
328 .cs_parse = &r300_cs_parse,
329 .ring_start = &r300_ring_start,
330 .ring_test = &r100_ring_test,
331 .ib_test = &r100_ib_test,
332 .is_lockup = &r100_gpu_is_lockup,
333 .get_rptr = &radeon_ring_generic_get_rptr,
334 .get_wptr = &radeon_ring_generic_get_wptr,
335 .set_wptr = &radeon_ring_generic_set_wptr,
336};
337
338static struct radeon_asic r300_asic = {
339 .init = &r300_init,
340 .fini = &r300_fini,
341 .suspend = &r300_suspend,
342 .resume = &r300_resume,
343 .vga_set_state = &r100_vga_set_state,
344 .asic_reset = &r300_asic_reset,
345 .ioctl_wait_idle = NULL,
346 .gui_idle = &r100_gui_idle,
347 .mc_wait_for_idle = &r300_mc_wait_for_idle,
348 .gart = {
349 .tlb_flush = &r100_pci_gart_tlb_flush,
350 .set_page = &r100_pci_gart_set_page,
351 },
352 .ring = {
353 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
354 },
355 .irq = {
356 .set = &r100_irq_set,
357 .process = &r100_irq_process,
358 },
359 .display = {
360 .bandwidth_update = &r100_bandwidth_update,
361 .get_vblank_counter = &r100_get_vblank_counter,
362 .wait_for_vblank = &r100_wait_for_vblank,
363 .set_backlight_level = &radeon_legacy_set_backlight_level,
364 .get_backlight_level = &radeon_legacy_get_backlight_level,
365 },
366 .copy = {
367 .blit = &r100_copy_blit,
368 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
369 .dma = &r200_copy_dma,
370 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
371 .copy = &r100_copy_blit,
372 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
373 },
374 .surface = {
375 .set_reg = r100_set_surface_reg,
376 .clear_reg = r100_clear_surface_reg,
377 },
378 .hpd = {
379 .init = &r100_hpd_init,
380 .fini = &r100_hpd_fini,
381 .sense = &r100_hpd_sense,
382 .set_polarity = &r100_hpd_set_polarity,
383 },
384 .pm = {
385 .misc = &r100_pm_misc,
386 .prepare = &r100_pm_prepare,
387 .finish = &r100_pm_finish,
388 .init_profile = &r100_pm_init_profile,
389 .get_dynpm_state = &r100_pm_get_dynpm_state,
390 .get_engine_clock = &radeon_legacy_get_engine_clock,
391 .set_engine_clock = &radeon_legacy_set_engine_clock,
392 .get_memory_clock = &radeon_legacy_get_memory_clock,
393 .set_memory_clock = NULL,
394 .get_pcie_lanes = &rv370_get_pcie_lanes,
395 .set_pcie_lanes = &rv370_set_pcie_lanes,
396 .set_clock_gating = &radeon_legacy_set_clock_gating,
397 },
398 .pflip = {
399 .pre_page_flip = &r100_pre_page_flip,
400 .page_flip = &r100_page_flip,
401 .post_page_flip = &r100_post_page_flip,
402 },
403};
404
405static struct radeon_asic r300_asic_pcie = {
406 .init = &r300_init,
407 .fini = &r300_fini,
408 .suspend = &r300_suspend,
409 .resume = &r300_resume,
410 .vga_set_state = &r100_vga_set_state,
411 .asic_reset = &r300_asic_reset,
412 .ioctl_wait_idle = NULL,
413 .gui_idle = &r100_gui_idle,
414 .mc_wait_for_idle = &r300_mc_wait_for_idle,
415 .gart = {
416 .tlb_flush = &rv370_pcie_gart_tlb_flush,
417 .set_page = &rv370_pcie_gart_set_page,
418 },
419 .ring = {
420 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
421 },
422 .irq = {
423 .set = &r100_irq_set,
424 .process = &r100_irq_process,
425 },
426 .display = {
427 .bandwidth_update = &r100_bandwidth_update,
428 .get_vblank_counter = &r100_get_vblank_counter,
429 .wait_for_vblank = &r100_wait_for_vblank,
430 .set_backlight_level = &radeon_legacy_set_backlight_level,
431 .get_backlight_level = &radeon_legacy_get_backlight_level,
432 },
433 .copy = {
434 .blit = &r100_copy_blit,
435 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
436 .dma = &r200_copy_dma,
437 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
438 .copy = &r100_copy_blit,
439 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
440 },
441 .surface = {
442 .set_reg = r100_set_surface_reg,
443 .clear_reg = r100_clear_surface_reg,
444 },
445 .hpd = {
446 .init = &r100_hpd_init,
447 .fini = &r100_hpd_fini,
448 .sense = &r100_hpd_sense,
449 .set_polarity = &r100_hpd_set_polarity,
450 },
451 .pm = {
452 .misc = &r100_pm_misc,
453 .prepare = &r100_pm_prepare,
454 .finish = &r100_pm_finish,
455 .init_profile = &r100_pm_init_profile,
456 .get_dynpm_state = &r100_pm_get_dynpm_state,
457 .get_engine_clock = &radeon_legacy_get_engine_clock,
458 .set_engine_clock = &radeon_legacy_set_engine_clock,
459 .get_memory_clock = &radeon_legacy_get_memory_clock,
460 .set_memory_clock = NULL,
461 .get_pcie_lanes = &rv370_get_pcie_lanes,
462 .set_pcie_lanes = &rv370_set_pcie_lanes,
463 .set_clock_gating = &radeon_legacy_set_clock_gating,
464 },
465 .pflip = {
466 .pre_page_flip = &r100_pre_page_flip,
467 .page_flip = &r100_page_flip,
468 .post_page_flip = &r100_post_page_flip,
469 },
470};
471
472static struct radeon_asic r420_asic = {
473 .init = &r420_init,
474 .fini = &r420_fini,
475 .suspend = &r420_suspend,
476 .resume = &r420_resume,
477 .vga_set_state = &r100_vga_set_state,
478 .asic_reset = &r300_asic_reset,
479 .ioctl_wait_idle = NULL,
480 .gui_idle = &r100_gui_idle,
481 .mc_wait_for_idle = &r300_mc_wait_for_idle,
482 .gart = {
483 .tlb_flush = &rv370_pcie_gart_tlb_flush,
484 .set_page = &rv370_pcie_gart_set_page,
485 },
486 .ring = {
487 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
488 },
489 .irq = {
490 .set = &r100_irq_set,
491 .process = &r100_irq_process,
492 },
493 .display = {
494 .bandwidth_update = &r100_bandwidth_update,
495 .get_vblank_counter = &r100_get_vblank_counter,
496 .wait_for_vblank = &r100_wait_for_vblank,
497 .set_backlight_level = &atombios_set_backlight_level,
498 .get_backlight_level = &atombios_get_backlight_level,
499 },
500 .copy = {
501 .blit = &r100_copy_blit,
502 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
503 .dma = &r200_copy_dma,
504 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
505 .copy = &r100_copy_blit,
506 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
507 },
508 .surface = {
509 .set_reg = r100_set_surface_reg,
510 .clear_reg = r100_clear_surface_reg,
511 },
512 .hpd = {
513 .init = &r100_hpd_init,
514 .fini = &r100_hpd_fini,
515 .sense = &r100_hpd_sense,
516 .set_polarity = &r100_hpd_set_polarity,
517 },
518 .pm = {
519 .misc = &r100_pm_misc,
520 .prepare = &r100_pm_prepare,
521 .finish = &r100_pm_finish,
522 .init_profile = &r420_pm_init_profile,
523 .get_dynpm_state = &r100_pm_get_dynpm_state,
524 .get_engine_clock = &radeon_atom_get_engine_clock,
525 .set_engine_clock = &radeon_atom_set_engine_clock,
526 .get_memory_clock = &radeon_atom_get_memory_clock,
527 .set_memory_clock = &radeon_atom_set_memory_clock,
528 .get_pcie_lanes = &rv370_get_pcie_lanes,
529 .set_pcie_lanes = &rv370_set_pcie_lanes,
530 .set_clock_gating = &radeon_atom_set_clock_gating,
531 },
532 .pflip = {
533 .pre_page_flip = &r100_pre_page_flip,
534 .page_flip = &r100_page_flip,
535 .post_page_flip = &r100_post_page_flip,
536 },
537};
538
539static struct radeon_asic rs400_asic = {
540 .init = &rs400_init,
541 .fini = &rs400_fini,
542 .suspend = &rs400_suspend,
543 .resume = &rs400_resume,
544 .vga_set_state = &r100_vga_set_state,
545 .asic_reset = &r300_asic_reset,
546 .ioctl_wait_idle = NULL,
547 .gui_idle = &r100_gui_idle,
548 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
549 .gart = {
550 .tlb_flush = &rs400_gart_tlb_flush,
551 .set_page = &rs400_gart_set_page,
552 },
553 .ring = {
554 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
555 },
556 .irq = {
557 .set = &r100_irq_set,
558 .process = &r100_irq_process,
559 },
560 .display = {
561 .bandwidth_update = &r100_bandwidth_update,
562 .get_vblank_counter = &r100_get_vblank_counter,
563 .wait_for_vblank = &r100_wait_for_vblank,
564 .set_backlight_level = &radeon_legacy_set_backlight_level,
565 .get_backlight_level = &radeon_legacy_get_backlight_level,
566 },
567 .copy = {
568 .blit = &r100_copy_blit,
569 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
570 .dma = &r200_copy_dma,
571 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
572 .copy = &r100_copy_blit,
573 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
574 },
575 .surface = {
576 .set_reg = r100_set_surface_reg,
577 .clear_reg = r100_clear_surface_reg,
578 },
579 .hpd = {
580 .init = &r100_hpd_init,
581 .fini = &r100_hpd_fini,
582 .sense = &r100_hpd_sense,
583 .set_polarity = &r100_hpd_set_polarity,
584 },
585 .pm = {
586 .misc = &r100_pm_misc,
587 .prepare = &r100_pm_prepare,
588 .finish = &r100_pm_finish,
589 .init_profile = &r100_pm_init_profile,
590 .get_dynpm_state = &r100_pm_get_dynpm_state,
591 .get_engine_clock = &radeon_legacy_get_engine_clock,
592 .set_engine_clock = &radeon_legacy_set_engine_clock,
593 .get_memory_clock = &radeon_legacy_get_memory_clock,
594 .set_memory_clock = NULL,
595 .get_pcie_lanes = NULL,
596 .set_pcie_lanes = NULL,
597 .set_clock_gating = &radeon_legacy_set_clock_gating,
598 },
599 .pflip = {
600 .pre_page_flip = &r100_pre_page_flip,
601 .page_flip = &r100_page_flip,
602 .post_page_flip = &r100_post_page_flip,
603 },
604};
605
606static struct radeon_asic rs600_asic = {
607 .init = &rs600_init,
608 .fini = &rs600_fini,
609 .suspend = &rs600_suspend,
610 .resume = &rs600_resume,
611 .vga_set_state = &r100_vga_set_state,
612 .asic_reset = &rs600_asic_reset,
613 .ioctl_wait_idle = NULL,
614 .gui_idle = &r100_gui_idle,
615 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
616 .gart = {
617 .tlb_flush = &rs600_gart_tlb_flush,
618 .set_page = &rs600_gart_set_page,
619 },
620 .ring = {
621 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
622 },
623 .irq = {
624 .set = &rs600_irq_set,
625 .process = &rs600_irq_process,
626 },
627 .display = {
628 .bandwidth_update = &rs600_bandwidth_update,
629 .get_vblank_counter = &rs600_get_vblank_counter,
630 .wait_for_vblank = &avivo_wait_for_vblank,
631 .set_backlight_level = &atombios_set_backlight_level,
632 .get_backlight_level = &atombios_get_backlight_level,
633 .hdmi_enable = &r600_hdmi_enable,
634 .hdmi_setmode = &r600_hdmi_setmode,
635 },
636 .copy = {
637 .blit = &r100_copy_blit,
638 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
639 .dma = &r200_copy_dma,
640 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
641 .copy = &r100_copy_blit,
642 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
643 },
644 .surface = {
645 .set_reg = r100_set_surface_reg,
646 .clear_reg = r100_clear_surface_reg,
647 },
648 .hpd = {
649 .init = &rs600_hpd_init,
650 .fini = &rs600_hpd_fini,
651 .sense = &rs600_hpd_sense,
652 .set_polarity = &rs600_hpd_set_polarity,
653 },
654 .pm = {
655 .misc = &rs600_pm_misc,
656 .prepare = &rs600_pm_prepare,
657 .finish = &rs600_pm_finish,
658 .init_profile = &r420_pm_init_profile,
659 .get_dynpm_state = &r100_pm_get_dynpm_state,
660 .get_engine_clock = &radeon_atom_get_engine_clock,
661 .set_engine_clock = &radeon_atom_set_engine_clock,
662 .get_memory_clock = &radeon_atom_get_memory_clock,
663 .set_memory_clock = &radeon_atom_set_memory_clock,
664 .get_pcie_lanes = NULL,
665 .set_pcie_lanes = NULL,
666 .set_clock_gating = &radeon_atom_set_clock_gating,
667 },
668 .pflip = {
669 .pre_page_flip = &rs600_pre_page_flip,
670 .page_flip = &rs600_page_flip,
671 .post_page_flip = &rs600_post_page_flip,
672 },
673};
674
675static struct radeon_asic rs690_asic = {
676 .init = &rs690_init,
677 .fini = &rs690_fini,
678 .suspend = &rs690_suspend,
679 .resume = &rs690_resume,
680 .vga_set_state = &r100_vga_set_state,
681 .asic_reset = &rs600_asic_reset,
682 .ioctl_wait_idle = NULL,
683 .gui_idle = &r100_gui_idle,
684 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
685 .gart = {
686 .tlb_flush = &rs400_gart_tlb_flush,
687 .set_page = &rs400_gart_set_page,
688 },
689 .ring = {
690 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
691 },
692 .irq = {
693 .set = &rs600_irq_set,
694 .process = &rs600_irq_process,
695 },
696 .display = {
697 .get_vblank_counter = &rs600_get_vblank_counter,
698 .bandwidth_update = &rs690_bandwidth_update,
699 .wait_for_vblank = &avivo_wait_for_vblank,
700 .set_backlight_level = &atombios_set_backlight_level,
701 .get_backlight_level = &atombios_get_backlight_level,
702 .hdmi_enable = &r600_hdmi_enable,
703 .hdmi_setmode = &r600_hdmi_setmode,
704 },
705 .copy = {
706 .blit = &r100_copy_blit,
707 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
708 .dma = &r200_copy_dma,
709 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
710 .copy = &r200_copy_dma,
711 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
712 },
713 .surface = {
714 .set_reg = r100_set_surface_reg,
715 .clear_reg = r100_clear_surface_reg,
716 },
717 .hpd = {
718 .init = &rs600_hpd_init,
719 .fini = &rs600_hpd_fini,
720 .sense = &rs600_hpd_sense,
721 .set_polarity = &rs600_hpd_set_polarity,
722 },
723 .pm = {
724 .misc = &rs600_pm_misc,
725 .prepare = &rs600_pm_prepare,
726 .finish = &rs600_pm_finish,
727 .init_profile = &r420_pm_init_profile,
728 .get_dynpm_state = &r100_pm_get_dynpm_state,
729 .get_engine_clock = &radeon_atom_get_engine_clock,
730 .set_engine_clock = &radeon_atom_set_engine_clock,
731 .get_memory_clock = &radeon_atom_get_memory_clock,
732 .set_memory_clock = &radeon_atom_set_memory_clock,
733 .get_pcie_lanes = NULL,
734 .set_pcie_lanes = NULL,
735 .set_clock_gating = &radeon_atom_set_clock_gating,
736 },
737 .pflip = {
738 .pre_page_flip = &rs600_pre_page_flip,
739 .page_flip = &rs600_page_flip,
740 .post_page_flip = &rs600_post_page_flip,
741 },
742};
743
744static struct radeon_asic rv515_asic = {
745 .init = &rv515_init,
746 .fini = &rv515_fini,
747 .suspend = &rv515_suspend,
748 .resume = &rv515_resume,
749 .vga_set_state = &r100_vga_set_state,
750 .asic_reset = &rs600_asic_reset,
751 .ioctl_wait_idle = NULL,
752 .gui_idle = &r100_gui_idle,
753 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
754 .gart = {
755 .tlb_flush = &rv370_pcie_gart_tlb_flush,
756 .set_page = &rv370_pcie_gart_set_page,
757 },
758 .ring = {
759 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
760 },
761 .irq = {
762 .set = &rs600_irq_set,
763 .process = &rs600_irq_process,
764 },
765 .display = {
766 .get_vblank_counter = &rs600_get_vblank_counter,
767 .bandwidth_update = &rv515_bandwidth_update,
768 .wait_for_vblank = &avivo_wait_for_vblank,
769 .set_backlight_level = &atombios_set_backlight_level,
770 .get_backlight_level = &atombios_get_backlight_level,
771 },
772 .copy = {
773 .blit = &r100_copy_blit,
774 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
775 .dma = &r200_copy_dma,
776 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
777 .copy = &r100_copy_blit,
778 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
779 },
780 .surface = {
781 .set_reg = r100_set_surface_reg,
782 .clear_reg = r100_clear_surface_reg,
783 },
784 .hpd = {
785 .init = &rs600_hpd_init,
786 .fini = &rs600_hpd_fini,
787 .sense = &rs600_hpd_sense,
788 .set_polarity = &rs600_hpd_set_polarity,
789 },
790 .pm = {
791 .misc = &rs600_pm_misc,
792 .prepare = &rs600_pm_prepare,
793 .finish = &rs600_pm_finish,
794 .init_profile = &r420_pm_init_profile,
795 .get_dynpm_state = &r100_pm_get_dynpm_state,
796 .get_engine_clock = &radeon_atom_get_engine_clock,
797 .set_engine_clock = &radeon_atom_set_engine_clock,
798 .get_memory_clock = &radeon_atom_get_memory_clock,
799 .set_memory_clock = &radeon_atom_set_memory_clock,
800 .get_pcie_lanes = &rv370_get_pcie_lanes,
801 .set_pcie_lanes = &rv370_set_pcie_lanes,
802 .set_clock_gating = &radeon_atom_set_clock_gating,
803 },
804 .pflip = {
805 .pre_page_flip = &rs600_pre_page_flip,
806 .page_flip = &rs600_page_flip,
807 .post_page_flip = &rs600_post_page_flip,
808 },
809};
810
811static struct radeon_asic r520_asic = {
812 .init = &r520_init,
813 .fini = &rv515_fini,
814 .suspend = &rv515_suspend,
815 .resume = &r520_resume,
816 .vga_set_state = &r100_vga_set_state,
817 .asic_reset = &rs600_asic_reset,
818 .ioctl_wait_idle = NULL,
819 .gui_idle = &r100_gui_idle,
820 .mc_wait_for_idle = &r520_mc_wait_for_idle,
821 .gart = {
822 .tlb_flush = &rv370_pcie_gart_tlb_flush,
823 .set_page = &rv370_pcie_gart_set_page,
824 },
825 .ring = {
826 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
827 },
828 .irq = {
829 .set = &rs600_irq_set,
830 .process = &rs600_irq_process,
831 },
832 .display = {
833 .bandwidth_update = &rv515_bandwidth_update,
834 .get_vblank_counter = &rs600_get_vblank_counter,
835 .wait_for_vblank = &avivo_wait_for_vblank,
836 .set_backlight_level = &atombios_set_backlight_level,
837 .get_backlight_level = &atombios_get_backlight_level,
838 },
839 .copy = {
840 .blit = &r100_copy_blit,
841 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
842 .dma = &r200_copy_dma,
843 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
844 .copy = &r100_copy_blit,
845 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
846 },
847 .surface = {
848 .set_reg = r100_set_surface_reg,
849 .clear_reg = r100_clear_surface_reg,
850 },
851 .hpd = {
852 .init = &rs600_hpd_init,
853 .fini = &rs600_hpd_fini,
854 .sense = &rs600_hpd_sense,
855 .set_polarity = &rs600_hpd_set_polarity,
856 },
857 .pm = {
858 .misc = &rs600_pm_misc,
859 .prepare = &rs600_pm_prepare,
860 .finish = &rs600_pm_finish,
861 .init_profile = &r420_pm_init_profile,
862 .get_dynpm_state = &r100_pm_get_dynpm_state,
863 .get_engine_clock = &radeon_atom_get_engine_clock,
864 .set_engine_clock = &radeon_atom_set_engine_clock,
865 .get_memory_clock = &radeon_atom_get_memory_clock,
866 .set_memory_clock = &radeon_atom_set_memory_clock,
867 .get_pcie_lanes = &rv370_get_pcie_lanes,
868 .set_pcie_lanes = &rv370_set_pcie_lanes,
869 .set_clock_gating = &radeon_atom_set_clock_gating,
870 },
871 .pflip = {
872 .pre_page_flip = &rs600_pre_page_flip,
873 .page_flip = &rs600_page_flip,
874 .post_page_flip = &rs600_post_page_flip,
875 },
876};
877
878static struct radeon_asic_ring r600_gfx_ring = {
879 .ib_execute = &r600_ring_ib_execute,
880 .emit_fence = &r600_fence_ring_emit,
881 .emit_semaphore = &r600_semaphore_ring_emit,
882 .cs_parse = &r600_cs_parse,
883 .ring_test = &r600_ring_test,
884 .ib_test = &r600_ib_test,
885 .is_lockup = &r600_gfx_is_lockup,
886 .get_rptr = &radeon_ring_generic_get_rptr,
887 .get_wptr = &radeon_ring_generic_get_wptr,
888 .set_wptr = &radeon_ring_generic_set_wptr,
889};
890
891static struct radeon_asic_ring r600_dma_ring = {
892 .ib_execute = &r600_dma_ring_ib_execute,
893 .emit_fence = &r600_dma_fence_ring_emit,
894 .emit_semaphore = &r600_dma_semaphore_ring_emit,
895 .cs_parse = &r600_dma_cs_parse,
896 .ring_test = &r600_dma_ring_test,
897 .ib_test = &r600_dma_ib_test,
898 .is_lockup = &r600_dma_is_lockup,
899 .get_rptr = &r600_dma_get_rptr,
900 .get_wptr = &r600_dma_get_wptr,
901 .set_wptr = &r600_dma_set_wptr,
902};
903
904static struct radeon_asic r600_asic = {
905 .init = &r600_init,
906 .fini = &r600_fini,
907 .suspend = &r600_suspend,
908 .resume = &r600_resume,
909 .vga_set_state = &r600_vga_set_state,
910 .asic_reset = &r600_asic_reset,
911 .ioctl_wait_idle = r600_ioctl_wait_idle,
912 .gui_idle = &r600_gui_idle,
913 .mc_wait_for_idle = &r600_mc_wait_for_idle,
914 .get_xclk = &r600_get_xclk,
915 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
916 .gart = {
917 .tlb_flush = &r600_pcie_gart_tlb_flush,
918 .set_page = &rs600_gart_set_page,
919 },
920 .ring = {
921 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
922 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
923 },
924 .irq = {
925 .set = &r600_irq_set,
926 .process = &r600_irq_process,
927 },
928 .display = {
929 .bandwidth_update = &rv515_bandwidth_update,
930 .get_vblank_counter = &rs600_get_vblank_counter,
931 .wait_for_vblank = &avivo_wait_for_vblank,
932 .set_backlight_level = &atombios_set_backlight_level,
933 .get_backlight_level = &atombios_get_backlight_level,
934 .hdmi_enable = &r600_hdmi_enable,
935 .hdmi_setmode = &r600_hdmi_setmode,
936 },
937 .copy = {
938 .blit = &r600_copy_cpdma,
939 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
940 .dma = &r600_copy_dma,
941 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
942 .copy = &r600_copy_cpdma,
943 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
944 },
945 .surface = {
946 .set_reg = r600_set_surface_reg,
947 .clear_reg = r600_clear_surface_reg,
948 },
949 .hpd = {
950 .init = &r600_hpd_init,
951 .fini = &r600_hpd_fini,
952 .sense = &r600_hpd_sense,
953 .set_polarity = &r600_hpd_set_polarity,
954 },
955 .pm = {
956 .misc = &r600_pm_misc,
957 .prepare = &rs600_pm_prepare,
958 .finish = &rs600_pm_finish,
959 .init_profile = &r600_pm_init_profile,
960 .get_dynpm_state = &r600_pm_get_dynpm_state,
961 .get_engine_clock = &radeon_atom_get_engine_clock,
962 .set_engine_clock = &radeon_atom_set_engine_clock,
963 .get_memory_clock = &radeon_atom_get_memory_clock,
964 .set_memory_clock = &radeon_atom_set_memory_clock,
965 .get_pcie_lanes = &r600_get_pcie_lanes,
966 .set_pcie_lanes = &r600_set_pcie_lanes,
967 .set_clock_gating = NULL,
968 .get_temperature = &rv6xx_get_temp,
969 },
970 .pflip = {
971 .pre_page_flip = &rs600_pre_page_flip,
972 .page_flip = &rs600_page_flip,
973 .post_page_flip = &rs600_post_page_flip,
974 },
975};
976
977static struct radeon_asic rv6xx_asic = {
978 .init = &r600_init,
979 .fini = &r600_fini,
980 .suspend = &r600_suspend,
981 .resume = &r600_resume,
982 .vga_set_state = &r600_vga_set_state,
983 .asic_reset = &r600_asic_reset,
984 .ioctl_wait_idle = r600_ioctl_wait_idle,
985 .gui_idle = &r600_gui_idle,
986 .mc_wait_for_idle = &r600_mc_wait_for_idle,
987 .get_xclk = &r600_get_xclk,
988 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
989 .gart = {
990 .tlb_flush = &r600_pcie_gart_tlb_flush,
991 .set_page = &rs600_gart_set_page,
992 },
993 .ring = {
994 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
995 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
996 },
997 .irq = {
998 .set = &r600_irq_set,
999 .process = &r600_irq_process,
1000 },
1001 .display = {
1002 .bandwidth_update = &rv515_bandwidth_update,
1003 .get_vblank_counter = &rs600_get_vblank_counter,
1004 .wait_for_vblank = &avivo_wait_for_vblank,
1005 .set_backlight_level = &atombios_set_backlight_level,
1006 .get_backlight_level = &atombios_get_backlight_level,
1007 .hdmi_enable = &r600_hdmi_enable,
1008 .hdmi_setmode = &r600_hdmi_setmode,
1009 },
1010 .copy = {
1011 .blit = &r600_copy_cpdma,
1012 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1013 .dma = &r600_copy_dma,
1014 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1015 .copy = &r600_copy_cpdma,
1016 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1017 },
1018 .surface = {
1019 .set_reg = r600_set_surface_reg,
1020 .clear_reg = r600_clear_surface_reg,
1021 },
1022 .hpd = {
1023 .init = &r600_hpd_init,
1024 .fini = &r600_hpd_fini,
1025 .sense = &r600_hpd_sense,
1026 .set_polarity = &r600_hpd_set_polarity,
1027 },
1028 .pm = {
1029 .misc = &r600_pm_misc,
1030 .prepare = &rs600_pm_prepare,
1031 .finish = &rs600_pm_finish,
1032 .init_profile = &r600_pm_init_profile,
1033 .get_dynpm_state = &r600_pm_get_dynpm_state,
1034 .get_engine_clock = &radeon_atom_get_engine_clock,
1035 .set_engine_clock = &radeon_atom_set_engine_clock,
1036 .get_memory_clock = &radeon_atom_get_memory_clock,
1037 .set_memory_clock = &radeon_atom_set_memory_clock,
1038 .get_pcie_lanes = &r600_get_pcie_lanes,
1039 .set_pcie_lanes = &r600_set_pcie_lanes,
1040 .set_clock_gating = NULL,
1041 .get_temperature = &rv6xx_get_temp,
1042 .set_uvd_clocks = &r600_set_uvd_clocks,
1043 },
1044 .dpm = {
1045 .init = &rv6xx_dpm_init,
1046 .setup_asic = &rv6xx_setup_asic,
1047 .enable = &rv6xx_dpm_enable,
1048 .late_enable = &r600_dpm_late_enable,
1049 .disable = &rv6xx_dpm_disable,
1050 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1051 .set_power_state = &rv6xx_dpm_set_power_state,
1052 .post_set_power_state = &r600_dpm_post_set_power_state,
1053 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1054 .fini = &rv6xx_dpm_fini,
1055 .get_sclk = &rv6xx_dpm_get_sclk,
1056 .get_mclk = &rv6xx_dpm_get_mclk,
1057 .print_power_state = &rv6xx_dpm_print_power_state,
1058 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1059 .force_performance_level = &rv6xx_dpm_force_performance_level,
1060 },
1061 .pflip = {
1062 .pre_page_flip = &rs600_pre_page_flip,
1063 .page_flip = &rs600_page_flip,
1064 .post_page_flip = &rs600_post_page_flip,
1065 },
1066};
1067
1068static struct radeon_asic rs780_asic = {
1069 .init = &r600_init,
1070 .fini = &r600_fini,
1071 .suspend = &r600_suspend,
1072 .resume = &r600_resume,
1073 .vga_set_state = &r600_vga_set_state,
1074 .asic_reset = &r600_asic_reset,
1075 .ioctl_wait_idle = r600_ioctl_wait_idle,
1076 .gui_idle = &r600_gui_idle,
1077 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1078 .get_xclk = &r600_get_xclk,
1079 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1080 .gart = {
1081 .tlb_flush = &r600_pcie_gart_tlb_flush,
1082 .set_page = &rs600_gart_set_page,
1083 },
1084 .ring = {
1085 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1086 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1087 },
1088 .irq = {
1089 .set = &r600_irq_set,
1090 .process = &r600_irq_process,
1091 },
1092 .display = {
1093 .bandwidth_update = &rs690_bandwidth_update,
1094 .get_vblank_counter = &rs600_get_vblank_counter,
1095 .wait_for_vblank = &avivo_wait_for_vblank,
1096 .set_backlight_level = &atombios_set_backlight_level,
1097 .get_backlight_level = &atombios_get_backlight_level,
1098 .hdmi_enable = &r600_hdmi_enable,
1099 .hdmi_setmode = &r600_hdmi_setmode,
1100 },
1101 .copy = {
1102 .blit = &r600_copy_cpdma,
1103 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1104 .dma = &r600_copy_dma,
1105 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1106 .copy = &r600_copy_cpdma,
1107 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1108 },
1109 .surface = {
1110 .set_reg = r600_set_surface_reg,
1111 .clear_reg = r600_clear_surface_reg,
1112 },
1113 .hpd = {
1114 .init = &r600_hpd_init,
1115 .fini = &r600_hpd_fini,
1116 .sense = &r600_hpd_sense,
1117 .set_polarity = &r600_hpd_set_polarity,
1118 },
1119 .pm = {
1120 .misc = &r600_pm_misc,
1121 .prepare = &rs600_pm_prepare,
1122 .finish = &rs600_pm_finish,
1123 .init_profile = &rs780_pm_init_profile,
1124 .get_dynpm_state = &r600_pm_get_dynpm_state,
1125 .get_engine_clock = &radeon_atom_get_engine_clock,
1126 .set_engine_clock = &radeon_atom_set_engine_clock,
1127 .get_memory_clock = NULL,
1128 .set_memory_clock = NULL,
1129 .get_pcie_lanes = NULL,
1130 .set_pcie_lanes = NULL,
1131 .set_clock_gating = NULL,
1132 .get_temperature = &rv6xx_get_temp,
1133 .set_uvd_clocks = &r600_set_uvd_clocks,
1134 },
1135 .dpm = {
1136 .init = &rs780_dpm_init,
1137 .setup_asic = &rs780_dpm_setup_asic,
1138 .enable = &rs780_dpm_enable,
1139 .late_enable = &r600_dpm_late_enable,
1140 .disable = &rs780_dpm_disable,
1141 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1142 .set_power_state = &rs780_dpm_set_power_state,
1143 .post_set_power_state = &r600_dpm_post_set_power_state,
1144 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1145 .fini = &rs780_dpm_fini,
1146 .get_sclk = &rs780_dpm_get_sclk,
1147 .get_mclk = &rs780_dpm_get_mclk,
1148 .print_power_state = &rs780_dpm_print_power_state,
1149 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
1150 .force_performance_level = &rs780_dpm_force_performance_level,
1151 },
1152 .pflip = {
1153 .pre_page_flip = &rs600_pre_page_flip,
1154 .page_flip = &rs600_page_flip,
1155 .post_page_flip = &rs600_post_page_flip,
1156 },
1157};
1158
1159static struct radeon_asic_ring rv770_uvd_ring = {
1160 .ib_execute = &uvd_v1_0_ib_execute,
1161 .emit_fence = &uvd_v2_2_fence_emit,
1162 .emit_semaphore = &uvd_v1_0_semaphore_emit,
1163 .cs_parse = &radeon_uvd_cs_parse,
1164 .ring_test = &uvd_v1_0_ring_test,
1165 .ib_test = &uvd_v1_0_ib_test,
1166 .is_lockup = &radeon_ring_test_lockup,
1167 .get_rptr = &uvd_v1_0_get_rptr,
1168 .get_wptr = &uvd_v1_0_get_wptr,
1169 .set_wptr = &uvd_v1_0_set_wptr,
1170};
1171
1172static struct radeon_asic rv770_asic = {
1173 .init = &rv770_init,
1174 .fini = &rv770_fini,
1175 .suspend = &rv770_suspend,
1176 .resume = &rv770_resume,
1177 .asic_reset = &r600_asic_reset,
1178 .vga_set_state = &r600_vga_set_state,
1179 .ioctl_wait_idle = r600_ioctl_wait_idle,
1180 .gui_idle = &r600_gui_idle,
1181 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1182 .get_xclk = &rv770_get_xclk,
1183 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1184 .gart = {
1185 .tlb_flush = &r600_pcie_gart_tlb_flush,
1186 .set_page = &rs600_gart_set_page,
1187 },
1188 .ring = {
1189 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1190 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1191 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1192 },
1193 .irq = {
1194 .set = &r600_irq_set,
1195 .process = &r600_irq_process,
1196 },
1197 .display = {
1198 .bandwidth_update = &rv515_bandwidth_update,
1199 .get_vblank_counter = &rs600_get_vblank_counter,
1200 .wait_for_vblank = &avivo_wait_for_vblank,
1201 .set_backlight_level = &atombios_set_backlight_level,
1202 .get_backlight_level = &atombios_get_backlight_level,
1203 .hdmi_enable = &r600_hdmi_enable,
1204 .hdmi_setmode = &r600_hdmi_setmode,
1205 },
1206 .copy = {
1207 .blit = &r600_copy_cpdma,
1208 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1209 .dma = &rv770_copy_dma,
1210 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1211 .copy = &rv770_copy_dma,
1212 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1213 },
1214 .surface = {
1215 .set_reg = r600_set_surface_reg,
1216 .clear_reg = r600_clear_surface_reg,
1217 },
1218 .hpd = {
1219 .init = &r600_hpd_init,
1220 .fini = &r600_hpd_fini,
1221 .sense = &r600_hpd_sense,
1222 .set_polarity = &r600_hpd_set_polarity,
1223 },
1224 .pm = {
1225 .misc = &rv770_pm_misc,
1226 .prepare = &rs600_pm_prepare,
1227 .finish = &rs600_pm_finish,
1228 .init_profile = &r600_pm_init_profile,
1229 .get_dynpm_state = &r600_pm_get_dynpm_state,
1230 .get_engine_clock = &radeon_atom_get_engine_clock,
1231 .set_engine_clock = &radeon_atom_set_engine_clock,
1232 .get_memory_clock = &radeon_atom_get_memory_clock,
1233 .set_memory_clock = &radeon_atom_set_memory_clock,
1234 .get_pcie_lanes = &r600_get_pcie_lanes,
1235 .set_pcie_lanes = &r600_set_pcie_lanes,
1236 .set_clock_gating = &radeon_atom_set_clock_gating,
1237 .set_uvd_clocks = &rv770_set_uvd_clocks,
1238 .get_temperature = &rv770_get_temp,
1239 },
1240 .dpm = {
1241 .init = &rv770_dpm_init,
1242 .setup_asic = &rv770_dpm_setup_asic,
1243 .enable = &rv770_dpm_enable,
1244 .late_enable = &rv770_dpm_late_enable,
1245 .disable = &rv770_dpm_disable,
1246 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1247 .set_power_state = &rv770_dpm_set_power_state,
1248 .post_set_power_state = &r600_dpm_post_set_power_state,
1249 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1250 .fini = &rv770_dpm_fini,
1251 .get_sclk = &rv770_dpm_get_sclk,
1252 .get_mclk = &rv770_dpm_get_mclk,
1253 .print_power_state = &rv770_dpm_print_power_state,
1254 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1255 .force_performance_level = &rv770_dpm_force_performance_level,
1256 .vblank_too_short = &rv770_dpm_vblank_too_short,
1257 },
1258 .pflip = {
1259 .pre_page_flip = &rs600_pre_page_flip,
1260 .page_flip = &rv770_page_flip,
1261 .post_page_flip = &rs600_post_page_flip,
1262 },
1263};
1264
1265static struct radeon_asic_ring evergreen_gfx_ring = {
1266 .ib_execute = &evergreen_ring_ib_execute,
1267 .emit_fence = &r600_fence_ring_emit,
1268 .emit_semaphore = &r600_semaphore_ring_emit,
1269 .cs_parse = &evergreen_cs_parse,
1270 .ring_test = &r600_ring_test,
1271 .ib_test = &r600_ib_test,
1272 .is_lockup = &evergreen_gfx_is_lockup,
1273 .get_rptr = &radeon_ring_generic_get_rptr,
1274 .get_wptr = &radeon_ring_generic_get_wptr,
1275 .set_wptr = &radeon_ring_generic_set_wptr,
1276};
1277
1278static struct radeon_asic_ring evergreen_dma_ring = {
1279 .ib_execute = &evergreen_dma_ring_ib_execute,
1280 .emit_fence = &evergreen_dma_fence_ring_emit,
1281 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1282 .cs_parse = &evergreen_dma_cs_parse,
1283 .ring_test = &r600_dma_ring_test,
1284 .ib_test = &r600_dma_ib_test,
1285 .is_lockup = &evergreen_dma_is_lockup,
1286 .get_rptr = &r600_dma_get_rptr,
1287 .get_wptr = &r600_dma_get_wptr,
1288 .set_wptr = &r600_dma_set_wptr,
1289};
1290
1291static struct radeon_asic evergreen_asic = {
1292 .init = &evergreen_init,
1293 .fini = &evergreen_fini,
1294 .suspend = &evergreen_suspend,
1295 .resume = &evergreen_resume,
1296 .asic_reset = &evergreen_asic_reset,
1297 .vga_set_state = &r600_vga_set_state,
1298 .ioctl_wait_idle = r600_ioctl_wait_idle,
1299 .gui_idle = &r600_gui_idle,
1300 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1301 .get_xclk = &rv770_get_xclk,
1302 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1303 .gart = {
1304 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1305 .set_page = &rs600_gart_set_page,
1306 },
1307 .ring = {
1308 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1309 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1310 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1311 },
1312 .irq = {
1313 .set = &evergreen_irq_set,
1314 .process = &evergreen_irq_process,
1315 },
1316 .display = {
1317 .bandwidth_update = &evergreen_bandwidth_update,
1318 .get_vblank_counter = &evergreen_get_vblank_counter,
1319 .wait_for_vblank = &dce4_wait_for_vblank,
1320 .set_backlight_level = &atombios_set_backlight_level,
1321 .get_backlight_level = &atombios_get_backlight_level,
1322 .hdmi_enable = &evergreen_hdmi_enable,
1323 .hdmi_setmode = &evergreen_hdmi_setmode,
1324 },
1325 .copy = {
1326 .blit = &r600_copy_cpdma,
1327 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1328 .dma = &evergreen_copy_dma,
1329 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1330 .copy = &evergreen_copy_dma,
1331 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1332 },
1333 .surface = {
1334 .set_reg = r600_set_surface_reg,
1335 .clear_reg = r600_clear_surface_reg,
1336 },
1337 .hpd = {
1338 .init = &evergreen_hpd_init,
1339 .fini = &evergreen_hpd_fini,
1340 .sense = &evergreen_hpd_sense,
1341 .set_polarity = &evergreen_hpd_set_polarity,
1342 },
1343 .pm = {
1344 .misc = &evergreen_pm_misc,
1345 .prepare = &evergreen_pm_prepare,
1346 .finish = &evergreen_pm_finish,
1347 .init_profile = &r600_pm_init_profile,
1348 .get_dynpm_state = &r600_pm_get_dynpm_state,
1349 .get_engine_clock = &radeon_atom_get_engine_clock,
1350 .set_engine_clock = &radeon_atom_set_engine_clock,
1351 .get_memory_clock = &radeon_atom_get_memory_clock,
1352 .set_memory_clock = &radeon_atom_set_memory_clock,
1353 .get_pcie_lanes = &r600_get_pcie_lanes,
1354 .set_pcie_lanes = &r600_set_pcie_lanes,
1355 .set_clock_gating = NULL,
1356 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1357 .get_temperature = &evergreen_get_temp,
1358 },
1359 .dpm = {
1360 .init = &cypress_dpm_init,
1361 .setup_asic = &cypress_dpm_setup_asic,
1362 .enable = &cypress_dpm_enable,
1363 .late_enable = &rv770_dpm_late_enable,
1364 .disable = &cypress_dpm_disable,
1365 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1366 .set_power_state = &cypress_dpm_set_power_state,
1367 .post_set_power_state = &r600_dpm_post_set_power_state,
1368 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1369 .fini = &cypress_dpm_fini,
1370 .get_sclk = &rv770_dpm_get_sclk,
1371 .get_mclk = &rv770_dpm_get_mclk,
1372 .print_power_state = &rv770_dpm_print_power_state,
1373 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1374 .force_performance_level = &rv770_dpm_force_performance_level,
1375 .vblank_too_short = &cypress_dpm_vblank_too_short,
1376 },
1377 .pflip = {
1378 .pre_page_flip = &evergreen_pre_page_flip,
1379 .page_flip = &evergreen_page_flip,
1380 .post_page_flip = &evergreen_post_page_flip,
1381 },
1382};
1383
1384static struct radeon_asic sumo_asic = {
1385 .init = &evergreen_init,
1386 .fini = &evergreen_fini,
1387 .suspend = &evergreen_suspend,
1388 .resume = &evergreen_resume,
1389 .asic_reset = &evergreen_asic_reset,
1390 .vga_set_state = &r600_vga_set_state,
1391 .ioctl_wait_idle = r600_ioctl_wait_idle,
1392 .gui_idle = &r600_gui_idle,
1393 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1394 .get_xclk = &r600_get_xclk,
1395 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1396 .gart = {
1397 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1398 .set_page = &rs600_gart_set_page,
1399 },
1400 .ring = {
1401 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1402 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1403 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1404 },
1405 .irq = {
1406 .set = &evergreen_irq_set,
1407 .process = &evergreen_irq_process,
1408 },
1409 .display = {
1410 .bandwidth_update = &evergreen_bandwidth_update,
1411 .get_vblank_counter = &evergreen_get_vblank_counter,
1412 .wait_for_vblank = &dce4_wait_for_vblank,
1413 .set_backlight_level = &atombios_set_backlight_level,
1414 .get_backlight_level = &atombios_get_backlight_level,
1415 .hdmi_enable = &evergreen_hdmi_enable,
1416 .hdmi_setmode = &evergreen_hdmi_setmode,
1417 },
1418 .copy = {
1419 .blit = &r600_copy_cpdma,
1420 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1421 .dma = &evergreen_copy_dma,
1422 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1423 .copy = &evergreen_copy_dma,
1424 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1425 },
1426 .surface = {
1427 .set_reg = r600_set_surface_reg,
1428 .clear_reg = r600_clear_surface_reg,
1429 },
1430 .hpd = {
1431 .init = &evergreen_hpd_init,
1432 .fini = &evergreen_hpd_fini,
1433 .sense = &evergreen_hpd_sense,
1434 .set_polarity = &evergreen_hpd_set_polarity,
1435 },
1436 .pm = {
1437 .misc = &evergreen_pm_misc,
1438 .prepare = &evergreen_pm_prepare,
1439 .finish = &evergreen_pm_finish,
1440 .init_profile = &sumo_pm_init_profile,
1441 .get_dynpm_state = &r600_pm_get_dynpm_state,
1442 .get_engine_clock = &radeon_atom_get_engine_clock,
1443 .set_engine_clock = &radeon_atom_set_engine_clock,
1444 .get_memory_clock = NULL,
1445 .set_memory_clock = NULL,
1446 .get_pcie_lanes = NULL,
1447 .set_pcie_lanes = NULL,
1448 .set_clock_gating = NULL,
1449 .set_uvd_clocks = &sumo_set_uvd_clocks,
1450 .get_temperature = &sumo_get_temp,
1451 },
1452 .dpm = {
1453 .init = &sumo_dpm_init,
1454 .setup_asic = &sumo_dpm_setup_asic,
1455 .enable = &sumo_dpm_enable,
1456 .late_enable = &sumo_dpm_late_enable,
1457 .disable = &sumo_dpm_disable,
1458 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
1459 .set_power_state = &sumo_dpm_set_power_state,
1460 .post_set_power_state = &sumo_dpm_post_set_power_state,
1461 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1462 .fini = &sumo_dpm_fini,
1463 .get_sclk = &sumo_dpm_get_sclk,
1464 .get_mclk = &sumo_dpm_get_mclk,
1465 .print_power_state = &sumo_dpm_print_power_state,
1466 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
1467 .force_performance_level = &sumo_dpm_force_performance_level,
1468 },
1469 .pflip = {
1470 .pre_page_flip = &evergreen_pre_page_flip,
1471 .page_flip = &evergreen_page_flip,
1472 .post_page_flip = &evergreen_post_page_flip,
1473 },
1474};
1475
1476static struct radeon_asic btc_asic = {
1477 .init = &evergreen_init,
1478 .fini = &evergreen_fini,
1479 .suspend = &evergreen_suspend,
1480 .resume = &evergreen_resume,
1481 .asic_reset = &evergreen_asic_reset,
1482 .vga_set_state = &r600_vga_set_state,
1483 .ioctl_wait_idle = r600_ioctl_wait_idle,
1484 .gui_idle = &r600_gui_idle,
1485 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1486 .get_xclk = &rv770_get_xclk,
1487 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1488 .gart = {
1489 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1490 .set_page = &rs600_gart_set_page,
1491 },
1492 .ring = {
1493 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1494 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1495 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1496 },
1497 .irq = {
1498 .set = &evergreen_irq_set,
1499 .process = &evergreen_irq_process,
1500 },
1501 .display = {
1502 .bandwidth_update = &evergreen_bandwidth_update,
1503 .get_vblank_counter = &evergreen_get_vblank_counter,
1504 .wait_for_vblank = &dce4_wait_for_vblank,
1505 .set_backlight_level = &atombios_set_backlight_level,
1506 .get_backlight_level = &atombios_get_backlight_level,
1507 .hdmi_enable = &evergreen_hdmi_enable,
1508 .hdmi_setmode = &evergreen_hdmi_setmode,
1509 },
1510 .copy = {
1511 .blit = &r600_copy_cpdma,
1512 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1513 .dma = &evergreen_copy_dma,
1514 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1515 .copy = &evergreen_copy_dma,
1516 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1517 },
1518 .surface = {
1519 .set_reg = r600_set_surface_reg,
1520 .clear_reg = r600_clear_surface_reg,
1521 },
1522 .hpd = {
1523 .init = &evergreen_hpd_init,
1524 .fini = &evergreen_hpd_fini,
1525 .sense = &evergreen_hpd_sense,
1526 .set_polarity = &evergreen_hpd_set_polarity,
1527 },
1528 .pm = {
1529 .misc = &evergreen_pm_misc,
1530 .prepare = &evergreen_pm_prepare,
1531 .finish = &evergreen_pm_finish,
1532 .init_profile = &btc_pm_init_profile,
1533 .get_dynpm_state = &r600_pm_get_dynpm_state,
1534 .get_engine_clock = &radeon_atom_get_engine_clock,
1535 .set_engine_clock = &radeon_atom_set_engine_clock,
1536 .get_memory_clock = &radeon_atom_get_memory_clock,
1537 .set_memory_clock = &radeon_atom_set_memory_clock,
1538 .get_pcie_lanes = &r600_get_pcie_lanes,
1539 .set_pcie_lanes = &r600_set_pcie_lanes,
1540 .set_clock_gating = NULL,
1541 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1542 .get_temperature = &evergreen_get_temp,
1543 },
1544 .dpm = {
1545 .init = &btc_dpm_init,
1546 .setup_asic = &btc_dpm_setup_asic,
1547 .enable = &btc_dpm_enable,
1548 .late_enable = &rv770_dpm_late_enable,
1549 .disable = &btc_dpm_disable,
1550 .pre_set_power_state = &btc_dpm_pre_set_power_state,
1551 .set_power_state = &btc_dpm_set_power_state,
1552 .post_set_power_state = &btc_dpm_post_set_power_state,
1553 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1554 .fini = &btc_dpm_fini,
1555 .get_sclk = &btc_dpm_get_sclk,
1556 .get_mclk = &btc_dpm_get_mclk,
1557 .print_power_state = &rv770_dpm_print_power_state,
1558 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1559 .force_performance_level = &rv770_dpm_force_performance_level,
1560 .vblank_too_short = &btc_dpm_vblank_too_short,
1561 },
1562 .pflip = {
1563 .pre_page_flip = &evergreen_pre_page_flip,
1564 .page_flip = &evergreen_page_flip,
1565 .post_page_flip = &evergreen_post_page_flip,
1566 },
1567};
1568
1569static struct radeon_asic_ring cayman_gfx_ring = {
1570 .ib_execute = &cayman_ring_ib_execute,
1571 .ib_parse = &evergreen_ib_parse,
1572 .emit_fence = &cayman_fence_ring_emit,
1573 .emit_semaphore = &r600_semaphore_ring_emit,
1574 .cs_parse = &evergreen_cs_parse,
1575 .ring_test = &r600_ring_test,
1576 .ib_test = &r600_ib_test,
1577 .is_lockup = &cayman_gfx_is_lockup,
1578 .vm_flush = &cayman_vm_flush,
1579 .get_rptr = &radeon_ring_generic_get_rptr,
1580 .get_wptr = &radeon_ring_generic_get_wptr,
1581 .set_wptr = &radeon_ring_generic_set_wptr,
1582};
1583
1584static struct radeon_asic_ring cayman_dma_ring = {
1585 .ib_execute = &cayman_dma_ring_ib_execute,
1586 .ib_parse = &evergreen_dma_ib_parse,
1587 .emit_fence = &evergreen_dma_fence_ring_emit,
1588 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1589 .cs_parse = &evergreen_dma_cs_parse,
1590 .ring_test = &r600_dma_ring_test,
1591 .ib_test = &r600_dma_ib_test,
1592 .is_lockup = &cayman_dma_is_lockup,
1593 .vm_flush = &cayman_dma_vm_flush,
1594 .get_rptr = &r600_dma_get_rptr,
1595 .get_wptr = &r600_dma_get_wptr,
1596 .set_wptr = &r600_dma_set_wptr
1597};
1598
1599static struct radeon_asic_ring cayman_uvd_ring = {
1600 .ib_execute = &uvd_v1_0_ib_execute,
1601 .emit_fence = &uvd_v2_2_fence_emit,
1602 .emit_semaphore = &uvd_v3_1_semaphore_emit,
1603 .cs_parse = &radeon_uvd_cs_parse,
1604 .ring_test = &uvd_v1_0_ring_test,
1605 .ib_test = &uvd_v1_0_ib_test,
1606 .is_lockup = &radeon_ring_test_lockup,
1607 .get_rptr = &uvd_v1_0_get_rptr,
1608 .get_wptr = &uvd_v1_0_get_wptr,
1609 .set_wptr = &uvd_v1_0_set_wptr,
1610};
1611
1612static struct radeon_asic cayman_asic = {
1613 .init = &cayman_init,
1614 .fini = &cayman_fini,
1615 .suspend = &cayman_suspend,
1616 .resume = &cayman_resume,
1617 .asic_reset = &cayman_asic_reset,
1618 .vga_set_state = &r600_vga_set_state,
1619 .ioctl_wait_idle = r600_ioctl_wait_idle,
1620 .gui_idle = &r600_gui_idle,
1621 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1622 .get_xclk = &rv770_get_xclk,
1623 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1624 .gart = {
1625 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1626 .set_page = &rs600_gart_set_page,
1627 },
1628 .vm = {
1629 .init = &cayman_vm_init,
1630 .fini = &cayman_vm_fini,
1631 .set_page = &cayman_dma_vm_set_page,
1632 },
1633 .ring = {
1634 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1635 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1636 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1637 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1638 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1639 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1640 },
1641 .irq = {
1642 .set = &evergreen_irq_set,
1643 .process = &evergreen_irq_process,
1644 },
1645 .display = {
1646 .bandwidth_update = &evergreen_bandwidth_update,
1647 .get_vblank_counter = &evergreen_get_vblank_counter,
1648 .wait_for_vblank = &dce4_wait_for_vblank,
1649 .set_backlight_level = &atombios_set_backlight_level,
1650 .get_backlight_level = &atombios_get_backlight_level,
1651 .hdmi_enable = &evergreen_hdmi_enable,
1652 .hdmi_setmode = &evergreen_hdmi_setmode,
1653 },
1654 .copy = {
1655 .blit = &r600_copy_cpdma,
1656 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1657 .dma = &evergreen_copy_dma,
1658 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1659 .copy = &evergreen_copy_dma,
1660 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1661 },
1662 .surface = {
1663 .set_reg = r600_set_surface_reg,
1664 .clear_reg = r600_clear_surface_reg,
1665 },
1666 .hpd = {
1667 .init = &evergreen_hpd_init,
1668 .fini = &evergreen_hpd_fini,
1669 .sense = &evergreen_hpd_sense,
1670 .set_polarity = &evergreen_hpd_set_polarity,
1671 },
1672 .pm = {
1673 .misc = &evergreen_pm_misc,
1674 .prepare = &evergreen_pm_prepare,
1675 .finish = &evergreen_pm_finish,
1676 .init_profile = &btc_pm_init_profile,
1677 .get_dynpm_state = &r600_pm_get_dynpm_state,
1678 .get_engine_clock = &radeon_atom_get_engine_clock,
1679 .set_engine_clock = &radeon_atom_set_engine_clock,
1680 .get_memory_clock = &radeon_atom_get_memory_clock,
1681 .set_memory_clock = &radeon_atom_set_memory_clock,
1682 .get_pcie_lanes = &r600_get_pcie_lanes,
1683 .set_pcie_lanes = &r600_set_pcie_lanes,
1684 .set_clock_gating = NULL,
1685 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1686 .get_temperature = &evergreen_get_temp,
1687 },
1688 .dpm = {
1689 .init = &ni_dpm_init,
1690 .setup_asic = &ni_dpm_setup_asic,
1691 .enable = &ni_dpm_enable,
1692 .late_enable = &rv770_dpm_late_enable,
1693 .disable = &ni_dpm_disable,
1694 .pre_set_power_state = &ni_dpm_pre_set_power_state,
1695 .set_power_state = &ni_dpm_set_power_state,
1696 .post_set_power_state = &ni_dpm_post_set_power_state,
1697 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1698 .fini = &ni_dpm_fini,
1699 .get_sclk = &ni_dpm_get_sclk,
1700 .get_mclk = &ni_dpm_get_mclk,
1701 .print_power_state = &ni_dpm_print_power_state,
1702 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
1703 .force_performance_level = &ni_dpm_force_performance_level,
1704 .vblank_too_short = &ni_dpm_vblank_too_short,
1705 },
1706 .pflip = {
1707 .pre_page_flip = &evergreen_pre_page_flip,
1708 .page_flip = &evergreen_page_flip,
1709 .post_page_flip = &evergreen_post_page_flip,
1710 },
1711};
1712
1713static struct radeon_asic trinity_asic = {
1714 .init = &cayman_init,
1715 .fini = &cayman_fini,
1716 .suspend = &cayman_suspend,
1717 .resume = &cayman_resume,
1718 .asic_reset = &cayman_asic_reset,
1719 .vga_set_state = &r600_vga_set_state,
1720 .ioctl_wait_idle = r600_ioctl_wait_idle,
1721 .gui_idle = &r600_gui_idle,
1722 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1723 .get_xclk = &r600_get_xclk,
1724 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1725 .gart = {
1726 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1727 .set_page = &rs600_gart_set_page,
1728 },
1729 .vm = {
1730 .init = &cayman_vm_init,
1731 .fini = &cayman_vm_fini,
1732 .set_page = &cayman_dma_vm_set_page,
1733 },
1734 .ring = {
1735 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1736 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1737 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1738 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1739 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1740 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1741 },
1742 .irq = {
1743 .set = &evergreen_irq_set,
1744 .process = &evergreen_irq_process,
1745 },
1746 .display = {
1747 .bandwidth_update = &dce6_bandwidth_update,
1748 .get_vblank_counter = &evergreen_get_vblank_counter,
1749 .wait_for_vblank = &dce4_wait_for_vblank,
1750 .set_backlight_level = &atombios_set_backlight_level,
1751 .get_backlight_level = &atombios_get_backlight_level,
1752 .hdmi_enable = &evergreen_hdmi_enable,
1753 .hdmi_setmode = &evergreen_hdmi_setmode,
1754 },
1755 .copy = {
1756 .blit = &r600_copy_cpdma,
1757 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1758 .dma = &evergreen_copy_dma,
1759 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1760 .copy = &evergreen_copy_dma,
1761 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1762 },
1763 .surface = {
1764 .set_reg = r600_set_surface_reg,
1765 .clear_reg = r600_clear_surface_reg,
1766 },
1767 .hpd = {
1768 .init = &evergreen_hpd_init,
1769 .fini = &evergreen_hpd_fini,
1770 .sense = &evergreen_hpd_sense,
1771 .set_polarity = &evergreen_hpd_set_polarity,
1772 },
1773 .pm = {
1774 .misc = &evergreen_pm_misc,
1775 .prepare = &evergreen_pm_prepare,
1776 .finish = &evergreen_pm_finish,
1777 .init_profile = &sumo_pm_init_profile,
1778 .get_dynpm_state = &r600_pm_get_dynpm_state,
1779 .get_engine_clock = &radeon_atom_get_engine_clock,
1780 .set_engine_clock = &radeon_atom_set_engine_clock,
1781 .get_memory_clock = NULL,
1782 .set_memory_clock = NULL,
1783 .get_pcie_lanes = NULL,
1784 .set_pcie_lanes = NULL,
1785 .set_clock_gating = NULL,
1786 .set_uvd_clocks = &sumo_set_uvd_clocks,
1787 .get_temperature = &tn_get_temp,
1788 },
1789 .dpm = {
1790 .init = &trinity_dpm_init,
1791 .setup_asic = &trinity_dpm_setup_asic,
1792 .enable = &trinity_dpm_enable,
1793 .late_enable = &trinity_dpm_late_enable,
1794 .disable = &trinity_dpm_disable,
1795 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
1796 .set_power_state = &trinity_dpm_set_power_state,
1797 .post_set_power_state = &trinity_dpm_post_set_power_state,
1798 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1799 .fini = &trinity_dpm_fini,
1800 .get_sclk = &trinity_dpm_get_sclk,
1801 .get_mclk = &trinity_dpm_get_mclk,
1802 .print_power_state = &trinity_dpm_print_power_state,
1803 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
1804 .force_performance_level = &trinity_dpm_force_performance_level,
1805 .enable_bapm = &trinity_dpm_enable_bapm,
1806 },
1807 .pflip = {
1808 .pre_page_flip = &evergreen_pre_page_flip,
1809 .page_flip = &evergreen_page_flip,
1810 .post_page_flip = &evergreen_post_page_flip,
1811 },
1812};
1813
1814static struct radeon_asic_ring si_gfx_ring = {
1815 .ib_execute = &si_ring_ib_execute,
1816 .ib_parse = &si_ib_parse,
1817 .emit_fence = &si_fence_ring_emit,
1818 .emit_semaphore = &r600_semaphore_ring_emit,
1819 .cs_parse = NULL,
1820 .ring_test = &r600_ring_test,
1821 .ib_test = &r600_ib_test,
1822 .is_lockup = &si_gfx_is_lockup,
1823 .vm_flush = &si_vm_flush,
1824 .get_rptr = &radeon_ring_generic_get_rptr,
1825 .get_wptr = &radeon_ring_generic_get_wptr,
1826 .set_wptr = &radeon_ring_generic_set_wptr,
1827};
1828
1829static struct radeon_asic_ring si_dma_ring = {
1830 .ib_execute = &cayman_dma_ring_ib_execute,
1831 .ib_parse = &evergreen_dma_ib_parse,
1832 .emit_fence = &evergreen_dma_fence_ring_emit,
1833 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1834 .cs_parse = NULL,
1835 .ring_test = &r600_dma_ring_test,
1836 .ib_test = &r600_dma_ib_test,
1837 .is_lockup = &si_dma_is_lockup,
1838 .vm_flush = &si_dma_vm_flush,
1839 .get_rptr = &r600_dma_get_rptr,
1840 .get_wptr = &r600_dma_get_wptr,
1841 .set_wptr = &r600_dma_set_wptr,
1842};
1843
1844static struct radeon_asic si_asic = {
1845 .init = &si_init,
1846 .fini = &si_fini,
1847 .suspend = &si_suspend,
1848 .resume = &si_resume,
1849 .asic_reset = &si_asic_reset,
1850 .vga_set_state = &r600_vga_set_state,
1851 .ioctl_wait_idle = r600_ioctl_wait_idle,
1852 .gui_idle = &r600_gui_idle,
1853 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1854 .get_xclk = &si_get_xclk,
1855 .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1856 .gart = {
1857 .tlb_flush = &si_pcie_gart_tlb_flush,
1858 .set_page = &rs600_gart_set_page,
1859 },
1860 .vm = {
1861 .init = &si_vm_init,
1862 .fini = &si_vm_fini,
1863 .set_page = &si_dma_vm_set_page,
1864 },
1865 .ring = {
1866 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1867 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1868 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1869 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1870 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1871 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1872 },
1873 .irq = {
1874 .set = &si_irq_set,
1875 .process = &si_irq_process,
1876 },
1877 .display = {
1878 .bandwidth_update = &dce6_bandwidth_update,
1879 .get_vblank_counter = &evergreen_get_vblank_counter,
1880 .wait_for_vblank = &dce4_wait_for_vblank,
1881 .set_backlight_level = &atombios_set_backlight_level,
1882 .get_backlight_level = &atombios_get_backlight_level,
1883 .hdmi_enable = &evergreen_hdmi_enable,
1884 .hdmi_setmode = &evergreen_hdmi_setmode,
1885 },
1886 .copy = {
1887 .blit = &r600_copy_cpdma,
1888 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1889 .dma = &si_copy_dma,
1890 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1891 .copy = &si_copy_dma,
1892 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1893 },
1894 .surface = {
1895 .set_reg = r600_set_surface_reg,
1896 .clear_reg = r600_clear_surface_reg,
1897 },
1898 .hpd = {
1899 .init = &evergreen_hpd_init,
1900 .fini = &evergreen_hpd_fini,
1901 .sense = &evergreen_hpd_sense,
1902 .set_polarity = &evergreen_hpd_set_polarity,
1903 },
1904 .pm = {
1905 .misc = &evergreen_pm_misc,
1906 .prepare = &evergreen_pm_prepare,
1907 .finish = &evergreen_pm_finish,
1908 .init_profile = &sumo_pm_init_profile,
1909 .get_dynpm_state = &r600_pm_get_dynpm_state,
1910 .get_engine_clock = &radeon_atom_get_engine_clock,
1911 .set_engine_clock = &radeon_atom_set_engine_clock,
1912 .get_memory_clock = &radeon_atom_get_memory_clock,
1913 .set_memory_clock = &radeon_atom_set_memory_clock,
1914 .get_pcie_lanes = &r600_get_pcie_lanes,
1915 .set_pcie_lanes = &r600_set_pcie_lanes,
1916 .set_clock_gating = NULL,
1917 .set_uvd_clocks = &si_set_uvd_clocks,
1918 .get_temperature = &si_get_temp,
1919 },
1920 .dpm = {
1921 .init = &si_dpm_init,
1922 .setup_asic = &si_dpm_setup_asic,
1923 .enable = &si_dpm_enable,
1924 .late_enable = &si_dpm_late_enable,
1925 .disable = &si_dpm_disable,
1926 .pre_set_power_state = &si_dpm_pre_set_power_state,
1927 .set_power_state = &si_dpm_set_power_state,
1928 .post_set_power_state = &si_dpm_post_set_power_state,
1929 .display_configuration_changed = &si_dpm_display_configuration_changed,
1930 .fini = &si_dpm_fini,
1931 .get_sclk = &ni_dpm_get_sclk,
1932 .get_mclk = &ni_dpm_get_mclk,
1933 .print_power_state = &ni_dpm_print_power_state,
1934 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
1935 .force_performance_level = &si_dpm_force_performance_level,
1936 .vblank_too_short = &ni_dpm_vblank_too_short,
1937 },
1938 .pflip = {
1939 .pre_page_flip = &evergreen_pre_page_flip,
1940 .page_flip = &evergreen_page_flip,
1941 .post_page_flip = &evergreen_post_page_flip,
1942 },
1943};
1944
1945static struct radeon_asic_ring ci_gfx_ring = {
1946 .ib_execute = &cik_ring_ib_execute,
1947 .ib_parse = &cik_ib_parse,
1948 .emit_fence = &cik_fence_gfx_ring_emit,
1949 .emit_semaphore = &cik_semaphore_ring_emit,
1950 .cs_parse = NULL,
1951 .ring_test = &cik_ring_test,
1952 .ib_test = &cik_ib_test,
1953 .is_lockup = &cik_gfx_is_lockup,
1954 .vm_flush = &cik_vm_flush,
1955 .get_rptr = &radeon_ring_generic_get_rptr,
1956 .get_wptr = &radeon_ring_generic_get_wptr,
1957 .set_wptr = &radeon_ring_generic_set_wptr,
1958};
1959
1960static struct radeon_asic_ring ci_cp_ring = {
1961 .ib_execute = &cik_ring_ib_execute,
1962 .ib_parse = &cik_ib_parse,
1963 .emit_fence = &cik_fence_compute_ring_emit,
1964 .emit_semaphore = &cik_semaphore_ring_emit,
1965 .cs_parse = NULL,
1966 .ring_test = &cik_ring_test,
1967 .ib_test = &cik_ib_test,
1968 .is_lockup = &cik_gfx_is_lockup,
1969 .vm_flush = &cik_vm_flush,
1970 .get_rptr = &cik_compute_ring_get_rptr,
1971 .get_wptr = &cik_compute_ring_get_wptr,
1972 .set_wptr = &cik_compute_ring_set_wptr,
1973};
1974
1975static struct radeon_asic_ring ci_dma_ring = {
1976 .ib_execute = &cik_sdma_ring_ib_execute,
1977 .ib_parse = &cik_ib_parse,
1978 .emit_fence = &cik_sdma_fence_ring_emit,
1979 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
1980 .cs_parse = NULL,
1981 .ring_test = &cik_sdma_ring_test,
1982 .ib_test = &cik_sdma_ib_test,
1983 .is_lockup = &cik_sdma_is_lockup,
1984 .vm_flush = &cik_dma_vm_flush,
1985 .get_rptr = &r600_dma_get_rptr,
1986 .get_wptr = &r600_dma_get_wptr,
1987 .set_wptr = &r600_dma_set_wptr,
1988};
1989
1990static struct radeon_asic ci_asic = {
1991 .init = &cik_init,
1992 .fini = &cik_fini,
1993 .suspend = &cik_suspend,
1994 .resume = &cik_resume,
1995 .asic_reset = &cik_asic_reset,
1996 .vga_set_state = &r600_vga_set_state,
1997 .ioctl_wait_idle = NULL,
1998 .gui_idle = &r600_gui_idle,
1999 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2000 .get_xclk = &cik_get_xclk,
2001 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2002 .gart = {
2003 .tlb_flush = &cik_pcie_gart_tlb_flush,
2004 .set_page = &rs600_gart_set_page,
2005 },
2006 .vm = {
2007 .init = &cik_vm_init,
2008 .fini = &cik_vm_fini,
2009 .set_page = &cik_sdma_vm_set_page,
2010 },
2011 .ring = {
2012 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2013 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2014 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2015 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2016 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2017 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2018 },
2019 .irq = {
2020 .set = &cik_irq_set,
2021 .process = &cik_irq_process,
2022 },
2023 .display = {
2024 .bandwidth_update = &dce8_bandwidth_update,
2025 .get_vblank_counter = &evergreen_get_vblank_counter,
2026 .wait_for_vblank = &dce4_wait_for_vblank,
2027 .set_backlight_level = &atombios_set_backlight_level,
2028 .get_backlight_level = &atombios_get_backlight_level,
2029 .hdmi_enable = &evergreen_hdmi_enable,
2030 .hdmi_setmode = &evergreen_hdmi_setmode,
2031 },
2032 .copy = {
2033 .blit = NULL,
2034 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2035 .dma = &cik_copy_dma,
2036 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2037 .copy = &cik_copy_dma,
2038 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2039 },
2040 .surface = {
2041 .set_reg = r600_set_surface_reg,
2042 .clear_reg = r600_clear_surface_reg,
2043 },
2044 .hpd = {
2045 .init = &evergreen_hpd_init,
2046 .fini = &evergreen_hpd_fini,
2047 .sense = &evergreen_hpd_sense,
2048 .set_polarity = &evergreen_hpd_set_polarity,
2049 },
2050 .pm = {
2051 .misc = &evergreen_pm_misc,
2052 .prepare = &evergreen_pm_prepare,
2053 .finish = &evergreen_pm_finish,
2054 .init_profile = &sumo_pm_init_profile,
2055 .get_dynpm_state = &r600_pm_get_dynpm_state,
2056 .get_engine_clock = &radeon_atom_get_engine_clock,
2057 .set_engine_clock = &radeon_atom_set_engine_clock,
2058 .get_memory_clock = &radeon_atom_get_memory_clock,
2059 .set_memory_clock = &radeon_atom_set_memory_clock,
2060 .get_pcie_lanes = NULL,
2061 .set_pcie_lanes = NULL,
2062 .set_clock_gating = NULL,
2063 .set_uvd_clocks = &cik_set_uvd_clocks,
2064 .get_temperature = &ci_get_temp,
2065 },
2066 .dpm = {
2067 .init = &ci_dpm_init,
2068 .setup_asic = &ci_dpm_setup_asic,
2069 .enable = &ci_dpm_enable,
2070 .late_enable = &ci_dpm_late_enable,
2071 .disable = &ci_dpm_disable,
2072 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2073 .set_power_state = &ci_dpm_set_power_state,
2074 .post_set_power_state = &ci_dpm_post_set_power_state,
2075 .display_configuration_changed = &ci_dpm_display_configuration_changed,
2076 .fini = &ci_dpm_fini,
2077 .get_sclk = &ci_dpm_get_sclk,
2078 .get_mclk = &ci_dpm_get_mclk,
2079 .print_power_state = &ci_dpm_print_power_state,
2080 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
2081 .force_performance_level = &ci_dpm_force_performance_level,
2082 .vblank_too_short = &ci_dpm_vblank_too_short,
2083 .powergate_uvd = &ci_dpm_powergate_uvd,
2084 },
2085 .pflip = {
2086 .pre_page_flip = &evergreen_pre_page_flip,
2087 .page_flip = &evergreen_page_flip,
2088 .post_page_flip = &evergreen_post_page_flip,
2089 },
2090};
2091
2092static struct radeon_asic kv_asic = {
2093 .init = &cik_init,
2094 .fini = &cik_fini,
2095 .suspend = &cik_suspend,
2096 .resume = &cik_resume,
2097 .asic_reset = &cik_asic_reset,
2098 .vga_set_state = &r600_vga_set_state,
2099 .ioctl_wait_idle = NULL,
2100 .gui_idle = &r600_gui_idle,
2101 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2102 .get_xclk = &cik_get_xclk,
2103 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2104 .gart = {
2105 .tlb_flush = &cik_pcie_gart_tlb_flush,
2106 .set_page = &rs600_gart_set_page,
2107 },
2108 .vm = {
2109 .init = &cik_vm_init,
2110 .fini = &cik_vm_fini,
2111 .set_page = &cik_sdma_vm_set_page,
2112 },
2113 .ring = {
2114 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2115 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2116 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2117 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2118 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2119 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2120 },
2121 .irq = {
2122 .set = &cik_irq_set,
2123 .process = &cik_irq_process,
2124 },
2125 .display = {
2126 .bandwidth_update = &dce8_bandwidth_update,
2127 .get_vblank_counter = &evergreen_get_vblank_counter,
2128 .wait_for_vblank = &dce4_wait_for_vblank,
2129 .set_backlight_level = &atombios_set_backlight_level,
2130 .get_backlight_level = &atombios_get_backlight_level,
2131 .hdmi_enable = &evergreen_hdmi_enable,
2132 .hdmi_setmode = &evergreen_hdmi_setmode,
2133 },
2134 .copy = {
2135 .blit = NULL,
2136 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2137 .dma = &cik_copy_dma,
2138 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2139 .copy = &cik_copy_dma,
2140 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2141 },
2142 .surface = {
2143 .set_reg = r600_set_surface_reg,
2144 .clear_reg = r600_clear_surface_reg,
2145 },
2146 .hpd = {
2147 .init = &evergreen_hpd_init,
2148 .fini = &evergreen_hpd_fini,
2149 .sense = &evergreen_hpd_sense,
2150 .set_polarity = &evergreen_hpd_set_polarity,
2151 },
2152 .pm = {
2153 .misc = &evergreen_pm_misc,
2154 .prepare = &evergreen_pm_prepare,
2155 .finish = &evergreen_pm_finish,
2156 .init_profile = &sumo_pm_init_profile,
2157 .get_dynpm_state = &r600_pm_get_dynpm_state,
2158 .get_engine_clock = &radeon_atom_get_engine_clock,
2159 .set_engine_clock = &radeon_atom_set_engine_clock,
2160 .get_memory_clock = &radeon_atom_get_memory_clock,
2161 .set_memory_clock = &radeon_atom_set_memory_clock,
2162 .get_pcie_lanes = NULL,
2163 .set_pcie_lanes = NULL,
2164 .set_clock_gating = NULL,
2165 .set_uvd_clocks = &cik_set_uvd_clocks,
2166 .get_temperature = &kv_get_temp,
2167 },
2168 .dpm = {
2169 .init = &kv_dpm_init,
2170 .setup_asic = &kv_dpm_setup_asic,
2171 .enable = &kv_dpm_enable,
2172 .late_enable = &kv_dpm_late_enable,
2173 .disable = &kv_dpm_disable,
2174 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2175 .set_power_state = &kv_dpm_set_power_state,
2176 .post_set_power_state = &kv_dpm_post_set_power_state,
2177 .display_configuration_changed = &kv_dpm_display_configuration_changed,
2178 .fini = &kv_dpm_fini,
2179 .get_sclk = &kv_dpm_get_sclk,
2180 .get_mclk = &kv_dpm_get_mclk,
2181 .print_power_state = &kv_dpm_print_power_state,
2182 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2183 .force_performance_level = &kv_dpm_force_performance_level,
2184 .powergate_uvd = &kv_dpm_powergate_uvd,
2185 .enable_bapm = &kv_dpm_enable_bapm,
2186 },
2187 .pflip = {
2188 .pre_page_flip = &evergreen_pre_page_flip,
2189 .page_flip = &evergreen_page_flip,
2190 .post_page_flip = &evergreen_post_page_flip,
2191 },
2192};
2193
2194/**
2195 * radeon_asic_init - register asic specific callbacks
2196 *
2197 * @rdev: radeon device pointer
2198 *
2199 * Registers the appropriate asic specific callbacks for each
2200 * chip family. Also sets other asics specific info like the number
2201 * of crtcs and the register aperture accessors (all asics).
2202 * Returns 0 for success.
2203 */
2204int radeon_asic_init(struct radeon_device *rdev)
2205{
2206 radeon_register_accessor_init(rdev);
2207
2208 /* set the number of crtcs */
2209 if (rdev->flags & RADEON_SINGLE_CRTC)
2210 rdev->num_crtc = 1;
2211 else
2212 rdev->num_crtc = 2;
2213
2214 rdev->has_uvd = false;
2215
2216 switch (rdev->family) {
2217 case CHIP_R100:
2218 case CHIP_RV100:
2219 case CHIP_RS100:
2220 case CHIP_RV200:
2221 case CHIP_RS200:
2222 rdev->asic = &r100_asic;
2223 break;
2224 case CHIP_R200:
2225 case CHIP_RV250:
2226 case CHIP_RS300:
2227 case CHIP_RV280:
2228 rdev->asic = &r200_asic;
2229 break;
2230 case CHIP_R300:
2231 case CHIP_R350:
2232 case CHIP_RV350:
2233 case CHIP_RV380:
2234 if (rdev->flags & RADEON_IS_PCIE)
2235 rdev->asic = &r300_asic_pcie;
2236 else
2237 rdev->asic = &r300_asic;
2238 break;
2239 case CHIP_R420:
2240 case CHIP_R423:
2241 case CHIP_RV410:
2242 rdev->asic = &r420_asic;
2243 /* handle macs */
2244 if (rdev->bios == NULL) {
2245 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2246 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2247 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2248 rdev->asic->pm.set_memory_clock = NULL;
2249 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2250 }
2251 break;
2252 case CHIP_RS400:
2253 case CHIP_RS480:
2254 rdev->asic = &rs400_asic;
2255 break;
2256 case CHIP_RS600:
2257 rdev->asic = &rs600_asic;
2258 break;
2259 case CHIP_RS690:
2260 case CHIP_RS740:
2261 rdev->asic = &rs690_asic;
2262 break;
2263 case CHIP_RV515:
2264 rdev->asic = &rv515_asic;
2265 break;
2266 case CHIP_R520:
2267 case CHIP_RV530:
2268 case CHIP_RV560:
2269 case CHIP_RV570:
2270 case CHIP_R580:
2271 rdev->asic = &r520_asic;
2272 break;
2273 case CHIP_R600:
2274 rdev->asic = &r600_asic;
2275 break;
2276 case CHIP_RV610:
2277 case CHIP_RV630:
2278 case CHIP_RV620:
2279 case CHIP_RV635:
2280 case CHIP_RV670:
2281 rdev->asic = &rv6xx_asic;
2282 rdev->has_uvd = true;
2283 break;
2284 case CHIP_RS780:
2285 case CHIP_RS880:
2286 rdev->asic = &rs780_asic;
2287 rdev->has_uvd = true;
2288 break;
2289 case CHIP_RV770:
2290 case CHIP_RV730:
2291 case CHIP_RV710:
2292 case CHIP_RV740:
2293 rdev->asic = &rv770_asic;
2294 rdev->has_uvd = true;
2295 break;
2296 case CHIP_CEDAR:
2297 case CHIP_REDWOOD:
2298 case CHIP_JUNIPER:
2299 case CHIP_CYPRESS:
2300 case CHIP_HEMLOCK:
2301 /* set num crtcs */
2302 if (rdev->family == CHIP_CEDAR)
2303 rdev->num_crtc = 4;
2304 else
2305 rdev->num_crtc = 6;
2306 rdev->asic = &evergreen_asic;
2307 rdev->has_uvd = true;
2308 break;
2309 case CHIP_PALM:
2310 case CHIP_SUMO:
2311 case CHIP_SUMO2:
2312 rdev->asic = &sumo_asic;
2313 rdev->has_uvd = true;
2314 break;
2315 case CHIP_BARTS:
2316 case CHIP_TURKS:
2317 case CHIP_CAICOS:
2318 /* set num crtcs */
2319 if (rdev->family == CHIP_CAICOS)
2320 rdev->num_crtc = 4;
2321 else
2322 rdev->num_crtc = 6;
2323 rdev->asic = &btc_asic;
2324 rdev->has_uvd = true;
2325 break;
2326 case CHIP_CAYMAN:
2327 rdev->asic = &cayman_asic;
2328 /* set num crtcs */
2329 rdev->num_crtc = 6;
2330 rdev->has_uvd = true;
2331 break;
2332 case CHIP_ARUBA:
2333 rdev->asic = &trinity_asic;
2334 /* set num crtcs */
2335 rdev->num_crtc = 4;
2336 rdev->has_uvd = true;
2337 break;
2338 case CHIP_TAHITI:
2339 case CHIP_PITCAIRN:
2340 case CHIP_VERDE:
2341 case CHIP_OLAND:
2342 case CHIP_HAINAN:
2343 rdev->asic = &si_asic;
2344 /* set num crtcs */
2345 if (rdev->family == CHIP_HAINAN)
2346 rdev->num_crtc = 0;
2347 else if (rdev->family == CHIP_OLAND)
2348 rdev->num_crtc = 2;
2349 else
2350 rdev->num_crtc = 6;
2351 if (rdev->family == CHIP_HAINAN)
2352 rdev->has_uvd = false;
2353 else
2354 rdev->has_uvd = true;
2355 switch (rdev->family) {
2356 case CHIP_TAHITI:
2357 rdev->cg_flags =
2358 RADEON_CG_SUPPORT_GFX_MGCG |
2359 RADEON_CG_SUPPORT_GFX_MGLS |
2360 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2361 RADEON_CG_SUPPORT_GFX_CGLS |
2362 RADEON_CG_SUPPORT_GFX_CGTS |
2363 RADEON_CG_SUPPORT_GFX_CP_LS |
2364 RADEON_CG_SUPPORT_MC_MGCG |
2365 RADEON_CG_SUPPORT_SDMA_MGCG |
2366 RADEON_CG_SUPPORT_BIF_LS |
2367 RADEON_CG_SUPPORT_VCE_MGCG |
2368 RADEON_CG_SUPPORT_UVD_MGCG |
2369 RADEON_CG_SUPPORT_HDP_LS |
2370 RADEON_CG_SUPPORT_HDP_MGCG;
2371 rdev->pg_flags = 0;
2372 break;
2373 case CHIP_PITCAIRN:
2374 rdev->cg_flags =
2375 RADEON_CG_SUPPORT_GFX_MGCG |
2376 RADEON_CG_SUPPORT_GFX_MGLS |
2377 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2378 RADEON_CG_SUPPORT_GFX_CGLS |
2379 RADEON_CG_SUPPORT_GFX_CGTS |
2380 RADEON_CG_SUPPORT_GFX_CP_LS |
2381 RADEON_CG_SUPPORT_GFX_RLC_LS |
2382 RADEON_CG_SUPPORT_MC_LS |
2383 RADEON_CG_SUPPORT_MC_MGCG |
2384 RADEON_CG_SUPPORT_SDMA_MGCG |
2385 RADEON_CG_SUPPORT_BIF_LS |
2386 RADEON_CG_SUPPORT_VCE_MGCG |
2387 RADEON_CG_SUPPORT_UVD_MGCG |
2388 RADEON_CG_SUPPORT_HDP_LS |
2389 RADEON_CG_SUPPORT_HDP_MGCG;
2390 rdev->pg_flags = 0;
2391 break;
2392 case CHIP_VERDE:
2393 rdev->cg_flags =
2394 RADEON_CG_SUPPORT_GFX_MGCG |
2395 RADEON_CG_SUPPORT_GFX_MGLS |
2396 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2397 RADEON_CG_SUPPORT_GFX_CGLS |
2398 RADEON_CG_SUPPORT_GFX_CGTS |
2399 RADEON_CG_SUPPORT_GFX_CP_LS |
2400 RADEON_CG_SUPPORT_GFX_RLC_LS |
2401 RADEON_CG_SUPPORT_MC_LS |
2402 RADEON_CG_SUPPORT_MC_MGCG |
2403 RADEON_CG_SUPPORT_SDMA_MGCG |
2404 RADEON_CG_SUPPORT_BIF_LS |
2405 RADEON_CG_SUPPORT_VCE_MGCG |
2406 RADEON_CG_SUPPORT_UVD_MGCG |
2407 RADEON_CG_SUPPORT_HDP_LS |
2408 RADEON_CG_SUPPORT_HDP_MGCG;
2409 rdev->pg_flags = 0 |
2410 /*RADEON_PG_SUPPORT_GFX_PG | */
2411 RADEON_PG_SUPPORT_SDMA;
2412 break;
2413 case CHIP_OLAND:
2414 rdev->cg_flags =
2415 RADEON_CG_SUPPORT_GFX_MGCG |
2416 RADEON_CG_SUPPORT_GFX_MGLS |
2417 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2418 RADEON_CG_SUPPORT_GFX_CGLS |
2419 RADEON_CG_SUPPORT_GFX_CGTS |
2420 RADEON_CG_SUPPORT_GFX_CP_LS |
2421 RADEON_CG_SUPPORT_GFX_RLC_LS |
2422 RADEON_CG_SUPPORT_MC_LS |
2423 RADEON_CG_SUPPORT_MC_MGCG |
2424 RADEON_CG_SUPPORT_SDMA_MGCG |
2425 RADEON_CG_SUPPORT_BIF_LS |
2426 RADEON_CG_SUPPORT_UVD_MGCG |
2427 RADEON_CG_SUPPORT_HDP_LS |
2428 RADEON_CG_SUPPORT_HDP_MGCG;
2429 rdev->pg_flags = 0;
2430 break;
2431 case CHIP_HAINAN:
2432 rdev->cg_flags =
2433 RADEON_CG_SUPPORT_GFX_MGCG |
2434 RADEON_CG_SUPPORT_GFX_MGLS |
2435 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2436 RADEON_CG_SUPPORT_GFX_CGLS |
2437 RADEON_CG_SUPPORT_GFX_CGTS |
2438 RADEON_CG_SUPPORT_GFX_CP_LS |
2439 RADEON_CG_SUPPORT_GFX_RLC_LS |
2440 RADEON_CG_SUPPORT_MC_LS |
2441 RADEON_CG_SUPPORT_MC_MGCG |
2442 RADEON_CG_SUPPORT_SDMA_MGCG |
2443 RADEON_CG_SUPPORT_BIF_LS |
2444 RADEON_CG_SUPPORT_HDP_LS |
2445 RADEON_CG_SUPPORT_HDP_MGCG;
2446 rdev->pg_flags = 0;
2447 break;
2448 default:
2449 rdev->cg_flags = 0;
2450 rdev->pg_flags = 0;
2451 break;
2452 }
2453 break;
2454 case CHIP_BONAIRE:
2455 case CHIP_HAWAII:
2456 rdev->asic = &ci_asic;
2457 rdev->num_crtc = 6;
2458 rdev->has_uvd = true;
2459 if (rdev->family == CHIP_BONAIRE) {
2460 rdev->cg_flags =
2461 RADEON_CG_SUPPORT_GFX_MGCG |
2462 RADEON_CG_SUPPORT_GFX_MGLS |
2463 RADEON_CG_SUPPORT_GFX_CGCG |
2464 RADEON_CG_SUPPORT_GFX_CGLS |
2465 RADEON_CG_SUPPORT_GFX_CGTS |
2466 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2467 RADEON_CG_SUPPORT_GFX_CP_LS |
2468 RADEON_CG_SUPPORT_MC_LS |
2469 RADEON_CG_SUPPORT_MC_MGCG |
2470 RADEON_CG_SUPPORT_SDMA_MGCG |
2471 RADEON_CG_SUPPORT_SDMA_LS |
2472 RADEON_CG_SUPPORT_BIF_LS |
2473 RADEON_CG_SUPPORT_VCE_MGCG |
2474 RADEON_CG_SUPPORT_UVD_MGCG |
2475 RADEON_CG_SUPPORT_HDP_LS |
2476 RADEON_CG_SUPPORT_HDP_MGCG;
2477 rdev->pg_flags = 0;
2478 } else {
2479 rdev->cg_flags =
2480 RADEON_CG_SUPPORT_GFX_MGCG |
2481 RADEON_CG_SUPPORT_GFX_MGLS |
2482 RADEON_CG_SUPPORT_GFX_CGCG |
2483 RADEON_CG_SUPPORT_GFX_CGLS |
2484 RADEON_CG_SUPPORT_GFX_CGTS |
2485 RADEON_CG_SUPPORT_GFX_CP_LS |
2486 RADEON_CG_SUPPORT_MC_LS |
2487 RADEON_CG_SUPPORT_MC_MGCG |
2488 RADEON_CG_SUPPORT_SDMA_MGCG |
2489 RADEON_CG_SUPPORT_SDMA_LS |
2490 RADEON_CG_SUPPORT_BIF_LS |
2491 RADEON_CG_SUPPORT_VCE_MGCG |
2492 RADEON_CG_SUPPORT_UVD_MGCG |
2493 RADEON_CG_SUPPORT_HDP_LS |
2494 RADEON_CG_SUPPORT_HDP_MGCG;
2495 rdev->pg_flags = 0;
2496 }
2497 break;
2498 case CHIP_KAVERI:
2499 case CHIP_KABINI:
2500 rdev->asic = &kv_asic;
2501 /* set num crtcs */
2502 if (rdev->family == CHIP_KAVERI) {
2503 rdev->num_crtc = 4;
2504 rdev->cg_flags =
2505 RADEON_CG_SUPPORT_GFX_MGCG |
2506 RADEON_CG_SUPPORT_GFX_MGLS |
2507 RADEON_CG_SUPPORT_GFX_CGCG |
2508 RADEON_CG_SUPPORT_GFX_CGLS |
2509 RADEON_CG_SUPPORT_GFX_CGTS |
2510 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2511 RADEON_CG_SUPPORT_GFX_CP_LS |
2512 RADEON_CG_SUPPORT_SDMA_MGCG |
2513 RADEON_CG_SUPPORT_SDMA_LS |
2514 RADEON_CG_SUPPORT_BIF_LS |
2515 RADEON_CG_SUPPORT_VCE_MGCG |
2516 RADEON_CG_SUPPORT_UVD_MGCG |
2517 RADEON_CG_SUPPORT_HDP_LS |
2518 RADEON_CG_SUPPORT_HDP_MGCG;
2519 rdev->pg_flags = 0;
2520 /*RADEON_PG_SUPPORT_GFX_PG |
2521 RADEON_PG_SUPPORT_GFX_SMG |
2522 RADEON_PG_SUPPORT_GFX_DMG |
2523 RADEON_PG_SUPPORT_UVD |
2524 RADEON_PG_SUPPORT_VCE |
2525 RADEON_PG_SUPPORT_CP |
2526 RADEON_PG_SUPPORT_GDS |
2527 RADEON_PG_SUPPORT_RLC_SMU_HS |
2528 RADEON_PG_SUPPORT_ACP |
2529 RADEON_PG_SUPPORT_SAMU;*/
2530 } else {
2531 rdev->num_crtc = 2;
2532 rdev->cg_flags =
2533 RADEON_CG_SUPPORT_GFX_MGCG |
2534 RADEON_CG_SUPPORT_GFX_MGLS |
2535 RADEON_CG_SUPPORT_GFX_CGCG |
2536 RADEON_CG_SUPPORT_GFX_CGLS |
2537 RADEON_CG_SUPPORT_GFX_CGTS |
2538 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2539 RADEON_CG_SUPPORT_GFX_CP_LS |
2540 RADEON_CG_SUPPORT_SDMA_MGCG |
2541 RADEON_CG_SUPPORT_SDMA_LS |
2542 RADEON_CG_SUPPORT_BIF_LS |
2543 RADEON_CG_SUPPORT_VCE_MGCG |
2544 RADEON_CG_SUPPORT_UVD_MGCG |
2545 RADEON_CG_SUPPORT_HDP_LS |
2546 RADEON_CG_SUPPORT_HDP_MGCG;
2547 rdev->pg_flags = 0;
2548 /*RADEON_PG_SUPPORT_GFX_PG |
2549 RADEON_PG_SUPPORT_GFX_SMG |
2550 RADEON_PG_SUPPORT_UVD |
2551 RADEON_PG_SUPPORT_VCE |
2552 RADEON_PG_SUPPORT_CP |
2553 RADEON_PG_SUPPORT_GDS |
2554 RADEON_PG_SUPPORT_RLC_SMU_HS |
2555 RADEON_PG_SUPPORT_SAMU;*/
2556 }
2557 rdev->has_uvd = true;
2558 break;
2559 default:
2560 /* FIXME: not supported yet */
2561 return -EINVAL;
2562 }
2563
2564 if (rdev->flags & RADEON_IS_IGP) {
2565 rdev->asic->pm.get_memory_clock = NULL;
2566 rdev->asic->pm.set_memory_clock = NULL;
2567 }
2568
2569 return 0;
2570}
2571
Linux kernel - Deliverables
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