| 1 | /* |
| 2 | * Copyright (C) STMicroelectronics SA 2014 |
| 3 | * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> |
| 4 | * Fabien Dessenne <fabien.dessenne@st.com> |
| 5 | * for STMicroelectronics. |
| 6 | * License terms: GNU General Public License (GPL), version 2 |
| 7 | */ |
| 8 | #include <linux/seq_file.h> |
| 9 | |
| 10 | #include <drm/drm_atomic.h> |
| 11 | #include <drm/drm_fb_cma_helper.h> |
| 12 | #include <drm/drm_gem_cma_helper.h> |
| 13 | |
| 14 | #include "sti_compositor.h" |
| 15 | #include "sti_gdp.h" |
| 16 | #include "sti_plane.h" |
| 17 | #include "sti_vtg.h" |
| 18 | |
| 19 | #define ALPHASWITCH BIT(6) |
| 20 | #define ENA_COLOR_FILL BIT(8) |
| 21 | #define BIGNOTLITTLE BIT(23) |
| 22 | #define WAIT_NEXT_VSYNC BIT(31) |
| 23 | |
| 24 | /* GDP color formats */ |
| 25 | #define GDP_RGB565 0x00 |
| 26 | #define GDP_RGB888 0x01 |
| 27 | #define GDP_RGB888_32 0x02 |
| 28 | #define GDP_XBGR8888 (GDP_RGB888_32 | BIGNOTLITTLE | ALPHASWITCH) |
| 29 | #define GDP_ARGB8565 0x04 |
| 30 | #define GDP_ARGB8888 0x05 |
| 31 | #define GDP_ABGR8888 (GDP_ARGB8888 | BIGNOTLITTLE | ALPHASWITCH) |
| 32 | #define GDP_ARGB1555 0x06 |
| 33 | #define GDP_ARGB4444 0x07 |
| 34 | |
| 35 | #define GDP2STR(fmt) { GDP_ ## fmt, #fmt } |
| 36 | |
| 37 | static struct gdp_format_to_str { |
| 38 | int format; |
| 39 | char name[20]; |
| 40 | } gdp_format_to_str[] = { |
| 41 | GDP2STR(RGB565), |
| 42 | GDP2STR(RGB888), |
| 43 | GDP2STR(RGB888_32), |
| 44 | GDP2STR(XBGR8888), |
| 45 | GDP2STR(ARGB8565), |
| 46 | GDP2STR(ARGB8888), |
| 47 | GDP2STR(ABGR8888), |
| 48 | GDP2STR(ARGB1555), |
| 49 | GDP2STR(ARGB4444) |
| 50 | }; |
| 51 | |
| 52 | #define GAM_GDP_CTL_OFFSET 0x00 |
| 53 | #define GAM_GDP_AGC_OFFSET 0x04 |
| 54 | #define GAM_GDP_VPO_OFFSET 0x0C |
| 55 | #define GAM_GDP_VPS_OFFSET 0x10 |
| 56 | #define GAM_GDP_PML_OFFSET 0x14 |
| 57 | #define GAM_GDP_PMP_OFFSET 0x18 |
| 58 | #define GAM_GDP_SIZE_OFFSET 0x1C |
| 59 | #define GAM_GDP_NVN_OFFSET 0x24 |
| 60 | #define GAM_GDP_KEY1_OFFSET 0x28 |
| 61 | #define GAM_GDP_KEY2_OFFSET 0x2C |
| 62 | #define GAM_GDP_PPT_OFFSET 0x34 |
| 63 | #define GAM_GDP_CML_OFFSET 0x3C |
| 64 | #define GAM_GDP_MST_OFFSET 0x68 |
| 65 | |
| 66 | #define GAM_GDP_ALPHARANGE_255 BIT(5) |
| 67 | #define GAM_GDP_AGC_FULL_RANGE 0x00808080 |
| 68 | #define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0)) |
| 69 | #define GAM_GDP_SIZE_MAX 0x7FF |
| 70 | |
| 71 | #define GDP_NODE_NB_BANK 2 |
| 72 | #define GDP_NODE_PER_FIELD 2 |
| 73 | |
| 74 | struct sti_gdp_node { |
| 75 | u32 gam_gdp_ctl; |
| 76 | u32 gam_gdp_agc; |
| 77 | u32 reserved1; |
| 78 | u32 gam_gdp_vpo; |
| 79 | u32 gam_gdp_vps; |
| 80 | u32 gam_gdp_pml; |
| 81 | u32 gam_gdp_pmp; |
| 82 | u32 gam_gdp_size; |
| 83 | u32 reserved2; |
| 84 | u32 gam_gdp_nvn; |
| 85 | u32 gam_gdp_key1; |
| 86 | u32 gam_gdp_key2; |
| 87 | u32 reserved3; |
| 88 | u32 gam_gdp_ppt; |
| 89 | u32 reserved4; |
| 90 | u32 gam_gdp_cml; |
| 91 | }; |
| 92 | |
| 93 | struct sti_gdp_node_list { |
| 94 | struct sti_gdp_node *top_field; |
| 95 | dma_addr_t top_field_paddr; |
| 96 | struct sti_gdp_node *btm_field; |
| 97 | dma_addr_t btm_field_paddr; |
| 98 | }; |
| 99 | |
| 100 | /** |
| 101 | * STI GDP structure |
| 102 | * |
| 103 | * @sti_plane: sti_plane structure |
| 104 | * @dev: driver device |
| 105 | * @regs: gdp registers |
| 106 | * @clk_pix: pixel clock for the current gdp |
| 107 | * @clk_main_parent: gdp parent clock if main path used |
| 108 | * @clk_aux_parent: gdp parent clock if aux path used |
| 109 | * @vtg_field_nb: callback for VTG FIELD (top or bottom) notification |
| 110 | * @is_curr_top: true if the current node processed is the top field |
| 111 | * @node_list: array of node list |
| 112 | * @vtg: registered vtg |
| 113 | */ |
| 114 | struct sti_gdp { |
| 115 | struct sti_plane plane; |
| 116 | struct device *dev; |
| 117 | void __iomem *regs; |
| 118 | struct clk *clk_pix; |
| 119 | struct clk *clk_main_parent; |
| 120 | struct clk *clk_aux_parent; |
| 121 | struct notifier_block vtg_field_nb; |
| 122 | bool is_curr_top; |
| 123 | struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK]; |
| 124 | struct sti_vtg *vtg; |
| 125 | }; |
| 126 | |
| 127 | #define to_sti_gdp(x) container_of(x, struct sti_gdp, plane) |
| 128 | |
| 129 | static const uint32_t gdp_supported_formats[] = { |
| 130 | DRM_FORMAT_XRGB8888, |
| 131 | DRM_FORMAT_XBGR8888, |
| 132 | DRM_FORMAT_ARGB8888, |
| 133 | DRM_FORMAT_ABGR8888, |
| 134 | DRM_FORMAT_ARGB4444, |
| 135 | DRM_FORMAT_ARGB1555, |
| 136 | DRM_FORMAT_RGB565, |
| 137 | DRM_FORMAT_RGB888, |
| 138 | }; |
| 139 | |
| 140 | #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ |
| 141 | readl(gdp->regs + reg ## _OFFSET)) |
| 142 | |
| 143 | static void gdp_dbg_ctl(struct seq_file *s, int val) |
| 144 | { |
| 145 | int i; |
| 146 | |
| 147 | seq_puts(s, "\tColor:"); |
| 148 | for (i = 0; i < ARRAY_SIZE(gdp_format_to_str); i++) { |
| 149 | if (gdp_format_to_str[i].format == (val & 0x1F)) { |
| 150 | seq_printf(s, gdp_format_to_str[i].name); |
| 151 | break; |
| 152 | } |
| 153 | } |
| 154 | if (i == ARRAY_SIZE(gdp_format_to_str)) |
| 155 | seq_puts(s, "<UNKNOWN>"); |
| 156 | |
| 157 | seq_printf(s, "\tWaitNextVsync:%d", val & WAIT_NEXT_VSYNC ? 1 : 0); |
| 158 | } |
| 159 | |
| 160 | static void gdp_dbg_vpo(struct seq_file *s, int val) |
| 161 | { |
| 162 | seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF); |
| 163 | } |
| 164 | |
| 165 | static void gdp_dbg_vps(struct seq_file *s, int val) |
| 166 | { |
| 167 | seq_printf(s, "\txds:%4d\tyds:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF); |
| 168 | } |
| 169 | |
| 170 | static void gdp_dbg_size(struct seq_file *s, int val) |
| 171 | { |
| 172 | seq_printf(s, "\t%d x %d", val & 0xFFFF, (val >> 16) & 0xFFFF); |
| 173 | } |
| 174 | |
| 175 | static void gdp_dbg_nvn(struct seq_file *s, struct sti_gdp *gdp, int val) |
| 176 | { |
| 177 | void *base = NULL; |
| 178 | unsigned int i; |
| 179 | |
| 180 | for (i = 0; i < GDP_NODE_NB_BANK; i++) { |
| 181 | if (gdp->node_list[i].top_field_paddr == val) { |
| 182 | base = gdp->node_list[i].top_field; |
| 183 | break; |
| 184 | } |
| 185 | if (gdp->node_list[i].btm_field_paddr == val) { |
| 186 | base = gdp->node_list[i].btm_field; |
| 187 | break; |
| 188 | } |
| 189 | } |
| 190 | |
| 191 | if (base) |
| 192 | seq_printf(s, "\tVirt @: %p", base); |
| 193 | } |
| 194 | |
| 195 | static void gdp_dbg_ppt(struct seq_file *s, int val) |
| 196 | { |
| 197 | if (val & GAM_GDP_PPT_IGNORE) |
| 198 | seq_puts(s, "\tNot displayed on mixer!"); |
| 199 | } |
| 200 | |
| 201 | static void gdp_dbg_mst(struct seq_file *s, int val) |
| 202 | { |
| 203 | if (val & 1) |
| 204 | seq_puts(s, "\tBUFFER UNDERFLOW!"); |
| 205 | } |
| 206 | |
| 207 | static int gdp_dbg_show(struct seq_file *s, void *data) |
| 208 | { |
| 209 | struct drm_info_node *node = s->private; |
| 210 | struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data; |
| 211 | struct drm_plane *drm_plane = &gdp->plane.drm_plane; |
| 212 | struct drm_crtc *crtc = drm_plane->crtc; |
| 213 | |
| 214 | seq_printf(s, "%s: (vaddr = 0x%p)", |
| 215 | sti_plane_to_str(&gdp->plane), gdp->regs); |
| 216 | |
| 217 | DBGFS_DUMP(GAM_GDP_CTL); |
| 218 | gdp_dbg_ctl(s, readl(gdp->regs + GAM_GDP_CTL_OFFSET)); |
| 219 | DBGFS_DUMP(GAM_GDP_AGC); |
| 220 | DBGFS_DUMP(GAM_GDP_VPO); |
| 221 | gdp_dbg_vpo(s, readl(gdp->regs + GAM_GDP_VPO_OFFSET)); |
| 222 | DBGFS_DUMP(GAM_GDP_VPS); |
| 223 | gdp_dbg_vps(s, readl(gdp->regs + GAM_GDP_VPS_OFFSET)); |
| 224 | DBGFS_DUMP(GAM_GDP_PML); |
| 225 | DBGFS_DUMP(GAM_GDP_PMP); |
| 226 | DBGFS_DUMP(GAM_GDP_SIZE); |
| 227 | gdp_dbg_size(s, readl(gdp->regs + GAM_GDP_SIZE_OFFSET)); |
| 228 | DBGFS_DUMP(GAM_GDP_NVN); |
| 229 | gdp_dbg_nvn(s, gdp, readl(gdp->regs + GAM_GDP_NVN_OFFSET)); |
| 230 | DBGFS_DUMP(GAM_GDP_KEY1); |
| 231 | DBGFS_DUMP(GAM_GDP_KEY2); |
| 232 | DBGFS_DUMP(GAM_GDP_PPT); |
| 233 | gdp_dbg_ppt(s, readl(gdp->regs + GAM_GDP_PPT_OFFSET)); |
| 234 | DBGFS_DUMP(GAM_GDP_CML); |
| 235 | DBGFS_DUMP(GAM_GDP_MST); |
| 236 | gdp_dbg_mst(s, readl(gdp->regs + GAM_GDP_MST_OFFSET)); |
| 237 | |
| 238 | seq_puts(s, "\n\n"); |
| 239 | if (!crtc) |
| 240 | seq_puts(s, " Not connected to any DRM CRTC\n"); |
| 241 | else |
| 242 | seq_printf(s, " Connected to DRM CRTC #%d (%s)\n", |
| 243 | crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc))); |
| 244 | |
| 245 | return 0; |
| 246 | } |
| 247 | |
| 248 | static void gdp_node_dump_node(struct seq_file *s, struct sti_gdp_node *node) |
| 249 | { |
| 250 | seq_printf(s, "\t@:0x%p", node); |
| 251 | seq_printf(s, "\n\tCTL 0x%08X", node->gam_gdp_ctl); |
| 252 | gdp_dbg_ctl(s, node->gam_gdp_ctl); |
| 253 | seq_printf(s, "\n\tAGC 0x%08X", node->gam_gdp_agc); |
| 254 | seq_printf(s, "\n\tVPO 0x%08X", node->gam_gdp_vpo); |
| 255 | gdp_dbg_vpo(s, node->gam_gdp_vpo); |
| 256 | seq_printf(s, "\n\tVPS 0x%08X", node->gam_gdp_vps); |
| 257 | gdp_dbg_vps(s, node->gam_gdp_vps); |
| 258 | seq_printf(s, "\n\tPML 0x%08X", node->gam_gdp_pml); |
| 259 | seq_printf(s, "\n\tPMP 0x%08X", node->gam_gdp_pmp); |
| 260 | seq_printf(s, "\n\tSIZE 0x%08X", node->gam_gdp_size); |
| 261 | gdp_dbg_size(s, node->gam_gdp_size); |
| 262 | seq_printf(s, "\n\tNVN 0x%08X", node->gam_gdp_nvn); |
| 263 | seq_printf(s, "\n\tKEY1 0x%08X", node->gam_gdp_key1); |
| 264 | seq_printf(s, "\n\tKEY2 0x%08X", node->gam_gdp_key2); |
| 265 | seq_printf(s, "\n\tPPT 0x%08X", node->gam_gdp_ppt); |
| 266 | gdp_dbg_ppt(s, node->gam_gdp_ppt); |
| 267 | seq_printf(s, "\n\tCML 0x%08X", node->gam_gdp_cml); |
| 268 | seq_puts(s, "\n"); |
| 269 | } |
| 270 | |
| 271 | static int gdp_node_dbg_show(struct seq_file *s, void *arg) |
| 272 | { |
| 273 | struct drm_info_node *node = s->private; |
| 274 | struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data; |
| 275 | unsigned int b; |
| 276 | |
| 277 | for (b = 0; b < GDP_NODE_NB_BANK; b++) { |
| 278 | seq_printf(s, "\n%s[%d].top", sti_plane_to_str(&gdp->plane), b); |
| 279 | gdp_node_dump_node(s, gdp->node_list[b].top_field); |
| 280 | seq_printf(s, "\n%s[%d].btm", sti_plane_to_str(&gdp->plane), b); |
| 281 | gdp_node_dump_node(s, gdp->node_list[b].btm_field); |
| 282 | } |
| 283 | |
| 284 | return 0; |
| 285 | } |
| 286 | |
| 287 | static struct drm_info_list gdp0_debugfs_files[] = { |
| 288 | { "gdp0", gdp_dbg_show, 0, NULL }, |
| 289 | { "gdp0_node", gdp_node_dbg_show, 0, NULL }, |
| 290 | }; |
| 291 | |
| 292 | static struct drm_info_list gdp1_debugfs_files[] = { |
| 293 | { "gdp1", gdp_dbg_show, 0, NULL }, |
| 294 | { "gdp1_node", gdp_node_dbg_show, 0, NULL }, |
| 295 | }; |
| 296 | |
| 297 | static struct drm_info_list gdp2_debugfs_files[] = { |
| 298 | { "gdp2", gdp_dbg_show, 0, NULL }, |
| 299 | { "gdp2_node", gdp_node_dbg_show, 0, NULL }, |
| 300 | }; |
| 301 | |
| 302 | static struct drm_info_list gdp3_debugfs_files[] = { |
| 303 | { "gdp3", gdp_dbg_show, 0, NULL }, |
| 304 | { "gdp3_node", gdp_node_dbg_show, 0, NULL }, |
| 305 | }; |
| 306 | |
| 307 | static int gdp_debugfs_init(struct sti_gdp *gdp, struct drm_minor *minor) |
| 308 | { |
| 309 | unsigned int i; |
| 310 | struct drm_info_list *gdp_debugfs_files; |
| 311 | int nb_files; |
| 312 | |
| 313 | switch (gdp->plane.desc) { |
| 314 | case STI_GDP_0: |
| 315 | gdp_debugfs_files = gdp0_debugfs_files; |
| 316 | nb_files = ARRAY_SIZE(gdp0_debugfs_files); |
| 317 | break; |
| 318 | case STI_GDP_1: |
| 319 | gdp_debugfs_files = gdp1_debugfs_files; |
| 320 | nb_files = ARRAY_SIZE(gdp1_debugfs_files); |
| 321 | break; |
| 322 | case STI_GDP_2: |
| 323 | gdp_debugfs_files = gdp2_debugfs_files; |
| 324 | nb_files = ARRAY_SIZE(gdp2_debugfs_files); |
| 325 | break; |
| 326 | case STI_GDP_3: |
| 327 | gdp_debugfs_files = gdp3_debugfs_files; |
| 328 | nb_files = ARRAY_SIZE(gdp3_debugfs_files); |
| 329 | break; |
| 330 | default: |
| 331 | return -EINVAL; |
| 332 | } |
| 333 | |
| 334 | for (i = 0; i < nb_files; i++) |
| 335 | gdp_debugfs_files[i].data = gdp; |
| 336 | |
| 337 | return drm_debugfs_create_files(gdp_debugfs_files, |
| 338 | nb_files, |
| 339 | minor->debugfs_root, minor); |
| 340 | } |
| 341 | |
| 342 | static int sti_gdp_fourcc2format(int fourcc) |
| 343 | { |
| 344 | switch (fourcc) { |
| 345 | case DRM_FORMAT_XRGB8888: |
| 346 | return GDP_RGB888_32; |
| 347 | case DRM_FORMAT_XBGR8888: |
| 348 | return GDP_XBGR8888; |
| 349 | case DRM_FORMAT_ARGB8888: |
| 350 | return GDP_ARGB8888; |
| 351 | case DRM_FORMAT_ABGR8888: |
| 352 | return GDP_ABGR8888; |
| 353 | case DRM_FORMAT_ARGB4444: |
| 354 | return GDP_ARGB4444; |
| 355 | case DRM_FORMAT_ARGB1555: |
| 356 | return GDP_ARGB1555; |
| 357 | case DRM_FORMAT_RGB565: |
| 358 | return GDP_RGB565; |
| 359 | case DRM_FORMAT_RGB888: |
| 360 | return GDP_RGB888; |
| 361 | } |
| 362 | return -1; |
| 363 | } |
| 364 | |
| 365 | static int sti_gdp_get_alpharange(int format) |
| 366 | { |
| 367 | switch (format) { |
| 368 | case GDP_ARGB8565: |
| 369 | case GDP_ARGB8888: |
| 370 | case GDP_ABGR8888: |
| 371 | return GAM_GDP_ALPHARANGE_255; |
| 372 | } |
| 373 | return 0; |
| 374 | } |
| 375 | |
| 376 | /** |
| 377 | * sti_gdp_get_free_nodes |
| 378 | * @gdp: gdp pointer |
| 379 | * |
| 380 | * Look for a GDP node list that is not currently read by the HW. |
| 381 | * |
| 382 | * RETURNS: |
| 383 | * Pointer to the free GDP node list |
| 384 | */ |
| 385 | static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_gdp *gdp) |
| 386 | { |
| 387 | int hw_nvn; |
| 388 | unsigned int i; |
| 389 | |
| 390 | hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); |
| 391 | if (!hw_nvn) |
| 392 | goto end; |
| 393 | |
| 394 | for (i = 0; i < GDP_NODE_NB_BANK; i++) |
| 395 | if ((hw_nvn != gdp->node_list[i].btm_field_paddr) && |
| 396 | (hw_nvn != gdp->node_list[i].top_field_paddr)) |
| 397 | return &gdp->node_list[i]; |
| 398 | |
| 399 | /* in hazardious cases restart with the first node */ |
| 400 | DRM_ERROR("inconsistent NVN for %s: 0x%08X\n", |
| 401 | sti_plane_to_str(&gdp->plane), hw_nvn); |
| 402 | |
| 403 | end: |
| 404 | return &gdp->node_list[0]; |
| 405 | } |
| 406 | |
| 407 | /** |
| 408 | * sti_gdp_get_current_nodes |
| 409 | * @gdp: gdp pointer |
| 410 | * |
| 411 | * Look for GDP nodes that are currently read by the HW. |
| 412 | * |
| 413 | * RETURNS: |
| 414 | * Pointer to the current GDP node list |
| 415 | */ |
| 416 | static |
| 417 | struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_gdp *gdp) |
| 418 | { |
| 419 | int hw_nvn; |
| 420 | unsigned int i; |
| 421 | |
| 422 | hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); |
| 423 | if (!hw_nvn) |
| 424 | goto end; |
| 425 | |
| 426 | for (i = 0; i < GDP_NODE_NB_BANK; i++) |
| 427 | if ((hw_nvn == gdp->node_list[i].btm_field_paddr) || |
| 428 | (hw_nvn == gdp->node_list[i].top_field_paddr)) |
| 429 | return &gdp->node_list[i]; |
| 430 | |
| 431 | end: |
| 432 | DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n", |
| 433 | hw_nvn, sti_plane_to_str(&gdp->plane)); |
| 434 | |
| 435 | return NULL; |
| 436 | } |
| 437 | |
| 438 | /** |
| 439 | * sti_gdp_disable |
| 440 | * @gdp: gdp pointer |
| 441 | * |
| 442 | * Disable a GDP. |
| 443 | */ |
| 444 | static void sti_gdp_disable(struct sti_gdp *gdp) |
| 445 | { |
| 446 | unsigned int i; |
| 447 | |
| 448 | DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&gdp->plane)); |
| 449 | |
| 450 | /* Set the nodes as 'to be ignored on mixer' */ |
| 451 | for (i = 0; i < GDP_NODE_NB_BANK; i++) { |
| 452 | gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; |
| 453 | gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; |
| 454 | } |
| 455 | |
| 456 | if (sti_vtg_unregister_client(gdp->vtg, &gdp->vtg_field_nb)) |
| 457 | DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n"); |
| 458 | |
| 459 | if (gdp->clk_pix) |
| 460 | clk_disable_unprepare(gdp->clk_pix); |
| 461 | |
| 462 | gdp->plane.status = STI_PLANE_DISABLED; |
| 463 | } |
| 464 | |
| 465 | /** |
| 466 | * sti_gdp_field_cb |
| 467 | * @nb: notifier block |
| 468 | * @event: event message |
| 469 | * @data: private data |
| 470 | * |
| 471 | * Handle VTG top field and bottom field event. |
| 472 | * |
| 473 | * RETURNS: |
| 474 | * 0 on success. |
| 475 | */ |
| 476 | int sti_gdp_field_cb(struct notifier_block *nb, |
| 477 | unsigned long event, void *data) |
| 478 | { |
| 479 | struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb); |
| 480 | |
| 481 | if (gdp->plane.status == STI_PLANE_FLUSHING) { |
| 482 | /* disable need to be synchronize on vsync event */ |
| 483 | DRM_DEBUG_DRIVER("Vsync event received => disable %s\n", |
| 484 | sti_plane_to_str(&gdp->plane)); |
| 485 | |
| 486 | sti_gdp_disable(gdp); |
| 487 | } |
| 488 | |
| 489 | switch (event) { |
| 490 | case VTG_TOP_FIELD_EVENT: |
| 491 | gdp->is_curr_top = true; |
| 492 | break; |
| 493 | case VTG_BOTTOM_FIELD_EVENT: |
| 494 | gdp->is_curr_top = false; |
| 495 | break; |
| 496 | default: |
| 497 | DRM_ERROR("unsupported event: %lu\n", event); |
| 498 | break; |
| 499 | } |
| 500 | |
| 501 | return 0; |
| 502 | } |
| 503 | |
| 504 | static void sti_gdp_init(struct sti_gdp *gdp) |
| 505 | { |
| 506 | struct device_node *np = gdp->dev->of_node; |
| 507 | dma_addr_t dma_addr; |
| 508 | void *base; |
| 509 | unsigned int i, size; |
| 510 | |
| 511 | /* Allocate all the nodes within a single memory page */ |
| 512 | size = sizeof(struct sti_gdp_node) * |
| 513 | GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK; |
| 514 | base = dma_alloc_wc(gdp->dev, size, &dma_addr, GFP_KERNEL | GFP_DMA); |
| 515 | |
| 516 | if (!base) { |
| 517 | DRM_ERROR("Failed to allocate memory for GDP node\n"); |
| 518 | return; |
| 519 | } |
| 520 | memset(base, 0, size); |
| 521 | |
| 522 | for (i = 0; i < GDP_NODE_NB_BANK; i++) { |
| 523 | if (dma_addr & 0xF) { |
| 524 | DRM_ERROR("Mem alignment failed\n"); |
| 525 | return; |
| 526 | } |
| 527 | gdp->node_list[i].top_field = base; |
| 528 | gdp->node_list[i].top_field_paddr = dma_addr; |
| 529 | |
| 530 | DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base); |
| 531 | base += sizeof(struct sti_gdp_node); |
| 532 | dma_addr += sizeof(struct sti_gdp_node); |
| 533 | |
| 534 | if (dma_addr & 0xF) { |
| 535 | DRM_ERROR("Mem alignment failed\n"); |
| 536 | return; |
| 537 | } |
| 538 | gdp->node_list[i].btm_field = base; |
| 539 | gdp->node_list[i].btm_field_paddr = dma_addr; |
| 540 | DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base); |
| 541 | base += sizeof(struct sti_gdp_node); |
| 542 | dma_addr += sizeof(struct sti_gdp_node); |
| 543 | } |
| 544 | |
| 545 | if (of_device_is_compatible(np, "st,stih407-compositor")) { |
| 546 | /* GDP of STiH407 chip have its own pixel clock */ |
| 547 | char *clk_name; |
| 548 | |
| 549 | switch (gdp->plane.desc) { |
| 550 | case STI_GDP_0: |
| 551 | clk_name = "pix_gdp1"; |
| 552 | break; |
| 553 | case STI_GDP_1: |
| 554 | clk_name = "pix_gdp2"; |
| 555 | break; |
| 556 | case STI_GDP_2: |
| 557 | clk_name = "pix_gdp3"; |
| 558 | break; |
| 559 | case STI_GDP_3: |
| 560 | clk_name = "pix_gdp4"; |
| 561 | break; |
| 562 | default: |
| 563 | DRM_ERROR("GDP id not recognized\n"); |
| 564 | return; |
| 565 | } |
| 566 | |
| 567 | gdp->clk_pix = devm_clk_get(gdp->dev, clk_name); |
| 568 | if (IS_ERR(gdp->clk_pix)) |
| 569 | DRM_ERROR("Cannot get %s clock\n", clk_name); |
| 570 | |
| 571 | gdp->clk_main_parent = devm_clk_get(gdp->dev, "main_parent"); |
| 572 | if (IS_ERR(gdp->clk_main_parent)) |
| 573 | DRM_ERROR("Cannot get main_parent clock\n"); |
| 574 | |
| 575 | gdp->clk_aux_parent = devm_clk_get(gdp->dev, "aux_parent"); |
| 576 | if (IS_ERR(gdp->clk_aux_parent)) |
| 577 | DRM_ERROR("Cannot get aux_parent clock\n"); |
| 578 | } |
| 579 | } |
| 580 | |
| 581 | /** |
| 582 | * sti_gdp_get_dst |
| 583 | * @dev: device |
| 584 | * @dst: requested destination size |
| 585 | * @src: source size |
| 586 | * |
| 587 | * Return the cropped / clamped destination size |
| 588 | * |
| 589 | * RETURNS: |
| 590 | * cropped / clamped destination size |
| 591 | */ |
| 592 | static int sti_gdp_get_dst(struct device *dev, int dst, int src) |
| 593 | { |
| 594 | if (dst == src) |
| 595 | return dst; |
| 596 | |
| 597 | if (dst < src) { |
| 598 | dev_dbg(dev, "WARNING: GDP scale not supported, will crop\n"); |
| 599 | return dst; |
| 600 | } |
| 601 | |
| 602 | dev_dbg(dev, "WARNING: GDP scale not supported, will clamp\n"); |
| 603 | return src; |
| 604 | } |
| 605 | |
| 606 | static int sti_gdp_atomic_check(struct drm_plane *drm_plane, |
| 607 | struct drm_plane_state *state) |
| 608 | { |
| 609 | struct sti_plane *plane = to_sti_plane(drm_plane); |
| 610 | struct sti_gdp *gdp = to_sti_gdp(plane); |
| 611 | struct drm_crtc *crtc = state->crtc; |
| 612 | struct sti_compositor *compo = dev_get_drvdata(gdp->dev); |
| 613 | struct drm_framebuffer *fb = state->fb; |
| 614 | bool first_prepare = plane->status == STI_PLANE_DISABLED ? true : false; |
| 615 | struct drm_crtc_state *crtc_state; |
| 616 | struct sti_mixer *mixer; |
| 617 | struct drm_display_mode *mode; |
| 618 | int dst_x, dst_y, dst_w, dst_h; |
| 619 | int src_x, src_y, src_w, src_h; |
| 620 | int format; |
| 621 | |
| 622 | /* no need for further checks if the plane is being disabled */ |
| 623 | if (!crtc || !fb) |
| 624 | return 0; |
| 625 | |
| 626 | mixer = to_sti_mixer(crtc); |
| 627 | crtc_state = drm_atomic_get_crtc_state(state->state, crtc); |
| 628 | mode = &crtc_state->mode; |
| 629 | dst_x = state->crtc_x; |
| 630 | dst_y = state->crtc_y; |
| 631 | dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x); |
| 632 | dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y); |
| 633 | /* src_x are in 16.16 format */ |
| 634 | src_x = state->src_x >> 16; |
| 635 | src_y = state->src_y >> 16; |
| 636 | src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX); |
| 637 | src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX); |
| 638 | |
| 639 | format = sti_gdp_fourcc2format(fb->pixel_format); |
| 640 | if (format == -1) { |
| 641 | DRM_ERROR("Format not supported by GDP %.4s\n", |
| 642 | (char *)&fb->pixel_format); |
| 643 | return -EINVAL; |
| 644 | } |
| 645 | |
| 646 | if (!drm_fb_cma_get_gem_obj(fb, 0)) { |
| 647 | DRM_ERROR("Can't get CMA GEM object for fb\n"); |
| 648 | return -EINVAL; |
| 649 | } |
| 650 | |
| 651 | if (first_prepare) { |
| 652 | /* Register gdp callback */ |
| 653 | gdp->vtg = mixer->id == STI_MIXER_MAIN ? |
| 654 | compo->vtg_main : compo->vtg_aux; |
| 655 | if (sti_vtg_register_client(gdp->vtg, |
| 656 | &gdp->vtg_field_nb, crtc)) { |
| 657 | DRM_ERROR("Cannot register VTG notifier\n"); |
| 658 | return -EINVAL; |
| 659 | } |
| 660 | |
| 661 | /* Set and enable gdp clock */ |
| 662 | if (gdp->clk_pix) { |
| 663 | struct clk *clkp; |
| 664 | int rate = mode->clock * 1000; |
| 665 | int res; |
| 666 | |
| 667 | /* |
| 668 | * According to the mixer used, the gdp pixel clock |
| 669 | * should have a different parent clock. |
| 670 | */ |
| 671 | if (mixer->id == STI_MIXER_MAIN) |
| 672 | clkp = gdp->clk_main_parent; |
| 673 | else |
| 674 | clkp = gdp->clk_aux_parent; |
| 675 | |
| 676 | if (clkp) |
| 677 | clk_set_parent(gdp->clk_pix, clkp); |
| 678 | |
| 679 | res = clk_set_rate(gdp->clk_pix, rate); |
| 680 | if (res < 0) { |
| 681 | DRM_ERROR("Cannot set rate (%dHz) for gdp\n", |
| 682 | rate); |
| 683 | return -EINVAL; |
| 684 | } |
| 685 | |
| 686 | if (clk_prepare_enable(gdp->clk_pix)) { |
| 687 | DRM_ERROR("Failed to prepare/enable gdp\n"); |
| 688 | return -EINVAL; |
| 689 | } |
| 690 | } |
| 691 | } |
| 692 | |
| 693 | DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n", |
| 694 | crtc->base.id, sti_mixer_to_str(mixer), |
| 695 | drm_plane->base.id, sti_plane_to_str(plane)); |
| 696 | DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n", |
| 697 | sti_plane_to_str(plane), |
| 698 | dst_w, dst_h, dst_x, dst_y, |
| 699 | src_w, src_h, src_x, src_y); |
| 700 | |
| 701 | return 0; |
| 702 | } |
| 703 | |
| 704 | static void sti_gdp_atomic_update(struct drm_plane *drm_plane, |
| 705 | struct drm_plane_state *oldstate) |
| 706 | { |
| 707 | struct drm_plane_state *state = drm_plane->state; |
| 708 | struct sti_plane *plane = to_sti_plane(drm_plane); |
| 709 | struct sti_gdp *gdp = to_sti_gdp(plane); |
| 710 | struct drm_crtc *crtc = state->crtc; |
| 711 | struct drm_framebuffer *fb = state->fb; |
| 712 | struct drm_display_mode *mode; |
| 713 | int dst_x, dst_y, dst_w, dst_h; |
| 714 | int src_x, src_y, src_w, src_h; |
| 715 | struct drm_gem_cma_object *cma_obj; |
| 716 | struct sti_gdp_node_list *list; |
| 717 | struct sti_gdp_node_list *curr_list; |
| 718 | struct sti_gdp_node *top_field, *btm_field; |
| 719 | u32 dma_updated_top; |
| 720 | u32 dma_updated_btm; |
| 721 | int format; |
| 722 | unsigned int depth, bpp; |
| 723 | u32 ydo, xdo, yds, xds; |
| 724 | |
| 725 | if (!crtc || !fb) |
| 726 | return; |
| 727 | |
| 728 | mode = &crtc->mode; |
| 729 | dst_x = state->crtc_x; |
| 730 | dst_y = state->crtc_y; |
| 731 | dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x); |
| 732 | dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y); |
| 733 | /* src_x are in 16.16 format */ |
| 734 | src_x = state->src_x >> 16; |
| 735 | src_y = state->src_y >> 16; |
| 736 | src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX); |
| 737 | src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX); |
| 738 | |
| 739 | list = sti_gdp_get_free_nodes(gdp); |
| 740 | top_field = list->top_field; |
| 741 | btm_field = list->btm_field; |
| 742 | |
| 743 | dev_dbg(gdp->dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__, |
| 744 | sti_plane_to_str(plane), top_field, btm_field); |
| 745 | |
| 746 | /* build the top field */ |
| 747 | top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE; |
| 748 | top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC; |
| 749 | format = sti_gdp_fourcc2format(fb->pixel_format); |
| 750 | top_field->gam_gdp_ctl |= format; |
| 751 | top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format); |
| 752 | top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE; |
| 753 | |
| 754 | cma_obj = drm_fb_cma_get_gem_obj(fb, 0); |
| 755 | |
| 756 | DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id, |
| 757 | (char *)&fb->pixel_format, |
| 758 | (unsigned long)cma_obj->paddr); |
| 759 | |
| 760 | /* pixel memory location */ |
| 761 | drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp); |
| 762 | top_field->gam_gdp_pml = (u32)cma_obj->paddr + fb->offsets[0]; |
| 763 | top_field->gam_gdp_pml += src_x * (bpp >> 3); |
| 764 | top_field->gam_gdp_pml += src_y * fb->pitches[0]; |
| 765 | |
| 766 | /* output parameters (clamped / cropped) */ |
| 767 | dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w); |
| 768 | dst_h = sti_gdp_get_dst(gdp->dev, dst_h, src_h); |
| 769 | ydo = sti_vtg_get_line_number(*mode, dst_y); |
| 770 | yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1); |
| 771 | xdo = sti_vtg_get_pixel_number(*mode, dst_x); |
| 772 | xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1); |
| 773 | top_field->gam_gdp_vpo = (ydo << 16) | xdo; |
| 774 | top_field->gam_gdp_vps = (yds << 16) | xds; |
| 775 | |
| 776 | /* input parameters */ |
| 777 | src_w = dst_w; |
| 778 | top_field->gam_gdp_pmp = fb->pitches[0]; |
| 779 | top_field->gam_gdp_size = src_h << 16 | src_w; |
| 780 | |
| 781 | /* Same content and chained together */ |
| 782 | memcpy(btm_field, top_field, sizeof(*btm_field)); |
| 783 | top_field->gam_gdp_nvn = list->btm_field_paddr; |
| 784 | btm_field->gam_gdp_nvn = list->top_field_paddr; |
| 785 | |
| 786 | /* Interlaced mode */ |
| 787 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 788 | btm_field->gam_gdp_pml = top_field->gam_gdp_pml + |
| 789 | fb->pitches[0]; |
| 790 | |
| 791 | /* Update the NVN field of the 'right' field of the current GDP node |
| 792 | * (being used by the HW) with the address of the updated ('free') top |
| 793 | * field GDP node. |
| 794 | * - In interlaced mode the 'right' field is the bottom field as we |
| 795 | * update frames starting from their top field |
| 796 | * - In progressive mode, we update both bottom and top fields which |
| 797 | * are equal nodes. |
| 798 | * At the next VSYNC, the updated node list will be used by the HW. |
| 799 | */ |
| 800 | curr_list = sti_gdp_get_current_nodes(gdp); |
| 801 | dma_updated_top = list->top_field_paddr; |
| 802 | dma_updated_btm = list->btm_field_paddr; |
| 803 | |
| 804 | dev_dbg(gdp->dev, "Current NVN:0x%X\n", |
| 805 | readl(gdp->regs + GAM_GDP_NVN_OFFSET)); |
| 806 | dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n", |
| 807 | (unsigned long)cma_obj->paddr, |
| 808 | readl(gdp->regs + GAM_GDP_PML_OFFSET)); |
| 809 | |
| 810 | if (!curr_list) { |
| 811 | /* First update or invalid node should directly write in the |
| 812 | * hw register */ |
| 813 | DRM_DEBUG_DRIVER("%s first update (or invalid node)", |
| 814 | sti_plane_to_str(plane)); |
| 815 | |
| 816 | writel(gdp->is_curr_top ? |
| 817 | dma_updated_btm : dma_updated_top, |
| 818 | gdp->regs + GAM_GDP_NVN_OFFSET); |
| 819 | goto end; |
| 820 | } |
| 821 | |
| 822 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
| 823 | if (gdp->is_curr_top) { |
| 824 | /* Do not update in the middle of the frame, but |
| 825 | * postpone the update after the bottom field has |
| 826 | * been displayed */ |
| 827 | curr_list->btm_field->gam_gdp_nvn = dma_updated_top; |
| 828 | } else { |
| 829 | /* Direct update to avoid one frame delay */ |
| 830 | writel(dma_updated_top, |
| 831 | gdp->regs + GAM_GDP_NVN_OFFSET); |
| 832 | } |
| 833 | } else { |
| 834 | /* Direct update for progressive to avoid one frame delay */ |
| 835 | writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET); |
| 836 | } |
| 837 | |
| 838 | end: |
| 839 | sti_plane_update_fps(plane, true, false); |
| 840 | |
| 841 | plane->status = STI_PLANE_UPDATED; |
| 842 | } |
| 843 | |
| 844 | static void sti_gdp_atomic_disable(struct drm_plane *drm_plane, |
| 845 | struct drm_plane_state *oldstate) |
| 846 | { |
| 847 | struct sti_plane *plane = to_sti_plane(drm_plane); |
| 848 | |
| 849 | if (!drm_plane->crtc) { |
| 850 | DRM_DEBUG_DRIVER("drm plane:%d not enabled\n", |
| 851 | drm_plane->base.id); |
| 852 | return; |
| 853 | } |
| 854 | |
| 855 | DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n", |
| 856 | drm_plane->crtc->base.id, |
| 857 | sti_mixer_to_str(to_sti_mixer(drm_plane->crtc)), |
| 858 | drm_plane->base.id, sti_plane_to_str(plane)); |
| 859 | |
| 860 | plane->status = STI_PLANE_DISABLING; |
| 861 | } |
| 862 | |
| 863 | static const struct drm_plane_helper_funcs sti_gdp_helpers_funcs = { |
| 864 | .atomic_check = sti_gdp_atomic_check, |
| 865 | .atomic_update = sti_gdp_atomic_update, |
| 866 | .atomic_disable = sti_gdp_atomic_disable, |
| 867 | }; |
| 868 | |
| 869 | static void sti_gdp_destroy(struct drm_plane *drm_plane) |
| 870 | { |
| 871 | DRM_DEBUG_DRIVER("\n"); |
| 872 | |
| 873 | drm_plane_helper_disable(drm_plane); |
| 874 | drm_plane_cleanup(drm_plane); |
| 875 | } |
| 876 | |
| 877 | static int sti_gdp_late_register(struct drm_plane *drm_plane) |
| 878 | { |
| 879 | struct sti_plane *plane = to_sti_plane(drm_plane); |
| 880 | struct sti_gdp *gdp = to_sti_gdp(plane); |
| 881 | |
| 882 | return gdp_debugfs_init(gdp, drm_plane->dev->primary); |
| 883 | } |
| 884 | |
| 885 | struct drm_plane_funcs sti_gdp_plane_helpers_funcs = { |
| 886 | .update_plane = drm_atomic_helper_update_plane, |
| 887 | .disable_plane = drm_atomic_helper_disable_plane, |
| 888 | .destroy = sti_gdp_destroy, |
| 889 | .set_property = sti_plane_set_property, |
| 890 | .reset = drm_atomic_helper_plane_reset, |
| 891 | .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, |
| 892 | .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, |
| 893 | .late_register = sti_gdp_late_register, |
| 894 | }; |
| 895 | |
| 896 | struct drm_plane *sti_gdp_create(struct drm_device *drm_dev, |
| 897 | struct device *dev, int desc, |
| 898 | void __iomem *baseaddr, |
| 899 | unsigned int possible_crtcs, |
| 900 | enum drm_plane_type type) |
| 901 | { |
| 902 | struct sti_gdp *gdp; |
| 903 | int res; |
| 904 | |
| 905 | gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL); |
| 906 | if (!gdp) { |
| 907 | DRM_ERROR("Failed to allocate memory for GDP\n"); |
| 908 | return NULL; |
| 909 | } |
| 910 | |
| 911 | gdp->dev = dev; |
| 912 | gdp->regs = baseaddr; |
| 913 | gdp->plane.desc = desc; |
| 914 | gdp->plane.status = STI_PLANE_DISABLED; |
| 915 | |
| 916 | gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb; |
| 917 | |
| 918 | sti_gdp_init(gdp); |
| 919 | |
| 920 | res = drm_universal_plane_init(drm_dev, &gdp->plane.drm_plane, |
| 921 | possible_crtcs, |
| 922 | &sti_gdp_plane_helpers_funcs, |
| 923 | gdp_supported_formats, |
| 924 | ARRAY_SIZE(gdp_supported_formats), |
| 925 | type, NULL); |
| 926 | if (res) { |
| 927 | DRM_ERROR("Failed to initialize universal plane\n"); |
| 928 | goto err; |
| 929 | } |
| 930 | |
| 931 | drm_plane_helper_add(&gdp->plane.drm_plane, &sti_gdp_helpers_funcs); |
| 932 | |
| 933 | sti_plane_init_property(&gdp->plane, type); |
| 934 | |
| 935 | return &gdp->plane.drm_plane; |
| 936 | |
| 937 | err: |
| 938 | devm_kfree(dev, gdp); |
| 939 | return NULL; |
| 940 | } |