| 1 | /****************************************************************************** |
| 2 | * x86_emulate.c |
| 3 | * |
| 4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. |
| 5 | * |
| 6 | * Copyright (c) 2005 Keir Fraser |
| 7 | * |
| 8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode |
| 9 | * privileged instructions: |
| 10 | * |
| 11 | * Copyright (C) 2006 Qumranet |
| 12 | * |
| 13 | * Avi Kivity <avi@qumranet.com> |
| 14 | * Yaniv Kamay <yaniv@qumranet.com> |
| 15 | * |
| 16 | * This work is licensed under the terms of the GNU GPL, version 2. See |
| 17 | * the COPYING file in the top-level directory. |
| 18 | * |
| 19 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 |
| 20 | */ |
| 21 | |
| 22 | #ifndef __KERNEL__ |
| 23 | #include <stdio.h> |
| 24 | #include <stdint.h> |
| 25 | #include <public/xen.h> |
| 26 | #define DPRINTF(_f, _a ...) printf(_f , ## _a) |
| 27 | #else |
| 28 | #include "kvm.h" |
| 29 | #include "x86.h" |
| 30 | #define DPRINTF(x...) do {} while (0) |
| 31 | #endif |
| 32 | #include "x86_emulate.h" |
| 33 | #include <linux/module.h> |
| 34 | |
| 35 | /* |
| 36 | * Opcode effective-address decode tables. |
| 37 | * Note that we only emulate instructions that have at least one memory |
| 38 | * operand (excluding implicit stack references). We assume that stack |
| 39 | * references and instruction fetches will never occur in special memory |
| 40 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need |
| 41 | * not be handled. |
| 42 | */ |
| 43 | |
| 44 | /* Operand sizes: 8-bit operands or specified/overridden size. */ |
| 45 | #define ByteOp (1<<0) /* 8-bit operands. */ |
| 46 | /* Destination operand type. */ |
| 47 | #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */ |
| 48 | #define DstReg (2<<1) /* Register operand. */ |
| 49 | #define DstMem (3<<1) /* Memory operand. */ |
| 50 | #define DstMask (3<<1) |
| 51 | /* Source operand type. */ |
| 52 | #define SrcNone (0<<3) /* No source operand. */ |
| 53 | #define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */ |
| 54 | #define SrcReg (1<<3) /* Register operand. */ |
| 55 | #define SrcMem (2<<3) /* Memory operand. */ |
| 56 | #define SrcMem16 (3<<3) /* Memory operand (16-bit). */ |
| 57 | #define SrcMem32 (4<<3) /* Memory operand (32-bit). */ |
| 58 | #define SrcImm (5<<3) /* Immediate operand. */ |
| 59 | #define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */ |
| 60 | #define SrcMask (7<<3) |
| 61 | /* Generic ModRM decode. */ |
| 62 | #define ModRM (1<<6) |
| 63 | /* Destination is only written; never read. */ |
| 64 | #define Mov (1<<7) |
| 65 | #define BitOp (1<<8) |
| 66 | #define MemAbs (1<<9) /* Memory operand is absolute displacement */ |
| 67 | |
| 68 | static u16 opcode_table[256] = { |
| 69 | /* 0x00 - 0x07 */ |
| 70 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, |
| 71 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
| 72 | 0, 0, 0, 0, |
| 73 | /* 0x08 - 0x0F */ |
| 74 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, |
| 75 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
| 76 | 0, 0, 0, 0, |
| 77 | /* 0x10 - 0x17 */ |
| 78 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, |
| 79 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
| 80 | 0, 0, 0, 0, |
| 81 | /* 0x18 - 0x1F */ |
| 82 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, |
| 83 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
| 84 | 0, 0, 0, 0, |
| 85 | /* 0x20 - 0x27 */ |
| 86 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, |
| 87 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
| 88 | SrcImmByte, SrcImm, 0, 0, |
| 89 | /* 0x28 - 0x2F */ |
| 90 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, |
| 91 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
| 92 | 0, 0, 0, 0, |
| 93 | /* 0x30 - 0x37 */ |
| 94 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, |
| 95 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
| 96 | 0, 0, 0, 0, |
| 97 | /* 0x38 - 0x3F */ |
| 98 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, |
| 99 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
| 100 | 0, 0, 0, 0, |
| 101 | /* 0x40 - 0x47 */ |
| 102 | DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, |
| 103 | /* 0x48 - 0x4F */ |
| 104 | DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, |
| 105 | /* 0x50 - 0x57 */ |
| 106 | SrcReg, SrcReg, SrcReg, SrcReg, SrcReg, SrcReg, SrcReg, SrcReg, |
| 107 | /* 0x58 - 0x5F */ |
| 108 | DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, |
| 109 | /* 0x60 - 0x67 */ |
| 110 | 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ , |
| 111 | 0, 0, 0, 0, |
| 112 | /* 0x68 - 0x6F */ |
| 113 | 0, 0, ImplicitOps|Mov, 0, |
| 114 | SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */ |
| 115 | SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */ |
| 116 | /* 0x70 - 0x77 */ |
| 117 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, |
| 118 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, |
| 119 | /* 0x78 - 0x7F */ |
| 120 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, |
| 121 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, |
| 122 | /* 0x80 - 0x87 */ |
| 123 | ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM, |
| 124 | ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM, |
| 125 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, |
| 126 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, |
| 127 | /* 0x88 - 0x8F */ |
| 128 | ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov, |
| 129 | ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, |
| 130 | 0, ModRM | DstReg, 0, DstMem | SrcNone | ModRM | Mov, |
| 131 | /* 0x90 - 0x9F */ |
| 132 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps, ImplicitOps, 0, 0, |
| 133 | /* 0xA0 - 0xA7 */ |
| 134 | ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs, |
| 135 | ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs, |
| 136 | ByteOp | ImplicitOps | Mov, ImplicitOps | Mov, |
| 137 | ByteOp | ImplicitOps, ImplicitOps, |
| 138 | /* 0xA8 - 0xAF */ |
| 139 | 0, 0, ByteOp | ImplicitOps | Mov, ImplicitOps | Mov, |
| 140 | ByteOp | ImplicitOps | Mov, ImplicitOps | Mov, |
| 141 | ByteOp | ImplicitOps, ImplicitOps, |
| 142 | /* 0xB0 - 0xBF */ |
| 143 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 144 | /* 0xC0 - 0xC7 */ |
| 145 | ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM, |
| 146 | 0, ImplicitOps, 0, 0, |
| 147 | ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov, |
| 148 | /* 0xC8 - 0xCF */ |
| 149 | 0, 0, 0, 0, 0, 0, 0, 0, |
| 150 | /* 0xD0 - 0xD7 */ |
| 151 | ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM, |
| 152 | ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM, |
| 153 | 0, 0, 0, 0, |
| 154 | /* 0xD8 - 0xDF */ |
| 155 | 0, 0, 0, 0, 0, 0, 0, 0, |
| 156 | /* 0xE0 - 0xE7 */ |
| 157 | 0, 0, 0, 0, 0, 0, 0, 0, |
| 158 | /* 0xE8 - 0xEF */ |
| 159 | ImplicitOps, SrcImm|ImplicitOps, 0, SrcImmByte|ImplicitOps, 0, 0, 0, 0, |
| 160 | /* 0xF0 - 0xF7 */ |
| 161 | 0, 0, 0, 0, |
| 162 | ImplicitOps, ImplicitOps, |
| 163 | ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, |
| 164 | /* 0xF8 - 0xFF */ |
| 165 | ImplicitOps, 0, ImplicitOps, ImplicitOps, |
| 166 | 0, 0, ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM |
| 167 | }; |
| 168 | |
| 169 | static u16 twobyte_table[256] = { |
| 170 | /* 0x00 - 0x0F */ |
| 171 | 0, SrcMem | ModRM | DstReg, 0, 0, 0, 0, ImplicitOps, 0, |
| 172 | ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0, |
| 173 | /* 0x10 - 0x1F */ |
| 174 | 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0, |
| 175 | /* 0x20 - 0x2F */ |
| 176 | ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0, |
| 177 | 0, 0, 0, 0, 0, 0, 0, 0, |
| 178 | /* 0x30 - 0x3F */ |
| 179 | ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 180 | /* 0x40 - 0x47 */ |
| 181 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, |
| 182 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, |
| 183 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, |
| 184 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, |
| 185 | /* 0x48 - 0x4F */ |
| 186 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, |
| 187 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, |
| 188 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, |
| 189 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, |
| 190 | /* 0x50 - 0x5F */ |
| 191 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 192 | /* 0x60 - 0x6F */ |
| 193 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 194 | /* 0x70 - 0x7F */ |
| 195 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 196 | /* 0x80 - 0x8F */ |
| 197 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, |
| 198 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, |
| 199 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, |
| 200 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, |
| 201 | /* 0x90 - 0x9F */ |
| 202 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 203 | /* 0xA0 - 0xA7 */ |
| 204 | 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0, |
| 205 | /* 0xA8 - 0xAF */ |
| 206 | 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0, |
| 207 | /* 0xB0 - 0xB7 */ |
| 208 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0, |
| 209 | DstMem | SrcReg | ModRM | BitOp, |
| 210 | 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov, |
| 211 | DstReg | SrcMem16 | ModRM | Mov, |
| 212 | /* 0xB8 - 0xBF */ |
| 213 | 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp, |
| 214 | 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov, |
| 215 | DstReg | SrcMem16 | ModRM | Mov, |
| 216 | /* 0xC0 - 0xCF */ |
| 217 | 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM, |
| 218 | 0, 0, 0, 0, 0, 0, 0, 0, |
| 219 | /* 0xD0 - 0xDF */ |
| 220 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 221 | /* 0xE0 - 0xEF */ |
| 222 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 223 | /* 0xF0 - 0xFF */ |
| 224 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 |
| 225 | }; |
| 226 | |
| 227 | /* EFLAGS bit definitions. */ |
| 228 | #define EFLG_OF (1<<11) |
| 229 | #define EFLG_DF (1<<10) |
| 230 | #define EFLG_SF (1<<7) |
| 231 | #define EFLG_ZF (1<<6) |
| 232 | #define EFLG_AF (1<<4) |
| 233 | #define EFLG_PF (1<<2) |
| 234 | #define EFLG_CF (1<<0) |
| 235 | |
| 236 | /* |
| 237 | * Instruction emulation: |
| 238 | * Most instructions are emulated directly via a fragment of inline assembly |
| 239 | * code. This allows us to save/restore EFLAGS and thus very easily pick up |
| 240 | * any modified flags. |
| 241 | */ |
| 242 | |
| 243 | #if defined(CONFIG_X86_64) |
| 244 | #define _LO32 "k" /* force 32-bit operand */ |
| 245 | #define _STK "%%rsp" /* stack pointer */ |
| 246 | #elif defined(__i386__) |
| 247 | #define _LO32 "" /* force 32-bit operand */ |
| 248 | #define _STK "%%esp" /* stack pointer */ |
| 249 | #endif |
| 250 | |
| 251 | /* |
| 252 | * These EFLAGS bits are restored from saved value during emulation, and |
| 253 | * any changes are written back to the saved value after emulation. |
| 254 | */ |
| 255 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) |
| 256 | |
| 257 | /* Before executing instruction: restore necessary bits in EFLAGS. */ |
| 258 | #define _PRE_EFLAGS(_sav, _msk, _tmp) \ |
| 259 | /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); */ \ |
| 260 | "push %"_sav"; " \ |
| 261 | "movl %"_msk",%"_LO32 _tmp"; " \ |
| 262 | "andl %"_LO32 _tmp",("_STK"); " \ |
| 263 | "pushf; " \ |
| 264 | "notl %"_LO32 _tmp"; " \ |
| 265 | "andl %"_LO32 _tmp",("_STK"); " \ |
| 266 | "pop %"_tmp"; " \ |
| 267 | "orl %"_LO32 _tmp",("_STK"); " \ |
| 268 | "popf; " \ |
| 269 | /* _sav &= ~msk; */ \ |
| 270 | "movl %"_msk",%"_LO32 _tmp"; " \ |
| 271 | "notl %"_LO32 _tmp"; " \ |
| 272 | "andl %"_LO32 _tmp",%"_sav"; " |
| 273 | |
| 274 | /* After executing instruction: write-back necessary bits in EFLAGS. */ |
| 275 | #define _POST_EFLAGS(_sav, _msk, _tmp) \ |
| 276 | /* _sav |= EFLAGS & _msk; */ \ |
| 277 | "pushf; " \ |
| 278 | "pop %"_tmp"; " \ |
| 279 | "andl %"_msk",%"_LO32 _tmp"; " \ |
| 280 | "orl %"_LO32 _tmp",%"_sav"; " |
| 281 | |
| 282 | /* Raw emulation: instruction has two explicit operands. */ |
| 283 | #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \ |
| 284 | do { \ |
| 285 | unsigned long _tmp; \ |
| 286 | \ |
| 287 | switch ((_dst).bytes) { \ |
| 288 | case 2: \ |
| 289 | __asm__ __volatile__ ( \ |
| 290 | _PRE_EFLAGS("0", "4", "2") \ |
| 291 | _op"w %"_wx"3,%1; " \ |
| 292 | _POST_EFLAGS("0", "4", "2") \ |
| 293 | : "=m" (_eflags), "=m" ((_dst).val), \ |
| 294 | "=&r" (_tmp) \ |
| 295 | : _wy ((_src).val), "i" (EFLAGS_MASK)); \ |
| 296 | break; \ |
| 297 | case 4: \ |
| 298 | __asm__ __volatile__ ( \ |
| 299 | _PRE_EFLAGS("0", "4", "2") \ |
| 300 | _op"l %"_lx"3,%1; " \ |
| 301 | _POST_EFLAGS("0", "4", "2") \ |
| 302 | : "=m" (_eflags), "=m" ((_dst).val), \ |
| 303 | "=&r" (_tmp) \ |
| 304 | : _ly ((_src).val), "i" (EFLAGS_MASK)); \ |
| 305 | break; \ |
| 306 | case 8: \ |
| 307 | __emulate_2op_8byte(_op, _src, _dst, \ |
| 308 | _eflags, _qx, _qy); \ |
| 309 | break; \ |
| 310 | } \ |
| 311 | } while (0) |
| 312 | |
| 313 | #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ |
| 314 | do { \ |
| 315 | unsigned long _tmp; \ |
| 316 | switch ((_dst).bytes) { \ |
| 317 | case 1: \ |
| 318 | __asm__ __volatile__ ( \ |
| 319 | _PRE_EFLAGS("0", "4", "2") \ |
| 320 | _op"b %"_bx"3,%1; " \ |
| 321 | _POST_EFLAGS("0", "4", "2") \ |
| 322 | : "=m" (_eflags), "=m" ((_dst).val), \ |
| 323 | "=&r" (_tmp) \ |
| 324 | : _by ((_src).val), "i" (EFLAGS_MASK)); \ |
| 325 | break; \ |
| 326 | default: \ |
| 327 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ |
| 328 | _wx, _wy, _lx, _ly, _qx, _qy); \ |
| 329 | break; \ |
| 330 | } \ |
| 331 | } while (0) |
| 332 | |
| 333 | /* Source operand is byte-sized and may be restricted to just %cl. */ |
| 334 | #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \ |
| 335 | __emulate_2op(_op, _src, _dst, _eflags, \ |
| 336 | "b", "c", "b", "c", "b", "c", "b", "c") |
| 337 | |
| 338 | /* Source operand is byte, word, long or quad sized. */ |
| 339 | #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \ |
| 340 | __emulate_2op(_op, _src, _dst, _eflags, \ |
| 341 | "b", "q", "w", "r", _LO32, "r", "", "r") |
| 342 | |
| 343 | /* Source operand is word, long or quad sized. */ |
| 344 | #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \ |
| 345 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ |
| 346 | "w", "r", _LO32, "r", "", "r") |
| 347 | |
| 348 | /* Instruction has only one explicit operand (no source operand). */ |
| 349 | #define emulate_1op(_op, _dst, _eflags) \ |
| 350 | do { \ |
| 351 | unsigned long _tmp; \ |
| 352 | \ |
| 353 | switch ((_dst).bytes) { \ |
| 354 | case 1: \ |
| 355 | __asm__ __volatile__ ( \ |
| 356 | _PRE_EFLAGS("0", "3", "2") \ |
| 357 | _op"b %1; " \ |
| 358 | _POST_EFLAGS("0", "3", "2") \ |
| 359 | : "=m" (_eflags), "=m" ((_dst).val), \ |
| 360 | "=&r" (_tmp) \ |
| 361 | : "i" (EFLAGS_MASK)); \ |
| 362 | break; \ |
| 363 | case 2: \ |
| 364 | __asm__ __volatile__ ( \ |
| 365 | _PRE_EFLAGS("0", "3", "2") \ |
| 366 | _op"w %1; " \ |
| 367 | _POST_EFLAGS("0", "3", "2") \ |
| 368 | : "=m" (_eflags), "=m" ((_dst).val), \ |
| 369 | "=&r" (_tmp) \ |
| 370 | : "i" (EFLAGS_MASK)); \ |
| 371 | break; \ |
| 372 | case 4: \ |
| 373 | __asm__ __volatile__ ( \ |
| 374 | _PRE_EFLAGS("0", "3", "2") \ |
| 375 | _op"l %1; " \ |
| 376 | _POST_EFLAGS("0", "3", "2") \ |
| 377 | : "=m" (_eflags), "=m" ((_dst).val), \ |
| 378 | "=&r" (_tmp) \ |
| 379 | : "i" (EFLAGS_MASK)); \ |
| 380 | break; \ |
| 381 | case 8: \ |
| 382 | __emulate_1op_8byte(_op, _dst, _eflags); \ |
| 383 | break; \ |
| 384 | } \ |
| 385 | } while (0) |
| 386 | |
| 387 | /* Emulate an instruction with quadword operands (x86/64 only). */ |
| 388 | #if defined(CONFIG_X86_64) |
| 389 | #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \ |
| 390 | do { \ |
| 391 | __asm__ __volatile__ ( \ |
| 392 | _PRE_EFLAGS("0", "4", "2") \ |
| 393 | _op"q %"_qx"3,%1; " \ |
| 394 | _POST_EFLAGS("0", "4", "2") \ |
| 395 | : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \ |
| 396 | : _qy ((_src).val), "i" (EFLAGS_MASK)); \ |
| 397 | } while (0) |
| 398 | |
| 399 | #define __emulate_1op_8byte(_op, _dst, _eflags) \ |
| 400 | do { \ |
| 401 | __asm__ __volatile__ ( \ |
| 402 | _PRE_EFLAGS("0", "3", "2") \ |
| 403 | _op"q %1; " \ |
| 404 | _POST_EFLAGS("0", "3", "2") \ |
| 405 | : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \ |
| 406 | : "i" (EFLAGS_MASK)); \ |
| 407 | } while (0) |
| 408 | |
| 409 | #elif defined(__i386__) |
| 410 | #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) |
| 411 | #define __emulate_1op_8byte(_op, _dst, _eflags) |
| 412 | #endif /* __i386__ */ |
| 413 | |
| 414 | /* Fetch next part of the instruction being emulated. */ |
| 415 | #define insn_fetch(_type, _size, _eip) \ |
| 416 | ({ unsigned long _x; \ |
| 417 | rc = ops->read_std((unsigned long)(_eip) + ctxt->cs_base, &_x, \ |
| 418 | (_size), ctxt->vcpu); \ |
| 419 | if (rc != 0) \ |
| 420 | goto done; \ |
| 421 | (_eip) += (_size); \ |
| 422 | (_type)_x; \ |
| 423 | }) |
| 424 | |
| 425 | /* Access/update address held in a register, based on addressing mode. */ |
| 426 | #define address_mask(reg) \ |
| 427 | ((c->ad_bytes == sizeof(unsigned long)) ? \ |
| 428 | (reg) : ((reg) & ((1UL << (c->ad_bytes << 3)) - 1))) |
| 429 | #define register_address(base, reg) \ |
| 430 | ((base) + address_mask(reg)) |
| 431 | #define register_address_increment(reg, inc) \ |
| 432 | do { \ |
| 433 | /* signed type ensures sign extension to long */ \ |
| 434 | int _inc = (inc); \ |
| 435 | if (c->ad_bytes == sizeof(unsigned long)) \ |
| 436 | (reg) += _inc; \ |
| 437 | else \ |
| 438 | (reg) = ((reg) & \ |
| 439 | ~((1UL << (c->ad_bytes << 3)) - 1)) | \ |
| 440 | (((reg) + _inc) & \ |
| 441 | ((1UL << (c->ad_bytes << 3)) - 1)); \ |
| 442 | } while (0) |
| 443 | |
| 444 | #define JMP_REL(rel) \ |
| 445 | do { \ |
| 446 | register_address_increment(c->eip, rel); \ |
| 447 | } while (0) |
| 448 | |
| 449 | /* |
| 450 | * Given the 'reg' portion of a ModRM byte, and a register block, return a |
| 451 | * pointer into the block that addresses the relevant register. |
| 452 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. |
| 453 | */ |
| 454 | static void *decode_register(u8 modrm_reg, unsigned long *regs, |
| 455 | int highbyte_regs) |
| 456 | { |
| 457 | void *p; |
| 458 | |
| 459 | p = ®s[modrm_reg]; |
| 460 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) |
| 461 | p = (unsigned char *)®s[modrm_reg & 3] + 1; |
| 462 | return p; |
| 463 | } |
| 464 | |
| 465 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, |
| 466 | struct x86_emulate_ops *ops, |
| 467 | void *ptr, |
| 468 | u16 *size, unsigned long *address, int op_bytes) |
| 469 | { |
| 470 | int rc; |
| 471 | |
| 472 | if (op_bytes == 2) |
| 473 | op_bytes = 3; |
| 474 | *address = 0; |
| 475 | rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2, |
| 476 | ctxt->vcpu); |
| 477 | if (rc) |
| 478 | return rc; |
| 479 | rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes, |
| 480 | ctxt->vcpu); |
| 481 | return rc; |
| 482 | } |
| 483 | |
| 484 | static int test_cc(unsigned int condition, unsigned int flags) |
| 485 | { |
| 486 | int rc = 0; |
| 487 | |
| 488 | switch ((condition & 15) >> 1) { |
| 489 | case 0: /* o */ |
| 490 | rc |= (flags & EFLG_OF); |
| 491 | break; |
| 492 | case 1: /* b/c/nae */ |
| 493 | rc |= (flags & EFLG_CF); |
| 494 | break; |
| 495 | case 2: /* z/e */ |
| 496 | rc |= (flags & EFLG_ZF); |
| 497 | break; |
| 498 | case 3: /* be/na */ |
| 499 | rc |= (flags & (EFLG_CF|EFLG_ZF)); |
| 500 | break; |
| 501 | case 4: /* s */ |
| 502 | rc |= (flags & EFLG_SF); |
| 503 | break; |
| 504 | case 5: /* p/pe */ |
| 505 | rc |= (flags & EFLG_PF); |
| 506 | break; |
| 507 | case 7: /* le/ng */ |
| 508 | rc |= (flags & EFLG_ZF); |
| 509 | /* fall through */ |
| 510 | case 6: /* l/nge */ |
| 511 | rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); |
| 512 | break; |
| 513 | } |
| 514 | |
| 515 | /* Odd condition identifiers (lsb == 1) have inverted sense. */ |
| 516 | return (!!rc ^ (condition & 1)); |
| 517 | } |
| 518 | |
| 519 | static void decode_register_operand(struct operand *op, |
| 520 | struct decode_cache *c, |
| 521 | int inhibit_bytereg) |
| 522 | { |
| 523 | unsigned reg = c->modrm_reg; |
| 524 | int highbyte_regs = c->rex_prefix == 0; |
| 525 | |
| 526 | if (!(c->d & ModRM)) |
| 527 | reg = (c->b & 7) | ((c->rex_prefix & 1) << 3); |
| 528 | op->type = OP_REG; |
| 529 | if ((c->d & ByteOp) && !inhibit_bytereg) { |
| 530 | op->ptr = decode_register(reg, c->regs, highbyte_regs); |
| 531 | op->val = *(u8 *)op->ptr; |
| 532 | op->bytes = 1; |
| 533 | } else { |
| 534 | op->ptr = decode_register(reg, c->regs, 0); |
| 535 | op->bytes = c->op_bytes; |
| 536 | switch (op->bytes) { |
| 537 | case 2: |
| 538 | op->val = *(u16 *)op->ptr; |
| 539 | break; |
| 540 | case 4: |
| 541 | op->val = *(u32 *)op->ptr; |
| 542 | break; |
| 543 | case 8: |
| 544 | op->val = *(u64 *) op->ptr; |
| 545 | break; |
| 546 | } |
| 547 | } |
| 548 | op->orig_val = op->val; |
| 549 | } |
| 550 | |
| 551 | int |
| 552 | x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
| 553 | { |
| 554 | struct decode_cache *c = &ctxt->decode; |
| 555 | u8 sib; |
| 556 | int rc = 0; |
| 557 | int mode = ctxt->mode; |
| 558 | int index_reg = 0, base_reg = 0, scale, rip_relative = 0; |
| 559 | |
| 560 | /* Shadow copy of register state. Committed on successful emulation. */ |
| 561 | |
| 562 | memset(c, 0, sizeof(struct decode_cache)); |
| 563 | c->eip = ctxt->vcpu->rip; |
| 564 | memcpy(c->regs, ctxt->vcpu->regs, sizeof c->regs); |
| 565 | |
| 566 | switch (mode) { |
| 567 | case X86EMUL_MODE_REAL: |
| 568 | case X86EMUL_MODE_PROT16: |
| 569 | c->op_bytes = c->ad_bytes = 2; |
| 570 | break; |
| 571 | case X86EMUL_MODE_PROT32: |
| 572 | c->op_bytes = c->ad_bytes = 4; |
| 573 | break; |
| 574 | #ifdef CONFIG_X86_64 |
| 575 | case X86EMUL_MODE_PROT64: |
| 576 | c->op_bytes = 4; |
| 577 | c->ad_bytes = 8; |
| 578 | break; |
| 579 | #endif |
| 580 | default: |
| 581 | return -1; |
| 582 | } |
| 583 | |
| 584 | /* Legacy prefixes. */ |
| 585 | for (;;) { |
| 586 | switch (c->b = insn_fetch(u8, 1, c->eip)) { |
| 587 | case 0x66: /* operand-size override */ |
| 588 | c->op_bytes ^= 6; /* switch between 2/4 bytes */ |
| 589 | break; |
| 590 | case 0x67: /* address-size override */ |
| 591 | if (mode == X86EMUL_MODE_PROT64) |
| 592 | /* switch between 4/8 bytes */ |
| 593 | c->ad_bytes ^= 12; |
| 594 | else |
| 595 | /* switch between 2/4 bytes */ |
| 596 | c->ad_bytes ^= 6; |
| 597 | break; |
| 598 | case 0x2e: /* CS override */ |
| 599 | c->override_base = &ctxt->cs_base; |
| 600 | break; |
| 601 | case 0x3e: /* DS override */ |
| 602 | c->override_base = &ctxt->ds_base; |
| 603 | break; |
| 604 | case 0x26: /* ES override */ |
| 605 | c->override_base = &ctxt->es_base; |
| 606 | break; |
| 607 | case 0x64: /* FS override */ |
| 608 | c->override_base = &ctxt->fs_base; |
| 609 | break; |
| 610 | case 0x65: /* GS override */ |
| 611 | c->override_base = &ctxt->gs_base; |
| 612 | break; |
| 613 | case 0x36: /* SS override */ |
| 614 | c->override_base = &ctxt->ss_base; |
| 615 | break; |
| 616 | case 0x40 ... 0x4f: /* REX */ |
| 617 | if (mode != X86EMUL_MODE_PROT64) |
| 618 | goto done_prefixes; |
| 619 | c->rex_prefix = c->b; |
| 620 | continue; |
| 621 | case 0xf0: /* LOCK */ |
| 622 | c->lock_prefix = 1; |
| 623 | break; |
| 624 | case 0xf2: /* REPNE/REPNZ */ |
| 625 | case 0xf3: /* REP/REPE/REPZ */ |
| 626 | c->rep_prefix = 1; |
| 627 | break; |
| 628 | default: |
| 629 | goto done_prefixes; |
| 630 | } |
| 631 | |
| 632 | /* Any legacy prefix after a REX prefix nullifies its effect. */ |
| 633 | |
| 634 | c->rex_prefix = 0; |
| 635 | } |
| 636 | |
| 637 | done_prefixes: |
| 638 | |
| 639 | /* REX prefix. */ |
| 640 | if (c->rex_prefix) { |
| 641 | if (c->rex_prefix & 8) |
| 642 | c->op_bytes = 8; /* REX.W */ |
| 643 | c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */ |
| 644 | index_reg = (c->rex_prefix & 2) << 2; /* REX.X */ |
| 645 | c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */ |
| 646 | } |
| 647 | |
| 648 | /* Opcode byte(s). */ |
| 649 | c->d = opcode_table[c->b]; |
| 650 | if (c->d == 0) { |
| 651 | /* Two-byte opcode? */ |
| 652 | if (c->b == 0x0f) { |
| 653 | c->twobyte = 1; |
| 654 | c->b = insn_fetch(u8, 1, c->eip); |
| 655 | c->d = twobyte_table[c->b]; |
| 656 | } |
| 657 | |
| 658 | /* Unrecognised? */ |
| 659 | if (c->d == 0) { |
| 660 | DPRINTF("Cannot emulate %02x\n", c->b); |
| 661 | return -1; |
| 662 | } |
| 663 | } |
| 664 | |
| 665 | /* ModRM and SIB bytes. */ |
| 666 | if (c->d & ModRM) { |
| 667 | c->modrm = insn_fetch(u8, 1, c->eip); |
| 668 | c->modrm_mod |= (c->modrm & 0xc0) >> 6; |
| 669 | c->modrm_reg |= (c->modrm & 0x38) >> 3; |
| 670 | c->modrm_rm |= (c->modrm & 0x07); |
| 671 | c->modrm_ea = 0; |
| 672 | c->use_modrm_ea = 1; |
| 673 | |
| 674 | if (c->modrm_mod == 3) { |
| 675 | c->modrm_val = *(unsigned long *) |
| 676 | decode_register(c->modrm_rm, c->regs, c->d & ByteOp); |
| 677 | goto modrm_done; |
| 678 | } |
| 679 | |
| 680 | if (c->ad_bytes == 2) { |
| 681 | unsigned bx = c->regs[VCPU_REGS_RBX]; |
| 682 | unsigned bp = c->regs[VCPU_REGS_RBP]; |
| 683 | unsigned si = c->regs[VCPU_REGS_RSI]; |
| 684 | unsigned di = c->regs[VCPU_REGS_RDI]; |
| 685 | |
| 686 | /* 16-bit ModR/M decode. */ |
| 687 | switch (c->modrm_mod) { |
| 688 | case 0: |
| 689 | if (c->modrm_rm == 6) |
| 690 | c->modrm_ea += |
| 691 | insn_fetch(u16, 2, c->eip); |
| 692 | break; |
| 693 | case 1: |
| 694 | c->modrm_ea += insn_fetch(s8, 1, c->eip); |
| 695 | break; |
| 696 | case 2: |
| 697 | c->modrm_ea += insn_fetch(u16, 2, c->eip); |
| 698 | break; |
| 699 | } |
| 700 | switch (c->modrm_rm) { |
| 701 | case 0: |
| 702 | c->modrm_ea += bx + si; |
| 703 | break; |
| 704 | case 1: |
| 705 | c->modrm_ea += bx + di; |
| 706 | break; |
| 707 | case 2: |
| 708 | c->modrm_ea += bp + si; |
| 709 | break; |
| 710 | case 3: |
| 711 | c->modrm_ea += bp + di; |
| 712 | break; |
| 713 | case 4: |
| 714 | c->modrm_ea += si; |
| 715 | break; |
| 716 | case 5: |
| 717 | c->modrm_ea += di; |
| 718 | break; |
| 719 | case 6: |
| 720 | if (c->modrm_mod != 0) |
| 721 | c->modrm_ea += bp; |
| 722 | break; |
| 723 | case 7: |
| 724 | c->modrm_ea += bx; |
| 725 | break; |
| 726 | } |
| 727 | if (c->modrm_rm == 2 || c->modrm_rm == 3 || |
| 728 | (c->modrm_rm == 6 && c->modrm_mod != 0)) |
| 729 | if (!c->override_base) |
| 730 | c->override_base = &ctxt->ss_base; |
| 731 | c->modrm_ea = (u16)c->modrm_ea; |
| 732 | } else { |
| 733 | /* 32/64-bit ModR/M decode. */ |
| 734 | switch (c->modrm_rm) { |
| 735 | case 4: |
| 736 | case 12: |
| 737 | sib = insn_fetch(u8, 1, c->eip); |
| 738 | index_reg |= (sib >> 3) & 7; |
| 739 | base_reg |= sib & 7; |
| 740 | scale = sib >> 6; |
| 741 | |
| 742 | switch (base_reg) { |
| 743 | case 5: |
| 744 | if (c->modrm_mod != 0) |
| 745 | c->modrm_ea += |
| 746 | c->regs[base_reg]; |
| 747 | else |
| 748 | c->modrm_ea += |
| 749 | insn_fetch(s32, 4, c->eip); |
| 750 | break; |
| 751 | default: |
| 752 | c->modrm_ea += c->regs[base_reg]; |
| 753 | } |
| 754 | switch (index_reg) { |
| 755 | case 4: |
| 756 | break; |
| 757 | default: |
| 758 | c->modrm_ea += |
| 759 | c->regs[index_reg] << scale; |
| 760 | |
| 761 | } |
| 762 | break; |
| 763 | case 5: |
| 764 | if (c->modrm_mod != 0) |
| 765 | c->modrm_ea += c->regs[c->modrm_rm]; |
| 766 | else if (mode == X86EMUL_MODE_PROT64) |
| 767 | rip_relative = 1; |
| 768 | break; |
| 769 | default: |
| 770 | c->modrm_ea += c->regs[c->modrm_rm]; |
| 771 | break; |
| 772 | } |
| 773 | switch (c->modrm_mod) { |
| 774 | case 0: |
| 775 | if (c->modrm_rm == 5) |
| 776 | c->modrm_ea += |
| 777 | insn_fetch(s32, 4, c->eip); |
| 778 | break; |
| 779 | case 1: |
| 780 | c->modrm_ea += insn_fetch(s8, 1, c->eip); |
| 781 | break; |
| 782 | case 2: |
| 783 | c->modrm_ea += insn_fetch(s32, 4, c->eip); |
| 784 | break; |
| 785 | } |
| 786 | } |
| 787 | if (rip_relative) { |
| 788 | c->modrm_ea += c->eip; |
| 789 | switch (c->d & SrcMask) { |
| 790 | case SrcImmByte: |
| 791 | c->modrm_ea += 1; |
| 792 | break; |
| 793 | case SrcImm: |
| 794 | if (c->d & ByteOp) |
| 795 | c->modrm_ea += 1; |
| 796 | else |
| 797 | if (c->op_bytes == 8) |
| 798 | c->modrm_ea += 4; |
| 799 | else |
| 800 | c->modrm_ea += c->op_bytes; |
| 801 | } |
| 802 | } |
| 803 | modrm_done: |
| 804 | ; |
| 805 | } else if (c->d & MemAbs) { |
| 806 | switch (c->ad_bytes) { |
| 807 | case 2: |
| 808 | c->modrm_ea = insn_fetch(u16, 2, c->eip); |
| 809 | break; |
| 810 | case 4: |
| 811 | c->modrm_ea = insn_fetch(u32, 4, c->eip); |
| 812 | break; |
| 813 | case 8: |
| 814 | c->modrm_ea = insn_fetch(u64, 8, c->eip); |
| 815 | break; |
| 816 | } |
| 817 | |
| 818 | } |
| 819 | |
| 820 | if (!c->override_base) |
| 821 | c->override_base = &ctxt->ds_base; |
| 822 | if (mode == X86EMUL_MODE_PROT64 && |
| 823 | c->override_base != &ctxt->fs_base && |
| 824 | c->override_base != &ctxt->gs_base) |
| 825 | c->override_base = NULL; |
| 826 | |
| 827 | if (c->override_base) |
| 828 | c->modrm_ea += *c->override_base; |
| 829 | |
| 830 | if (c->ad_bytes != 8) |
| 831 | c->modrm_ea = (u32)c->modrm_ea; |
| 832 | /* |
| 833 | * Decode and fetch the source operand: register, memory |
| 834 | * or immediate. |
| 835 | */ |
| 836 | switch (c->d & SrcMask) { |
| 837 | case SrcNone: |
| 838 | break; |
| 839 | case SrcReg: |
| 840 | decode_register_operand(&c->src, c, 0); |
| 841 | break; |
| 842 | case SrcMem16: |
| 843 | c->src.bytes = 2; |
| 844 | goto srcmem_common; |
| 845 | case SrcMem32: |
| 846 | c->src.bytes = 4; |
| 847 | goto srcmem_common; |
| 848 | case SrcMem: |
| 849 | c->src.bytes = (c->d & ByteOp) ? 1 : |
| 850 | c->op_bytes; |
| 851 | /* Don't fetch the address for invlpg: it could be unmapped. */ |
| 852 | if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7) |
| 853 | break; |
| 854 | srcmem_common: |
| 855 | /* |
| 856 | * For instructions with a ModR/M byte, switch to register |
| 857 | * access if Mod = 3. |
| 858 | */ |
| 859 | if ((c->d & ModRM) && c->modrm_mod == 3) { |
| 860 | c->src.type = OP_REG; |
| 861 | break; |
| 862 | } |
| 863 | c->src.type = OP_MEM; |
| 864 | break; |
| 865 | case SrcImm: |
| 866 | c->src.type = OP_IMM; |
| 867 | c->src.ptr = (unsigned long *)c->eip; |
| 868 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; |
| 869 | if (c->src.bytes == 8) |
| 870 | c->src.bytes = 4; |
| 871 | /* NB. Immediates are sign-extended as necessary. */ |
| 872 | switch (c->src.bytes) { |
| 873 | case 1: |
| 874 | c->src.val = insn_fetch(s8, 1, c->eip); |
| 875 | break; |
| 876 | case 2: |
| 877 | c->src.val = insn_fetch(s16, 2, c->eip); |
| 878 | break; |
| 879 | case 4: |
| 880 | c->src.val = insn_fetch(s32, 4, c->eip); |
| 881 | break; |
| 882 | } |
| 883 | break; |
| 884 | case SrcImmByte: |
| 885 | c->src.type = OP_IMM; |
| 886 | c->src.ptr = (unsigned long *)c->eip; |
| 887 | c->src.bytes = 1; |
| 888 | c->src.val = insn_fetch(s8, 1, c->eip); |
| 889 | break; |
| 890 | } |
| 891 | |
| 892 | /* Decode and fetch the destination operand: register or memory. */ |
| 893 | switch (c->d & DstMask) { |
| 894 | case ImplicitOps: |
| 895 | /* Special instructions do their own operand decoding. */ |
| 896 | return 0; |
| 897 | case DstReg: |
| 898 | decode_register_operand(&c->dst, c, |
| 899 | c->twobyte && (c->b == 0xb6 || c->b == 0xb7)); |
| 900 | break; |
| 901 | case DstMem: |
| 902 | if ((c->d & ModRM) && c->modrm_mod == 3) { |
| 903 | c->dst.type = OP_REG; |
| 904 | break; |
| 905 | } |
| 906 | c->dst.type = OP_MEM; |
| 907 | break; |
| 908 | } |
| 909 | |
| 910 | done: |
| 911 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; |
| 912 | } |
| 913 | |
| 914 | static inline void emulate_push(struct x86_emulate_ctxt *ctxt) |
| 915 | { |
| 916 | struct decode_cache *c = &ctxt->decode; |
| 917 | |
| 918 | c->dst.type = OP_MEM; |
| 919 | c->dst.bytes = c->op_bytes; |
| 920 | c->dst.val = c->src.val; |
| 921 | register_address_increment(c->regs[VCPU_REGS_RSP], -c->op_bytes); |
| 922 | c->dst.ptr = (void *) register_address(ctxt->ss_base, |
| 923 | c->regs[VCPU_REGS_RSP]); |
| 924 | } |
| 925 | |
| 926 | static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt, |
| 927 | struct x86_emulate_ops *ops) |
| 928 | { |
| 929 | struct decode_cache *c = &ctxt->decode; |
| 930 | int rc; |
| 931 | |
| 932 | /* 64-bit mode: POP always pops a 64-bit operand. */ |
| 933 | |
| 934 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
| 935 | c->dst.bytes = 8; |
| 936 | |
| 937 | rc = ops->read_std(register_address(ctxt->ss_base, |
| 938 | c->regs[VCPU_REGS_RSP]), |
| 939 | &c->dst.val, c->dst.bytes, ctxt->vcpu); |
| 940 | if (rc != 0) |
| 941 | return rc; |
| 942 | |
| 943 | register_address_increment(c->regs[VCPU_REGS_RSP], c->dst.bytes); |
| 944 | |
| 945 | return 0; |
| 946 | } |
| 947 | |
| 948 | static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt) |
| 949 | { |
| 950 | struct decode_cache *c = &ctxt->decode; |
| 951 | switch (c->modrm_reg) { |
| 952 | case 0: /* rol */ |
| 953 | emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags); |
| 954 | break; |
| 955 | case 1: /* ror */ |
| 956 | emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags); |
| 957 | break; |
| 958 | case 2: /* rcl */ |
| 959 | emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags); |
| 960 | break; |
| 961 | case 3: /* rcr */ |
| 962 | emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags); |
| 963 | break; |
| 964 | case 4: /* sal/shl */ |
| 965 | case 6: /* sal/shl */ |
| 966 | emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags); |
| 967 | break; |
| 968 | case 5: /* shr */ |
| 969 | emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags); |
| 970 | break; |
| 971 | case 7: /* sar */ |
| 972 | emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags); |
| 973 | break; |
| 974 | } |
| 975 | } |
| 976 | |
| 977 | static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt, |
| 978 | struct x86_emulate_ops *ops) |
| 979 | { |
| 980 | struct decode_cache *c = &ctxt->decode; |
| 981 | int rc = 0; |
| 982 | |
| 983 | switch (c->modrm_reg) { |
| 984 | case 0 ... 1: /* test */ |
| 985 | /* |
| 986 | * Special case in Grp3: test has an immediate |
| 987 | * source operand. |
| 988 | */ |
| 989 | c->src.type = OP_IMM; |
| 990 | c->src.ptr = (unsigned long *)c->eip; |
| 991 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; |
| 992 | if (c->src.bytes == 8) |
| 993 | c->src.bytes = 4; |
| 994 | switch (c->src.bytes) { |
| 995 | case 1: |
| 996 | c->src.val = insn_fetch(s8, 1, c->eip); |
| 997 | break; |
| 998 | case 2: |
| 999 | c->src.val = insn_fetch(s16, 2, c->eip); |
| 1000 | break; |
| 1001 | case 4: |
| 1002 | c->src.val = insn_fetch(s32, 4, c->eip); |
| 1003 | break; |
| 1004 | } |
| 1005 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
| 1006 | break; |
| 1007 | case 2: /* not */ |
| 1008 | c->dst.val = ~c->dst.val; |
| 1009 | break; |
| 1010 | case 3: /* neg */ |
| 1011 | emulate_1op("neg", c->dst, ctxt->eflags); |
| 1012 | break; |
| 1013 | default: |
| 1014 | DPRINTF("Cannot emulate %02x\n", c->b); |
| 1015 | rc = X86EMUL_UNHANDLEABLE; |
| 1016 | break; |
| 1017 | } |
| 1018 | done: |
| 1019 | return rc; |
| 1020 | } |
| 1021 | |
| 1022 | static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt, |
| 1023 | struct x86_emulate_ops *ops) |
| 1024 | { |
| 1025 | struct decode_cache *c = &ctxt->decode; |
| 1026 | int rc; |
| 1027 | |
| 1028 | switch (c->modrm_reg) { |
| 1029 | case 0: /* inc */ |
| 1030 | emulate_1op("inc", c->dst, ctxt->eflags); |
| 1031 | break; |
| 1032 | case 1: /* dec */ |
| 1033 | emulate_1op("dec", c->dst, ctxt->eflags); |
| 1034 | break; |
| 1035 | case 4: /* jmp abs */ |
| 1036 | if (c->b == 0xff) |
| 1037 | c->eip = c->dst.val; |
| 1038 | else { |
| 1039 | DPRINTF("Cannot emulate %02x\n", c->b); |
| 1040 | return X86EMUL_UNHANDLEABLE; |
| 1041 | } |
| 1042 | break; |
| 1043 | case 6: /* push */ |
| 1044 | |
| 1045 | /* 64-bit mode: PUSH always pushes a 64-bit operand. */ |
| 1046 | |
| 1047 | if (ctxt->mode == X86EMUL_MODE_PROT64) { |
| 1048 | c->dst.bytes = 8; |
| 1049 | rc = ops->read_std((unsigned long)c->dst.ptr, |
| 1050 | &c->dst.val, 8, ctxt->vcpu); |
| 1051 | if (rc != 0) |
| 1052 | return rc; |
| 1053 | } |
| 1054 | register_address_increment(c->regs[VCPU_REGS_RSP], |
| 1055 | -c->dst.bytes); |
| 1056 | rc = ops->write_emulated(register_address(ctxt->ss_base, |
| 1057 | c->regs[VCPU_REGS_RSP]), &c->dst.val, |
| 1058 | c->dst.bytes, ctxt->vcpu); |
| 1059 | if (rc != 0) |
| 1060 | return rc; |
| 1061 | c->dst.type = OP_NONE; |
| 1062 | break; |
| 1063 | default: |
| 1064 | DPRINTF("Cannot emulate %02x\n", c->b); |
| 1065 | return X86EMUL_UNHANDLEABLE; |
| 1066 | } |
| 1067 | return 0; |
| 1068 | } |
| 1069 | |
| 1070 | static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt, |
| 1071 | struct x86_emulate_ops *ops, |
| 1072 | unsigned long cr2) |
| 1073 | { |
| 1074 | struct decode_cache *c = &ctxt->decode; |
| 1075 | u64 old, new; |
| 1076 | int rc; |
| 1077 | |
| 1078 | rc = ops->read_emulated(cr2, &old, 8, ctxt->vcpu); |
| 1079 | if (rc != 0) |
| 1080 | return rc; |
| 1081 | |
| 1082 | if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) || |
| 1083 | ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) { |
| 1084 | |
| 1085 | c->regs[VCPU_REGS_RAX] = (u32) (old >> 0); |
| 1086 | c->regs[VCPU_REGS_RDX] = (u32) (old >> 32); |
| 1087 | ctxt->eflags &= ~EFLG_ZF; |
| 1088 | |
| 1089 | } else { |
| 1090 | new = ((u64)c->regs[VCPU_REGS_RCX] << 32) | |
| 1091 | (u32) c->regs[VCPU_REGS_RBX]; |
| 1092 | |
| 1093 | rc = ops->cmpxchg_emulated(cr2, &old, &new, 8, ctxt->vcpu); |
| 1094 | if (rc != 0) |
| 1095 | return rc; |
| 1096 | ctxt->eflags |= EFLG_ZF; |
| 1097 | } |
| 1098 | return 0; |
| 1099 | } |
| 1100 | |
| 1101 | static inline int writeback(struct x86_emulate_ctxt *ctxt, |
| 1102 | struct x86_emulate_ops *ops) |
| 1103 | { |
| 1104 | int rc; |
| 1105 | struct decode_cache *c = &ctxt->decode; |
| 1106 | |
| 1107 | switch (c->dst.type) { |
| 1108 | case OP_REG: |
| 1109 | /* The 4-byte case *is* correct: |
| 1110 | * in 64-bit mode we zero-extend. |
| 1111 | */ |
| 1112 | switch (c->dst.bytes) { |
| 1113 | case 1: |
| 1114 | *(u8 *)c->dst.ptr = (u8)c->dst.val; |
| 1115 | break; |
| 1116 | case 2: |
| 1117 | *(u16 *)c->dst.ptr = (u16)c->dst.val; |
| 1118 | break; |
| 1119 | case 4: |
| 1120 | *c->dst.ptr = (u32)c->dst.val; |
| 1121 | break; /* 64b: zero-ext */ |
| 1122 | case 8: |
| 1123 | *c->dst.ptr = c->dst.val; |
| 1124 | break; |
| 1125 | } |
| 1126 | break; |
| 1127 | case OP_MEM: |
| 1128 | if (c->lock_prefix) |
| 1129 | rc = ops->cmpxchg_emulated( |
| 1130 | (unsigned long)c->dst.ptr, |
| 1131 | &c->dst.orig_val, |
| 1132 | &c->dst.val, |
| 1133 | c->dst.bytes, |
| 1134 | ctxt->vcpu); |
| 1135 | else |
| 1136 | rc = ops->write_emulated( |
| 1137 | (unsigned long)c->dst.ptr, |
| 1138 | &c->dst.val, |
| 1139 | c->dst.bytes, |
| 1140 | ctxt->vcpu); |
| 1141 | if (rc != 0) |
| 1142 | return rc; |
| 1143 | break; |
| 1144 | case OP_NONE: |
| 1145 | /* no writeback */ |
| 1146 | break; |
| 1147 | default: |
| 1148 | break; |
| 1149 | } |
| 1150 | return 0; |
| 1151 | } |
| 1152 | |
| 1153 | int |
| 1154 | x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
| 1155 | { |
| 1156 | unsigned long cr2 = ctxt->cr2; |
| 1157 | u64 msr_data; |
| 1158 | unsigned long saved_eip = 0; |
| 1159 | struct decode_cache *c = &ctxt->decode; |
| 1160 | int rc = 0; |
| 1161 | |
| 1162 | /* Shadow copy of register state. Committed on successful emulation. |
| 1163 | * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't |
| 1164 | * modify them. |
| 1165 | */ |
| 1166 | |
| 1167 | memcpy(c->regs, ctxt->vcpu->regs, sizeof c->regs); |
| 1168 | saved_eip = c->eip; |
| 1169 | |
| 1170 | if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs)) |
| 1171 | cr2 = c->modrm_ea; |
| 1172 | |
| 1173 | if (c->src.type == OP_MEM) { |
| 1174 | c->src.ptr = (unsigned long *)cr2; |
| 1175 | c->src.val = 0; |
| 1176 | rc = ops->read_emulated((unsigned long)c->src.ptr, |
| 1177 | &c->src.val, |
| 1178 | c->src.bytes, |
| 1179 | ctxt->vcpu); |
| 1180 | if (rc != 0) |
| 1181 | goto done; |
| 1182 | c->src.orig_val = c->src.val; |
| 1183 | } |
| 1184 | |
| 1185 | if ((c->d & DstMask) == ImplicitOps) |
| 1186 | goto special_insn; |
| 1187 | |
| 1188 | |
| 1189 | if (c->dst.type == OP_MEM) { |
| 1190 | c->dst.ptr = (unsigned long *)cr2; |
| 1191 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; |
| 1192 | c->dst.val = 0; |
| 1193 | if (c->d & BitOp) { |
| 1194 | unsigned long mask = ~(c->dst.bytes * 8 - 1); |
| 1195 | |
| 1196 | c->dst.ptr = (void *)c->dst.ptr + |
| 1197 | (c->src.val & mask) / 8; |
| 1198 | } |
| 1199 | if (!(c->d & Mov) && |
| 1200 | /* optimisation - avoid slow emulated read */ |
| 1201 | ((rc = ops->read_emulated((unsigned long)c->dst.ptr, |
| 1202 | &c->dst.val, |
| 1203 | c->dst.bytes, ctxt->vcpu)) != 0)) |
| 1204 | goto done; |
| 1205 | } |
| 1206 | c->dst.orig_val = c->dst.val; |
| 1207 | |
| 1208 | if (c->twobyte) |
| 1209 | goto twobyte_insn; |
| 1210 | |
| 1211 | switch (c->b) { |
| 1212 | case 0x00 ... 0x05: |
| 1213 | add: /* add */ |
| 1214 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); |
| 1215 | break; |
| 1216 | case 0x08 ... 0x0d: |
| 1217 | or: /* or */ |
| 1218 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); |
| 1219 | break; |
| 1220 | case 0x10 ... 0x15: |
| 1221 | adc: /* adc */ |
| 1222 | emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags); |
| 1223 | break; |
| 1224 | case 0x18 ... 0x1d: |
| 1225 | sbb: /* sbb */ |
| 1226 | emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags); |
| 1227 | break; |
| 1228 | case 0x20 ... 0x23: |
| 1229 | and: /* and */ |
| 1230 | emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags); |
| 1231 | break; |
| 1232 | case 0x24: /* and al imm8 */ |
| 1233 | c->dst.type = OP_REG; |
| 1234 | c->dst.ptr = &c->regs[VCPU_REGS_RAX]; |
| 1235 | c->dst.val = *(u8 *)c->dst.ptr; |
| 1236 | c->dst.bytes = 1; |
| 1237 | c->dst.orig_val = c->dst.val; |
| 1238 | goto and; |
| 1239 | case 0x25: /* and ax imm16, or eax imm32 */ |
| 1240 | c->dst.type = OP_REG; |
| 1241 | c->dst.bytes = c->op_bytes; |
| 1242 | c->dst.ptr = &c->regs[VCPU_REGS_RAX]; |
| 1243 | if (c->op_bytes == 2) |
| 1244 | c->dst.val = *(u16 *)c->dst.ptr; |
| 1245 | else |
| 1246 | c->dst.val = *(u32 *)c->dst.ptr; |
| 1247 | c->dst.orig_val = c->dst.val; |
| 1248 | goto and; |
| 1249 | case 0x28 ... 0x2d: |
| 1250 | sub: /* sub */ |
| 1251 | emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags); |
| 1252 | break; |
| 1253 | case 0x30 ... 0x35: |
| 1254 | xor: /* xor */ |
| 1255 | emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags); |
| 1256 | break; |
| 1257 | case 0x38 ... 0x3d: |
| 1258 | cmp: /* cmp */ |
| 1259 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
| 1260 | break; |
| 1261 | case 0x40 ... 0x47: /* inc r16/r32 */ |
| 1262 | emulate_1op("inc", c->dst, ctxt->eflags); |
| 1263 | break; |
| 1264 | case 0x48 ... 0x4f: /* dec r16/r32 */ |
| 1265 | emulate_1op("dec", c->dst, ctxt->eflags); |
| 1266 | break; |
| 1267 | case 0x50 ... 0x57: /* push reg */ |
| 1268 | c->dst.type = OP_MEM; |
| 1269 | c->dst.bytes = c->op_bytes; |
| 1270 | c->dst.val = c->src.val; |
| 1271 | register_address_increment(c->regs[VCPU_REGS_RSP], |
| 1272 | -c->op_bytes); |
| 1273 | c->dst.ptr = (void *) register_address( |
| 1274 | ctxt->ss_base, c->regs[VCPU_REGS_RSP]); |
| 1275 | break; |
| 1276 | case 0x58 ... 0x5f: /* pop reg */ |
| 1277 | pop_instruction: |
| 1278 | if ((rc = ops->read_std(register_address(ctxt->ss_base, |
| 1279 | c->regs[VCPU_REGS_RSP]), c->dst.ptr, |
| 1280 | c->op_bytes, ctxt->vcpu)) != 0) |
| 1281 | goto done; |
| 1282 | |
| 1283 | register_address_increment(c->regs[VCPU_REGS_RSP], |
| 1284 | c->op_bytes); |
| 1285 | c->dst.type = OP_NONE; /* Disable writeback. */ |
| 1286 | break; |
| 1287 | case 0x63: /* movsxd */ |
| 1288 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
| 1289 | goto cannot_emulate; |
| 1290 | c->dst.val = (s32) c->src.val; |
| 1291 | break; |
| 1292 | case 0x80 ... 0x83: /* Grp1 */ |
| 1293 | switch (c->modrm_reg) { |
| 1294 | case 0: |
| 1295 | goto add; |
| 1296 | case 1: |
| 1297 | goto or; |
| 1298 | case 2: |
| 1299 | goto adc; |
| 1300 | case 3: |
| 1301 | goto sbb; |
| 1302 | case 4: |
| 1303 | goto and; |
| 1304 | case 5: |
| 1305 | goto sub; |
| 1306 | case 6: |
| 1307 | goto xor; |
| 1308 | case 7: |
| 1309 | goto cmp; |
| 1310 | } |
| 1311 | break; |
| 1312 | case 0x84 ... 0x85: |
| 1313 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
| 1314 | break; |
| 1315 | case 0x86 ... 0x87: /* xchg */ |
| 1316 | /* Write back the register source. */ |
| 1317 | switch (c->dst.bytes) { |
| 1318 | case 1: |
| 1319 | *(u8 *) c->src.ptr = (u8) c->dst.val; |
| 1320 | break; |
| 1321 | case 2: |
| 1322 | *(u16 *) c->src.ptr = (u16) c->dst.val; |
| 1323 | break; |
| 1324 | case 4: |
| 1325 | *c->src.ptr = (u32) c->dst.val; |
| 1326 | break; /* 64b reg: zero-extend */ |
| 1327 | case 8: |
| 1328 | *c->src.ptr = c->dst.val; |
| 1329 | break; |
| 1330 | } |
| 1331 | /* |
| 1332 | * Write back the memory destination with implicit LOCK |
| 1333 | * prefix. |
| 1334 | */ |
| 1335 | c->dst.val = c->src.val; |
| 1336 | c->lock_prefix = 1; |
| 1337 | break; |
| 1338 | case 0x88 ... 0x8b: /* mov */ |
| 1339 | goto mov; |
| 1340 | case 0x8d: /* lea r16/r32, m */ |
| 1341 | c->dst.val = c->modrm_val; |
| 1342 | break; |
| 1343 | case 0x8f: /* pop (sole member of Grp1a) */ |
| 1344 | rc = emulate_grp1a(ctxt, ops); |
| 1345 | if (rc != 0) |
| 1346 | goto done; |
| 1347 | break; |
| 1348 | case 0xa0 ... 0xa1: /* mov */ |
| 1349 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; |
| 1350 | c->dst.val = c->src.val; |
| 1351 | break; |
| 1352 | case 0xa2 ... 0xa3: /* mov */ |
| 1353 | c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX]; |
| 1354 | break; |
| 1355 | case 0xc0 ... 0xc1: |
| 1356 | emulate_grp2(ctxt); |
| 1357 | break; |
| 1358 | case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */ |
| 1359 | mov: |
| 1360 | c->dst.val = c->src.val; |
| 1361 | break; |
| 1362 | case 0xd0 ... 0xd1: /* Grp2 */ |
| 1363 | c->src.val = 1; |
| 1364 | emulate_grp2(ctxt); |
| 1365 | break; |
| 1366 | case 0xd2 ... 0xd3: /* Grp2 */ |
| 1367 | c->src.val = c->regs[VCPU_REGS_RCX]; |
| 1368 | emulate_grp2(ctxt); |
| 1369 | break; |
| 1370 | case 0xf6 ... 0xf7: /* Grp3 */ |
| 1371 | rc = emulate_grp3(ctxt, ops); |
| 1372 | if (rc != 0) |
| 1373 | goto done; |
| 1374 | break; |
| 1375 | case 0xfe ... 0xff: /* Grp4/Grp5 */ |
| 1376 | rc = emulate_grp45(ctxt, ops); |
| 1377 | if (rc != 0) |
| 1378 | goto done; |
| 1379 | break; |
| 1380 | } |
| 1381 | |
| 1382 | writeback: |
| 1383 | rc = writeback(ctxt, ops); |
| 1384 | if (rc != 0) |
| 1385 | goto done; |
| 1386 | |
| 1387 | /* Commit shadow register state. */ |
| 1388 | memcpy(ctxt->vcpu->regs, c->regs, sizeof c->regs); |
| 1389 | ctxt->vcpu->rip = c->eip; |
| 1390 | |
| 1391 | done: |
| 1392 | if (rc == X86EMUL_UNHANDLEABLE) { |
| 1393 | c->eip = saved_eip; |
| 1394 | return -1; |
| 1395 | } |
| 1396 | return 0; |
| 1397 | |
| 1398 | special_insn: |
| 1399 | if (c->twobyte) |
| 1400 | goto twobyte_special_insn; |
| 1401 | switch (c->b) { |
| 1402 | case 0x6a: /* push imm8 */ |
| 1403 | c->src.val = 0L; |
| 1404 | c->src.val = insn_fetch(s8, 1, c->eip); |
| 1405 | emulate_push(ctxt); |
| 1406 | break; |
| 1407 | case 0x6c: /* insb */ |
| 1408 | case 0x6d: /* insw/insd */ |
| 1409 | if (kvm_emulate_pio_string(ctxt->vcpu, NULL, |
| 1410 | 1, |
| 1411 | (c->d & ByteOp) ? 1 : c->op_bytes, |
| 1412 | c->rep_prefix ? |
| 1413 | address_mask(c->regs[VCPU_REGS_RCX]) : 1, |
| 1414 | (ctxt->eflags & EFLG_DF), |
| 1415 | register_address(ctxt->es_base, |
| 1416 | c->regs[VCPU_REGS_RDI]), |
| 1417 | c->rep_prefix, |
| 1418 | c->regs[VCPU_REGS_RDX]) == 0) { |
| 1419 | c->eip = saved_eip; |
| 1420 | return -1; |
| 1421 | } |
| 1422 | return 0; |
| 1423 | case 0x6e: /* outsb */ |
| 1424 | case 0x6f: /* outsw/outsd */ |
| 1425 | if (kvm_emulate_pio_string(ctxt->vcpu, NULL, |
| 1426 | 0, |
| 1427 | (c->d & ByteOp) ? 1 : c->op_bytes, |
| 1428 | c->rep_prefix ? |
| 1429 | address_mask(c->regs[VCPU_REGS_RCX]) : 1, |
| 1430 | (ctxt->eflags & EFLG_DF), |
| 1431 | register_address(c->override_base ? |
| 1432 | *c->override_base : |
| 1433 | ctxt->ds_base, |
| 1434 | c->regs[VCPU_REGS_RSI]), |
| 1435 | c->rep_prefix, |
| 1436 | c->regs[VCPU_REGS_RDX]) == 0) { |
| 1437 | c->eip = saved_eip; |
| 1438 | return -1; |
| 1439 | } |
| 1440 | return 0; |
| 1441 | case 0x70 ... 0x7f: /* jcc (short) */ { |
| 1442 | int rel = insn_fetch(s8, 1, c->eip); |
| 1443 | |
| 1444 | if (test_cc(c->b, ctxt->eflags)) |
| 1445 | JMP_REL(rel); |
| 1446 | break; |
| 1447 | } |
| 1448 | case 0x9c: /* pushf */ |
| 1449 | c->src.val = (unsigned long) ctxt->eflags; |
| 1450 | emulate_push(ctxt); |
| 1451 | break; |
| 1452 | case 0x9d: /* popf */ |
| 1453 | c->dst.ptr = (unsigned long *) &ctxt->eflags; |
| 1454 | goto pop_instruction; |
| 1455 | case 0xc3: /* ret */ |
| 1456 | c->dst.ptr = &c->eip; |
| 1457 | goto pop_instruction; |
| 1458 | case 0xf4: /* hlt */ |
| 1459 | ctxt->vcpu->halt_request = 1; |
| 1460 | goto done; |
| 1461 | case 0xf5: /* cmc */ |
| 1462 | /* complement carry flag from eflags reg */ |
| 1463 | ctxt->eflags ^= EFLG_CF; |
| 1464 | c->dst.type = OP_NONE; /* Disable writeback. */ |
| 1465 | break; |
| 1466 | case 0xf8: /* clc */ |
| 1467 | ctxt->eflags &= ~EFLG_CF; |
| 1468 | c->dst.type = OP_NONE; /* Disable writeback. */ |
| 1469 | break; |
| 1470 | case 0xfa: /* cli */ |
| 1471 | ctxt->eflags &= ~X86_EFLAGS_IF; |
| 1472 | c->dst.type = OP_NONE; /* Disable writeback. */ |
| 1473 | break; |
| 1474 | case 0xfb: /* sti */ |
| 1475 | ctxt->eflags |= X86_EFLAGS_IF; |
| 1476 | c->dst.type = OP_NONE; /* Disable writeback. */ |
| 1477 | break; |
| 1478 | } |
| 1479 | if (c->rep_prefix) { |
| 1480 | if (c->regs[VCPU_REGS_RCX] == 0) { |
| 1481 | ctxt->vcpu->rip = c->eip; |
| 1482 | goto done; |
| 1483 | } |
| 1484 | c->regs[VCPU_REGS_RCX]--; |
| 1485 | c->eip = ctxt->vcpu->rip; |
| 1486 | } |
| 1487 | switch (c->b) { |
| 1488 | case 0xa4 ... 0xa5: /* movs */ |
| 1489 | c->dst.type = OP_MEM; |
| 1490 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; |
| 1491 | c->dst.ptr = (unsigned long *)register_address( |
| 1492 | ctxt->es_base, |
| 1493 | c->regs[VCPU_REGS_RDI]); |
| 1494 | if ((rc = ops->read_emulated(register_address( |
| 1495 | c->override_base ? *c->override_base : |
| 1496 | ctxt->ds_base, |
| 1497 | c->regs[VCPU_REGS_RSI]), |
| 1498 | &c->dst.val, |
| 1499 | c->dst.bytes, ctxt->vcpu)) != 0) |
| 1500 | goto done; |
| 1501 | register_address_increment(c->regs[VCPU_REGS_RSI], |
| 1502 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
| 1503 | : c->dst.bytes); |
| 1504 | register_address_increment(c->regs[VCPU_REGS_RDI], |
| 1505 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
| 1506 | : c->dst.bytes); |
| 1507 | break; |
| 1508 | case 0xa6 ... 0xa7: /* cmps */ |
| 1509 | DPRINTF("Urk! I don't handle CMPS.\n"); |
| 1510 | goto cannot_emulate; |
| 1511 | case 0xaa ... 0xab: /* stos */ |
| 1512 | c->dst.type = OP_MEM; |
| 1513 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; |
| 1514 | c->dst.ptr = (unsigned long *)cr2; |
| 1515 | c->dst.val = c->regs[VCPU_REGS_RAX]; |
| 1516 | register_address_increment(c->regs[VCPU_REGS_RDI], |
| 1517 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
| 1518 | : c->dst.bytes); |
| 1519 | break; |
| 1520 | case 0xac ... 0xad: /* lods */ |
| 1521 | c->dst.type = OP_REG; |
| 1522 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; |
| 1523 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; |
| 1524 | if ((rc = ops->read_emulated(cr2, &c->dst.val, |
| 1525 | c->dst.bytes, |
| 1526 | ctxt->vcpu)) != 0) |
| 1527 | goto done; |
| 1528 | register_address_increment(c->regs[VCPU_REGS_RSI], |
| 1529 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
| 1530 | : c->dst.bytes); |
| 1531 | break; |
| 1532 | case 0xae ... 0xaf: /* scas */ |
| 1533 | DPRINTF("Urk! I don't handle SCAS.\n"); |
| 1534 | goto cannot_emulate; |
| 1535 | case 0xe8: /* call (near) */ { |
| 1536 | long int rel; |
| 1537 | switch (c->op_bytes) { |
| 1538 | case 2: |
| 1539 | rel = insn_fetch(s16, 2, c->eip); |
| 1540 | break; |
| 1541 | case 4: |
| 1542 | rel = insn_fetch(s32, 4, c->eip); |
| 1543 | break; |
| 1544 | case 8: |
| 1545 | rel = insn_fetch(s64, 8, c->eip); |
| 1546 | break; |
| 1547 | default: |
| 1548 | DPRINTF("Call: Invalid op_bytes\n"); |
| 1549 | goto cannot_emulate; |
| 1550 | } |
| 1551 | c->src.val = (unsigned long) c->eip; |
| 1552 | JMP_REL(rel); |
| 1553 | c->op_bytes = c->ad_bytes; |
| 1554 | emulate_push(ctxt); |
| 1555 | break; |
| 1556 | } |
| 1557 | case 0xe9: /* jmp rel */ |
| 1558 | case 0xeb: /* jmp rel short */ |
| 1559 | JMP_REL(c->src.val); |
| 1560 | c->dst.type = OP_NONE; /* Disable writeback. */ |
| 1561 | break; |
| 1562 | |
| 1563 | |
| 1564 | } |
| 1565 | goto writeback; |
| 1566 | |
| 1567 | twobyte_insn: |
| 1568 | switch (c->b) { |
| 1569 | case 0x01: /* lgdt, lidt, lmsw */ |
| 1570 | switch (c->modrm_reg) { |
| 1571 | u16 size; |
| 1572 | unsigned long address; |
| 1573 | |
| 1574 | case 0: /* vmcall */ |
| 1575 | if (c->modrm_mod != 3 || c->modrm_rm != 1) |
| 1576 | goto cannot_emulate; |
| 1577 | |
| 1578 | rc = kvm_fix_hypercall(ctxt->vcpu); |
| 1579 | if (rc) |
| 1580 | goto done; |
| 1581 | |
| 1582 | kvm_emulate_hypercall(ctxt->vcpu); |
| 1583 | break; |
| 1584 | case 2: /* lgdt */ |
| 1585 | rc = read_descriptor(ctxt, ops, c->src.ptr, |
| 1586 | &size, &address, c->op_bytes); |
| 1587 | if (rc) |
| 1588 | goto done; |
| 1589 | realmode_lgdt(ctxt->vcpu, size, address); |
| 1590 | break; |
| 1591 | case 3: /* lidt/vmmcall */ |
| 1592 | if (c->modrm_mod == 3 && c->modrm_rm == 1) { |
| 1593 | rc = kvm_fix_hypercall(ctxt->vcpu); |
| 1594 | if (rc) |
| 1595 | goto done; |
| 1596 | kvm_emulate_hypercall(ctxt->vcpu); |
| 1597 | } else { |
| 1598 | rc = read_descriptor(ctxt, ops, c->src.ptr, |
| 1599 | &size, &address, |
| 1600 | c->op_bytes); |
| 1601 | if (rc) |
| 1602 | goto done; |
| 1603 | realmode_lidt(ctxt->vcpu, size, address); |
| 1604 | } |
| 1605 | break; |
| 1606 | case 4: /* smsw */ |
| 1607 | if (c->modrm_mod != 3) |
| 1608 | goto cannot_emulate; |
| 1609 | *(u16 *)&c->regs[c->modrm_rm] |
| 1610 | = realmode_get_cr(ctxt->vcpu, 0); |
| 1611 | break; |
| 1612 | case 6: /* lmsw */ |
| 1613 | if (c->modrm_mod != 3) |
| 1614 | goto cannot_emulate; |
| 1615 | realmode_lmsw(ctxt->vcpu, (u16)c->modrm_val, |
| 1616 | &ctxt->eflags); |
| 1617 | break; |
| 1618 | case 7: /* invlpg*/ |
| 1619 | emulate_invlpg(ctxt->vcpu, cr2); |
| 1620 | break; |
| 1621 | default: |
| 1622 | goto cannot_emulate; |
| 1623 | } |
| 1624 | /* Disable writeback. */ |
| 1625 | c->dst.type = OP_NONE; |
| 1626 | break; |
| 1627 | case 0x21: /* mov from dr to reg */ |
| 1628 | if (c->modrm_mod != 3) |
| 1629 | goto cannot_emulate; |
| 1630 | rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]); |
| 1631 | if (rc) |
| 1632 | goto cannot_emulate; |
| 1633 | c->dst.type = OP_NONE; /* no writeback */ |
| 1634 | break; |
| 1635 | case 0x23: /* mov from reg to dr */ |
| 1636 | if (c->modrm_mod != 3) |
| 1637 | goto cannot_emulate; |
| 1638 | rc = emulator_set_dr(ctxt, c->modrm_reg, |
| 1639 | c->regs[c->modrm_rm]); |
| 1640 | if (rc) |
| 1641 | goto cannot_emulate; |
| 1642 | c->dst.type = OP_NONE; /* no writeback */ |
| 1643 | break; |
| 1644 | case 0x40 ... 0x4f: /* cmov */ |
| 1645 | c->dst.val = c->dst.orig_val = c->src.val; |
| 1646 | if (!test_cc(c->b, ctxt->eflags)) |
| 1647 | c->dst.type = OP_NONE; /* no writeback */ |
| 1648 | break; |
| 1649 | case 0xa3: |
| 1650 | bt: /* bt */ |
| 1651 | c->dst.type = OP_NONE; |
| 1652 | /* only subword offset */ |
| 1653 | c->src.val &= (c->dst.bytes << 3) - 1; |
| 1654 | emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags); |
| 1655 | break; |
| 1656 | case 0xab: |
| 1657 | bts: /* bts */ |
| 1658 | /* only subword offset */ |
| 1659 | c->src.val &= (c->dst.bytes << 3) - 1; |
| 1660 | emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags); |
| 1661 | break; |
| 1662 | case 0xb0 ... 0xb1: /* cmpxchg */ |
| 1663 | /* |
| 1664 | * Save real source value, then compare EAX against |
| 1665 | * destination. |
| 1666 | */ |
| 1667 | c->src.orig_val = c->src.val; |
| 1668 | c->src.val = c->regs[VCPU_REGS_RAX]; |
| 1669 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
| 1670 | if (ctxt->eflags & EFLG_ZF) { |
| 1671 | /* Success: write back to memory. */ |
| 1672 | c->dst.val = c->src.orig_val; |
| 1673 | } else { |
| 1674 | /* Failure: write the value we saw to EAX. */ |
| 1675 | c->dst.type = OP_REG; |
| 1676 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; |
| 1677 | } |
| 1678 | break; |
| 1679 | case 0xb3: |
| 1680 | btr: /* btr */ |
| 1681 | /* only subword offset */ |
| 1682 | c->src.val &= (c->dst.bytes << 3) - 1; |
| 1683 | emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags); |
| 1684 | break; |
| 1685 | case 0xb6 ... 0xb7: /* movzx */ |
| 1686 | c->dst.bytes = c->op_bytes; |
| 1687 | c->dst.val = (c->d & ByteOp) ? (u8) c->src.val |
| 1688 | : (u16) c->src.val; |
| 1689 | break; |
| 1690 | case 0xba: /* Grp8 */ |
| 1691 | switch (c->modrm_reg & 3) { |
| 1692 | case 0: |
| 1693 | goto bt; |
| 1694 | case 1: |
| 1695 | goto bts; |
| 1696 | case 2: |
| 1697 | goto btr; |
| 1698 | case 3: |
| 1699 | goto btc; |
| 1700 | } |
| 1701 | break; |
| 1702 | case 0xbb: |
| 1703 | btc: /* btc */ |
| 1704 | /* only subword offset */ |
| 1705 | c->src.val &= (c->dst.bytes << 3) - 1; |
| 1706 | emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags); |
| 1707 | break; |
| 1708 | case 0xbe ... 0xbf: /* movsx */ |
| 1709 | c->dst.bytes = c->op_bytes; |
| 1710 | c->dst.val = (c->d & ByteOp) ? (s8) c->src.val : |
| 1711 | (s16) c->src.val; |
| 1712 | break; |
| 1713 | case 0xc3: /* movnti */ |
| 1714 | c->dst.bytes = c->op_bytes; |
| 1715 | c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val : |
| 1716 | (u64) c->src.val; |
| 1717 | break; |
| 1718 | } |
| 1719 | goto writeback; |
| 1720 | |
| 1721 | twobyte_special_insn: |
| 1722 | switch (c->b) { |
| 1723 | case 0x06: |
| 1724 | emulate_clts(ctxt->vcpu); |
| 1725 | break; |
| 1726 | case 0x08: /* invd */ |
| 1727 | break; |
| 1728 | case 0x09: /* wbinvd */ |
| 1729 | break; |
| 1730 | case 0x0d: /* GrpP (prefetch) */ |
| 1731 | case 0x18: /* Grp16 (prefetch/nop) */ |
| 1732 | break; |
| 1733 | case 0x20: /* mov cr, reg */ |
| 1734 | if (c->modrm_mod != 3) |
| 1735 | goto cannot_emulate; |
| 1736 | c->regs[c->modrm_rm] = |
| 1737 | realmode_get_cr(ctxt->vcpu, c->modrm_reg); |
| 1738 | break; |
| 1739 | case 0x22: /* mov reg, cr */ |
| 1740 | if (c->modrm_mod != 3) |
| 1741 | goto cannot_emulate; |
| 1742 | realmode_set_cr(ctxt->vcpu, |
| 1743 | c->modrm_reg, c->modrm_val, &ctxt->eflags); |
| 1744 | break; |
| 1745 | case 0x30: |
| 1746 | /* wrmsr */ |
| 1747 | msr_data = (u32)c->regs[VCPU_REGS_RAX] |
| 1748 | | ((u64)c->regs[VCPU_REGS_RDX] << 32); |
| 1749 | rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data); |
| 1750 | if (rc) { |
| 1751 | kvm_x86_ops->inject_gp(ctxt->vcpu, 0); |
| 1752 | c->eip = ctxt->vcpu->rip; |
| 1753 | } |
| 1754 | rc = X86EMUL_CONTINUE; |
| 1755 | break; |
| 1756 | case 0x32: |
| 1757 | /* rdmsr */ |
| 1758 | rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data); |
| 1759 | if (rc) { |
| 1760 | kvm_x86_ops->inject_gp(ctxt->vcpu, 0); |
| 1761 | c->eip = ctxt->vcpu->rip; |
| 1762 | } else { |
| 1763 | c->regs[VCPU_REGS_RAX] = (u32)msr_data; |
| 1764 | c->regs[VCPU_REGS_RDX] = msr_data >> 32; |
| 1765 | } |
| 1766 | rc = X86EMUL_CONTINUE; |
| 1767 | break; |
| 1768 | case 0x80 ... 0x8f: /* jnz rel, etc*/ { |
| 1769 | long int rel; |
| 1770 | |
| 1771 | switch (c->op_bytes) { |
| 1772 | case 2: |
| 1773 | rel = insn_fetch(s16, 2, c->eip); |
| 1774 | break; |
| 1775 | case 4: |
| 1776 | rel = insn_fetch(s32, 4, c->eip); |
| 1777 | break; |
| 1778 | case 8: |
| 1779 | rel = insn_fetch(s64, 8, c->eip); |
| 1780 | break; |
| 1781 | default: |
| 1782 | DPRINTF("jnz: Invalid op_bytes\n"); |
| 1783 | goto cannot_emulate; |
| 1784 | } |
| 1785 | if (test_cc(c->b, ctxt->eflags)) |
| 1786 | JMP_REL(rel); |
| 1787 | break; |
| 1788 | } |
| 1789 | case 0xc7: /* Grp9 (cmpxchg8b) */ |
| 1790 | rc = emulate_grp9(ctxt, ops, cr2); |
| 1791 | if (rc != 0) |
| 1792 | goto done; |
| 1793 | break; |
| 1794 | } |
| 1795 | /* Disable writeback. */ |
| 1796 | c->dst.type = OP_NONE; |
| 1797 | goto writeback; |
| 1798 | |
| 1799 | cannot_emulate: |
| 1800 | DPRINTF("Cannot emulate %02x\n", c->b); |
| 1801 | c->eip = saved_eip; |
| 1802 | return -1; |
| 1803 | } |