| 1 | /* |
| 2 | * Linux-DVB Driver for DiBcom's DiB9000 and demodulator-family. |
| 3 | * |
| 4 | * Copyright (C) 2005-10 DiBcom (http://www.dibcom.fr/) |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation, version 2. |
| 9 | */ |
| 10 | #include <linux/kernel.h> |
| 11 | #include <linux/i2c.h> |
| 12 | #include <linux/mutex.h> |
| 13 | |
| 14 | #include "dvb_math.h" |
| 15 | #include "dvb_frontend.h" |
| 16 | |
| 17 | #include "dib9000.h" |
| 18 | #include "dibx000_common.h" |
| 19 | |
| 20 | static int debug; |
| 21 | module_param(debug, int, 0644); |
| 22 | MODULE_PARM_DESC(debug, "turn on debugging (default: 0)"); |
| 23 | |
| 24 | #define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB9000: "); printk(args); printk("\n"); } } while (0) |
| 25 | #define MAX_NUMBER_OF_FRONTENDS 6 |
| 26 | |
| 27 | struct i2c_device { |
| 28 | struct i2c_adapter *i2c_adap; |
| 29 | u8 i2c_addr; |
| 30 | }; |
| 31 | |
| 32 | /* lock */ |
| 33 | #define DIB_LOCK struct mutex |
| 34 | #define DibAcquireLock(lock) do { if (mutex_lock_interruptible(lock) < 0) dprintk("could not get the lock"); } while (0) |
| 35 | #define DibReleaseLock(lock) mutex_unlock(lock) |
| 36 | #define DibInitLock(lock) mutex_init(lock) |
| 37 | #define DibFreeLock(lock) |
| 38 | |
| 39 | struct dib9000_state { |
| 40 | struct i2c_device i2c; |
| 41 | |
| 42 | struct dibx000_i2c_master i2c_master; |
| 43 | struct i2c_adapter tuner_adap; |
| 44 | struct i2c_adapter component_bus; |
| 45 | |
| 46 | u16 revision; |
| 47 | u8 reg_offs; |
| 48 | |
| 49 | enum frontend_tune_state tune_state; |
| 50 | u32 status; |
| 51 | struct dvb_frontend_parametersContext channel_status; |
| 52 | |
| 53 | u8 fe_id; |
| 54 | |
| 55 | #define DIB9000_GPIO_DEFAULT_DIRECTIONS 0xffff |
| 56 | u16 gpio_dir; |
| 57 | #define DIB9000_GPIO_DEFAULT_VALUES 0x0000 |
| 58 | u16 gpio_val; |
| 59 | #define DIB9000_GPIO_DEFAULT_PWM_POS 0xffff |
| 60 | u16 gpio_pwm_pos; |
| 61 | |
| 62 | union { /* common for all chips */ |
| 63 | struct { |
| 64 | u8 mobile_mode:1; |
| 65 | } host; |
| 66 | |
| 67 | struct { |
| 68 | struct dib9000_fe_memory_map { |
| 69 | u16 addr; |
| 70 | u16 size; |
| 71 | } fe_mm[18]; |
| 72 | u8 memcmd; |
| 73 | |
| 74 | DIB_LOCK mbx_if_lock; /* to protect read/write operations */ |
| 75 | DIB_LOCK mbx_lock; /* to protect the whole mailbox handling */ |
| 76 | |
| 77 | DIB_LOCK mem_lock; /* to protect the memory accesses */ |
| 78 | DIB_LOCK mem_mbx_lock; /* to protect the memory-based mailbox */ |
| 79 | |
| 80 | #define MBX_MAX_WORDS (256 - 200 - 2) |
| 81 | #define DIB9000_MSG_CACHE_SIZE 2 |
| 82 | u16 message_cache[DIB9000_MSG_CACHE_SIZE][MBX_MAX_WORDS]; |
| 83 | u8 fw_is_running; |
| 84 | } risc; |
| 85 | } platform; |
| 86 | |
| 87 | union { /* common for all platforms */ |
| 88 | struct { |
| 89 | struct dib9000_config cfg; |
| 90 | } d9; |
| 91 | } chip; |
| 92 | |
| 93 | struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS]; |
| 94 | u16 component_bus_speed; |
| 95 | }; |
| 96 | |
| 97 | u32 fe_info[44] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 98 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 99 | 0, 0, 0 |
| 100 | }; |
| 101 | |
| 102 | enum dib9000_power_mode { |
| 103 | DIB9000_POWER_ALL = 0, |
| 104 | |
| 105 | DIB9000_POWER_NO, |
| 106 | DIB9000_POWER_INTERF_ANALOG_AGC, |
| 107 | DIB9000_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD, |
| 108 | DIB9000_POWER_COR4_CRY_ESRAM_MOUT_NUD, |
| 109 | DIB9000_POWER_INTERFACE_ONLY, |
| 110 | }; |
| 111 | |
| 112 | enum dib9000_out_messages { |
| 113 | OUT_MSG_HBM_ACK, |
| 114 | OUT_MSG_HOST_BUF_FAIL, |
| 115 | OUT_MSG_REQ_VERSION, |
| 116 | OUT_MSG_BRIDGE_I2C_W, |
| 117 | OUT_MSG_BRIDGE_I2C_R, |
| 118 | OUT_MSG_BRIDGE_APB_W, |
| 119 | OUT_MSG_BRIDGE_APB_R, |
| 120 | OUT_MSG_SCAN_CHANNEL, |
| 121 | OUT_MSG_MONIT_DEMOD, |
| 122 | OUT_MSG_CONF_GPIO, |
| 123 | OUT_MSG_DEBUG_HELP, |
| 124 | OUT_MSG_SUBBAND_SEL, |
| 125 | OUT_MSG_ENABLE_TIME_SLICE, |
| 126 | OUT_MSG_FE_FW_DL, |
| 127 | OUT_MSG_FE_CHANNEL_SEARCH, |
| 128 | OUT_MSG_FE_CHANNEL_TUNE, |
| 129 | OUT_MSG_FE_SLEEP, |
| 130 | OUT_MSG_FE_SYNC, |
| 131 | OUT_MSG_CTL_MONIT, |
| 132 | |
| 133 | OUT_MSG_CONF_SVC, |
| 134 | OUT_MSG_SET_HBM, |
| 135 | OUT_MSG_INIT_DEMOD, |
| 136 | OUT_MSG_ENABLE_DIVERSITY, |
| 137 | OUT_MSG_SET_OUTPUT_MODE, |
| 138 | OUT_MSG_SET_PRIORITARY_CHANNEL, |
| 139 | OUT_MSG_ACK_FRG, |
| 140 | OUT_MSG_INIT_PMU, |
| 141 | }; |
| 142 | |
| 143 | enum dib9000_in_messages { |
| 144 | IN_MSG_DATA, |
| 145 | IN_MSG_FRAME_INFO, |
| 146 | IN_MSG_CTL_MONIT, |
| 147 | IN_MSG_ACK_FREE_ITEM, |
| 148 | IN_MSG_DEBUG_BUF, |
| 149 | IN_MSG_MPE_MONITOR, |
| 150 | IN_MSG_RAWTS_MONITOR, |
| 151 | IN_MSG_END_BRIDGE_I2C_RW, |
| 152 | IN_MSG_END_BRIDGE_APB_RW, |
| 153 | IN_MSG_VERSION, |
| 154 | IN_MSG_END_OF_SCAN, |
| 155 | IN_MSG_MONIT_DEMOD, |
| 156 | IN_MSG_ERROR, |
| 157 | IN_MSG_FE_FW_DL_DONE, |
| 158 | IN_MSG_EVENT, |
| 159 | IN_MSG_ACK_CHANGE_SVC, |
| 160 | IN_MSG_HBM_PROF, |
| 161 | }; |
| 162 | |
| 163 | /* memory_access requests */ |
| 164 | #define FE_MM_W_CHANNEL 0 |
| 165 | #define FE_MM_W_FE_INFO 1 |
| 166 | #define FE_MM_RW_SYNC 2 |
| 167 | |
| 168 | #define FE_SYNC_CHANNEL 1 |
| 169 | #define FE_SYNC_W_GENERIC_MONIT 2 |
| 170 | #define FE_SYNC_COMPONENT_ACCESS 3 |
| 171 | |
| 172 | #define FE_MM_R_CHANNEL_SEARCH_STATE 3 |
| 173 | #define FE_MM_R_CHANNEL_UNION_CONTEXT 4 |
| 174 | #define FE_MM_R_FE_INFO 5 |
| 175 | #define FE_MM_R_FE_MONITOR 6 |
| 176 | |
| 177 | #define FE_MM_W_CHANNEL_HEAD 7 |
| 178 | #define FE_MM_W_CHANNEL_UNION 8 |
| 179 | #define FE_MM_W_CHANNEL_CONTEXT 9 |
| 180 | #define FE_MM_R_CHANNEL_UNION 10 |
| 181 | #define FE_MM_R_CHANNEL_CONTEXT 11 |
| 182 | #define FE_MM_R_CHANNEL_TUNE_STATE 12 |
| 183 | |
| 184 | #define FE_MM_R_GENERIC_MONITORING_SIZE 13 |
| 185 | #define FE_MM_W_GENERIC_MONITORING 14 |
| 186 | #define FE_MM_R_GENERIC_MONITORING 15 |
| 187 | |
| 188 | #define FE_MM_W_COMPONENT_ACCESS 16 |
| 189 | #define FE_MM_RW_COMPONENT_ACCESS_BUFFER 17 |
| 190 | static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen, u8 * b, u32 len); |
| 191 | static int dib9000_risc_apb_access_write(struct dib9000_state *state, u32 address, u16 attribute, const u8 * b, u32 len); |
| 192 | |
| 193 | static u16 to_fw_output_mode(u16 mode) |
| 194 | { |
| 195 | switch (mode) { |
| 196 | case OUTMODE_HIGH_Z: |
| 197 | return 0; |
| 198 | case OUTMODE_MPEG2_PAR_GATED_CLK: |
| 199 | return 4; |
| 200 | case OUTMODE_MPEG2_PAR_CONT_CLK: |
| 201 | return 8; |
| 202 | case OUTMODE_MPEG2_SERIAL: |
| 203 | return 16; |
| 204 | case OUTMODE_DIVERSITY: |
| 205 | return 128; |
| 206 | case OUTMODE_MPEG2_FIFO: |
| 207 | return 2; |
| 208 | case OUTMODE_ANALOG_ADC: |
| 209 | return 1; |
| 210 | default: |
| 211 | return 0; |
| 212 | } |
| 213 | } |
| 214 | |
| 215 | static u16 dib9000_read16_attr(struct dib9000_state *state, u16 reg, u8 * b, u32 len, u16 attribute) |
| 216 | { |
| 217 | u32 chunk_size = 126; |
| 218 | u32 l; |
| 219 | int ret; |
| 220 | u8 wb[2] = { reg >> 8, reg & 0xff }; |
| 221 | struct i2c_msg msg[2] = { |
| 222 | {.addr = state->i2c.i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2}, |
| 223 | {.addr = state->i2c.i2c_addr >> 1, .flags = I2C_M_RD, .buf = b, .len = len}, |
| 224 | }; |
| 225 | |
| 226 | if (state->platform.risc.fw_is_running && (reg < 1024)) |
| 227 | return dib9000_risc_apb_access_read(state, reg, attribute, NULL, 0, b, len); |
| 228 | |
| 229 | if (attribute & DATA_BUS_ACCESS_MODE_8BIT) |
| 230 | wb[0] |= (1 << 5); |
| 231 | if (attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT) |
| 232 | wb[0] |= (1 << 4); |
| 233 | |
| 234 | do { |
| 235 | l = len < chunk_size ? len : chunk_size; |
| 236 | msg[1].len = l; |
| 237 | msg[1].buf = b; |
| 238 | ret = i2c_transfer(state->i2c.i2c_adap, msg, 2) != 2 ? -EREMOTEIO : 0; |
| 239 | if (ret != 0) { |
| 240 | dprintk("i2c read error on %d", reg); |
| 241 | return -EREMOTEIO; |
| 242 | } |
| 243 | |
| 244 | b += l; |
| 245 | len -= l; |
| 246 | |
| 247 | if (!(attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)) |
| 248 | reg += l / 2; |
| 249 | } while ((ret == 0) && len); |
| 250 | |
| 251 | return 0; |
| 252 | } |
| 253 | |
| 254 | static u16 dib9000_i2c_read16(struct i2c_device *i2c, u16 reg) |
| 255 | { |
| 256 | u8 b[2]; |
| 257 | u8 wb[2] = { reg >> 8, reg & 0xff }; |
| 258 | struct i2c_msg msg[2] = { |
| 259 | {.addr = i2c->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2}, |
| 260 | {.addr = i2c->i2c_addr >> 1, .flags = I2C_M_RD, .buf = b, .len = 2}, |
| 261 | }; |
| 262 | |
| 263 | if (i2c_transfer(i2c->i2c_adap, msg, 2) != 2) { |
| 264 | dprintk("read register %x error", reg); |
| 265 | return 0; |
| 266 | } |
| 267 | |
| 268 | return (b[0] << 8) | b[1]; |
| 269 | } |
| 270 | |
| 271 | static inline u16 dib9000_read_word(struct dib9000_state *state, u16 reg) |
| 272 | { |
| 273 | u8 b[2]; |
| 274 | if (dib9000_read16_attr(state, reg, b, 2, 0) != 0) |
| 275 | return 0; |
| 276 | return (b[0] << 8 | b[1]); |
| 277 | } |
| 278 | |
| 279 | static inline u16 dib9000_read_word_attr(struct dib9000_state *state, u16 reg, u16 attribute) |
| 280 | { |
| 281 | u8 b[2]; |
| 282 | if (dib9000_read16_attr(state, reg, b, 2, attribute) != 0) |
| 283 | return 0; |
| 284 | return (b[0] << 8 | b[1]); |
| 285 | } |
| 286 | |
| 287 | #define dib9000_read16_noinc_attr(state, reg, b, len, attribute) dib9000_read16_attr(state, reg, b, len, (attribute) | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT) |
| 288 | |
| 289 | static u16 dib9000_write16_attr(struct dib9000_state *state, u16 reg, const u8 * buf, u32 len, u16 attribute) |
| 290 | { |
| 291 | u8 b[255]; |
| 292 | u32 chunk_size = 126; |
| 293 | u32 l; |
| 294 | int ret; |
| 295 | |
| 296 | struct i2c_msg msg = { |
| 297 | .addr = state->i2c.i2c_addr >> 1, .flags = 0, .buf = b, .len = len + 2 |
| 298 | }; |
| 299 | |
| 300 | if (state->platform.risc.fw_is_running && (reg < 1024)) { |
| 301 | if (dib9000_risc_apb_access_write |
| 302 | (state, reg, DATA_BUS_ACCESS_MODE_16BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | attribute, buf, len) != 0) |
| 303 | return -EINVAL; |
| 304 | return 0; |
| 305 | } |
| 306 | |
| 307 | b[0] = (reg >> 8) & 0xff; |
| 308 | b[1] = (reg) & 0xff; |
| 309 | |
| 310 | if (attribute & DATA_BUS_ACCESS_MODE_8BIT) |
| 311 | b[0] |= (1 << 5); |
| 312 | if (attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT) |
| 313 | b[0] |= (1 << 4); |
| 314 | |
| 315 | do { |
| 316 | l = len < chunk_size ? len : chunk_size; |
| 317 | msg.len = l + 2; |
| 318 | memcpy(&b[2], buf, l); |
| 319 | |
| 320 | ret = i2c_transfer(state->i2c.i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0; |
| 321 | |
| 322 | buf += l; |
| 323 | len -= l; |
| 324 | |
| 325 | if (!(attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)) |
| 326 | reg += l / 2; |
| 327 | } while ((ret == 0) && len); |
| 328 | |
| 329 | return ret; |
| 330 | } |
| 331 | |
| 332 | static int dib9000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val) |
| 333 | { |
| 334 | u8 b[4] = { (reg >> 8) & 0xff, reg & 0xff, (val >> 8) & 0xff, val & 0xff }; |
| 335 | struct i2c_msg msg = { |
| 336 | .addr = i2c->i2c_addr >> 1, .flags = 0, .buf = b, .len = 4 |
| 337 | }; |
| 338 | |
| 339 | return i2c_transfer(i2c->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0; |
| 340 | } |
| 341 | |
| 342 | static inline int dib9000_write_word(struct dib9000_state *state, u16 reg, u16 val) |
| 343 | { |
| 344 | u8 b[2] = { val >> 8, val & 0xff }; |
| 345 | return dib9000_write16_attr(state, reg, b, 2, 0); |
| 346 | } |
| 347 | |
| 348 | static inline int dib9000_write_word_attr(struct dib9000_state *state, u16 reg, u16 val, u16 attribute) |
| 349 | { |
| 350 | u8 b[2] = { val >> 8, val & 0xff }; |
| 351 | return dib9000_write16_attr(state, reg, b, 2, attribute); |
| 352 | } |
| 353 | |
| 354 | #define dib9000_write(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, 0) |
| 355 | #define dib9000_write16_noinc(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT) |
| 356 | #define dib9000_write16_noinc_attr(state, reg, buf, len, attribute) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | (attribute)) |
| 357 | |
| 358 | #define dib9000_mbx_send(state, id, data, len) dib9000_mbx_send_attr(state, id, data, len, 0) |
| 359 | #define dib9000_mbx_get_message(state, id, msg, len) dib9000_mbx_get_message_attr(state, id, msg, len, 0) |
| 360 | |
| 361 | #define MAC_IRQ (1 << 1) |
| 362 | #define IRQ_POL_MSK (1 << 4) |
| 363 | |
| 364 | #define dib9000_risc_mem_read_chunks(state, b, len) dib9000_read16_attr(state, 1063, b, len, DATA_BUS_ACCESS_MODE_8BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT) |
| 365 | #define dib9000_risc_mem_write_chunks(state, buf, len) dib9000_write16_attr(state, 1063, buf, len, DATA_BUS_ACCESS_MODE_8BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT) |
| 366 | |
| 367 | static void dib9000_risc_mem_setup_cmd(struct dib9000_state *state, u32 addr, u32 len, u8 reading) |
| 368 | { |
| 369 | u8 b[14] = { 0 }; |
| 370 | |
| 371 | /* dprintk("%d memcmd: %d %d %d\n", state->fe_id, addr, addr+len, len); */ |
| 372 | /* b[0] = 0 << 7; */ |
| 373 | b[1] = 1; |
| 374 | |
| 375 | /* b[2] = 0; */ |
| 376 | /* b[3] = 0; */ |
| 377 | b[4] = (u8) (addr >> 8); |
| 378 | b[5] = (u8) (addr & 0xff); |
| 379 | |
| 380 | /* b[10] = 0; */ |
| 381 | /* b[11] = 0; */ |
| 382 | b[12] = (u8) (addr >> 8); |
| 383 | b[13] = (u8) (addr & 0xff); |
| 384 | |
| 385 | addr += len; |
| 386 | /* b[6] = 0; */ |
| 387 | /* b[7] = 0; */ |
| 388 | b[8] = (u8) (addr >> 8); |
| 389 | b[9] = (u8) (addr & 0xff); |
| 390 | |
| 391 | dib9000_write(state, 1056, b, 14); |
| 392 | if (reading) |
| 393 | dib9000_write_word(state, 1056, (1 << 15) | 1); |
| 394 | state->platform.risc.memcmd = -1; /* if it was called directly reset it - to force a future setup-call to set it */ |
| 395 | } |
| 396 | |
| 397 | static void dib9000_risc_mem_setup(struct dib9000_state *state, u8 cmd) |
| 398 | { |
| 399 | struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd & 0x7f]; |
| 400 | /* decide whether we need to "refresh" the memory controller */ |
| 401 | if (state->platform.risc.memcmd == cmd && /* same command */ |
| 402 | !(cmd & 0x80 && m->size < 67)) /* and we do not want to read something with less than 67 bytes looping - working around a bug in the memory controller */ |
| 403 | return; |
| 404 | dib9000_risc_mem_setup_cmd(state, m->addr, m->size, cmd & 0x80); |
| 405 | state->platform.risc.memcmd = cmd; |
| 406 | } |
| 407 | |
| 408 | static int dib9000_risc_mem_read(struct dib9000_state *state, u8 cmd, u8 * b, u16 len) |
| 409 | { |
| 410 | if (!state->platform.risc.fw_is_running) |
| 411 | return -EIO; |
| 412 | |
| 413 | DibAcquireLock(&state->platform.risc.mem_lock); |
| 414 | dib9000_risc_mem_setup(state, cmd | 0x80); |
| 415 | dib9000_risc_mem_read_chunks(state, b, len); |
| 416 | DibReleaseLock(&state->platform.risc.mem_lock); |
| 417 | return 0; |
| 418 | } |
| 419 | |
| 420 | static int dib9000_risc_mem_write(struct dib9000_state *state, u8 cmd, const u8 * b) |
| 421 | { |
| 422 | struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd]; |
| 423 | if (!state->platform.risc.fw_is_running) |
| 424 | return -EIO; |
| 425 | |
| 426 | DibAcquireLock(&state->platform.risc.mem_lock); |
| 427 | dib9000_risc_mem_setup(state, cmd); |
| 428 | dib9000_risc_mem_write_chunks(state, b, m->size); |
| 429 | DibReleaseLock(&state->platform.risc.mem_lock); |
| 430 | return 0; |
| 431 | } |
| 432 | |
| 433 | static int dib9000_firmware_download(struct dib9000_state *state, u8 risc_id, u16 key, const u8 * code, u32 len) |
| 434 | { |
| 435 | u16 offs; |
| 436 | |
| 437 | if (risc_id == 1) |
| 438 | offs = 16; |
| 439 | else |
| 440 | offs = 0; |
| 441 | |
| 442 | /* config crtl reg */ |
| 443 | dib9000_write_word(state, 1024 + offs, 0x000f); |
| 444 | dib9000_write_word(state, 1025 + offs, 0); |
| 445 | dib9000_write_word(state, 1031 + offs, key); |
| 446 | |
| 447 | dprintk("going to download %dB of microcode", len); |
| 448 | if (dib9000_write16_noinc(state, 1026 + offs, (u8 *) code, (u16) len) != 0) { |
| 449 | dprintk("error while downloading microcode for RISC %c", 'A' + risc_id); |
| 450 | return -EIO; |
| 451 | } |
| 452 | |
| 453 | dprintk("Microcode for RISC %c loaded", 'A' + risc_id); |
| 454 | |
| 455 | return 0; |
| 456 | } |
| 457 | |
| 458 | static int dib9000_mbx_host_init(struct dib9000_state *state, u8 risc_id) |
| 459 | { |
| 460 | u16 mbox_offs; |
| 461 | u16 reset_reg; |
| 462 | u16 tries = 1000; |
| 463 | |
| 464 | if (risc_id == 1) |
| 465 | mbox_offs = 16; |
| 466 | else |
| 467 | mbox_offs = 0; |
| 468 | |
| 469 | /* Reset mailbox */ |
| 470 | dib9000_write_word(state, 1027 + mbox_offs, 0x8000); |
| 471 | |
| 472 | /* Read reset status */ |
| 473 | do { |
| 474 | reset_reg = dib9000_read_word(state, 1027 + mbox_offs); |
| 475 | msleep(100); |
| 476 | } while ((reset_reg & 0x8000) && --tries); |
| 477 | |
| 478 | if (reset_reg & 0x8000) { |
| 479 | dprintk("MBX: init ERROR, no response from RISC %c", 'A' + risc_id); |
| 480 | return -EIO; |
| 481 | } |
| 482 | dprintk("MBX: initialized"); |
| 483 | return 0; |
| 484 | } |
| 485 | |
| 486 | #define MAX_MAILBOX_TRY 100 |
| 487 | static int dib9000_mbx_send_attr(struct dib9000_state *state, u8 id, u16 * data, u8 len, u16 attr) |
| 488 | { |
| 489 | u8 *d, b[2]; |
| 490 | u16 tmp; |
| 491 | u16 size; |
| 492 | u32 i; |
| 493 | int ret = 0; |
| 494 | |
| 495 | if (!state->platform.risc.fw_is_running) |
| 496 | return -EINVAL; |
| 497 | |
| 498 | DibAcquireLock(&state->platform.risc.mbx_if_lock); |
| 499 | tmp = MAX_MAILBOX_TRY; |
| 500 | do { |
| 501 | size = dib9000_read_word_attr(state, 1043, attr) & 0xff; |
| 502 | if ((size + len + 1) > MBX_MAX_WORDS && --tmp) { |
| 503 | dprintk("MBX: RISC mbx full, retrying"); |
| 504 | msleep(100); |
| 505 | } else |
| 506 | break; |
| 507 | } while (1); |
| 508 | |
| 509 | /*dprintk( "MBX: size: %d", size); */ |
| 510 | |
| 511 | if (tmp == 0) { |
| 512 | ret = -EINVAL; |
| 513 | goto out; |
| 514 | } |
| 515 | #ifdef DUMP_MSG |
| 516 | dprintk("--> %02x %d ", id, len + 1); |
| 517 | for (i = 0; i < len; i++) |
| 518 | dprintk("%04x ", data[i]); |
| 519 | dprintk("\n"); |
| 520 | #endif |
| 521 | |
| 522 | /* byte-order conversion - works on big (where it is not necessary) or little endian */ |
| 523 | d = (u8 *) data; |
| 524 | for (i = 0; i < len; i++) { |
| 525 | tmp = data[i]; |
| 526 | *d++ = tmp >> 8; |
| 527 | *d++ = tmp & 0xff; |
| 528 | } |
| 529 | |
| 530 | /* write msg */ |
| 531 | b[0] = id; |
| 532 | b[1] = len + 1; |
| 533 | if (dib9000_write16_noinc_attr(state, 1045, b, 2, attr) != 0 || dib9000_write16_noinc_attr(state, 1045, (u8 *) data, len * 2, attr) != 0) { |
| 534 | ret = -EIO; |
| 535 | goto out; |
| 536 | } |
| 537 | |
| 538 | /* update register nb_mes_in_RX */ |
| 539 | ret = (u8) dib9000_write_word_attr(state, 1043, 1 << 14, attr); |
| 540 | |
| 541 | out: |
| 542 | DibReleaseLock(&state->platform.risc.mbx_if_lock); |
| 543 | |
| 544 | return ret; |
| 545 | } |
| 546 | |
| 547 | static u8 dib9000_mbx_read(struct dib9000_state *state, u16 * data, u8 risc_id, u16 attr) |
| 548 | { |
| 549 | #ifdef DUMP_MSG |
| 550 | u16 *d = data; |
| 551 | #endif |
| 552 | |
| 553 | u16 tmp, i; |
| 554 | u8 size; |
| 555 | u8 mc_base; |
| 556 | |
| 557 | if (!state->platform.risc.fw_is_running) |
| 558 | return 0; |
| 559 | |
| 560 | DibAcquireLock(&state->platform.risc.mbx_if_lock); |
| 561 | if (risc_id == 1) |
| 562 | mc_base = 16; |
| 563 | else |
| 564 | mc_base = 0; |
| 565 | |
| 566 | /* Length and type in the first word */ |
| 567 | *data = dib9000_read_word_attr(state, 1029 + mc_base, attr); |
| 568 | |
| 569 | size = *data & 0xff; |
| 570 | if (size <= MBX_MAX_WORDS) { |
| 571 | data++; |
| 572 | size--; /* Initial word already read */ |
| 573 | |
| 574 | dib9000_read16_noinc_attr(state, 1029 + mc_base, (u8 *) data, size * 2, attr); |
| 575 | |
| 576 | /* to word conversion */ |
| 577 | for (i = 0; i < size; i++) { |
| 578 | tmp = *data; |
| 579 | *data = (tmp >> 8) | (tmp << 8); |
| 580 | data++; |
| 581 | } |
| 582 | |
| 583 | #ifdef DUMP_MSG |
| 584 | dprintk("<-- "); |
| 585 | for (i = 0; i < size + 1; i++) |
| 586 | dprintk("%04x ", d[i]); |
| 587 | dprintk("\n"); |
| 588 | #endif |
| 589 | } else { |
| 590 | dprintk("MBX: message is too big for message cache (%d), flushing message", size); |
| 591 | size--; /* Initial word already read */ |
| 592 | while (size--) |
| 593 | dib9000_read16_noinc_attr(state, 1029 + mc_base, (u8 *) data, 2, attr); |
| 594 | } |
| 595 | /* Update register nb_mes_in_TX */ |
| 596 | dib9000_write_word_attr(state, 1028 + mc_base, 1 << 14, attr); |
| 597 | |
| 598 | DibReleaseLock(&state->platform.risc.mbx_if_lock); |
| 599 | |
| 600 | return size + 1; |
| 601 | } |
| 602 | |
| 603 | static int dib9000_risc_debug_buf(struct dib9000_state *state, u16 * data, u8 size) |
| 604 | { |
| 605 | u32 ts = data[1] << 16 | data[0]; |
| 606 | char *b = (char *)&data[2]; |
| 607 | |
| 608 | b[2 * (size - 2) - 1] = '\0'; /* Bullet proof the buffer */ |
| 609 | if (*b == '~') { |
| 610 | b++; |
| 611 | dprintk(b); |
| 612 | } else |
| 613 | dprintk("RISC%d: %d.%04d %s", state->fe_id, ts / 10000, ts % 10000, *b ? b : "<emtpy>"); |
| 614 | return 1; |
| 615 | } |
| 616 | |
| 617 | static int dib9000_mbx_fetch_to_cache(struct dib9000_state *state, u16 attr) |
| 618 | { |
| 619 | int i; |
| 620 | u8 size; |
| 621 | u16 *block; |
| 622 | /* find a free slot */ |
| 623 | for (i = 0; i < DIB9000_MSG_CACHE_SIZE; i++) { |
| 624 | block = state->platform.risc.message_cache[i]; |
| 625 | if (*block == 0) { |
| 626 | size = dib9000_mbx_read(state, block, 1, attr); |
| 627 | |
| 628 | /* dprintk( "MBX: fetched %04x message to cache", *block); */ |
| 629 | |
| 630 | switch (*block >> 8) { |
| 631 | case IN_MSG_DEBUG_BUF: |
| 632 | dib9000_risc_debug_buf(state, block + 1, size); /* debug-messages are going to be printed right away */ |
| 633 | *block = 0; /* free the block */ |
| 634 | break; |
| 635 | #if 0 |
| 636 | case IN_MSG_DATA: /* FE-TRACE */ |
| 637 | dib9000_risc_data_process(state, block + 1, size); |
| 638 | *block = 0; |
| 639 | break; |
| 640 | #endif |
| 641 | default: |
| 642 | break; |
| 643 | } |
| 644 | |
| 645 | return 1; |
| 646 | } |
| 647 | } |
| 648 | dprintk("MBX: no free cache-slot found for new message..."); |
| 649 | return -1; |
| 650 | } |
| 651 | |
| 652 | static u8 dib9000_mbx_count(struct dib9000_state *state, u8 risc_id, u16 attr) |
| 653 | { |
| 654 | if (risc_id == 0) |
| 655 | return (u8) (dib9000_read_word_attr(state, 1028, attr) >> 10) & 0x1f; /* 5 bit field */ |
| 656 | else |
| 657 | return (u8) (dib9000_read_word_attr(state, 1044, attr) >> 8) & 0x7f; /* 7 bit field */ |
| 658 | } |
| 659 | |
| 660 | static int dib9000_mbx_process(struct dib9000_state *state, u16 attr) |
| 661 | { |
| 662 | int ret = 0; |
| 663 | u16 tmp; |
| 664 | |
| 665 | if (!state->platform.risc.fw_is_running) |
| 666 | return -1; |
| 667 | |
| 668 | DibAcquireLock(&state->platform.risc.mbx_lock); |
| 669 | |
| 670 | if (dib9000_mbx_count(state, 1, attr)) /* 1=RiscB */ |
| 671 | ret = dib9000_mbx_fetch_to_cache(state, attr); |
| 672 | |
| 673 | tmp = dib9000_read_word_attr(state, 1229, attr); /* Clear the IRQ */ |
| 674 | /* if (tmp) */ |
| 675 | /* dprintk( "cleared IRQ: %x", tmp); */ |
| 676 | DibReleaseLock(&state->platform.risc.mbx_lock); |
| 677 | |
| 678 | return ret; |
| 679 | } |
| 680 | |
| 681 | static int dib9000_mbx_get_message_attr(struct dib9000_state *state, u16 id, u16 * msg, u8 * size, u16 attr) |
| 682 | { |
| 683 | u8 i; |
| 684 | u16 *block; |
| 685 | u16 timeout = 30; |
| 686 | |
| 687 | *msg = 0; |
| 688 | do { |
| 689 | /* dib9000_mbx_get_from_cache(); */ |
| 690 | for (i = 0; i < DIB9000_MSG_CACHE_SIZE; i++) { |
| 691 | block = state->platform.risc.message_cache[i]; |
| 692 | if ((*block >> 8) == id) { |
| 693 | *size = (*block & 0xff) - 1; |
| 694 | memcpy(msg, block + 1, (*size) * 2); |
| 695 | *block = 0; /* free the block */ |
| 696 | i = 0; /* signal that we found a message */ |
| 697 | break; |
| 698 | } |
| 699 | } |
| 700 | |
| 701 | if (i == 0) |
| 702 | break; |
| 703 | |
| 704 | if (dib9000_mbx_process(state, attr) == -1) /* try to fetch one message - if any */ |
| 705 | return -1; |
| 706 | |
| 707 | } while (--timeout); |
| 708 | |
| 709 | if (timeout == 0) { |
| 710 | dprintk("waiting for message %d timed out", id); |
| 711 | return -1; |
| 712 | } |
| 713 | |
| 714 | return i == 0; |
| 715 | } |
| 716 | |
| 717 | static int dib9000_risc_check_version(struct dib9000_state *state) |
| 718 | { |
| 719 | u8 r[4]; |
| 720 | u8 size; |
| 721 | u16 fw_version = 0; |
| 722 | |
| 723 | if (dib9000_mbx_send(state, OUT_MSG_REQ_VERSION, &fw_version, 1) != 0) |
| 724 | return -EIO; |
| 725 | |
| 726 | if (dib9000_mbx_get_message(state, IN_MSG_VERSION, (u16 *) r, &size) < 0) |
| 727 | return -EIO; |
| 728 | |
| 729 | fw_version = (r[0] << 8) | r[1]; |
| 730 | dprintk("RISC: ver: %d.%02d (IC: %d)", fw_version >> 10, fw_version & 0x3ff, (r[2] << 8) | r[3]); |
| 731 | |
| 732 | if ((fw_version >> 10) != 7) |
| 733 | return -EINVAL; |
| 734 | |
| 735 | switch (fw_version & 0x3ff) { |
| 736 | case 11: |
| 737 | case 12: |
| 738 | case 14: |
| 739 | case 15: |
| 740 | case 16: |
| 741 | case 17: |
| 742 | break; |
| 743 | default: |
| 744 | dprintk("RISC: invalid firmware version"); |
| 745 | return -EINVAL; |
| 746 | } |
| 747 | |
| 748 | dprintk("RISC: valid firmware version"); |
| 749 | return 0; |
| 750 | } |
| 751 | |
| 752 | static int dib9000_fw_boot(struct dib9000_state *state, const u8 * codeA, u32 lenA, const u8 * codeB, u32 lenB) |
| 753 | { |
| 754 | /* Reconfig pool mac ram */ |
| 755 | dib9000_write_word(state, 1225, 0x02); /* A: 8k C, 4 k D - B: 32k C 6 k D - IRAM 96k */ |
| 756 | dib9000_write_word(state, 1226, 0x05); |
| 757 | |
| 758 | /* Toggles IP crypto to Host APB interface. */ |
| 759 | dib9000_write_word(state, 1542, 1); |
| 760 | |
| 761 | /* Set jump and no jump in the dma box */ |
| 762 | dib9000_write_word(state, 1074, 0); |
| 763 | dib9000_write_word(state, 1075, 0); |
| 764 | |
| 765 | /* Set MAC as APB Master. */ |
| 766 | dib9000_write_word(state, 1237, 0); |
| 767 | |
| 768 | /* Reset the RISCs */ |
| 769 | if (codeA != NULL) |
| 770 | dib9000_write_word(state, 1024, 2); |
| 771 | else |
| 772 | dib9000_write_word(state, 1024, 15); |
| 773 | if (codeB != NULL) |
| 774 | dib9000_write_word(state, 1040, 2); |
| 775 | |
| 776 | if (codeA != NULL) |
| 777 | dib9000_firmware_download(state, 0, 0x1234, codeA, lenA); |
| 778 | if (codeB != NULL) |
| 779 | dib9000_firmware_download(state, 1, 0x1234, codeB, lenB); |
| 780 | |
| 781 | /* Run the RISCs */ |
| 782 | if (codeA != NULL) |
| 783 | dib9000_write_word(state, 1024, 0); |
| 784 | if (codeB != NULL) |
| 785 | dib9000_write_word(state, 1040, 0); |
| 786 | |
| 787 | if (codeA != NULL) |
| 788 | if (dib9000_mbx_host_init(state, 0) != 0) |
| 789 | return -EIO; |
| 790 | if (codeB != NULL) |
| 791 | if (dib9000_mbx_host_init(state, 1) != 0) |
| 792 | return -EIO; |
| 793 | |
| 794 | msleep(100); |
| 795 | state->platform.risc.fw_is_running = 1; |
| 796 | |
| 797 | if (dib9000_risc_check_version(state) != 0) |
| 798 | return -EINVAL; |
| 799 | |
| 800 | state->platform.risc.memcmd = 0xff; |
| 801 | return 0; |
| 802 | } |
| 803 | |
| 804 | static u16 dib9000_identify(struct i2c_device *client) |
| 805 | { |
| 806 | u16 value; |
| 807 | |
| 808 | value = dib9000_i2c_read16(client, 896); |
| 809 | if (value != 0x01b3) { |
| 810 | dprintk("wrong Vendor ID (0x%x)", value); |
| 811 | return 0; |
| 812 | } |
| 813 | |
| 814 | value = dib9000_i2c_read16(client, 897); |
| 815 | if (value != 0x4000 && value != 0x4001 && value != 0x4002 && value != 0x4003 && value != 0x4004 && value != 0x4005) { |
| 816 | dprintk("wrong Device ID (0x%x)", value); |
| 817 | return 0; |
| 818 | } |
| 819 | |
| 820 | /* protect this driver to be used with 7000PC */ |
| 821 | if (value == 0x4000 && dib9000_i2c_read16(client, 769) == 0x4000) { |
| 822 | dprintk("this driver does not work with DiB7000PC"); |
| 823 | return 0; |
| 824 | } |
| 825 | |
| 826 | switch (value) { |
| 827 | case 0x4000: |
| 828 | dprintk("found DiB7000MA/PA/MB/PB"); |
| 829 | break; |
| 830 | case 0x4001: |
| 831 | dprintk("found DiB7000HC"); |
| 832 | break; |
| 833 | case 0x4002: |
| 834 | dprintk("found DiB7000MC"); |
| 835 | break; |
| 836 | case 0x4003: |
| 837 | dprintk("found DiB9000A"); |
| 838 | break; |
| 839 | case 0x4004: |
| 840 | dprintk("found DiB9000H"); |
| 841 | break; |
| 842 | case 0x4005: |
| 843 | dprintk("found DiB9000M"); |
| 844 | break; |
| 845 | } |
| 846 | |
| 847 | return value; |
| 848 | } |
| 849 | |
| 850 | static void dib9000_set_power_mode(struct dib9000_state *state, enum dib9000_power_mode mode) |
| 851 | { |
| 852 | /* by default everything is going to be powered off */ |
| 853 | u16 reg_903 = 0x3fff, reg_904 = 0xffff, reg_905 = 0xffff, reg_906; |
| 854 | u8 offset; |
| 855 | |
| 856 | if (state->revision == 0x4003 || state->revision == 0x4004 || state->revision == 0x4005) |
| 857 | offset = 1; |
| 858 | else |
| 859 | offset = 0; |
| 860 | |
| 861 | reg_906 = dib9000_read_word(state, 906 + offset) | 0x3; /* keep settings for RISC */ |
| 862 | |
| 863 | /* now, depending on the requested mode, we power on */ |
| 864 | switch (mode) { |
| 865 | /* power up everything in the demod */ |
| 866 | case DIB9000_POWER_ALL: |
| 867 | reg_903 = 0x0000; |
| 868 | reg_904 = 0x0000; |
| 869 | reg_905 = 0x0000; |
| 870 | reg_906 = 0x0000; |
| 871 | break; |
| 872 | |
| 873 | /* just leave power on the control-interfaces: GPIO and (I2C or SDIO or SRAM) */ |
| 874 | case DIB9000_POWER_INTERFACE_ONLY: /* TODO power up either SDIO or I2C or SRAM */ |
| 875 | reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 2)); |
| 876 | break; |
| 877 | |
| 878 | case DIB9000_POWER_INTERF_ANALOG_AGC: |
| 879 | reg_903 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10)); |
| 880 | reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | (1 << 2)); |
| 881 | reg_906 &= ~((1 << 0)); |
| 882 | break; |
| 883 | |
| 884 | case DIB9000_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD: |
| 885 | reg_903 = 0x0000; |
| 886 | reg_904 = 0x801f; |
| 887 | reg_905 = 0x0000; |
| 888 | reg_906 &= ~((1 << 0)); |
| 889 | break; |
| 890 | |
| 891 | case DIB9000_POWER_COR4_CRY_ESRAM_MOUT_NUD: |
| 892 | reg_903 = 0x0000; |
| 893 | reg_904 = 0x8000; |
| 894 | reg_905 = 0x010b; |
| 895 | reg_906 &= ~((1 << 0)); |
| 896 | break; |
| 897 | default: |
| 898 | case DIB9000_POWER_NO: |
| 899 | break; |
| 900 | } |
| 901 | |
| 902 | /* always power down unused parts */ |
| 903 | if (!state->platform.host.mobile_mode) |
| 904 | reg_904 |= (1 << 7) | (1 << 6) | (1 << 4) | (1 << 2) | (1 << 1); |
| 905 | |
| 906 | /* P_sdio_select_clk = 0 on MC and after */ |
| 907 | if (state->revision != 0x4000) |
| 908 | reg_906 <<= 1; |
| 909 | |
| 910 | dib9000_write_word(state, 903 + offset, reg_903); |
| 911 | dib9000_write_word(state, 904 + offset, reg_904); |
| 912 | dib9000_write_word(state, 905 + offset, reg_905); |
| 913 | dib9000_write_word(state, 906 + offset, reg_906); |
| 914 | } |
| 915 | |
| 916 | static int dib9000_fw_reset(struct dvb_frontend *fe) |
| 917 | { |
| 918 | struct dib9000_state *state = fe->demodulator_priv; |
| 919 | |
| 920 | dib9000_write_word(state, 1817, 0x0003); |
| 921 | |
| 922 | dib9000_write_word(state, 1227, 1); |
| 923 | dib9000_write_word(state, 1227, 0); |
| 924 | |
| 925 | switch ((state->revision = dib9000_identify(&state->i2c))) { |
| 926 | case 0x4003: |
| 927 | case 0x4004: |
| 928 | case 0x4005: |
| 929 | state->reg_offs = 1; |
| 930 | break; |
| 931 | default: |
| 932 | return -EINVAL; |
| 933 | } |
| 934 | |
| 935 | /* reset the i2c-master to use the host interface */ |
| 936 | dibx000_reset_i2c_master(&state->i2c_master); |
| 937 | |
| 938 | dib9000_set_power_mode(state, DIB9000_POWER_ALL); |
| 939 | |
| 940 | /* unforce divstr regardless whether i2c enumeration was done or not */ |
| 941 | dib9000_write_word(state, 1794, dib9000_read_word(state, 1794) & ~(1 << 1)); |
| 942 | dib9000_write_word(state, 1796, 0); |
| 943 | dib9000_write_word(state, 1805, 0x805); |
| 944 | |
| 945 | /* restart all parts */ |
| 946 | dib9000_write_word(state, 898, 0xffff); |
| 947 | dib9000_write_word(state, 899, 0xffff); |
| 948 | dib9000_write_word(state, 900, 0x0001); |
| 949 | dib9000_write_word(state, 901, 0xff19); |
| 950 | dib9000_write_word(state, 902, 0x003c); |
| 951 | |
| 952 | dib9000_write_word(state, 898, 0); |
| 953 | dib9000_write_word(state, 899, 0); |
| 954 | dib9000_write_word(state, 900, 0); |
| 955 | dib9000_write_word(state, 901, 0); |
| 956 | dib9000_write_word(state, 902, 0); |
| 957 | |
| 958 | dib9000_write_word(state, 911, state->chip.d9.cfg.if_drives); |
| 959 | |
| 960 | dib9000_set_power_mode(state, DIB9000_POWER_INTERFACE_ONLY); |
| 961 | |
| 962 | return 0; |
| 963 | } |
| 964 | |
| 965 | static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen, u8 * b, u32 len) |
| 966 | { |
| 967 | u16 mb[10]; |
| 968 | u8 i, s; |
| 969 | |
| 970 | if (address >= 1024 || !state->platform.risc.fw_is_running) |
| 971 | return -EINVAL; |
| 972 | |
| 973 | /* dprintk( "APB access thru rd fw %d %x", address, attribute); */ |
| 974 | |
| 975 | mb[0] = (u16) address; |
| 976 | mb[1] = len / 2; |
| 977 | dib9000_mbx_send_attr(state, OUT_MSG_BRIDGE_APB_R, mb, 2, attribute); |
| 978 | switch (dib9000_mbx_get_message_attr(state, IN_MSG_END_BRIDGE_APB_RW, mb, &s, attribute)) { |
| 979 | case 1: |
| 980 | s--; |
| 981 | for (i = 0; i < s; i++) { |
| 982 | b[i * 2] = (mb[i + 1] >> 8) & 0xff; |
| 983 | b[i * 2 + 1] = (mb[i + 1]) & 0xff; |
| 984 | } |
| 985 | return 0; |
| 986 | default: |
| 987 | return -EIO; |
| 988 | } |
| 989 | return -EIO; |
| 990 | } |
| 991 | |
| 992 | static int dib9000_risc_apb_access_write(struct dib9000_state *state, u32 address, u16 attribute, const u8 * b, u32 len) |
| 993 | { |
| 994 | u16 mb[10]; |
| 995 | u8 s, i; |
| 996 | |
| 997 | if (address >= 1024 || !state->platform.risc.fw_is_running) |
| 998 | return -EINVAL; |
| 999 | |
| 1000 | /* dprintk( "APB access thru wr fw %d %x", address, attribute); */ |
| 1001 | |
| 1002 | mb[0] = (unsigned short)address; |
| 1003 | for (i = 0; i < len && i < 20; i += 2) |
| 1004 | mb[1 + (i / 2)] = (b[i] << 8 | b[i + 1]); |
| 1005 | |
| 1006 | dib9000_mbx_send_attr(state, OUT_MSG_BRIDGE_APB_W, mb, 1 + len / 2, attribute); |
| 1007 | return dib9000_mbx_get_message_attr(state, IN_MSG_END_BRIDGE_APB_RW, mb, &s, attribute) == 1 ? 0 : -EINVAL; |
| 1008 | } |
| 1009 | |
| 1010 | static int dib9000_fw_memmbx_sync(struct dib9000_state *state, u8 i) |
| 1011 | { |
| 1012 | u8 index_loop = 10; |
| 1013 | |
| 1014 | if (!state->platform.risc.fw_is_running) |
| 1015 | return 0; |
| 1016 | dib9000_risc_mem_write(state, FE_MM_RW_SYNC, &i); |
| 1017 | do { |
| 1018 | dib9000_risc_mem_read(state, FE_MM_RW_SYNC, &i, 1); |
| 1019 | } while (i && index_loop--); |
| 1020 | |
| 1021 | if (index_loop > 0) |
| 1022 | return 0; |
| 1023 | return -EIO; |
| 1024 | } |
| 1025 | |
| 1026 | static int dib9000_fw_init(struct dib9000_state *state) |
| 1027 | { |
| 1028 | struct dibGPIOFunction *f; |
| 1029 | u16 b[40] = { 0 }; |
| 1030 | u8 i; |
| 1031 | u8 size; |
| 1032 | |
| 1033 | if (dib9000_fw_boot(state, NULL, 0, state->chip.d9.cfg.microcode_B_fe_buffer, state->chip.d9.cfg.microcode_B_fe_size) != 0) |
| 1034 | return -EIO; |
| 1035 | |
| 1036 | /* initialize the firmware */ |
| 1037 | for (i = 0; i < ARRAY_SIZE(state->chip.d9.cfg.gpio_function); i++) { |
| 1038 | f = &state->chip.d9.cfg.gpio_function[i]; |
| 1039 | if (f->mask) { |
| 1040 | switch (f->function) { |
| 1041 | case BOARD_GPIO_FUNCTION_COMPONENT_ON: |
| 1042 | b[0] = (u16) f->mask; |
| 1043 | b[1] = (u16) f->direction; |
| 1044 | b[2] = (u16) f->value; |
| 1045 | break; |
| 1046 | case BOARD_GPIO_FUNCTION_COMPONENT_OFF: |
| 1047 | b[3] = (u16) f->mask; |
| 1048 | b[4] = (u16) f->direction; |
| 1049 | b[5] = (u16) f->value; |
| 1050 | break; |
| 1051 | } |
| 1052 | } |
| 1053 | } |
| 1054 | if (dib9000_mbx_send(state, OUT_MSG_CONF_GPIO, b, 15) != 0) |
| 1055 | return -EIO; |
| 1056 | |
| 1057 | /* subband */ |
| 1058 | b[0] = state->chip.d9.cfg.subband.size; /* type == 0 -> GPIO - PWM not yet supported */ |
| 1059 | for (i = 0; i < state->chip.d9.cfg.subband.size; i++) { |
| 1060 | b[1 + i * 4] = state->chip.d9.cfg.subband.subband[i].f_mhz; |
| 1061 | b[2 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.mask; |
| 1062 | b[3 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.direction; |
| 1063 | b[4 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.value; |
| 1064 | } |
| 1065 | b[1 + i * 4] = 0; /* fe_id */ |
| 1066 | if (dib9000_mbx_send(state, OUT_MSG_SUBBAND_SEL, b, 2 + 4 * i) != 0) |
| 1067 | return -EIO; |
| 1068 | |
| 1069 | /* 0 - id, 1 - no_of_frontends */ |
| 1070 | b[0] = (0 << 8) | 1; |
| 1071 | /* 0 = i2c-address demod, 0 = tuner */ |
| 1072 | b[1] = (0 << 8) | (0); |
| 1073 | b[2] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000) >> 16) & 0xffff); |
| 1074 | b[3] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000)) & 0xffff); |
| 1075 | b[4] = (u16) ((state->chip.d9.cfg.vcxo_timer >> 16) & 0xffff); |
| 1076 | b[5] = (u16) ((state->chip.d9.cfg.vcxo_timer) & 0xffff); |
| 1077 | b[6] = (u16) ((state->chip.d9.cfg.timing_frequency >> 16) & 0xffff); |
| 1078 | b[7] = (u16) ((state->chip.d9.cfg.timing_frequency) & 0xffff); |
| 1079 | b[29] = state->chip.d9.cfg.if_drives; |
| 1080 | if (dib9000_mbx_send(state, OUT_MSG_INIT_DEMOD, b, ARRAY_SIZE(b)) != 0) |
| 1081 | return -EIO; |
| 1082 | |
| 1083 | if (dib9000_mbx_send(state, OUT_MSG_FE_FW_DL, NULL, 0) != 0) |
| 1084 | return -EIO; |
| 1085 | |
| 1086 | if (dib9000_mbx_get_message(state, IN_MSG_FE_FW_DL_DONE, b, &size) < 0) |
| 1087 | return -EIO; |
| 1088 | |
| 1089 | if (size > ARRAY_SIZE(b)) { |
| 1090 | dprintk("error : firmware returned %dbytes needed but the used buffer has only %dbytes\n Firmware init ABORTED", size, |
| 1091 | (int)ARRAY_SIZE(b)); |
| 1092 | return -EINVAL; |
| 1093 | } |
| 1094 | |
| 1095 | for (i = 0; i < size; i += 2) { |
| 1096 | state->platform.risc.fe_mm[i / 2].addr = b[i + 0]; |
| 1097 | state->platform.risc.fe_mm[i / 2].size = b[i + 1]; |
| 1098 | } |
| 1099 | |
| 1100 | return 0; |
| 1101 | } |
| 1102 | |
| 1103 | static void dib9000_fw_set_channel_head(struct dib9000_state *state, struct dvb_frontend_parameters *ch) |
| 1104 | { |
| 1105 | u8 b[9]; |
| 1106 | u32 freq = state->fe[0]->dtv_property_cache.frequency / 1000; |
| 1107 | if (state->fe_id % 2) |
| 1108 | freq += 101; |
| 1109 | |
| 1110 | b[0] = (u8) ((freq >> 0) & 0xff); |
| 1111 | b[1] = (u8) ((freq >> 8) & 0xff); |
| 1112 | b[2] = (u8) ((freq >> 16) & 0xff); |
| 1113 | b[3] = (u8) ((freq >> 24) & 0xff); |
| 1114 | b[4] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 0) & 0xff); |
| 1115 | b[5] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 8) & 0xff); |
| 1116 | b[6] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 16) & 0xff); |
| 1117 | b[7] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 24) & 0xff); |
| 1118 | b[8] = 0x80; /* do not wait for CELL ID when doing autosearch */ |
| 1119 | if (state->fe[0]->dtv_property_cache.delivery_system == SYS_DVBT) |
| 1120 | b[8] |= 1; |
| 1121 | dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_HEAD, b); |
| 1122 | } |
| 1123 | |
| 1124 | static int dib9000_fw_get_channel(struct dvb_frontend *fe, struct dvb_frontend_parameters *channel) |
| 1125 | { |
| 1126 | struct dib9000_state *state = fe->demodulator_priv; |
| 1127 | struct dibDVBTChannel { |
| 1128 | s8 spectrum_inversion; |
| 1129 | |
| 1130 | s8 nfft; |
| 1131 | s8 guard; |
| 1132 | s8 constellation; |
| 1133 | |
| 1134 | s8 hrch; |
| 1135 | s8 alpha; |
| 1136 | s8 code_rate_hp; |
| 1137 | s8 code_rate_lp; |
| 1138 | s8 select_hp; |
| 1139 | |
| 1140 | s8 intlv_native; |
| 1141 | }; |
| 1142 | struct dibDVBTChannel ch; |
| 1143 | int ret = 0; |
| 1144 | |
| 1145 | DibAcquireLock(&state->platform.risc.mem_mbx_lock); |
| 1146 | if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) { |
| 1147 | goto error; |
| 1148 | ret = -EIO; |
| 1149 | } |
| 1150 | |
| 1151 | dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_UNION, (u8 *) &ch, sizeof(struct dibDVBTChannel)); |
| 1152 | |
| 1153 | switch (ch.spectrum_inversion & 0x7) { |
| 1154 | case 1: |
| 1155 | state->fe[0]->dtv_property_cache.inversion = INVERSION_ON; |
| 1156 | break; |
| 1157 | case 0: |
| 1158 | state->fe[0]->dtv_property_cache.inversion = INVERSION_OFF; |
| 1159 | break; |
| 1160 | default: |
| 1161 | case -1: |
| 1162 | state->fe[0]->dtv_property_cache.inversion = INVERSION_AUTO; |
| 1163 | break; |
| 1164 | } |
| 1165 | switch (ch.nfft) { |
| 1166 | case 0: |
| 1167 | state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_2K; |
| 1168 | break; |
| 1169 | case 2: |
| 1170 | state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_4K; |
| 1171 | break; |
| 1172 | case 1: |
| 1173 | state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K; |
| 1174 | break; |
| 1175 | default: |
| 1176 | case -1: |
| 1177 | state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_AUTO; |
| 1178 | break; |
| 1179 | } |
| 1180 | switch (ch.guard) { |
| 1181 | case 0: |
| 1182 | state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_32; |
| 1183 | break; |
| 1184 | case 1: |
| 1185 | state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_16; |
| 1186 | break; |
| 1187 | case 2: |
| 1188 | state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8; |
| 1189 | break; |
| 1190 | case 3: |
| 1191 | state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_4; |
| 1192 | break; |
| 1193 | default: |
| 1194 | case -1: |
| 1195 | state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_AUTO; |
| 1196 | break; |
| 1197 | } |
| 1198 | switch (ch.constellation) { |
| 1199 | case 2: |
| 1200 | state->fe[0]->dtv_property_cache.modulation = QAM_64; |
| 1201 | break; |
| 1202 | case 1: |
| 1203 | state->fe[0]->dtv_property_cache.modulation = QAM_16; |
| 1204 | break; |
| 1205 | case 0: |
| 1206 | state->fe[0]->dtv_property_cache.modulation = QPSK; |
| 1207 | break; |
| 1208 | default: |
| 1209 | case -1: |
| 1210 | state->fe[0]->dtv_property_cache.modulation = QAM_AUTO; |
| 1211 | break; |
| 1212 | } |
| 1213 | switch (ch.hrch) { |
| 1214 | case 0: |
| 1215 | state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_NONE; |
| 1216 | break; |
| 1217 | case 1: |
| 1218 | state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_1; |
| 1219 | break; |
| 1220 | default: |
| 1221 | case -1: |
| 1222 | state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_AUTO; |
| 1223 | break; |
| 1224 | } |
| 1225 | switch (ch.code_rate_hp) { |
| 1226 | case 1: |
| 1227 | state->fe[0]->dtv_property_cache.code_rate_HP = FEC_1_2; |
| 1228 | break; |
| 1229 | case 2: |
| 1230 | state->fe[0]->dtv_property_cache.code_rate_HP = FEC_2_3; |
| 1231 | break; |
| 1232 | case 3: |
| 1233 | state->fe[0]->dtv_property_cache.code_rate_HP = FEC_3_4; |
| 1234 | break; |
| 1235 | case 5: |
| 1236 | state->fe[0]->dtv_property_cache.code_rate_HP = FEC_5_6; |
| 1237 | break; |
| 1238 | case 7: |
| 1239 | state->fe[0]->dtv_property_cache.code_rate_HP = FEC_7_8; |
| 1240 | break; |
| 1241 | default: |
| 1242 | case -1: |
| 1243 | state->fe[0]->dtv_property_cache.code_rate_HP = FEC_AUTO; |
| 1244 | break; |
| 1245 | } |
| 1246 | switch (ch.code_rate_lp) { |
| 1247 | case 1: |
| 1248 | state->fe[0]->dtv_property_cache.code_rate_LP = FEC_1_2; |
| 1249 | break; |
| 1250 | case 2: |
| 1251 | state->fe[0]->dtv_property_cache.code_rate_LP = FEC_2_3; |
| 1252 | break; |
| 1253 | case 3: |
| 1254 | state->fe[0]->dtv_property_cache.code_rate_LP = FEC_3_4; |
| 1255 | break; |
| 1256 | case 5: |
| 1257 | state->fe[0]->dtv_property_cache.code_rate_LP = FEC_5_6; |
| 1258 | break; |
| 1259 | case 7: |
| 1260 | state->fe[0]->dtv_property_cache.code_rate_LP = FEC_7_8; |
| 1261 | break; |
| 1262 | default: |
| 1263 | case -1: |
| 1264 | state->fe[0]->dtv_property_cache.code_rate_LP = FEC_AUTO; |
| 1265 | break; |
| 1266 | } |
| 1267 | |
| 1268 | error: |
| 1269 | DibReleaseLock(&state->platform.risc.mem_mbx_lock); |
| 1270 | return ret; |
| 1271 | } |
| 1272 | |
| 1273 | static int dib9000_fw_set_channel_union(struct dvb_frontend *fe, struct dvb_frontend_parameters *channel) |
| 1274 | { |
| 1275 | struct dib9000_state *state = fe->demodulator_priv; |
| 1276 | struct dibDVBTChannel { |
| 1277 | s8 spectrum_inversion; |
| 1278 | |
| 1279 | s8 nfft; |
| 1280 | s8 guard; |
| 1281 | s8 constellation; |
| 1282 | |
| 1283 | s8 hrch; |
| 1284 | s8 alpha; |
| 1285 | s8 code_rate_hp; |
| 1286 | s8 code_rate_lp; |
| 1287 | s8 select_hp; |
| 1288 | |
| 1289 | s8 intlv_native; |
| 1290 | }; |
| 1291 | struct dibDVBTChannel ch; |
| 1292 | |
| 1293 | switch (state->fe[0]->dtv_property_cache.inversion) { |
| 1294 | case INVERSION_ON: |
| 1295 | ch.spectrum_inversion = 1; |
| 1296 | break; |
| 1297 | case INVERSION_OFF: |
| 1298 | ch.spectrum_inversion = 0; |
| 1299 | break; |
| 1300 | default: |
| 1301 | case INVERSION_AUTO: |
| 1302 | ch.spectrum_inversion = -1; |
| 1303 | break; |
| 1304 | } |
| 1305 | switch (state->fe[0]->dtv_property_cache.transmission_mode) { |
| 1306 | case TRANSMISSION_MODE_2K: |
| 1307 | ch.nfft = 0; |
| 1308 | break; |
| 1309 | case TRANSMISSION_MODE_4K: |
| 1310 | ch.nfft = 2; |
| 1311 | break; |
| 1312 | case TRANSMISSION_MODE_8K: |
| 1313 | ch.nfft = 1; |
| 1314 | break; |
| 1315 | default: |
| 1316 | case TRANSMISSION_MODE_AUTO: |
| 1317 | ch.nfft = 1; |
| 1318 | break; |
| 1319 | } |
| 1320 | switch (state->fe[0]->dtv_property_cache.guard_interval) { |
| 1321 | case GUARD_INTERVAL_1_32: |
| 1322 | ch.guard = 0; |
| 1323 | break; |
| 1324 | case GUARD_INTERVAL_1_16: |
| 1325 | ch.guard = 1; |
| 1326 | break; |
| 1327 | case GUARD_INTERVAL_1_8: |
| 1328 | ch.guard = 2; |
| 1329 | break; |
| 1330 | case GUARD_INTERVAL_1_4: |
| 1331 | ch.guard = 3; |
| 1332 | break; |
| 1333 | default: |
| 1334 | case GUARD_INTERVAL_AUTO: |
| 1335 | ch.guard = -1; |
| 1336 | break; |
| 1337 | } |
| 1338 | switch (state->fe[0]->dtv_property_cache.modulation) { |
| 1339 | case QAM_64: |
| 1340 | ch.constellation = 2; |
| 1341 | break; |
| 1342 | case QAM_16: |
| 1343 | ch.constellation = 1; |
| 1344 | break; |
| 1345 | case QPSK: |
| 1346 | ch.constellation = 0; |
| 1347 | break; |
| 1348 | default: |
| 1349 | case QAM_AUTO: |
| 1350 | ch.constellation = -1; |
| 1351 | break; |
| 1352 | } |
| 1353 | switch (state->fe[0]->dtv_property_cache.hierarchy) { |
| 1354 | case HIERARCHY_NONE: |
| 1355 | ch.hrch = 0; |
| 1356 | break; |
| 1357 | case HIERARCHY_1: |
| 1358 | case HIERARCHY_2: |
| 1359 | case HIERARCHY_4: |
| 1360 | ch.hrch = 1; |
| 1361 | break; |
| 1362 | default: |
| 1363 | case HIERARCHY_AUTO: |
| 1364 | ch.hrch = -1; |
| 1365 | break; |
| 1366 | } |
| 1367 | ch.alpha = 1; |
| 1368 | switch (state->fe[0]->dtv_property_cache.code_rate_HP) { |
| 1369 | case FEC_1_2: |
| 1370 | ch.code_rate_hp = 1; |
| 1371 | break; |
| 1372 | case FEC_2_3: |
| 1373 | ch.code_rate_hp = 2; |
| 1374 | break; |
| 1375 | case FEC_3_4: |
| 1376 | ch.code_rate_hp = 3; |
| 1377 | break; |
| 1378 | case FEC_5_6: |
| 1379 | ch.code_rate_hp = 5; |
| 1380 | break; |
| 1381 | case FEC_7_8: |
| 1382 | ch.code_rate_hp = 7; |
| 1383 | break; |
| 1384 | default: |
| 1385 | case FEC_AUTO: |
| 1386 | ch.code_rate_hp = -1; |
| 1387 | break; |
| 1388 | } |
| 1389 | switch (state->fe[0]->dtv_property_cache.code_rate_LP) { |
| 1390 | case FEC_1_2: |
| 1391 | ch.code_rate_lp = 1; |
| 1392 | break; |
| 1393 | case FEC_2_3: |
| 1394 | ch.code_rate_lp = 2; |
| 1395 | break; |
| 1396 | case FEC_3_4: |
| 1397 | ch.code_rate_lp = 3; |
| 1398 | break; |
| 1399 | case FEC_5_6: |
| 1400 | ch.code_rate_lp = 5; |
| 1401 | break; |
| 1402 | case FEC_7_8: |
| 1403 | ch.code_rate_lp = 7; |
| 1404 | break; |
| 1405 | default: |
| 1406 | case FEC_AUTO: |
| 1407 | ch.code_rate_lp = -1; |
| 1408 | break; |
| 1409 | } |
| 1410 | ch.select_hp = 1; |
| 1411 | ch.intlv_native = 1; |
| 1412 | |
| 1413 | dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_UNION, (u8 *) &ch); |
| 1414 | |
| 1415 | return 0; |
| 1416 | } |
| 1417 | |
| 1418 | static int dib9000_fw_tune(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch) |
| 1419 | { |
| 1420 | struct dib9000_state *state = fe->demodulator_priv; |
| 1421 | int ret = 10, search = state->channel_status.status == CHANNEL_STATUS_PARAMETERS_UNKNOWN; |
| 1422 | s8 i; |
| 1423 | |
| 1424 | switch (state->tune_state) { |
| 1425 | case CT_DEMOD_START: |
| 1426 | dib9000_fw_set_channel_head(state, ch); |
| 1427 | |
| 1428 | /* write the channel context - a channel is initialized to 0, so it is OK */ |
| 1429 | dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_CONTEXT, (u8 *) fe_info); |
| 1430 | dib9000_risc_mem_write(state, FE_MM_W_FE_INFO, (u8 *) fe_info); |
| 1431 | |
| 1432 | if (search) |
| 1433 | dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_SEARCH, NULL, 0); |
| 1434 | else { |
| 1435 | dib9000_fw_set_channel_union(fe, ch); |
| 1436 | dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_TUNE, NULL, 0); |
| 1437 | } |
| 1438 | state->tune_state = CT_DEMOD_STEP_1; |
| 1439 | break; |
| 1440 | case CT_DEMOD_STEP_1: |
| 1441 | if (search) |
| 1442 | dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_SEARCH_STATE, (u8 *) &i, 1); |
| 1443 | else |
| 1444 | dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_TUNE_STATE, (u8 *) &i, 1); |
| 1445 | switch (i) { /* something happened */ |
| 1446 | case 0: |
| 1447 | break; |
| 1448 | case -2: /* tps locks are "slower" than MPEG locks -> even in autosearch data is OK here */ |
| 1449 | if (search) |
| 1450 | state->status = FE_STATUS_DEMOD_SUCCESS; |
| 1451 | else { |
| 1452 | state->tune_state = CT_DEMOD_STOP; |
| 1453 | state->status = FE_STATUS_LOCKED; |
| 1454 | } |
| 1455 | break; |
| 1456 | default: |
| 1457 | state->status = FE_STATUS_TUNE_FAILED; |
| 1458 | state->tune_state = CT_DEMOD_STOP; |
| 1459 | break; |
| 1460 | } |
| 1461 | break; |
| 1462 | default: |
| 1463 | ret = FE_CALLBACK_TIME_NEVER; |
| 1464 | break; |
| 1465 | } |
| 1466 | |
| 1467 | return ret; |
| 1468 | } |
| 1469 | |
| 1470 | static int dib9000_fw_set_diversity_in(struct dvb_frontend *fe, int onoff) |
| 1471 | { |
| 1472 | struct dib9000_state *state = fe->demodulator_priv; |
| 1473 | u16 mode = (u16) onoff; |
| 1474 | return dib9000_mbx_send(state, OUT_MSG_ENABLE_DIVERSITY, &mode, 1); |
| 1475 | } |
| 1476 | |
| 1477 | static int dib9000_fw_set_output_mode(struct dvb_frontend *fe, int mode) |
| 1478 | { |
| 1479 | struct dib9000_state *state = fe->demodulator_priv; |
| 1480 | u16 outreg, smo_mode; |
| 1481 | |
| 1482 | dprintk("setting output mode for demod %p to %d", fe, mode); |
| 1483 | |
| 1484 | switch (mode) { |
| 1485 | case OUTMODE_MPEG2_PAR_GATED_CLK: |
| 1486 | outreg = (1 << 10); /* 0x0400 */ |
| 1487 | break; |
| 1488 | case OUTMODE_MPEG2_PAR_CONT_CLK: |
| 1489 | outreg = (1 << 10) | (1 << 6); /* 0x0440 */ |
| 1490 | break; |
| 1491 | case OUTMODE_MPEG2_SERIAL: |
| 1492 | outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */ |
| 1493 | break; |
| 1494 | case OUTMODE_DIVERSITY: |
| 1495 | outreg = (1 << 10) | (4 << 6); /* 0x0500 */ |
| 1496 | break; |
| 1497 | case OUTMODE_MPEG2_FIFO: |
| 1498 | outreg = (1 << 10) | (5 << 6); |
| 1499 | break; |
| 1500 | case OUTMODE_HIGH_Z: |
| 1501 | outreg = 0; |
| 1502 | break; |
| 1503 | default: |
| 1504 | dprintk("Unhandled output_mode passed to be set for demod %p", &state->fe[0]); |
| 1505 | return -EINVAL; |
| 1506 | } |
| 1507 | |
| 1508 | dib9000_write_word(state, 1795, outreg); |
| 1509 | |
| 1510 | switch (mode) { |
| 1511 | case OUTMODE_MPEG2_PAR_GATED_CLK: |
| 1512 | case OUTMODE_MPEG2_PAR_CONT_CLK: |
| 1513 | case OUTMODE_MPEG2_SERIAL: |
| 1514 | case OUTMODE_MPEG2_FIFO: |
| 1515 | smo_mode = (dib9000_read_word(state, 295) & 0x0010) | (1 << 1); |
| 1516 | if (state->chip.d9.cfg.output_mpeg2_in_188_bytes) |
| 1517 | smo_mode |= (1 << 5); |
| 1518 | dib9000_write_word(state, 295, smo_mode); |
| 1519 | break; |
| 1520 | } |
| 1521 | |
| 1522 | outreg = to_fw_output_mode(mode); |
| 1523 | return dib9000_mbx_send(state, OUT_MSG_SET_OUTPUT_MODE, &outreg, 1); |
| 1524 | } |
| 1525 | |
| 1526 | static int dib9000_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num) |
| 1527 | { |
| 1528 | struct dib9000_state *state = i2c_get_adapdata(i2c_adap); |
| 1529 | u16 i, len, t, index_msg; |
| 1530 | |
| 1531 | for (index_msg = 0; index_msg < num; index_msg++) { |
| 1532 | if (msg[index_msg].flags & I2C_M_RD) { /* read */ |
| 1533 | len = msg[index_msg].len; |
| 1534 | if (len > 16) |
| 1535 | len = 16; |
| 1536 | |
| 1537 | if (dib9000_read_word(state, 790) != 0) |
| 1538 | dprintk("TunerITF: read busy"); |
| 1539 | |
| 1540 | dib9000_write_word(state, 784, (u16) (msg[index_msg].addr)); |
| 1541 | dib9000_write_word(state, 787, (len / 2) - 1); |
| 1542 | dib9000_write_word(state, 786, 1); /* start read */ |
| 1543 | |
| 1544 | i = 1000; |
| 1545 | while (dib9000_read_word(state, 790) != (len / 2) && i) |
| 1546 | i--; |
| 1547 | |
| 1548 | if (i == 0) |
| 1549 | dprintk("TunerITF: read failed"); |
| 1550 | |
| 1551 | for (i = 0; i < len; i += 2) { |
| 1552 | t = dib9000_read_word(state, 785); |
| 1553 | msg[index_msg].buf[i] = (t >> 8) & 0xff; |
| 1554 | msg[index_msg].buf[i + 1] = (t) & 0xff; |
| 1555 | } |
| 1556 | if (dib9000_read_word(state, 790) != 0) |
| 1557 | dprintk("TunerITF: read more data than expected"); |
| 1558 | } else { |
| 1559 | i = 1000; |
| 1560 | while (dib9000_read_word(state, 789) && i) |
| 1561 | i--; |
| 1562 | if (i == 0) |
| 1563 | dprintk("TunerITF: write busy"); |
| 1564 | |
| 1565 | len = msg[index_msg].len; |
| 1566 | if (len > 16) |
| 1567 | len = 16; |
| 1568 | |
| 1569 | for (i = 0; i < len; i += 2) |
| 1570 | dib9000_write_word(state, 785, (msg[index_msg].buf[i] << 8) | msg[index_msg].buf[i + 1]); |
| 1571 | dib9000_write_word(state, 784, (u16) msg[index_msg].addr); |
| 1572 | dib9000_write_word(state, 787, (len / 2) - 1); |
| 1573 | dib9000_write_word(state, 786, 0); /* start write */ |
| 1574 | |
| 1575 | i = 1000; |
| 1576 | while (dib9000_read_word(state, 791) > 0 && i) |
| 1577 | i--; |
| 1578 | if (i == 0) |
| 1579 | dprintk("TunerITF: write failed"); |
| 1580 | } |
| 1581 | } |
| 1582 | return num; |
| 1583 | } |
| 1584 | |
| 1585 | int dib9000_fw_set_component_bus_speed(struct dvb_frontend *fe, u16 speed) |
| 1586 | { |
| 1587 | struct dib9000_state *state = fe->demodulator_priv; |
| 1588 | |
| 1589 | state->component_bus_speed = speed; |
| 1590 | return 0; |
| 1591 | } |
| 1592 | EXPORT_SYMBOL(dib9000_fw_set_component_bus_speed); |
| 1593 | |
| 1594 | static int dib9000_fw_component_bus_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num) |
| 1595 | { |
| 1596 | struct dib9000_state *state = i2c_get_adapdata(i2c_adap); |
| 1597 | u8 type = 0; /* I2C */ |
| 1598 | u8 port = DIBX000_I2C_INTERFACE_GPIO_3_4; |
| 1599 | u16 scl = state->component_bus_speed; /* SCL frequency */ |
| 1600 | struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[FE_MM_RW_COMPONENT_ACCESS_BUFFER]; |
| 1601 | u8 p[13] = { 0 }; |
| 1602 | |
| 1603 | p[0] = type; |
| 1604 | p[1] = port; |
| 1605 | p[2] = msg[0].addr << 1; |
| 1606 | |
| 1607 | p[3] = (u8) scl & 0xff; /* scl */ |
| 1608 | p[4] = (u8) (scl >> 8); |
| 1609 | |
| 1610 | p[7] = 0; |
| 1611 | p[8] = 0; |
| 1612 | |
| 1613 | p[9] = (u8) (msg[0].len); |
| 1614 | p[10] = (u8) (msg[0].len >> 8); |
| 1615 | if ((num > 1) && (msg[1].flags & I2C_M_RD)) { |
| 1616 | p[11] = (u8) (msg[1].len); |
| 1617 | p[12] = (u8) (msg[1].len >> 8); |
| 1618 | } else { |
| 1619 | p[11] = 0; |
| 1620 | p[12] = 0; |
| 1621 | } |
| 1622 | |
| 1623 | DibAcquireLock(&state->platform.risc.mem_mbx_lock); |
| 1624 | |
| 1625 | dib9000_risc_mem_write(state, FE_MM_W_COMPONENT_ACCESS, p); |
| 1626 | |
| 1627 | { /* write-part */ |
| 1628 | dib9000_risc_mem_setup_cmd(state, m->addr, msg[0].len, 0); |
| 1629 | dib9000_risc_mem_write_chunks(state, msg[0].buf, msg[0].len); |
| 1630 | } |
| 1631 | |
| 1632 | /* do the transaction */ |
| 1633 | if (dib9000_fw_memmbx_sync(state, FE_SYNC_COMPONENT_ACCESS) < 0) { |
| 1634 | DibReleaseLock(&state->platform.risc.mem_mbx_lock); |
| 1635 | return 0; |
| 1636 | } |
| 1637 | |
| 1638 | /* read back any possible result */ |
| 1639 | if ((num > 1) && (msg[1].flags & I2C_M_RD)) |
| 1640 | dib9000_risc_mem_read(state, FE_MM_RW_COMPONENT_ACCESS_BUFFER, msg[1].buf, msg[1].len); |
| 1641 | |
| 1642 | DibReleaseLock(&state->platform.risc.mem_mbx_lock); |
| 1643 | |
| 1644 | return num; |
| 1645 | } |
| 1646 | |
| 1647 | static u32 dib9000_i2c_func(struct i2c_adapter *adapter) |
| 1648 | { |
| 1649 | return I2C_FUNC_I2C; |
| 1650 | } |
| 1651 | |
| 1652 | static struct i2c_algorithm dib9000_tuner_algo = { |
| 1653 | .master_xfer = dib9000_tuner_xfer, |
| 1654 | .functionality = dib9000_i2c_func, |
| 1655 | }; |
| 1656 | |
| 1657 | static struct i2c_algorithm dib9000_component_bus_algo = { |
| 1658 | .master_xfer = dib9000_fw_component_bus_xfer, |
| 1659 | .functionality = dib9000_i2c_func, |
| 1660 | }; |
| 1661 | |
| 1662 | struct i2c_adapter *dib9000_get_tuner_interface(struct dvb_frontend *fe) |
| 1663 | { |
| 1664 | struct dib9000_state *st = fe->demodulator_priv; |
| 1665 | return &st->tuner_adap; |
| 1666 | } |
| 1667 | EXPORT_SYMBOL(dib9000_get_tuner_interface); |
| 1668 | |
| 1669 | struct i2c_adapter *dib9000_get_component_bus_interface(struct dvb_frontend *fe) |
| 1670 | { |
| 1671 | struct dib9000_state *st = fe->demodulator_priv; |
| 1672 | return &st->component_bus; |
| 1673 | } |
| 1674 | EXPORT_SYMBOL(dib9000_get_component_bus_interface); |
| 1675 | |
| 1676 | struct i2c_adapter *dib9000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating) |
| 1677 | { |
| 1678 | struct dib9000_state *st = fe->demodulator_priv; |
| 1679 | return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating); |
| 1680 | } |
| 1681 | EXPORT_SYMBOL(dib9000_get_i2c_master); |
| 1682 | |
| 1683 | int dib9000_set_i2c_adapter(struct dvb_frontend *fe, struct i2c_adapter *i2c) |
| 1684 | { |
| 1685 | struct dib9000_state *st = fe->demodulator_priv; |
| 1686 | |
| 1687 | st->i2c.i2c_adap = i2c; |
| 1688 | return 0; |
| 1689 | } |
| 1690 | EXPORT_SYMBOL(dib9000_set_i2c_adapter); |
| 1691 | |
| 1692 | static int dib9000_cfg_gpio(struct dib9000_state *st, u8 num, u8 dir, u8 val) |
| 1693 | { |
| 1694 | st->gpio_dir = dib9000_read_word(st, 773); |
| 1695 | st->gpio_dir &= ~(1 << num); /* reset the direction bit */ |
| 1696 | st->gpio_dir |= (dir & 0x1) << num; /* set the new direction */ |
| 1697 | dib9000_write_word(st, 773, st->gpio_dir); |
| 1698 | |
| 1699 | st->gpio_val = dib9000_read_word(st, 774); |
| 1700 | st->gpio_val &= ~(1 << num); /* reset the direction bit */ |
| 1701 | st->gpio_val |= (val & 0x01) << num; /* set the new value */ |
| 1702 | dib9000_write_word(st, 774, st->gpio_val); |
| 1703 | |
| 1704 | dprintk("gpio dir: %04x: gpio val: %04x", st->gpio_dir, st->gpio_val); |
| 1705 | |
| 1706 | return 0; |
| 1707 | } |
| 1708 | |
| 1709 | int dib9000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val) |
| 1710 | { |
| 1711 | struct dib9000_state *state = fe->demodulator_priv; |
| 1712 | return dib9000_cfg_gpio(state, num, dir, val); |
| 1713 | } |
| 1714 | EXPORT_SYMBOL(dib9000_set_gpio); |
| 1715 | |
| 1716 | int dib9000_fw_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff) |
| 1717 | { |
| 1718 | struct dib9000_state *state = fe->demodulator_priv; |
| 1719 | u16 val = dib9000_read_word(state, 294 + 1) & 0xffef; |
| 1720 | val |= (onoff & 0x1) << 4; |
| 1721 | |
| 1722 | dprintk("PID filter enabled %d", onoff); |
| 1723 | return dib9000_write_word(state, 294 + 1, val); |
| 1724 | } |
| 1725 | EXPORT_SYMBOL(dib9000_fw_pid_filter_ctrl); |
| 1726 | |
| 1727 | int dib9000_fw_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff) |
| 1728 | { |
| 1729 | struct dib9000_state *state = fe->demodulator_priv; |
| 1730 | dprintk("Index %x, PID %d, OnOff %d", id, pid, onoff); |
| 1731 | return dib9000_write_word(state, 300 + 1 + id, onoff ? (1 << 13) | pid : 0); |
| 1732 | } |
| 1733 | EXPORT_SYMBOL(dib9000_fw_pid_filter); |
| 1734 | |
| 1735 | int dib9000_firmware_post_pll_init(struct dvb_frontend *fe) |
| 1736 | { |
| 1737 | struct dib9000_state *state = fe->demodulator_priv; |
| 1738 | return dib9000_fw_init(state); |
| 1739 | } |
| 1740 | EXPORT_SYMBOL(dib9000_firmware_post_pll_init); |
| 1741 | |
| 1742 | static void dib9000_release(struct dvb_frontend *demod) |
| 1743 | { |
| 1744 | struct dib9000_state *st = demod->demodulator_priv; |
| 1745 | u8 index_frontend; |
| 1746 | |
| 1747 | for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++) |
| 1748 | dvb_frontend_detach(st->fe[index_frontend]); |
| 1749 | |
| 1750 | DibFreeLock(&state->platform.risc.mbx_if_lock); |
| 1751 | DibFreeLock(&state->platform.risc.mbx_lock); |
| 1752 | DibFreeLock(&state->platform.risc.mem_lock); |
| 1753 | DibFreeLock(&state->platform.risc.mem_mbx_lock); |
| 1754 | dibx000_exit_i2c_master(&st->i2c_master); |
| 1755 | |
| 1756 | i2c_del_adapter(&st->tuner_adap); |
| 1757 | i2c_del_adapter(&st->component_bus); |
| 1758 | kfree(st->fe[0]); |
| 1759 | kfree(st); |
| 1760 | } |
| 1761 | |
| 1762 | static int dib9000_wakeup(struct dvb_frontend *fe) |
| 1763 | { |
| 1764 | return 0; |
| 1765 | } |
| 1766 | |
| 1767 | static int dib9000_sleep(struct dvb_frontend *fe) |
| 1768 | { |
| 1769 | struct dib9000_state *state = fe->demodulator_priv; |
| 1770 | u8 index_frontend; |
| 1771 | int ret; |
| 1772 | |
| 1773 | for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { |
| 1774 | ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]); |
| 1775 | if (ret < 0) |
| 1776 | return ret; |
| 1777 | } |
| 1778 | return dib9000_mbx_send(state, OUT_MSG_FE_SLEEP, NULL, 0); |
| 1779 | } |
| 1780 | |
| 1781 | static int dib9000_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune) |
| 1782 | { |
| 1783 | tune->min_delay_ms = 1000; |
| 1784 | return 0; |
| 1785 | } |
| 1786 | |
| 1787 | static int dib9000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep) |
| 1788 | { |
| 1789 | struct dib9000_state *state = fe->demodulator_priv; |
| 1790 | u8 index_frontend, sub_index_frontend; |
| 1791 | fe_status_t stat; |
| 1792 | int ret; |
| 1793 | |
| 1794 | for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { |
| 1795 | state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat); |
| 1796 | if (stat & FE_HAS_SYNC) { |
| 1797 | dprintk("TPS lock on the slave%i", index_frontend); |
| 1798 | |
| 1799 | /* synchronize the cache with the other frontends */ |
| 1800 | state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], fep); |
| 1801 | for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); |
| 1802 | sub_index_frontend++) { |
| 1803 | if (sub_index_frontend != index_frontend) { |
| 1804 | state->fe[sub_index_frontend]->dtv_property_cache.modulation = |
| 1805 | state->fe[index_frontend]->dtv_property_cache.modulation; |
| 1806 | state->fe[sub_index_frontend]->dtv_property_cache.inversion = |
| 1807 | state->fe[index_frontend]->dtv_property_cache.inversion; |
| 1808 | state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode = |
| 1809 | state->fe[index_frontend]->dtv_property_cache.transmission_mode; |
| 1810 | state->fe[sub_index_frontend]->dtv_property_cache.guard_interval = |
| 1811 | state->fe[index_frontend]->dtv_property_cache.guard_interval; |
| 1812 | state->fe[sub_index_frontend]->dtv_property_cache.hierarchy = |
| 1813 | state->fe[index_frontend]->dtv_property_cache.hierarchy; |
| 1814 | state->fe[sub_index_frontend]->dtv_property_cache.code_rate_HP = |
| 1815 | state->fe[index_frontend]->dtv_property_cache.code_rate_HP; |
| 1816 | state->fe[sub_index_frontend]->dtv_property_cache.code_rate_LP = |
| 1817 | state->fe[index_frontend]->dtv_property_cache.code_rate_LP; |
| 1818 | state->fe[sub_index_frontend]->dtv_property_cache.rolloff = |
| 1819 | state->fe[index_frontend]->dtv_property_cache.rolloff; |
| 1820 | } |
| 1821 | } |
| 1822 | return 0; |
| 1823 | } |
| 1824 | } |
| 1825 | |
| 1826 | /* get the channel from master chip */ |
| 1827 | ret = dib9000_fw_get_channel(fe, fep); |
| 1828 | if (ret != 0) |
| 1829 | return ret; |
| 1830 | |
| 1831 | /* synchronize the cache with the other frontends */ |
| 1832 | for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { |
| 1833 | state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion; |
| 1834 | state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmission_mode; |
| 1835 | state->fe[index_frontend]->dtv_property_cache.guard_interval = fe->dtv_property_cache.guard_interval; |
| 1836 | state->fe[index_frontend]->dtv_property_cache.modulation = fe->dtv_property_cache.modulation; |
| 1837 | state->fe[index_frontend]->dtv_property_cache.hierarchy = fe->dtv_property_cache.hierarchy; |
| 1838 | state->fe[index_frontend]->dtv_property_cache.code_rate_HP = fe->dtv_property_cache.code_rate_HP; |
| 1839 | state->fe[index_frontend]->dtv_property_cache.code_rate_LP = fe->dtv_property_cache.code_rate_LP; |
| 1840 | state->fe[index_frontend]->dtv_property_cache.rolloff = fe->dtv_property_cache.rolloff; |
| 1841 | } |
| 1842 | |
| 1843 | return 0; |
| 1844 | } |
| 1845 | |
| 1846 | static int dib9000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state) |
| 1847 | { |
| 1848 | struct dib9000_state *state = fe->demodulator_priv; |
| 1849 | state->tune_state = tune_state; |
| 1850 | if (tune_state == CT_DEMOD_START) |
| 1851 | state->status = FE_STATUS_TUNE_PENDING; |
| 1852 | |
| 1853 | return 0; |
| 1854 | } |
| 1855 | |
| 1856 | static u32 dib9000_get_status(struct dvb_frontend *fe) |
| 1857 | { |
| 1858 | struct dib9000_state *state = fe->demodulator_priv; |
| 1859 | return state->status; |
| 1860 | } |
| 1861 | |
| 1862 | static int dib9000_set_channel_status(struct dvb_frontend *fe, struct dvb_frontend_parametersContext *channel_status) |
| 1863 | { |
| 1864 | struct dib9000_state *state = fe->demodulator_priv; |
| 1865 | |
| 1866 | memcpy(&state->channel_status, channel_status, sizeof(struct dvb_frontend_parametersContext)); |
| 1867 | return 0; |
| 1868 | } |
| 1869 | |
| 1870 | static int dib9000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep) |
| 1871 | { |
| 1872 | struct dib9000_state *state = fe->demodulator_priv; |
| 1873 | int sleep_time, sleep_time_slave; |
| 1874 | u32 frontend_status; |
| 1875 | u8 nbr_pending, exit_condition, index_frontend, index_frontend_success; |
| 1876 | struct dvb_frontend_parametersContext channel_status; |
| 1877 | |
| 1878 | /* check that the correct parameters are set */ |
| 1879 | if (state->fe[0]->dtv_property_cache.frequency == 0) { |
| 1880 | dprintk("dib9000: must specify frequency "); |
| 1881 | return 0; |
| 1882 | } |
| 1883 | |
| 1884 | if (state->fe[0]->dtv_property_cache.bandwidth_hz == 0) { |
| 1885 | dprintk("dib9000: must specify bandwidth "); |
| 1886 | return 0; |
| 1887 | } |
| 1888 | fe->dtv_property_cache.delivery_system = SYS_DVBT; |
| 1889 | |
| 1890 | /* set the master status */ |
| 1891 | if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO || |
| 1892 | fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO || fep->u.ofdm.constellation == QAM_AUTO || fep->u.ofdm.code_rate_HP == FEC_AUTO) { |
| 1893 | /* no channel specified, autosearch the channel */ |
| 1894 | state->channel_status.status = CHANNEL_STATUS_PARAMETERS_UNKNOWN; |
| 1895 | } else |
| 1896 | state->channel_status.status = CHANNEL_STATUS_PARAMETERS_SET; |
| 1897 | |
| 1898 | /* set mode and status for the different frontends */ |
| 1899 | for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { |
| 1900 | dib9000_fw_set_diversity_in(state->fe[index_frontend], 1); |
| 1901 | |
| 1902 | /* synchronization of the cache */ |
| 1903 | memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties)); |
| 1904 | |
| 1905 | state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_DVBT; |
| 1906 | dib9000_fw_set_output_mode(state->fe[index_frontend], OUTMODE_HIGH_Z); |
| 1907 | |
| 1908 | dib9000_set_channel_status(state->fe[index_frontend], &state->channel_status); |
| 1909 | dib9000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START); |
| 1910 | } |
| 1911 | |
| 1912 | /* actual tune */ |
| 1913 | exit_condition = 0; /* 0: tune pending; 1: tune failed; 2:tune success */ |
| 1914 | index_frontend_success = 0; |
| 1915 | do { |
| 1916 | sleep_time = dib9000_fw_tune(state->fe[0], NULL); |
| 1917 | for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { |
| 1918 | sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend], NULL); |
| 1919 | if (sleep_time == FE_CALLBACK_TIME_NEVER) |
| 1920 | sleep_time = sleep_time_slave; |
| 1921 | else if ((sleep_time_slave != FE_CALLBACK_TIME_NEVER) && (sleep_time_slave > sleep_time)) |
| 1922 | sleep_time = sleep_time_slave; |
| 1923 | } |
| 1924 | if (sleep_time != FE_CALLBACK_TIME_NEVER) |
| 1925 | msleep(sleep_time / 10); |
| 1926 | else |
| 1927 | break; |
| 1928 | |
| 1929 | nbr_pending = 0; |
| 1930 | exit_condition = 0; |
| 1931 | index_frontend_success = 0; |
| 1932 | for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { |
| 1933 | frontend_status = -dib9000_get_status(state->fe[index_frontend]); |
| 1934 | if (frontend_status > -FE_STATUS_TUNE_PENDING) { |
| 1935 | exit_condition = 2; /* tune success */ |
| 1936 | index_frontend_success = index_frontend; |
| 1937 | break; |
| 1938 | } |
| 1939 | if (frontend_status == -FE_STATUS_TUNE_PENDING) |
| 1940 | nbr_pending++; /* some frontends are still tuning */ |
| 1941 | } |
| 1942 | if ((exit_condition != 2) && (nbr_pending == 0)) |
| 1943 | exit_condition = 1; /* if all tune are done and no success, exit: tune failed */ |
| 1944 | |
| 1945 | } while (exit_condition == 0); |
| 1946 | |
| 1947 | /* check the tune result */ |
| 1948 | if (exit_condition == 1) { /* tune failed */ |
| 1949 | dprintk("tune failed"); |
| 1950 | return 0; |
| 1951 | } |
| 1952 | |
| 1953 | dprintk("tune success on frontend%i", index_frontend_success); |
| 1954 | |
| 1955 | /* synchronize all the channel cache */ |
| 1956 | dib9000_get_frontend(state->fe[0], fep); |
| 1957 | |
| 1958 | /* retune the other frontends with the found channel */ |
| 1959 | channel_status.status = CHANNEL_STATUS_PARAMETERS_SET; |
| 1960 | for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { |
| 1961 | /* only retune the frontends which was not tuned success */ |
| 1962 | if (index_frontend != index_frontend_success) { |
| 1963 | dib9000_set_channel_status(state->fe[index_frontend], &channel_status); |
| 1964 | dib9000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START); |
| 1965 | } |
| 1966 | } |
| 1967 | do { |
| 1968 | sleep_time = FE_CALLBACK_TIME_NEVER; |
| 1969 | for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { |
| 1970 | if (index_frontend != index_frontend_success) { |
| 1971 | sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend], NULL); |
| 1972 | if (sleep_time == FE_CALLBACK_TIME_NEVER) |
| 1973 | sleep_time = sleep_time_slave; |
| 1974 | else if ((sleep_time_slave != FE_CALLBACK_TIME_NEVER) && (sleep_time_slave > sleep_time)) |
| 1975 | sleep_time = sleep_time_slave; |
| 1976 | } |
| 1977 | } |
| 1978 | if (sleep_time != FE_CALLBACK_TIME_NEVER) |
| 1979 | msleep(sleep_time / 10); |
| 1980 | else |
| 1981 | break; |
| 1982 | |
| 1983 | nbr_pending = 0; |
| 1984 | for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { |
| 1985 | if (index_frontend != index_frontend_success) { |
| 1986 | frontend_status = -dib9000_get_status(state->fe[index_frontend]); |
| 1987 | if ((index_frontend != index_frontend_success) && (frontend_status == -FE_STATUS_TUNE_PENDING)) |
| 1988 | nbr_pending++; /* some frontends are still tuning */ |
| 1989 | } |
| 1990 | } |
| 1991 | } while (nbr_pending != 0); |
| 1992 | |
| 1993 | /* set the output mode */ |
| 1994 | dib9000_fw_set_output_mode(state->fe[0], state->chip.d9.cfg.output_mode); |
| 1995 | for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) |
| 1996 | dib9000_fw_set_output_mode(state->fe[index_frontend], OUTMODE_DIVERSITY); |
| 1997 | |
| 1998 | /* turn off the diversity for the last frontend */ |
| 1999 | dib9000_fw_set_diversity_in(state->fe[index_frontend - 1], 0); |
| 2000 | |
| 2001 | return 0; |
| 2002 | } |
| 2003 | |
| 2004 | static u16 dib9000_read_lock(struct dvb_frontend *fe) |
| 2005 | { |
| 2006 | struct dib9000_state *state = fe->demodulator_priv; |
| 2007 | |
| 2008 | return dib9000_read_word(state, 535); |
| 2009 | } |
| 2010 | |
| 2011 | static int dib9000_read_status(struct dvb_frontend *fe, fe_status_t * stat) |
| 2012 | { |
| 2013 | struct dib9000_state *state = fe->demodulator_priv; |
| 2014 | u8 index_frontend; |
| 2015 | u16 lock = 0, lock_slave = 0; |
| 2016 | |
| 2017 | for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) |
| 2018 | lock_slave |= dib9000_read_lock(state->fe[index_frontend]); |
| 2019 | |
| 2020 | lock = dib9000_read_word(state, 535); |
| 2021 | |
| 2022 | *stat = 0; |
| 2023 | |
| 2024 | if ((lock & 0x8000) || (lock_slave & 0x8000)) |
| 2025 | *stat |= FE_HAS_SIGNAL; |
| 2026 | if ((lock & 0x3000) || (lock_slave & 0x3000)) |
| 2027 | *stat |= FE_HAS_CARRIER; |
| 2028 | if ((lock & 0x0100) || (lock_slave & 0x0100)) |
| 2029 | *stat |= FE_HAS_VITERBI; |
| 2030 | if (((lock & 0x0038) == 0x38) || ((lock_slave & 0x0038) == 0x38)) |
| 2031 | *stat |= FE_HAS_SYNC; |
| 2032 | if ((lock & 0x0008) || (lock_slave & 0x0008)) |
| 2033 | *stat |= FE_HAS_LOCK; |
| 2034 | |
| 2035 | return 0; |
| 2036 | } |
| 2037 | |
| 2038 | static int dib9000_read_ber(struct dvb_frontend *fe, u32 * ber) |
| 2039 | { |
| 2040 | struct dib9000_state *state = fe->demodulator_priv; |
| 2041 | u16 c[16]; |
| 2042 | |
| 2043 | DibAcquireLock(&state->platform.risc.mem_mbx_lock); |
| 2044 | if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) |
| 2045 | return -EIO; |
| 2046 | dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c)); |
| 2047 | DibReleaseLock(&state->platform.risc.mem_mbx_lock); |
| 2048 | |
| 2049 | *ber = c[10] << 16 | c[11]; |
| 2050 | return 0; |
| 2051 | } |
| 2052 | |
| 2053 | static int dib9000_read_signal_strength(struct dvb_frontend *fe, u16 * strength) |
| 2054 | { |
| 2055 | struct dib9000_state *state = fe->demodulator_priv; |
| 2056 | u8 index_frontend; |
| 2057 | u16 c[16]; |
| 2058 | u16 val; |
| 2059 | |
| 2060 | *strength = 0; |
| 2061 | for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { |
| 2062 | state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val); |
| 2063 | if (val > 65535 - *strength) |
| 2064 | *strength = 65535; |
| 2065 | else |
| 2066 | *strength += val; |
| 2067 | } |
| 2068 | |
| 2069 | DibAcquireLock(&state->platform.risc.mem_mbx_lock); |
| 2070 | if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) |
| 2071 | return -EIO; |
| 2072 | dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c)); |
| 2073 | DibReleaseLock(&state->platform.risc.mem_mbx_lock); |
| 2074 | |
| 2075 | val = 65535 - c[4]; |
| 2076 | if (val > 65535 - *strength) |
| 2077 | *strength = 65535; |
| 2078 | else |
| 2079 | *strength += val; |
| 2080 | return 0; |
| 2081 | } |
| 2082 | |
| 2083 | static u32 dib9000_get_snr(struct dvb_frontend *fe) |
| 2084 | { |
| 2085 | struct dib9000_state *state = fe->demodulator_priv; |
| 2086 | u16 c[16]; |
| 2087 | u32 n, s, exp; |
| 2088 | u16 val; |
| 2089 | |
| 2090 | DibAcquireLock(&state->platform.risc.mem_mbx_lock); |
| 2091 | if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) |
| 2092 | return -EIO; |
| 2093 | dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c)); |
| 2094 | DibReleaseLock(&state->platform.risc.mem_mbx_lock); |
| 2095 | |
| 2096 | val = c[7]; |
| 2097 | n = (val >> 4) & 0xff; |
| 2098 | exp = ((val & 0xf) << 2); |
| 2099 | val = c[8]; |
| 2100 | exp += ((val >> 14) & 0x3); |
| 2101 | if ((exp & 0x20) != 0) |
| 2102 | exp -= 0x40; |
| 2103 | n <<= exp + 16; |
| 2104 | |
| 2105 | s = (val >> 6) & 0xFF; |
| 2106 | exp = (val & 0x3F); |
| 2107 | if ((exp & 0x20) != 0) |
| 2108 | exp -= 0x40; |
| 2109 | s <<= exp + 16; |
| 2110 | |
| 2111 | if (n > 0) { |
| 2112 | u32 t = (s / n) << 16; |
| 2113 | return t + ((s << 16) - n * t) / n; |
| 2114 | } |
| 2115 | return 0xffffffff; |
| 2116 | } |
| 2117 | |
| 2118 | static int dib9000_read_snr(struct dvb_frontend *fe, u16 * snr) |
| 2119 | { |
| 2120 | struct dib9000_state *state = fe->demodulator_priv; |
| 2121 | u8 index_frontend; |
| 2122 | u32 snr_master; |
| 2123 | |
| 2124 | snr_master = dib9000_get_snr(fe); |
| 2125 | for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) |
| 2126 | snr_master += dib9000_get_snr(state->fe[index_frontend]); |
| 2127 | |
| 2128 | if ((snr_master >> 16) != 0) { |
| 2129 | snr_master = 10 * intlog10(snr_master >> 16); |
| 2130 | *snr = snr_master / ((1 << 24) / 10); |
| 2131 | } else |
| 2132 | *snr = 0; |
| 2133 | |
| 2134 | return 0; |
| 2135 | } |
| 2136 | |
| 2137 | static int dib9000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc) |
| 2138 | { |
| 2139 | struct dib9000_state *state = fe->demodulator_priv; |
| 2140 | u16 c[16]; |
| 2141 | |
| 2142 | DibAcquireLock(&state->platform.risc.mem_mbx_lock); |
| 2143 | if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) |
| 2144 | return -EIO; |
| 2145 | dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c)); |
| 2146 | DibReleaseLock(&state->platform.risc.mem_mbx_lock); |
| 2147 | |
| 2148 | *unc = c[12]; |
| 2149 | return 0; |
| 2150 | } |
| 2151 | |
| 2152 | int dib9000_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, u8 first_addr) |
| 2153 | { |
| 2154 | int k = 0; |
| 2155 | u8 new_addr = 0; |
| 2156 | struct i2c_device client = {.i2c_adap = i2c }; |
| 2157 | |
| 2158 | client.i2c_addr = default_addr + 16; |
| 2159 | dib9000_i2c_write16(&client, 1796, 0x0); |
| 2160 | |
| 2161 | for (k = no_of_demods - 1; k >= 0; k--) { |
| 2162 | /* designated i2c address */ |
| 2163 | new_addr = first_addr + (k << 1); |
| 2164 | client.i2c_addr = default_addr; |
| 2165 | |
| 2166 | dib9000_i2c_write16(&client, 1817, 3); |
| 2167 | dib9000_i2c_write16(&client, 1796, 0); |
| 2168 | dib9000_i2c_write16(&client, 1227, 1); |
| 2169 | dib9000_i2c_write16(&client, 1227, 0); |
| 2170 | |
| 2171 | client.i2c_addr = new_addr; |
| 2172 | dib9000_i2c_write16(&client, 1817, 3); |
| 2173 | dib9000_i2c_write16(&client, 1796, 0); |
| 2174 | dib9000_i2c_write16(&client, 1227, 1); |
| 2175 | dib9000_i2c_write16(&client, 1227, 0); |
| 2176 | |
| 2177 | if (dib9000_identify(&client) == 0) { |
| 2178 | client.i2c_addr = default_addr; |
| 2179 | if (dib9000_identify(&client) == 0) { |
| 2180 | dprintk("DiB9000 #%d: not identified", k); |
| 2181 | return -EIO; |
| 2182 | } |
| 2183 | } |
| 2184 | |
| 2185 | dib9000_i2c_write16(&client, 1795, (1 << 10) | (4 << 6)); |
| 2186 | dib9000_i2c_write16(&client, 1794, (new_addr << 2) | 2); |
| 2187 | |
| 2188 | dprintk("IC %d initialized (to i2c_address 0x%x)", k, new_addr); |
| 2189 | } |
| 2190 | |
| 2191 | for (k = 0; k < no_of_demods; k++) { |
| 2192 | new_addr = first_addr | (k << 1); |
| 2193 | client.i2c_addr = new_addr; |
| 2194 | |
| 2195 | dib9000_i2c_write16(&client, 1794, (new_addr << 2)); |
| 2196 | dib9000_i2c_write16(&client, 1795, 0); |
| 2197 | } |
| 2198 | |
| 2199 | return 0; |
| 2200 | } |
| 2201 | EXPORT_SYMBOL(dib9000_i2c_enumeration); |
| 2202 | |
| 2203 | int dib9000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave) |
| 2204 | { |
| 2205 | struct dib9000_state *state = fe->demodulator_priv; |
| 2206 | u8 index_frontend = 1; |
| 2207 | |
| 2208 | while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL)) |
| 2209 | index_frontend++; |
| 2210 | if (index_frontend < MAX_NUMBER_OF_FRONTENDS) { |
| 2211 | dprintk("set slave fe %p to index %i", fe_slave, index_frontend); |
| 2212 | state->fe[index_frontend] = fe_slave; |
| 2213 | return 0; |
| 2214 | } |
| 2215 | |
| 2216 | dprintk("too many slave frontend"); |
| 2217 | return -ENOMEM; |
| 2218 | } |
| 2219 | EXPORT_SYMBOL(dib9000_set_slave_frontend); |
| 2220 | |
| 2221 | int dib9000_remove_slave_frontend(struct dvb_frontend *fe) |
| 2222 | { |
| 2223 | struct dib9000_state *state = fe->demodulator_priv; |
| 2224 | u8 index_frontend = 1; |
| 2225 | |
| 2226 | while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL)) |
| 2227 | index_frontend++; |
| 2228 | if (index_frontend != 1) { |
| 2229 | dprintk("remove slave fe %p (index %i)", state->fe[index_frontend - 1], index_frontend - 1); |
| 2230 | state->fe[index_frontend] = NULL; |
| 2231 | return 0; |
| 2232 | } |
| 2233 | |
| 2234 | dprintk("no frontend to be removed"); |
| 2235 | return -ENODEV; |
| 2236 | } |
| 2237 | EXPORT_SYMBOL(dib9000_remove_slave_frontend); |
| 2238 | |
| 2239 | struct dvb_frontend *dib9000_get_slave_frontend(struct dvb_frontend *fe, int slave_index) |
| 2240 | { |
| 2241 | struct dib9000_state *state = fe->demodulator_priv; |
| 2242 | |
| 2243 | if (slave_index >= MAX_NUMBER_OF_FRONTENDS) |
| 2244 | return NULL; |
| 2245 | return state->fe[slave_index]; |
| 2246 | } |
| 2247 | EXPORT_SYMBOL(dib9000_get_slave_frontend); |
| 2248 | |
| 2249 | static struct dvb_frontend_ops dib9000_ops; |
| 2250 | struct dvb_frontend *dib9000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, const struct dib9000_config *cfg) |
| 2251 | { |
| 2252 | struct dvb_frontend *fe; |
| 2253 | struct dib9000_state *st; |
| 2254 | st = kzalloc(sizeof(struct dib9000_state), GFP_KERNEL); |
| 2255 | if (st == NULL) |
| 2256 | return NULL; |
| 2257 | fe = kzalloc(sizeof(struct dvb_frontend), GFP_KERNEL); |
| 2258 | if (fe == NULL) |
| 2259 | return NULL; |
| 2260 | |
| 2261 | memcpy(&st->chip.d9.cfg, cfg, sizeof(struct dib9000_config)); |
| 2262 | st->i2c.i2c_adap = i2c_adap; |
| 2263 | st->i2c.i2c_addr = i2c_addr; |
| 2264 | |
| 2265 | st->gpio_dir = DIB9000_GPIO_DEFAULT_DIRECTIONS; |
| 2266 | st->gpio_val = DIB9000_GPIO_DEFAULT_VALUES; |
| 2267 | st->gpio_pwm_pos = DIB9000_GPIO_DEFAULT_PWM_POS; |
| 2268 | |
| 2269 | DibInitLock(&st->platform.risc.mbx_if_lock); |
| 2270 | DibInitLock(&st->platform.risc.mbx_lock); |
| 2271 | DibInitLock(&st->platform.risc.mem_lock); |
| 2272 | DibInitLock(&st->platform.risc.mem_mbx_lock); |
| 2273 | |
| 2274 | st->fe[0] = fe; |
| 2275 | fe->demodulator_priv = st; |
| 2276 | memcpy(&st->fe[0]->ops, &dib9000_ops, sizeof(struct dvb_frontend_ops)); |
| 2277 | |
| 2278 | /* Ensure the output mode remains at the previous default if it's |
| 2279 | * not specifically set by the caller. |
| 2280 | */ |
| 2281 | if ((st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK)) |
| 2282 | st->chip.d9.cfg.output_mode = OUTMODE_MPEG2_FIFO; |
| 2283 | |
| 2284 | if (dib9000_identify(&st->i2c) == 0) |
| 2285 | goto error; |
| 2286 | |
| 2287 | dibx000_init_i2c_master(&st->i2c_master, DIB7000MC, st->i2c.i2c_adap, st->i2c.i2c_addr); |
| 2288 | |
| 2289 | st->tuner_adap.dev.parent = i2c_adap->dev.parent; |
| 2290 | strncpy(st->tuner_adap.name, "DIB9000_FW TUNER ACCESS", sizeof(st->tuner_adap.name)); |
| 2291 | st->tuner_adap.algo = &dib9000_tuner_algo; |
| 2292 | st->tuner_adap.algo_data = NULL; |
| 2293 | i2c_set_adapdata(&st->tuner_adap, st); |
| 2294 | if (i2c_add_adapter(&st->tuner_adap) < 0) |
| 2295 | goto error; |
| 2296 | |
| 2297 | st->component_bus.dev.parent = i2c_adap->dev.parent; |
| 2298 | strncpy(st->component_bus.name, "DIB9000_FW COMPONENT BUS ACCESS", sizeof(st->component_bus.name)); |
| 2299 | st->component_bus.algo = &dib9000_component_bus_algo; |
| 2300 | st->component_bus.algo_data = NULL; |
| 2301 | st->component_bus_speed = 340; |
| 2302 | i2c_set_adapdata(&st->component_bus, st); |
| 2303 | if (i2c_add_adapter(&st->component_bus) < 0) |
| 2304 | goto component_bus_add_error; |
| 2305 | |
| 2306 | dib9000_fw_reset(fe); |
| 2307 | |
| 2308 | return fe; |
| 2309 | |
| 2310 | component_bus_add_error: |
| 2311 | i2c_del_adapter(&st->tuner_adap); |
| 2312 | error: |
| 2313 | kfree(st); |
| 2314 | return NULL; |
| 2315 | } |
| 2316 | EXPORT_SYMBOL(dib9000_attach); |
| 2317 | |
| 2318 | static struct dvb_frontend_ops dib9000_ops = { |
| 2319 | .info = { |
| 2320 | .name = "DiBcom 9000", |
| 2321 | .type = FE_OFDM, |
| 2322 | .frequency_min = 44250000, |
| 2323 | .frequency_max = 867250000, |
| 2324 | .frequency_stepsize = 62500, |
| 2325 | .caps = FE_CAN_INVERSION_AUTO | |
| 2326 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | |
| 2327 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | |
| 2328 | FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | |
| 2329 | FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO, |
| 2330 | }, |
| 2331 | |
| 2332 | .release = dib9000_release, |
| 2333 | |
| 2334 | .init = dib9000_wakeup, |
| 2335 | .sleep = dib9000_sleep, |
| 2336 | |
| 2337 | .set_frontend = dib9000_set_frontend, |
| 2338 | .get_tune_settings = dib9000_fe_get_tune_settings, |
| 2339 | .get_frontend = dib9000_get_frontend, |
| 2340 | |
| 2341 | .read_status = dib9000_read_status, |
| 2342 | .read_ber = dib9000_read_ber, |
| 2343 | .read_signal_strength = dib9000_read_signal_strength, |
| 2344 | .read_snr = dib9000_read_snr, |
| 2345 | .read_ucblocks = dib9000_read_unc_blocks, |
| 2346 | }; |
| 2347 | |
| 2348 | MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>"); |
| 2349 | MODULE_AUTHOR("Olivier Grenie <ogrenie@dibcom.fr>"); |
| 2350 | MODULE_DESCRIPTION("Driver for the DiBcom 9000 COFDM demodulator"); |
| 2351 | MODULE_LICENSE("GPL"); |