| 1 | /* |
| 2 | * vsp1_pipe.c -- R-Car VSP1 Pipeline |
| 3 | * |
| 4 | * Copyright (C) 2013-2015 Renesas Electronics Corporation |
| 5 | * |
| 6 | * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/list.h> |
| 15 | #include <linux/sched.h> |
| 16 | #include <linux/wait.h> |
| 17 | |
| 18 | #include <media/media-entity.h> |
| 19 | #include <media/v4l2-subdev.h> |
| 20 | |
| 21 | #include "vsp1.h" |
| 22 | #include "vsp1_bru.h" |
| 23 | #include "vsp1_entity.h" |
| 24 | #include "vsp1_pipe.h" |
| 25 | #include "vsp1_rwpf.h" |
| 26 | #include "vsp1_uds.h" |
| 27 | |
| 28 | /* ----------------------------------------------------------------------------- |
| 29 | * Helper Functions |
| 30 | */ |
| 31 | |
| 32 | static const struct vsp1_format_info vsp1_video_formats[] = { |
| 33 | { V4L2_PIX_FMT_RGB332, MEDIA_BUS_FMT_ARGB8888_1X32, |
| 34 | VI6_FMT_RGB_332, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 35 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, |
| 36 | 1, { 8, 0, 0 }, false, false, 1, 1, false }, |
| 37 | { V4L2_PIX_FMT_ARGB444, MEDIA_BUS_FMT_ARGB8888_1X32, |
| 38 | VI6_FMT_ARGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 39 | VI6_RPF_DSWAP_P_WDS, |
| 40 | 1, { 16, 0, 0 }, false, false, 1, 1, true }, |
| 41 | { V4L2_PIX_FMT_XRGB444, MEDIA_BUS_FMT_ARGB8888_1X32, |
| 42 | VI6_FMT_XRGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 43 | VI6_RPF_DSWAP_P_WDS, |
| 44 | 1, { 16, 0, 0 }, false, false, 1, 1, true }, |
| 45 | { V4L2_PIX_FMT_ARGB555, MEDIA_BUS_FMT_ARGB8888_1X32, |
| 46 | VI6_FMT_ARGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 47 | VI6_RPF_DSWAP_P_WDS, |
| 48 | 1, { 16, 0, 0 }, false, false, 1, 1, true }, |
| 49 | { V4L2_PIX_FMT_XRGB555, MEDIA_BUS_FMT_ARGB8888_1X32, |
| 50 | VI6_FMT_XRGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 51 | VI6_RPF_DSWAP_P_WDS, |
| 52 | 1, { 16, 0, 0 }, false, false, 1, 1, false }, |
| 53 | { V4L2_PIX_FMT_RGB565, MEDIA_BUS_FMT_ARGB8888_1X32, |
| 54 | VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 55 | VI6_RPF_DSWAP_P_WDS, |
| 56 | 1, { 16, 0, 0 }, false, false, 1, 1, false }, |
| 57 | { V4L2_PIX_FMT_BGR24, MEDIA_BUS_FMT_ARGB8888_1X32, |
| 58 | VI6_FMT_BGR_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 59 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, |
| 60 | 1, { 24, 0, 0 }, false, false, 1, 1, false }, |
| 61 | { V4L2_PIX_FMT_RGB24, MEDIA_BUS_FMT_ARGB8888_1X32, |
| 62 | VI6_FMT_RGB_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 63 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, |
| 64 | 1, { 24, 0, 0 }, false, false, 1, 1, false }, |
| 65 | { V4L2_PIX_FMT_ABGR32, MEDIA_BUS_FMT_ARGB8888_1X32, |
| 66 | VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS, |
| 67 | 1, { 32, 0, 0 }, false, false, 1, 1, true }, |
| 68 | { V4L2_PIX_FMT_XBGR32, MEDIA_BUS_FMT_ARGB8888_1X32, |
| 69 | VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS, |
| 70 | 1, { 32, 0, 0 }, false, false, 1, 1, false }, |
| 71 | { V4L2_PIX_FMT_ARGB32, MEDIA_BUS_FMT_ARGB8888_1X32, |
| 72 | VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 73 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, |
| 74 | 1, { 32, 0, 0 }, false, false, 1, 1, true }, |
| 75 | { V4L2_PIX_FMT_XRGB32, MEDIA_BUS_FMT_ARGB8888_1X32, |
| 76 | VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 77 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, |
| 78 | 1, { 32, 0, 0 }, false, false, 1, 1, false }, |
| 79 | { V4L2_PIX_FMT_UYVY, MEDIA_BUS_FMT_AYUV8_1X32, |
| 80 | VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 81 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, |
| 82 | 1, { 16, 0, 0 }, false, false, 2, 1, false }, |
| 83 | { V4L2_PIX_FMT_VYUY, MEDIA_BUS_FMT_AYUV8_1X32, |
| 84 | VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 85 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, |
| 86 | 1, { 16, 0, 0 }, false, true, 2, 1, false }, |
| 87 | { V4L2_PIX_FMT_YUYV, MEDIA_BUS_FMT_AYUV8_1X32, |
| 88 | VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 89 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, |
| 90 | 1, { 16, 0, 0 }, true, false, 2, 1, false }, |
| 91 | { V4L2_PIX_FMT_YVYU, MEDIA_BUS_FMT_AYUV8_1X32, |
| 92 | VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 93 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, |
| 94 | 1, { 16, 0, 0 }, true, true, 2, 1, false }, |
| 95 | { V4L2_PIX_FMT_NV12M, MEDIA_BUS_FMT_AYUV8_1X32, |
| 96 | VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 97 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, |
| 98 | 2, { 8, 16, 0 }, false, false, 2, 2, false }, |
| 99 | { V4L2_PIX_FMT_NV21M, MEDIA_BUS_FMT_AYUV8_1X32, |
| 100 | VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 101 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, |
| 102 | 2, { 8, 16, 0 }, false, true, 2, 2, false }, |
| 103 | { V4L2_PIX_FMT_NV16M, MEDIA_BUS_FMT_AYUV8_1X32, |
| 104 | VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 105 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, |
| 106 | 2, { 8, 16, 0 }, false, false, 2, 1, false }, |
| 107 | { V4L2_PIX_FMT_NV61M, MEDIA_BUS_FMT_AYUV8_1X32, |
| 108 | VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 109 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, |
| 110 | 2, { 8, 16, 0 }, false, true, 2, 1, false }, |
| 111 | { V4L2_PIX_FMT_YUV420M, MEDIA_BUS_FMT_AYUV8_1X32, |
| 112 | VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 113 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, |
| 114 | 3, { 8, 8, 8 }, false, false, 2, 2, false }, |
| 115 | { V4L2_PIX_FMT_YVU420M, MEDIA_BUS_FMT_AYUV8_1X32, |
| 116 | VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 117 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, |
| 118 | 3, { 8, 8, 8 }, false, true, 2, 2, false }, |
| 119 | { V4L2_PIX_FMT_YUV422M, MEDIA_BUS_FMT_AYUV8_1X32, |
| 120 | VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 121 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, |
| 122 | 3, { 8, 8, 8 }, false, false, 2, 1, false }, |
| 123 | { V4L2_PIX_FMT_YVU422M, MEDIA_BUS_FMT_AYUV8_1X32, |
| 124 | VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 125 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, |
| 126 | 3, { 8, 8, 8 }, false, true, 2, 1, false }, |
| 127 | { V4L2_PIX_FMT_YUV444M, MEDIA_BUS_FMT_AYUV8_1X32, |
| 128 | VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 129 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, |
| 130 | 3, { 8, 8, 8 }, false, false, 1, 1, false }, |
| 131 | { V4L2_PIX_FMT_YVU444M, MEDIA_BUS_FMT_AYUV8_1X32, |
| 132 | VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 133 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, |
| 134 | 3, { 8, 8, 8 }, false, true, 1, 1, false }, |
| 135 | }; |
| 136 | |
| 137 | /* |
| 138 | * vsp1_get_format_info - Retrieve format information for a 4CC |
| 139 | * @fourcc: the format 4CC |
| 140 | * |
| 141 | * Return a pointer to the format information structure corresponding to the |
| 142 | * given V4L2 format 4CC, or NULL if no corresponding format can be found. |
| 143 | */ |
| 144 | const struct vsp1_format_info *vsp1_get_format_info(u32 fourcc) |
| 145 | { |
| 146 | unsigned int i; |
| 147 | |
| 148 | for (i = 0; i < ARRAY_SIZE(vsp1_video_formats); ++i) { |
| 149 | const struct vsp1_format_info *info = &vsp1_video_formats[i]; |
| 150 | |
| 151 | if (info->fourcc == fourcc) |
| 152 | return info; |
| 153 | } |
| 154 | |
| 155 | return NULL; |
| 156 | } |
| 157 | |
| 158 | /* ----------------------------------------------------------------------------- |
| 159 | * Pipeline Management |
| 160 | */ |
| 161 | |
| 162 | void vsp1_pipeline_reset(struct vsp1_pipeline *pipe) |
| 163 | { |
| 164 | unsigned int i; |
| 165 | |
| 166 | if (pipe->bru) { |
| 167 | struct vsp1_bru *bru = to_bru(&pipe->bru->subdev); |
| 168 | |
| 169 | for (i = 0; i < ARRAY_SIZE(bru->inputs); ++i) |
| 170 | bru->inputs[i].rpf = NULL; |
| 171 | } |
| 172 | |
| 173 | for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) |
| 174 | pipe->inputs[i] = NULL; |
| 175 | |
| 176 | INIT_LIST_HEAD(&pipe->entities); |
| 177 | pipe->state = VSP1_PIPELINE_STOPPED; |
| 178 | pipe->buffers_ready = 0; |
| 179 | pipe->num_inputs = 0; |
| 180 | pipe->output = NULL; |
| 181 | pipe->bru = NULL; |
| 182 | pipe->lif = NULL; |
| 183 | pipe->uds = NULL; |
| 184 | } |
| 185 | |
| 186 | void vsp1_pipeline_init(struct vsp1_pipeline *pipe) |
| 187 | { |
| 188 | mutex_init(&pipe->lock); |
| 189 | spin_lock_init(&pipe->irqlock); |
| 190 | init_waitqueue_head(&pipe->wq); |
| 191 | |
| 192 | INIT_LIST_HEAD(&pipe->entities); |
| 193 | pipe->state = VSP1_PIPELINE_STOPPED; |
| 194 | } |
| 195 | |
| 196 | void vsp1_pipeline_run(struct vsp1_pipeline *pipe) |
| 197 | { |
| 198 | struct vsp1_device *vsp1 = pipe->output->entity.vsp1; |
| 199 | |
| 200 | vsp1_write(vsp1, VI6_CMD(pipe->output->entity.index), VI6_CMD_STRCMD); |
| 201 | pipe->state = VSP1_PIPELINE_RUNNING; |
| 202 | pipe->buffers_ready = 0; |
| 203 | } |
| 204 | |
| 205 | bool vsp1_pipeline_stopped(struct vsp1_pipeline *pipe) |
| 206 | { |
| 207 | unsigned long flags; |
| 208 | bool stopped; |
| 209 | |
| 210 | spin_lock_irqsave(&pipe->irqlock, flags); |
| 211 | stopped = pipe->state == VSP1_PIPELINE_STOPPED; |
| 212 | spin_unlock_irqrestore(&pipe->irqlock, flags); |
| 213 | |
| 214 | return stopped; |
| 215 | } |
| 216 | |
| 217 | int vsp1_pipeline_stop(struct vsp1_pipeline *pipe) |
| 218 | { |
| 219 | struct vsp1_entity *entity; |
| 220 | unsigned long flags; |
| 221 | int ret; |
| 222 | |
| 223 | spin_lock_irqsave(&pipe->irqlock, flags); |
| 224 | if (pipe->state == VSP1_PIPELINE_RUNNING) |
| 225 | pipe->state = VSP1_PIPELINE_STOPPING; |
| 226 | spin_unlock_irqrestore(&pipe->irqlock, flags); |
| 227 | |
| 228 | ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe), |
| 229 | msecs_to_jiffies(500)); |
| 230 | ret = ret == 0 ? -ETIMEDOUT : 0; |
| 231 | |
| 232 | list_for_each_entry(entity, &pipe->entities, list_pipe) { |
| 233 | if (entity->route && entity->route->reg) |
| 234 | vsp1_write(entity->vsp1, entity->route->reg, |
| 235 | VI6_DPR_NODE_UNUSED); |
| 236 | |
| 237 | v4l2_subdev_call(&entity->subdev, video, s_stream, 0); |
| 238 | } |
| 239 | |
| 240 | return ret; |
| 241 | } |
| 242 | |
| 243 | bool vsp1_pipeline_ready(struct vsp1_pipeline *pipe) |
| 244 | { |
| 245 | unsigned int mask; |
| 246 | |
| 247 | mask = ((1 << pipe->num_inputs) - 1) << 1; |
| 248 | if (!pipe->lif) |
| 249 | mask |= 1 << 0; |
| 250 | |
| 251 | return pipe->buffers_ready == mask; |
| 252 | } |
| 253 | |
| 254 | void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe) |
| 255 | { |
| 256 | enum vsp1_pipeline_state state; |
| 257 | unsigned long flags; |
| 258 | |
| 259 | if (pipe == NULL) |
| 260 | return; |
| 261 | |
| 262 | /* Signal frame end to the pipeline handler. */ |
| 263 | pipe->frame_end(pipe); |
| 264 | |
| 265 | spin_lock_irqsave(&pipe->irqlock, flags); |
| 266 | |
| 267 | state = pipe->state; |
| 268 | pipe->state = VSP1_PIPELINE_STOPPED; |
| 269 | |
| 270 | /* If a stop has been requested, mark the pipeline as stopped and |
| 271 | * return. |
| 272 | */ |
| 273 | if (state == VSP1_PIPELINE_STOPPING) { |
| 274 | wake_up(&pipe->wq); |
| 275 | goto done; |
| 276 | } |
| 277 | |
| 278 | /* Restart the pipeline if ready. */ |
| 279 | if (vsp1_pipeline_ready(pipe)) |
| 280 | vsp1_pipeline_run(pipe); |
| 281 | |
| 282 | done: |
| 283 | spin_unlock_irqrestore(&pipe->irqlock, flags); |
| 284 | } |
| 285 | |
| 286 | /* |
| 287 | * Propagate the alpha value through the pipeline. |
| 288 | * |
| 289 | * As the UDS has restricted scaling capabilities when the alpha component needs |
| 290 | * to be scaled, we disable alpha scaling when the UDS input has a fixed alpha |
| 291 | * value. The UDS then outputs a fixed alpha value which needs to be programmed |
| 292 | * from the input RPF alpha. |
| 293 | */ |
| 294 | void vsp1_pipeline_propagate_alpha(struct vsp1_pipeline *pipe, |
| 295 | struct vsp1_entity *input, |
| 296 | unsigned int alpha) |
| 297 | { |
| 298 | struct vsp1_entity *entity; |
| 299 | struct media_pad *pad; |
| 300 | |
| 301 | pad = media_entity_remote_pad(&input->pads[RWPF_PAD_SOURCE]); |
| 302 | |
| 303 | while (pad) { |
| 304 | if (!is_media_entity_v4l2_subdev(pad->entity)) |
| 305 | break; |
| 306 | |
| 307 | entity = to_vsp1_entity(media_entity_to_v4l2_subdev(pad->entity)); |
| 308 | |
| 309 | /* The BRU background color has a fixed alpha value set to 255, |
| 310 | * the output alpha value is thus always equal to 255. |
| 311 | */ |
| 312 | if (entity->type == VSP1_ENTITY_BRU) |
| 313 | alpha = 255; |
| 314 | |
| 315 | if (entity->type == VSP1_ENTITY_UDS) { |
| 316 | struct vsp1_uds *uds = to_uds(&entity->subdev); |
| 317 | |
| 318 | vsp1_uds_set_alpha(uds, alpha); |
| 319 | break; |
| 320 | } |
| 321 | |
| 322 | pad = &entity->pads[entity->source_pad]; |
| 323 | pad = media_entity_remote_pad(pad); |
| 324 | } |
| 325 | } |
| 326 | |
| 327 | void vsp1_pipelines_suspend(struct vsp1_device *vsp1) |
| 328 | { |
| 329 | unsigned long flags; |
| 330 | unsigned int i; |
| 331 | int ret; |
| 332 | |
| 333 | /* To avoid increasing the system suspend time needlessly, loop over the |
| 334 | * pipelines twice, first to set them all to the stopping state, and |
| 335 | * then to wait for the stop to complete. |
| 336 | */ |
| 337 | for (i = 0; i < vsp1->pdata.wpf_count; ++i) { |
| 338 | struct vsp1_rwpf *wpf = vsp1->wpf[i]; |
| 339 | struct vsp1_pipeline *pipe; |
| 340 | |
| 341 | if (wpf == NULL) |
| 342 | continue; |
| 343 | |
| 344 | pipe = to_vsp1_pipeline(&wpf->entity.subdev.entity); |
| 345 | if (pipe == NULL) |
| 346 | continue; |
| 347 | |
| 348 | spin_lock_irqsave(&pipe->irqlock, flags); |
| 349 | if (pipe->state == VSP1_PIPELINE_RUNNING) |
| 350 | pipe->state = VSP1_PIPELINE_STOPPING; |
| 351 | spin_unlock_irqrestore(&pipe->irqlock, flags); |
| 352 | } |
| 353 | |
| 354 | for (i = 0; i < vsp1->pdata.wpf_count; ++i) { |
| 355 | struct vsp1_rwpf *wpf = vsp1->wpf[i]; |
| 356 | struct vsp1_pipeline *pipe; |
| 357 | |
| 358 | if (wpf == NULL) |
| 359 | continue; |
| 360 | |
| 361 | pipe = to_vsp1_pipeline(&wpf->entity.subdev.entity); |
| 362 | if (pipe == NULL) |
| 363 | continue; |
| 364 | |
| 365 | ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe), |
| 366 | msecs_to_jiffies(500)); |
| 367 | if (ret == 0) |
| 368 | dev_warn(vsp1->dev, "pipeline %u stop timeout\n", |
| 369 | wpf->entity.index); |
| 370 | } |
| 371 | } |
| 372 | |
| 373 | void vsp1_pipelines_resume(struct vsp1_device *vsp1) |
| 374 | { |
| 375 | unsigned int i; |
| 376 | |
| 377 | /* Resume pipeline all running pipelines. */ |
| 378 | for (i = 0; i < vsp1->pdata.wpf_count; ++i) { |
| 379 | struct vsp1_rwpf *wpf = vsp1->wpf[i]; |
| 380 | struct vsp1_pipeline *pipe; |
| 381 | |
| 382 | if (wpf == NULL) |
| 383 | continue; |
| 384 | |
| 385 | pipe = to_vsp1_pipeline(&wpf->entity.subdev.entity); |
| 386 | if (pipe == NULL) |
| 387 | continue; |
| 388 | |
| 389 | if (vsp1_pipeline_ready(pipe)) |
| 390 | vsp1_pipeline_run(pipe); |
| 391 | } |
| 392 | } |