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V4L/DVB (13491): gspca - vc032x: Avoid crash on querymenu.
[deliverable/linux.git] / drivers / media / video / cx23885 / cx23885-dvb.c
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1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/device.h>
25#include <linux/fs.h>
26#include <linux/kthread.h>
27#include <linux/file.h>
28#include <linux/suspend.h>
29
30#include "cx23885.h"
31#include <media/v4l2-common.h>
32
33#include "dvb_ca_en50221.h"
34#include "s5h1409.h"
35#include "s5h1411.h"
36#include "mt2131.h"
37#include "tda8290.h"
38#include "tda18271.h"
39#include "lgdt330x.h"
40#include "xc5000.h"
41#include "max2165.h"
42#include "tda10048.h"
43#include "tuner-xc2028.h"
44#include "tuner-simple.h"
45#include "dib7000p.h"
46#include "dibx000_common.h"
47#include "zl10353.h"
48#include "stv0900.h"
49#include "stv0900_reg.h"
50#include "stv6110.h"
51#include "lnbh24.h"
52#include "cx24116.h"
53#include "cimax2.h"
54#include "lgs8gxx.h"
55#include "netup-eeprom.h"
56#include "netup-init.h"
57#include "lgdt3305.h"
58#include "atbm8830.h"
59
60static unsigned int debug;
61
62#define dprintk(level, fmt, arg...)\
63 do { if (debug >= level)\
64 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
65 } while (0)
66
67/* ------------------------------------------------------------------ */
68
69static unsigned int alt_tuner;
70module_param(alt_tuner, int, 0644);
71MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
72
73DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
74
75/* ------------------------------------------------------------------ */
76
77static int dvb_buf_setup(struct videobuf_queue *q,
78 unsigned int *count, unsigned int *size)
79{
80 struct cx23885_tsport *port = q->priv_data;
81
82 port->ts_packet_size = 188 * 4;
83 port->ts_packet_count = 32;
84
85 *size = port->ts_packet_size * port->ts_packet_count;
86 *count = 32;
87 return 0;
88}
89
90static int dvb_buf_prepare(struct videobuf_queue *q,
91 struct videobuf_buffer *vb, enum v4l2_field field)
92{
93 struct cx23885_tsport *port = q->priv_data;
94 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
95}
96
97static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
98{
99 struct cx23885_tsport *port = q->priv_data;
100 cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
101}
102
103static void dvb_buf_release(struct videobuf_queue *q,
104 struct videobuf_buffer *vb)
105{
106 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
107}
108
109static struct videobuf_queue_ops dvb_qops = {
110 .buf_setup = dvb_buf_setup,
111 .buf_prepare = dvb_buf_prepare,
112 .buf_queue = dvb_buf_queue,
113 .buf_release = dvb_buf_release,
114};
115
116static struct s5h1409_config hauppauge_generic_config = {
117 .demod_address = 0x32 >> 1,
118 .output_mode = S5H1409_SERIAL_OUTPUT,
119 .gpio = S5H1409_GPIO_ON,
120 .qam_if = 44000,
121 .inversion = S5H1409_INVERSION_OFF,
122 .status_mode = S5H1409_DEMODLOCKING,
123 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
124};
125
126static struct tda10048_config hauppauge_hvr1200_config = {
127 .demod_address = 0x10 >> 1,
128 .output_mode = TDA10048_SERIAL_OUTPUT,
129 .fwbulkwritelen = TDA10048_BULKWRITE_200,
130 .inversion = TDA10048_INVERSION_ON,
131 .dtv6_if_freq_khz = TDA10048_IF_3300,
132 .dtv7_if_freq_khz = TDA10048_IF_3800,
133 .dtv8_if_freq_khz = TDA10048_IF_4300,
134 .clk_freq_khz = TDA10048_CLK_16000,
135};
136
137static struct tda10048_config hauppauge_hvr1210_config = {
138 .demod_address = 0x10 >> 1,
139 .output_mode = TDA10048_SERIAL_OUTPUT,
140 .fwbulkwritelen = TDA10048_BULKWRITE_200,
141 .inversion = TDA10048_INVERSION_ON,
142 .dtv6_if_freq_khz = TDA10048_IF_3300,
143 .dtv7_if_freq_khz = TDA10048_IF_3500,
144 .dtv8_if_freq_khz = TDA10048_IF_4000,
145 .clk_freq_khz = TDA10048_CLK_16000,
146};
147
148static struct s5h1409_config hauppauge_ezqam_config = {
149 .demod_address = 0x32 >> 1,
150 .output_mode = S5H1409_SERIAL_OUTPUT,
151 .gpio = S5H1409_GPIO_OFF,
152 .qam_if = 4000,
153 .inversion = S5H1409_INVERSION_ON,
154 .status_mode = S5H1409_DEMODLOCKING,
155 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
156};
157
158static struct s5h1409_config hauppauge_hvr1800lp_config = {
159 .demod_address = 0x32 >> 1,
160 .output_mode = S5H1409_SERIAL_OUTPUT,
161 .gpio = S5H1409_GPIO_OFF,
162 .qam_if = 44000,
163 .inversion = S5H1409_INVERSION_OFF,
164 .status_mode = S5H1409_DEMODLOCKING,
165 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
166};
167
168static struct s5h1409_config hauppauge_hvr1500_config = {
169 .demod_address = 0x32 >> 1,
170 .output_mode = S5H1409_SERIAL_OUTPUT,
171 .gpio = S5H1409_GPIO_OFF,
172 .inversion = S5H1409_INVERSION_OFF,
173 .status_mode = S5H1409_DEMODLOCKING,
174 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
175};
176
177static struct mt2131_config hauppauge_generic_tunerconfig = {
178 0x61
179};
180
181static struct lgdt330x_config fusionhdtv_5_express = {
182 .demod_address = 0x0e,
183 .demod_chip = LGDT3303,
184 .serial_mpeg = 0x40,
185};
186
187static struct s5h1409_config hauppauge_hvr1500q_config = {
188 .demod_address = 0x32 >> 1,
189 .output_mode = S5H1409_SERIAL_OUTPUT,
190 .gpio = S5H1409_GPIO_ON,
191 .qam_if = 44000,
192 .inversion = S5H1409_INVERSION_OFF,
193 .status_mode = S5H1409_DEMODLOCKING,
194 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
195};
196
197static struct s5h1409_config dvico_s5h1409_config = {
198 .demod_address = 0x32 >> 1,
199 .output_mode = S5H1409_SERIAL_OUTPUT,
200 .gpio = S5H1409_GPIO_ON,
201 .qam_if = 44000,
202 .inversion = S5H1409_INVERSION_OFF,
203 .status_mode = S5H1409_DEMODLOCKING,
204 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
205};
206
207static struct s5h1411_config dvico_s5h1411_config = {
208 .output_mode = S5H1411_SERIAL_OUTPUT,
209 .gpio = S5H1411_GPIO_ON,
210 .qam_if = S5H1411_IF_44000,
211 .vsb_if = S5H1411_IF_44000,
212 .inversion = S5H1411_INVERSION_OFF,
213 .status_mode = S5H1411_DEMODLOCKING,
214 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
215};
216
217static struct s5h1411_config hcw_s5h1411_config = {
218 .output_mode = S5H1411_SERIAL_OUTPUT,
219 .gpio = S5H1411_GPIO_OFF,
220 .vsb_if = S5H1411_IF_44000,
221 .qam_if = S5H1411_IF_4000,
222 .inversion = S5H1411_INVERSION_ON,
223 .status_mode = S5H1411_DEMODLOCKING,
224 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
225};
226
227static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
228 .i2c_address = 0x61,
229 .if_khz = 5380,
230};
231
232static struct xc5000_config dvico_xc5000_tunerconfig = {
233 .i2c_address = 0x64,
234 .if_khz = 5380,
235};
236
237static struct tda829x_config tda829x_no_probe = {
238 .probe_tuner = TDA829X_DONT_PROBE,
239};
240
241static struct tda18271_std_map hauppauge_tda18271_std_map = {
242 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
243 .if_lvl = 6, .rfagc_top = 0x37 },
244 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
245 .if_lvl = 6, .rfagc_top = 0x37 },
246};
247
248static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
249 .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
250 .if_lvl = 1, .rfagc_top = 0x37, },
251 .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
252 .if_lvl = 1, .rfagc_top = 0x37, },
253 .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
254 .if_lvl = 1, .rfagc_top = 0x37, },
255};
256
257static struct tda18271_config hauppauge_tda18271_config = {
258 .std_map = &hauppauge_tda18271_std_map,
259 .gate = TDA18271_GATE_ANALOG,
260 .output_opt = TDA18271_OUTPUT_LT_OFF,
261};
262
263static struct tda18271_config hauppauge_hvr1200_tuner_config = {
264 .std_map = &hauppauge_hvr1200_tda18271_std_map,
265 .gate = TDA18271_GATE_ANALOG,
266 .output_opt = TDA18271_OUTPUT_LT_OFF,
267};
268
269static struct tda18271_config hauppauge_hvr1210_tuner_config = {
270 .gate = TDA18271_GATE_DIGITAL,
271 .output_opt = TDA18271_OUTPUT_LT_OFF,
272};
273
274static struct tda18271_std_map hauppauge_hvr127x_std_map = {
275 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
276 .if_lvl = 1, .rfagc_top = 0x58 },
277 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
278 .if_lvl = 1, .rfagc_top = 0x58 },
279};
280
281static struct tda18271_config hauppauge_hvr127x_config = {
282 .std_map = &hauppauge_hvr127x_std_map,
283 .output_opt = TDA18271_OUTPUT_LT_OFF,
284};
285
286static struct lgdt3305_config hauppauge_lgdt3305_config = {
287 .i2c_addr = 0x0e,
288 .mpeg_mode = LGDT3305_MPEG_SERIAL,
289 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
290 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
291 .deny_i2c_rptr = 1,
292 .spectral_inversion = 1,
293 .qam_if_khz = 4000,
294 .vsb_if_khz = 3250,
295};
296
297static struct dibx000_agc_config xc3028_agc_config = {
298 BAND_VHF | BAND_UHF, /* band_caps */
299
300 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
301 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
302 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
303 * P_agc_nb_est=2, P_agc_write=0
304 */
305 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
306 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
307
308 712, /* inv_gain */
309 21, /* time_stabiliz */
310
311 0, /* alpha_level */
312 118, /* thlock */
313
314 0, /* wbd_inv */
315 2867, /* wbd_ref */
316 0, /* wbd_sel */
317 2, /* wbd_alpha */
318
319 0, /* agc1_max */
320 0, /* agc1_min */
321 39718, /* agc2_max */
322 9930, /* agc2_min */
323 0, /* agc1_pt1 */
324 0, /* agc1_pt2 */
325 0, /* agc1_pt3 */
326 0, /* agc1_slope1 */
327 0, /* agc1_slope2 */
328 0, /* agc2_pt1 */
329 128, /* agc2_pt2 */
330 29, /* agc2_slope1 */
331 29, /* agc2_slope2 */
332
333 17, /* alpha_mant */
334 27, /* alpha_exp */
335 23, /* beta_mant */
336 51, /* beta_exp */
337
338 1, /* perform_agc_softsplit */
339};
340
341/* PLL Configuration for COFDM BW_MHz = 8.000000
342 * With external clock = 30.000000 */
343static struct dibx000_bandwidth_config xc3028_bw_config = {
344 60000, /* internal */
345 30000, /* sampling */
346 1, /* pll_cfg: prediv */
347 8, /* pll_cfg: ratio */
348 3, /* pll_cfg: range */
349 1, /* pll_cfg: reset */
350 0, /* pll_cfg: bypass */
351 0, /* misc: refdiv */
352 0, /* misc: bypclk_div */
353 1, /* misc: IO_CLK_en_core */
354 1, /* misc: ADClkSrc */
355 0, /* misc: modulo */
356 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
357 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
358 20452225, /* timf */
359 30000000 /* xtal_hz */
360};
361
362static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
363 .output_mpeg2_in_188_bytes = 1,
364 .hostbus_diversity = 1,
365 .tuner_is_baseband = 0,
366 .update_lna = NULL,
367
368 .agc_config_count = 1,
369 .agc = &xc3028_agc_config,
370 .bw = &xc3028_bw_config,
371
372 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
373 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
374 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
375
376 .pwm_freq_div = 0,
377 .agc_control = NULL,
378 .spur_protect = 0,
379
380 .output_mode = OUTMODE_MPEG2_SERIAL,
381};
382
383static struct zl10353_config dvico_fusionhdtv_xc3028 = {
384 .demod_address = 0x0f,
385 .if2 = 45600,
386 .no_tuner = 1,
387 .disable_i2c_gate_ctrl = 1,
388};
389
390static struct stv0900_reg stv0900_ts_regs[] = {
391 { R0900_TSGENERAL, 0x00 },
392 { R0900_P1_TSSPEED, 0x40 },
393 { R0900_P2_TSSPEED, 0x40 },
394 { R0900_P1_TSCFGM, 0xc0 },
395 { R0900_P2_TSCFGM, 0xc0 },
396 { R0900_P1_TSCFGH, 0xe0 },
397 { R0900_P2_TSCFGH, 0xe0 },
398 { R0900_P1_TSCFGL, 0x20 },
399 { R0900_P2_TSCFGL, 0x20 },
400 { 0xffff, 0xff }, /* terminate */
401};
402
403static struct stv0900_config netup_stv0900_config = {
404 .demod_address = 0x68,
405 .demod_mode = 1, /* dual */
406 .xtal = 8000000,
407 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
408 .diseqc_mode = 2,/* 2/3 PWM */
409 .ts_config_regs = stv0900_ts_regs,
410 .tun1_maddress = 0,/* 0x60 */
411 .tun2_maddress = 3,/* 0x63 */
412 .tun1_adc = 1,/* 1 Vpp */
413 .tun2_adc = 1,/* 1 Vpp */
414};
415
416static struct stv6110_config netup_stv6110_tunerconfig_a = {
417 .i2c_address = 0x60,
418 .mclk = 16000000,
419 .clk_div = 1,
420 .gain = 8, /* +16 dB - maximum gain */
421};
422
423static struct stv6110_config netup_stv6110_tunerconfig_b = {
424 .i2c_address = 0x63,
425 .mclk = 16000000,
426 .clk_div = 1,
427 .gain = 8, /* +16 dB - maximum gain */
428};
429
430static int tbs_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
431{
432 struct cx23885_tsport *port = fe->dvb->priv;
433 struct cx23885_dev *dev = port->dev;
434
435 if (voltage == SEC_VOLTAGE_18)
436 cx_write(MC417_RWD, 0x00001e00);/* GPIO-13 high */
437 else if (voltage == SEC_VOLTAGE_13)
438 cx_write(MC417_RWD, 0x00001a00);/* GPIO-13 low */
439 else
440 cx_write(MC417_RWD, 0x00001800);/* GPIO-12 low */
441 return 0;
442}
443
444static struct cx24116_config tbs_cx24116_config = {
445 .demod_address = 0x05,
446};
447
448static struct cx24116_config tevii_cx24116_config = {
449 .demod_address = 0x55,
450};
451
452static struct cx24116_config dvbworld_cx24116_config = {
453 .demod_address = 0x05,
454};
455
456static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
457 .prod = LGS8GXX_PROD_LGS8GL5,
458 .demod_address = 0x19,
459 .serial_ts = 0,
460 .ts_clk_pol = 1,
461 .ts_clk_gated = 1,
462 .if_clk_freq = 30400, /* 30.4 MHz */
463 .if_freq = 5380, /* 5.38 MHz */
464 .if_neg_center = 1,
465 .ext_adc = 0,
466 .adc_signed = 0,
467 .if_neg_edge = 0,
468};
469
470static struct xc5000_config mygica_x8506_xc5000_config = {
471 .i2c_address = 0x61,
472 .if_khz = 5380,
473};
474
475static int cx23885_dvb_set_frontend(struct dvb_frontend *fe,
476 struct dvb_frontend_parameters *param)
477{
478 struct cx23885_tsport *port = fe->dvb->priv;
479 struct cx23885_dev *dev = port->dev;
480
481 switch (dev->board) {
482 case CX23885_BOARD_HAUPPAUGE_HVR1275:
483 switch (param->u.vsb.modulation) {
484 case VSB_8:
485 cx23885_gpio_clear(dev, GPIO_5);
486 break;
487 case QAM_64:
488 case QAM_256:
489 default:
490 cx23885_gpio_set(dev, GPIO_5);
491 break;
492 }
493 break;
494 case CX23885_BOARD_MYGICA_X8506:
495 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
496 /* Select Digital TV */
497 cx23885_gpio_set(dev, GPIO_0);
498 break;
499 }
500 return 0;
501}
502
503static int cx23885_dvb_fe_ioctl_override(struct dvb_frontend *fe,
504 unsigned int cmd, void *parg,
505 unsigned int stage)
506{
507 int err = 0;
508
509 switch (stage) {
510 case DVB_FE_IOCTL_PRE:
511
512 switch (cmd) {
513 case FE_SET_FRONTEND:
514 err = cx23885_dvb_set_frontend(fe,
515 (struct dvb_frontend_parameters *) parg);
516 break;
517 }
518 break;
519
520 case DVB_FE_IOCTL_POST:
521 /* no post-ioctl handling required */
522 break;
523 }
524 return err;
525};
526
527
528static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
529 .prod = LGS8GXX_PROD_LGS8G75,
530 .demod_address = 0x19,
531 .serial_ts = 0,
532 .ts_clk_pol = 1,
533 .ts_clk_gated = 1,
534 .if_clk_freq = 30400, /* 30.4 MHz */
535 .if_freq = 6500, /* 6.50 MHz */
536 .if_neg_center = 1,
537 .ext_adc = 0,
538 .adc_signed = 1,
539 .adc_vpp = 2, /* 1.6 Vpp */
540 .if_neg_edge = 1,
541};
542
543static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
544 .i2c_address = 0x61,
545 .if_khz = 6500,
546};
547
548static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
549 .prod = ATBM8830_PROD_8830,
550 .demod_address = 0x44,
551 .serial_ts = 0,
552 .ts_sampling_edge = 1,
553 .ts_clk_gated = 0,
554 .osc_clk_freq = 30400, /* in kHz */
555 .if_freq = 0, /* zero IF */
556 .zif_swap_iq = 1,
557};
558
559static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
560 .i2c_address = 0x60,
561 .osc_clk = 20
562};
563
564static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
565 .prod = ATBM8830_PROD_8830,
566 .demod_address = 0x44,
567 .serial_ts = 1,
568 .ts_sampling_edge = 1,
569 .ts_clk_gated = 0,
570 .osc_clk_freq = 30400, /* in kHz */
571 .if_freq = 0, /* zero IF */
572 .zif_swap_iq = 1,
573};
574
575static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
576 .i2c_address = 0x60,
577 .osc_clk = 20
578};
579
580static int dvb_register(struct cx23885_tsport *port)
581{
582 struct cx23885_dev *dev = port->dev;
583 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
584 struct videobuf_dvb_frontend *fe0;
585 int ret;
586
587 /* Get the first frontend */
588 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
589 if (!fe0)
590 return -EINVAL;
591
592 /* init struct videobuf_dvb */
593 fe0->dvb.name = dev->name;
594
595 /* init frontend */
596 switch (dev->board) {
597 case CX23885_BOARD_HAUPPAUGE_HVR1250:
598 i2c_bus = &dev->i2c_bus[0];
599 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
600 &hauppauge_generic_config,
601 &i2c_bus->i2c_adap);
602 if (fe0->dvb.frontend != NULL) {
603 dvb_attach(mt2131_attach, fe0->dvb.frontend,
604 &i2c_bus->i2c_adap,
605 &hauppauge_generic_tunerconfig, 0);
606 }
607 break;
608 case CX23885_BOARD_HAUPPAUGE_HVR1270:
609 case CX23885_BOARD_HAUPPAUGE_HVR1275:
610 i2c_bus = &dev->i2c_bus[0];
611 fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
612 &hauppauge_lgdt3305_config,
613 &i2c_bus->i2c_adap);
614 if (fe0->dvb.frontend != NULL) {
615 dvb_attach(tda18271_attach, fe0->dvb.frontend,
616 0x60, &dev->i2c_bus[1].i2c_adap,
617 &hauppauge_hvr127x_config);
618 }
619 break;
620 case CX23885_BOARD_HAUPPAUGE_HVR1255:
621 i2c_bus = &dev->i2c_bus[0];
622 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
623 &hcw_s5h1411_config,
624 &i2c_bus->i2c_adap);
625 if (fe0->dvb.frontend != NULL) {
626 dvb_attach(tda18271_attach, fe0->dvb.frontend,
627 0x60, &dev->i2c_bus[1].i2c_adap,
628 &hauppauge_tda18271_config);
629 }
630 break;
631 case CX23885_BOARD_HAUPPAUGE_HVR1800:
632 i2c_bus = &dev->i2c_bus[0];
633 switch (alt_tuner) {
634 case 1:
635 fe0->dvb.frontend =
636 dvb_attach(s5h1409_attach,
637 &hauppauge_ezqam_config,
638 &i2c_bus->i2c_adap);
639 if (fe0->dvb.frontend != NULL) {
640 dvb_attach(tda829x_attach, fe0->dvb.frontend,
641 &dev->i2c_bus[1].i2c_adap, 0x42,
642 &tda829x_no_probe);
643 dvb_attach(tda18271_attach, fe0->dvb.frontend,
644 0x60, &dev->i2c_bus[1].i2c_adap,
645 &hauppauge_tda18271_config);
646 }
647 break;
648 case 0:
649 default:
650 fe0->dvb.frontend =
651 dvb_attach(s5h1409_attach,
652 &hauppauge_generic_config,
653 &i2c_bus->i2c_adap);
654 if (fe0->dvb.frontend != NULL)
655 dvb_attach(mt2131_attach, fe0->dvb.frontend,
656 &i2c_bus->i2c_adap,
657 &hauppauge_generic_tunerconfig, 0);
658 break;
659 }
660 break;
661 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
662 i2c_bus = &dev->i2c_bus[0];
663 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
664 &hauppauge_hvr1800lp_config,
665 &i2c_bus->i2c_adap);
666 if (fe0->dvb.frontend != NULL) {
667 dvb_attach(mt2131_attach, fe0->dvb.frontend,
668 &i2c_bus->i2c_adap,
669 &hauppauge_generic_tunerconfig, 0);
670 }
671 break;
672 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
673 i2c_bus = &dev->i2c_bus[0];
674 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
675 &fusionhdtv_5_express,
676 &i2c_bus->i2c_adap);
677 if (fe0->dvb.frontend != NULL) {
678 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
679 &i2c_bus->i2c_adap, 0x61,
680 TUNER_LG_TDVS_H06XF);
681 }
682 break;
683 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
684 i2c_bus = &dev->i2c_bus[1];
685 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
686 &hauppauge_hvr1500q_config,
687 &dev->i2c_bus[0].i2c_adap);
688 if (fe0->dvb.frontend != NULL)
689 dvb_attach(xc5000_attach, fe0->dvb.frontend,
690 &i2c_bus->i2c_adap,
691 &hauppauge_hvr1500q_tunerconfig);
692 break;
693 case CX23885_BOARD_HAUPPAUGE_HVR1500:
694 i2c_bus = &dev->i2c_bus[1];
695 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
696 &hauppauge_hvr1500_config,
697 &dev->i2c_bus[0].i2c_adap);
698 if (fe0->dvb.frontend != NULL) {
699 struct dvb_frontend *fe;
700 struct xc2028_config cfg = {
701 .i2c_adap = &i2c_bus->i2c_adap,
702 .i2c_addr = 0x61,
703 };
704 static struct xc2028_ctrl ctl = {
705 .fname = XC2028_DEFAULT_FIRMWARE,
706 .max_len = 64,
707 .demod = XC3028_FE_OREN538,
708 };
709
710 fe = dvb_attach(xc2028_attach,
711 fe0->dvb.frontend, &cfg);
712 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
713 fe->ops.tuner_ops.set_config(fe, &ctl);
714 }
715 break;
716 case CX23885_BOARD_HAUPPAUGE_HVR1200:
717 case CX23885_BOARD_HAUPPAUGE_HVR1700:
718 i2c_bus = &dev->i2c_bus[0];
719 fe0->dvb.frontend = dvb_attach(tda10048_attach,
720 &hauppauge_hvr1200_config,
721 &i2c_bus->i2c_adap);
722 if (fe0->dvb.frontend != NULL) {
723 dvb_attach(tda829x_attach, fe0->dvb.frontend,
724 &dev->i2c_bus[1].i2c_adap, 0x42,
725 &tda829x_no_probe);
726 dvb_attach(tda18271_attach, fe0->dvb.frontend,
727 0x60, &dev->i2c_bus[1].i2c_adap,
728 &hauppauge_hvr1200_tuner_config);
729 }
730 break;
731 case CX23885_BOARD_HAUPPAUGE_HVR1210:
732 i2c_bus = &dev->i2c_bus[0];
733 fe0->dvb.frontend = dvb_attach(tda10048_attach,
734 &hauppauge_hvr1210_config,
735 &i2c_bus->i2c_adap);
736 if (fe0->dvb.frontend != NULL) {
737 dvb_attach(tda18271_attach, fe0->dvb.frontend,
738 0x60, &dev->i2c_bus[1].i2c_adap,
739 &hauppauge_hvr1210_tuner_config);
740 }
741 break;
742 case CX23885_BOARD_HAUPPAUGE_HVR1400:
743 i2c_bus = &dev->i2c_bus[0];
744 fe0->dvb.frontend = dvb_attach(dib7000p_attach,
745 &i2c_bus->i2c_adap,
746 0x12, &hauppauge_hvr1400_dib7000_config);
747 if (fe0->dvb.frontend != NULL) {
748 struct dvb_frontend *fe;
749 struct xc2028_config cfg = {
750 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
751 .i2c_addr = 0x64,
752 };
753 static struct xc2028_ctrl ctl = {
754 .fname = XC3028L_DEFAULT_FIRMWARE,
755 .max_len = 64,
756 .demod = 5000,
757 /* This is true for all demods with
758 v36 firmware? */
759 .type = XC2028_D2633,
760 };
761
762 fe = dvb_attach(xc2028_attach,
763 fe0->dvb.frontend, &cfg);
764 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
765 fe->ops.tuner_ops.set_config(fe, &ctl);
766 }
767 break;
768 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
769 i2c_bus = &dev->i2c_bus[port->nr - 1];
770
771 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
772 &dvico_s5h1409_config,
773 &i2c_bus->i2c_adap);
774 if (fe0->dvb.frontend == NULL)
775 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
776 &dvico_s5h1411_config,
777 &i2c_bus->i2c_adap);
778 if (fe0->dvb.frontend != NULL)
779 dvb_attach(xc5000_attach, fe0->dvb.frontend,
780 &i2c_bus->i2c_adap,
781 &dvico_xc5000_tunerconfig);
782 break;
783 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
784 i2c_bus = &dev->i2c_bus[port->nr - 1];
785
786 fe0->dvb.frontend = dvb_attach(zl10353_attach,
787 &dvico_fusionhdtv_xc3028,
788 &i2c_bus->i2c_adap);
789 if (fe0->dvb.frontend != NULL) {
790 struct dvb_frontend *fe;
791 struct xc2028_config cfg = {
792 .i2c_adap = &i2c_bus->i2c_adap,
793 .i2c_addr = 0x61,
794 };
795 static struct xc2028_ctrl ctl = {
796 .fname = XC2028_DEFAULT_FIRMWARE,
797 .max_len = 64,
798 .demod = XC3028_FE_ZARLINK456,
799 };
800
801 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
802 &cfg);
803 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
804 fe->ops.tuner_ops.set_config(fe, &ctl);
805 }
806 break;
807 }
808 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
809 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
810 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
811 i2c_bus = &dev->i2c_bus[0];
812
813 fe0->dvb.frontend = dvb_attach(zl10353_attach,
814 &dvico_fusionhdtv_xc3028,
815 &i2c_bus->i2c_adap);
816 if (fe0->dvb.frontend != NULL) {
817 struct dvb_frontend *fe;
818 struct xc2028_config cfg = {
819 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
820 .i2c_addr = 0x61,
821 };
822 static struct xc2028_ctrl ctl = {
823 .fname = XC2028_DEFAULT_FIRMWARE,
824 .max_len = 64,
825 .demod = XC3028_FE_ZARLINK456,
826 };
827
828 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
829 &cfg);
830 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
831 fe->ops.tuner_ops.set_config(fe, &ctl);
832 }
833 break;
834 case CX23885_BOARD_TBS_6920:
835 i2c_bus = &dev->i2c_bus[0];
836
837 fe0->dvb.frontend = dvb_attach(cx24116_attach,
838 &tbs_cx24116_config,
839 &i2c_bus->i2c_adap);
840 if (fe0->dvb.frontend != NULL)
841 fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
842
843 break;
844 case CX23885_BOARD_TEVII_S470:
845 i2c_bus = &dev->i2c_bus[1];
846
847 fe0->dvb.frontend = dvb_attach(cx24116_attach,
848 &tevii_cx24116_config,
849 &i2c_bus->i2c_adap);
850 if (fe0->dvb.frontend != NULL)
851 fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
852
853 break;
854 case CX23885_BOARD_DVBWORLD_2005:
855 i2c_bus = &dev->i2c_bus[1];
856
857 fe0->dvb.frontend = dvb_attach(cx24116_attach,
858 &dvbworld_cx24116_config,
859 &i2c_bus->i2c_adap);
860 break;
861 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
862 i2c_bus = &dev->i2c_bus[0];
863 switch (port->nr) {
864 /* port B */
865 case 1:
866 fe0->dvb.frontend = dvb_attach(stv0900_attach,
867 &netup_stv0900_config,
868 &i2c_bus->i2c_adap, 0);
869 if (fe0->dvb.frontend != NULL) {
870 if (dvb_attach(stv6110_attach,
871 fe0->dvb.frontend,
872 &netup_stv6110_tunerconfig_a,
873 &i2c_bus->i2c_adap)) {
874 if (!dvb_attach(lnbh24_attach,
875 fe0->dvb.frontend,
876 &i2c_bus->i2c_adap,
877 LNBH24_PCL | LNBH24_TTX,
878 LNBH24_TEN, 0x09))
879 printk(KERN_ERR
880 "No LNBH24 found!\n");
881
882 }
883 }
884 break;
885 /* port C */
886 case 2:
887 fe0->dvb.frontend = dvb_attach(stv0900_attach,
888 &netup_stv0900_config,
889 &i2c_bus->i2c_adap, 1);
890 if (fe0->dvb.frontend != NULL) {
891 if (dvb_attach(stv6110_attach,
892 fe0->dvb.frontend,
893 &netup_stv6110_tunerconfig_b,
894 &i2c_bus->i2c_adap)) {
895 if (!dvb_attach(lnbh24_attach,
896 fe0->dvb.frontend,
897 &i2c_bus->i2c_adap,
898 LNBH24_PCL | LNBH24_TTX,
899 LNBH24_TEN, 0x0a))
900 printk(KERN_ERR
901 "No LNBH24 found!\n");
902
903 }
904 }
905 break;
906 }
907 break;
908 case CX23885_BOARD_MYGICA_X8506:
909 i2c_bus = &dev->i2c_bus[0];
910 i2c_bus2 = &dev->i2c_bus[1];
911 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
912 &mygica_x8506_lgs8gl5_config,
913 &i2c_bus->i2c_adap);
914 if (fe0->dvb.frontend != NULL) {
915 dvb_attach(xc5000_attach,
916 fe0->dvb.frontend,
917 &i2c_bus2->i2c_adap,
918 &mygica_x8506_xc5000_config);
919 }
920 break;
921 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
922 i2c_bus = &dev->i2c_bus[0];
923 i2c_bus2 = &dev->i2c_bus[1];
924 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
925 &magicpro_prohdtve2_lgs8g75_config,
926 &i2c_bus->i2c_adap);
927 if (fe0->dvb.frontend != NULL) {
928 dvb_attach(xc5000_attach,
929 fe0->dvb.frontend,
930 &i2c_bus2->i2c_adap,
931 &magicpro_prohdtve2_xc5000_config);
932 }
933 break;
934 case CX23885_BOARD_HAUPPAUGE_HVR1850:
935 case CX23885_BOARD_HAUPPAUGE_HVR1290:
936 i2c_bus = &dev->i2c_bus[0];
937 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
938 &hcw_s5h1411_config,
939 &i2c_bus->i2c_adap);
940 if (fe0->dvb.frontend != NULL)
941 dvb_attach(tda18271_attach, fe0->dvb.frontend,
942 0x60, &dev->i2c_bus[0].i2c_adap,
943 &hauppauge_tda18271_config);
944 break;
945 case CX23885_BOARD_MYGICA_X8558PRO:
946 switch (port->nr) {
947 /* port B */
948 case 1:
949 i2c_bus = &dev->i2c_bus[0];
950 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
951 &mygica_x8558pro_atbm8830_cfg1,
952 &i2c_bus->i2c_adap);
953 if (fe0->dvb.frontend != NULL) {
954 dvb_attach(max2165_attach,
955 fe0->dvb.frontend,
956 &i2c_bus->i2c_adap,
957 &mygic_x8558pro_max2165_cfg1);
958 }
959 break;
960 /* port C */
961 case 2:
962 i2c_bus = &dev->i2c_bus[1];
963 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
964 &mygica_x8558pro_atbm8830_cfg2,
965 &i2c_bus->i2c_adap);
966 if (fe0->dvb.frontend != NULL) {
967 dvb_attach(max2165_attach,
968 fe0->dvb.frontend,
969 &i2c_bus->i2c_adap,
970 &mygic_x8558pro_max2165_cfg2);
971 }
972 break;
973 }
974 break;
975
976 default:
977 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
978 " isn't supported yet\n",
979 dev->name);
980 break;
981 }
982 if (NULL == fe0->dvb.frontend) {
983 printk(KERN_ERR "%s: frontend initialization failed\n",
984 dev->name);
985 return -1;
986 }
987 /* define general-purpose callback pointer */
988 fe0->dvb.frontend->callback = cx23885_tuner_callback;
989
990 /* Put the analog decoder in standby to keep it quiet */
991 call_all(dev, core, s_power, 0);
992
993 if (fe0->dvb.frontend->ops.analog_ops.standby)
994 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
995
996 /* register everything */
997 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
998 &dev->pci->dev, adapter_nr, 0,
999 cx23885_dvb_fe_ioctl_override);
1000
1001 /* init CI & MAC */
1002 switch (dev->board) {
1003 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
1004 static struct netup_card_info cinfo;
1005
1006 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
1007 memcpy(port->frontends.adapter.proposed_mac,
1008 cinfo.port[port->nr - 1].mac, 6);
1009 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC="
1010 "%02X:%02X:%02X:%02X:%02X:%02X\n",
1011 port->nr,
1012 port->frontends.adapter.proposed_mac[0],
1013 port->frontends.adapter.proposed_mac[1],
1014 port->frontends.adapter.proposed_mac[2],
1015 port->frontends.adapter.proposed_mac[3],
1016 port->frontends.adapter.proposed_mac[4],
1017 port->frontends.adapter.proposed_mac[5]);
1018
1019 netup_ci_init(port);
1020 break;
1021 }
1022 }
1023
1024 return ret;
1025}
1026
1027int cx23885_dvb_register(struct cx23885_tsport *port)
1028{
1029
1030 struct videobuf_dvb_frontend *fe0;
1031 struct cx23885_dev *dev = port->dev;
1032 int err, i;
1033
1034 /* Here we need to allocate the correct number of frontends,
1035 * as reflected in the cards struct. The reality is that currrently
1036 * no cx23885 boards support this - yet. But, if we don't modify this
1037 * code then the second frontend would never be allocated (later)
1038 * and fail with error before the attach in dvb_register().
1039 * Without these changes we risk an OOPS later. The changes here
1040 * are for safety, and should provide a good foundation for the
1041 * future addition of any multi-frontend cx23885 based boards.
1042 */
1043 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
1044 port->num_frontends);
1045
1046 for (i = 1; i <= port->num_frontends; i++) {
1047 if (videobuf_dvb_alloc_frontend(
1048 &port->frontends, i) == NULL) {
1049 printk(KERN_ERR "%s() failed to alloc\n", __func__);
1050 return -ENOMEM;
1051 }
1052
1053 fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
1054 if (!fe0)
1055 err = -EINVAL;
1056
1057 dprintk(1, "%s\n", __func__);
1058 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
1059 dev->board,
1060 dev->name,
1061 dev->pci_bus,
1062 dev->pci_slot);
1063
1064 err = -ENODEV;
1065
1066 /* dvb stuff */
1067 /* We have to init the queue for each frontend on a port. */
1068 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
1069 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
1070 &dev->pci->dev, &port->slock,
1071 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
1072 sizeof(struct cx23885_buffer), port);
1073 }
1074 err = dvb_register(port);
1075 if (err != 0)
1076 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
1077 __func__, err);
1078
1079 return err;
1080}
1081
1082int cx23885_dvb_unregister(struct cx23885_tsport *port)
1083{
1084 struct videobuf_dvb_frontend *fe0;
1085
1086 /* FIXME: in an error condition where the we have
1087 * an expected number of frontends (attach problem)
1088 * then this might not clean up correctly, if 1
1089 * is invalid.
1090 * This comment only applies to future boards IF they
1091 * implement MFE support.
1092 */
1093 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
1094 if (fe0->dvb.frontend)
1095 videobuf_dvb_unregister_bus(&port->frontends);
1096
1097 switch (port->dev->board) {
1098 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1099 netup_ci_exit(port);
1100 break;
1101 }
1102
1103 return 0;
1104}
1105
Linux kernel - Deliverables
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