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mtd: denali: remove another set-but-unused variable
[deliverable/linux.git] / drivers / mtd / nand / denali.c
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CommitLineData
1/*
2 * NAND Flash Controller Device Driver
3 * Copyright © 2009-2010, Intel Corporation and its suppliers.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/dma-mapping.h>
22#include <linux/wait.h>
23#include <linux/mutex.h>
24#include <linux/slab.h>
25#include <linux/mtd/mtd.h>
26#include <linux/module.h>
27
28#include "denali.h"
29
30MODULE_LICENSE("GPL");
31
32/*
33 * We define a module parameter that allows the user to override
34 * the hardware and decide what timing mode should be used.
35 */
36#define NAND_DEFAULT_TIMINGS -1
37
38static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
39module_param(onfi_timing_mode, int, S_IRUGO);
40MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting."
41 " -1 indicates use default timings");
42
43#define DENALI_NAND_NAME "denali-nand"
44
45/*
46 * We define a macro here that combines all interrupts this driver uses into
47 * a single constant value, for convenience.
48 */
49#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
50 INTR_STATUS__ECC_TRANSACTION_DONE | \
51 INTR_STATUS__ECC_ERR | \
52 INTR_STATUS__PROGRAM_FAIL | \
53 INTR_STATUS__LOAD_COMP | \
54 INTR_STATUS__PROGRAM_COMP | \
55 INTR_STATUS__TIME_OUT | \
56 INTR_STATUS__ERASE_FAIL | \
57 INTR_STATUS__RST_COMP | \
58 INTR_STATUS__ERASE_COMP)
59
60/*
61 * indicates whether or not the internal value for the flash bank is
62 * valid or not
63 */
64#define CHIP_SELECT_INVALID -1
65
66#define SUPPORT_8BITECC 1
67
68/*
69 * This macro divides two integers and rounds fractional values up
70 * to the nearest integer value.
71 */
72#define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
73
74/*
75 * this macro allows us to convert from an MTD structure to our own
76 * device context (denali) structure.
77 */
78#define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd)
79
80/*
81 * These constants are defined by the driver to enable common driver
82 * configuration options.
83 */
84#define SPARE_ACCESS 0x41
85#define MAIN_ACCESS 0x42
86#define MAIN_SPARE_ACCESS 0x43
87#define PIPELINE_ACCESS 0x2000
88
89#define DENALI_READ 0
90#define DENALI_WRITE 0x100
91
92/* types of device accesses. We can issue commands and get status */
93#define COMMAND_CYCLE 0
94#define ADDR_CYCLE 1
95#define STATUS_CYCLE 2
96
97/*
98 * this is a helper macro that allows us to
99 * format the bank into the proper bits for the controller
100 */
101#define BANK(x) ((x) << 24)
102
103/* forward declarations */
104static void clear_interrupts(struct denali_nand_info *denali);
105static uint32_t wait_for_irq(struct denali_nand_info *denali,
106 uint32_t irq_mask);
107static void denali_irq_enable(struct denali_nand_info *denali,
108 uint32_t int_mask);
109static uint32_t read_interrupt_status(struct denali_nand_info *denali);
110
111/*
112 * Certain operations for the denali NAND controller use an indexed mode to
113 * read/write data. The operation is performed by writing the address value
114 * of the command to the device memory followed by the data. This function
115 * abstracts this common operation.
116 */
117static void index_addr(struct denali_nand_info *denali,
118 uint32_t address, uint32_t data)
119{
120 iowrite32(address, denali->flash_mem);
121 iowrite32(data, denali->flash_mem + 0x10);
122}
123
124/* Perform an indexed read of the device */
125static void index_addr_read_data(struct denali_nand_info *denali,
126 uint32_t address, uint32_t *pdata)
127{
128 iowrite32(address, denali->flash_mem);
129 *pdata = ioread32(denali->flash_mem + 0x10);
130}
131
132/*
133 * We need to buffer some data for some of the NAND core routines.
134 * The operations manage buffering that data.
135 */
136static void reset_buf(struct denali_nand_info *denali)
137{
138 denali->buf.head = denali->buf.tail = 0;
139}
140
141static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
142{
143 denali->buf.buf[denali->buf.tail++] = byte;
144}
145
146/* reads the status of the device */
147static void read_status(struct denali_nand_info *denali)
148{
149 uint32_t cmd;
150
151 /* initialize the data buffer to store status */
152 reset_buf(denali);
153
154 cmd = ioread32(denali->flash_reg + WRITE_PROTECT);
155 if (cmd)
156 write_byte_to_buf(denali, NAND_STATUS_WP);
157 else
158 write_byte_to_buf(denali, 0);
159}
160
161/* resets a specific device connected to the core */
162static void reset_bank(struct denali_nand_info *denali)
163{
164 uint32_t irq_status;
165 uint32_t irq_mask = INTR_STATUS__RST_COMP |
166 INTR_STATUS__TIME_OUT;
167
168 clear_interrupts(denali);
169
170 iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
171
172 irq_status = wait_for_irq(denali, irq_mask);
173
174 if (irq_status & INTR_STATUS__TIME_OUT)
175 dev_err(denali->dev, "reset bank failed.\n");
176}
177
178/* Reset the flash controller */
179static uint16_t denali_nand_reset(struct denali_nand_info *denali)
180{
181 int i;
182
183 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
184 __FILE__, __LINE__, __func__);
185
186 for (i = 0 ; i < denali->max_banks; i++)
187 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
188 denali->flash_reg + INTR_STATUS(i));
189
190 for (i = 0 ; i < denali->max_banks; i++) {
191 iowrite32(1 << i, denali->flash_reg + DEVICE_RESET);
192 while (!(ioread32(denali->flash_reg +
193 INTR_STATUS(i)) &
194 (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))
195 cpu_relax();
196 if (ioread32(denali->flash_reg + INTR_STATUS(i)) &
197 INTR_STATUS__TIME_OUT)
198 dev_dbg(denali->dev,
199 "NAND Reset operation timed out on bank %d\n", i);
200 }
201
202 for (i = 0; i < denali->max_banks; i++)
203 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
204 denali->flash_reg + INTR_STATUS(i));
205
206 return PASS;
207}
208
209/*
210 * this routine calculates the ONFI timing values for a given mode and
211 * programs the clocking register accordingly. The mode is determined by
212 * the get_onfi_nand_para routine.
213 */
214static void nand_onfi_timing_set(struct denali_nand_info *denali,
215 uint16_t mode)
216{
217 uint16_t Trea[6] = {40, 30, 25, 20, 20, 16};
218 uint16_t Trp[6] = {50, 25, 17, 15, 12, 10};
219 uint16_t Treh[6] = {30, 15, 15, 10, 10, 7};
220 uint16_t Trc[6] = {100, 50, 35, 30, 25, 20};
221 uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15};
222 uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5};
223 uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25};
224 uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70};
225 uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100};
226 uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100};
227 uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60};
228 uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15};
229
230 uint16_t TclsRising = 1;
231 uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
232 uint16_t dv_window = 0;
233 uint16_t en_lo, en_hi;
234 uint16_t acc_clks;
235 uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
236
237 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
238 __FILE__, __LINE__, __func__);
239
240 en_lo = CEIL_DIV(Trp[mode], CLK_X);
241 en_hi = CEIL_DIV(Treh[mode], CLK_X);
242#if ONFI_BLOOM_TIME
243 if ((en_hi * CLK_X) < (Treh[mode] + 2))
244 en_hi++;
245#endif
246
247 if ((en_lo + en_hi) * CLK_X < Trc[mode])
248 en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X);
249
250 if ((en_lo + en_hi) < CLK_MULTI)
251 en_lo += CLK_MULTI - en_lo - en_hi;
252
253 while (dv_window < 8) {
254 data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode];
255
256 data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode];
257
258 data_invalid =
259 data_invalid_rhoh <
260 data_invalid_rloh ? data_invalid_rhoh : data_invalid_rloh;
261
262 dv_window = data_invalid - Trea[mode];
263
264 if (dv_window < 8)
265 en_lo++;
266 }
267
268 acc_clks = CEIL_DIV(Trea[mode], CLK_X);
269
270 while (((acc_clks * CLK_X) - Trea[mode]) < 3)
271 acc_clks++;
272
273 if ((data_invalid - acc_clks * CLK_X) < 2)
274 dev_warn(denali->dev, "%s, Line %d: Warning!\n",
275 __FILE__, __LINE__);
276
277 addr_2_data = CEIL_DIV(Tadl[mode], CLK_X);
278 re_2_we = CEIL_DIV(Trhw[mode], CLK_X);
279 re_2_re = CEIL_DIV(Trhz[mode], CLK_X);
280 we_2_re = CEIL_DIV(Twhr[mode], CLK_X);
281 cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X);
282 if (!TclsRising)
283 cs_cnt = CEIL_DIV(Tcs[mode], CLK_X);
284 if (cs_cnt == 0)
285 cs_cnt = 1;
286
287 if (Tcea[mode]) {
288 while (((cs_cnt * CLK_X) + Trea[mode]) < Tcea[mode])
289 cs_cnt++;
290 }
291
292#if MODE5_WORKAROUND
293 if (mode == 5)
294 acc_clks = 5;
295#endif
296
297 /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
298 if ((ioread32(denali->flash_reg + MANUFACTURER_ID) == 0) &&
299 (ioread32(denali->flash_reg + DEVICE_ID) == 0x88))
300 acc_clks = 6;
301
302 iowrite32(acc_clks, denali->flash_reg + ACC_CLKS);
303 iowrite32(re_2_we, denali->flash_reg + RE_2_WE);
304 iowrite32(re_2_re, denali->flash_reg + RE_2_RE);
305 iowrite32(we_2_re, denali->flash_reg + WE_2_RE);
306 iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA);
307 iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
308 iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
309 iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
310}
311
312/* queries the NAND device to see what ONFI modes it supports. */
313static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
314{
315 int i;
316
317 /*
318 * we needn't to do a reset here because driver has already
319 * reset all the banks before
320 */
321 if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
322 ONFI_TIMING_MODE__VALUE))
323 return FAIL;
324
325 for (i = 5; i > 0; i--) {
326 if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
327 (0x01 << i))
328 break;
329 }
330
331 nand_onfi_timing_set(denali, i);
332
333 /*
334 * By now, all the ONFI devices we know support the page cache
335 * rw feature. So here we enable the pipeline_rw_ahead feature
336 */
337 /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */
338 /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */
339
340 return PASS;
341}
342
343static void get_samsung_nand_para(struct denali_nand_info *denali,
344 uint8_t device_id)
345{
346 if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
347 /* Set timing register values according to datasheet */
348 iowrite32(5, denali->flash_reg + ACC_CLKS);
349 iowrite32(20, denali->flash_reg + RE_2_WE);
350 iowrite32(12, denali->flash_reg + WE_2_RE);
351 iowrite32(14, denali->flash_reg + ADDR_2_DATA);
352 iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT);
353 iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT);
354 iowrite32(2, denali->flash_reg + CS_SETUP_CNT);
355 }
356}
357
358static void get_toshiba_nand_para(struct denali_nand_info *denali)
359{
360 uint32_t tmp;
361
362 /*
363 * Workaround to fix a controller bug which reports a wrong
364 * spare area size for some kind of Toshiba NAND device
365 */
366 if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
367 (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
368 iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
369 tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) *
370 ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
371 iowrite32(tmp,
372 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
373#if SUPPORT_15BITECC
374 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
375#elif SUPPORT_8BITECC
376 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
377#endif
378 }
379}
380
381static void get_hynix_nand_para(struct denali_nand_info *denali,
382 uint8_t device_id)
383{
384 uint32_t main_size, spare_size;
385
386 switch (device_id) {
387 case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
388 case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
389 iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK);
390 iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
391 iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
392 main_size = 4096 *
393 ioread32(denali->flash_reg + DEVICES_CONNECTED);
394 spare_size = 224 *
395 ioread32(denali->flash_reg + DEVICES_CONNECTED);
396 iowrite32(main_size,
397 denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
398 iowrite32(spare_size,
399 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
400 iowrite32(0, denali->flash_reg + DEVICE_WIDTH);
401#if SUPPORT_15BITECC
402 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
403#elif SUPPORT_8BITECC
404 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
405#endif
406 break;
407 default:
408 dev_warn(denali->dev,
409 "Spectra: Unknown Hynix NAND (Device ID: 0x%x)."
410 "Will use default parameter values instead.\n",
411 device_id);
412 }
413}
414
415/*
416 * determines how many NAND chips are connected to the controller. Note for
417 * Intel CE4100 devices we don't support more than one device.
418 */
419static void find_valid_banks(struct denali_nand_info *denali)
420{
421 uint32_t id[denali->max_banks];
422 int i;
423
424 denali->total_used_banks = 1;
425 for (i = 0; i < denali->max_banks; i++) {
426 index_addr(denali, MODE_11 | (i << 24) | 0, 0x90);
427 index_addr(denali, MODE_11 | (i << 24) | 1, 0);
428 index_addr_read_data(denali,
429 MODE_11 | (i << 24) | 2, &id[i]);
430
431 dev_dbg(denali->dev,
432 "Return 1st ID for bank[%d]: %x\n", i, id[i]);
433
434 if (i == 0) {
435 if (!(id[i] & 0x0ff))
436 break; /* WTF? */
437 } else {
438 if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
439 denali->total_used_banks++;
440 else
441 break;
442 }
443 }
444
445 if (denali->platform == INTEL_CE4100) {
446 /*
447 * Platform limitations of the CE4100 device limit
448 * users to a single chip solution for NAND.
449 * Multichip support is not enabled.
450 */
451 if (denali->total_used_banks != 1) {
452 dev_err(denali->dev,
453 "Sorry, Intel CE4100 only supports "
454 "a single NAND device.\n");
455 BUG();
456 }
457 }
458 dev_dbg(denali->dev,
459 "denali->total_used_banks: %d\n", denali->total_used_banks);
460}
461
462/*
463 * Use the configuration feature register to determine the maximum number of
464 * banks that the hardware supports.
465 */
466static void detect_max_banks(struct denali_nand_info *denali)
467{
468 uint32_t features = ioread32(denali->flash_reg + FEATURES);
469
470 denali->max_banks = 2 << (features & FEATURES__N_BANKS);
471}
472
473static void detect_partition_feature(struct denali_nand_info *denali)
474{
475 /*
476 * For MRST platform, denali->fwblks represent the
477 * number of blocks firmware is taken,
478 * FW is in protect partition and MTD driver has no
479 * permission to access it. So let driver know how many
480 * blocks it can't touch.
481 */
482 if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
483 if ((ioread32(denali->flash_reg + PERM_SRC_ID(1)) &
484 PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) {
485 denali->fwblks =
486 ((ioread32(denali->flash_reg + MIN_MAX_BANK(1)) &
487 MIN_MAX_BANK__MIN_VALUE) *
488 denali->blksperchip)
489 +
490 (ioread32(denali->flash_reg + MIN_BLK_ADDR(1)) &
491 MIN_BLK_ADDR__VALUE);
492 } else
493 denali->fwblks = SPECTRA_START_BLOCK;
494 } else
495 denali->fwblks = SPECTRA_START_BLOCK;
496}
497
498static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
499{
500 uint16_t status = PASS;
501 uint32_t id_bytes[8], addr;
502 uint8_t maf_id, device_id;
503 int i;
504
505 dev_dbg(denali->dev,
506 "%s, Line %d, Function: %s\n",
507 __FILE__, __LINE__, __func__);
508
509 /*
510 * Use read id method to get device ID and other params.
511 * For some NAND chips, controller can't report the correct
512 * device ID by reading from DEVICE_ID register
513 */
514 addr = MODE_11 | BANK(denali->flash_bank);
515 index_addr(denali, addr | 0, 0x90);
516 index_addr(denali, addr | 1, 0);
517 for (i = 0; i < 8; i++)
518 index_addr_read_data(denali, addr | 2, &id_bytes[i]);
519 maf_id = id_bytes[0];
520 device_id = id_bytes[1];
521
522 if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
523 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
524 if (FAIL == get_onfi_nand_para(denali))
525 return FAIL;
526 } else if (maf_id == 0xEC) { /* Samsung NAND */
527 get_samsung_nand_para(denali, device_id);
528 } else if (maf_id == 0x98) { /* Toshiba NAND */
529 get_toshiba_nand_para(denali);
530 } else if (maf_id == 0xAD) { /* Hynix NAND */
531 get_hynix_nand_para(denali, device_id);
532 }
533
534 dev_info(denali->dev,
535 "Dump timing register values:"
536 "acc_clks: %d, re_2_we: %d, re_2_re: %d\n"
537 "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n"
538 "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
539 ioread32(denali->flash_reg + ACC_CLKS),
540 ioread32(denali->flash_reg + RE_2_WE),
541 ioread32(denali->flash_reg + RE_2_RE),
542 ioread32(denali->flash_reg + WE_2_RE),
543 ioread32(denali->flash_reg + ADDR_2_DATA),
544 ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
545 ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
546 ioread32(denali->flash_reg + CS_SETUP_CNT));
547
548 find_valid_banks(denali);
549
550 detect_partition_feature(denali);
551
552 /*
553 * If the user specified to override the default timings
554 * with a specific ONFI mode, we apply those changes here.
555 */
556 if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
557 nand_onfi_timing_set(denali, onfi_timing_mode);
558
559 return status;
560}
561
562static void denali_set_intr_modes(struct denali_nand_info *denali,
563 uint16_t INT_ENABLE)
564{
565 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
566 __FILE__, __LINE__, __func__);
567
568 if (INT_ENABLE)
569 iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE);
570 else
571 iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
572}
573
574/*
575 * validation function to verify that the controlling software is making
576 * a valid request
577 */
578static inline bool is_flash_bank_valid(int flash_bank)
579{
580 return (flash_bank >= 0 && flash_bank < 4);
581}
582
583static void denali_irq_init(struct denali_nand_info *denali)
584{
585 uint32_t int_mask;
586 int i;
587
588 /* Disable global interrupts */
589 denali_set_intr_modes(denali, false);
590
591 int_mask = DENALI_IRQ_ALL;
592
593 /* Clear all status bits */
594 for (i = 0; i < denali->max_banks; ++i)
595 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i));
596
597 denali_irq_enable(denali, int_mask);
598}
599
600static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali)
601{
602 denali_set_intr_modes(denali, false);
603 free_irq(irqnum, denali);
604}
605
606static void denali_irq_enable(struct denali_nand_info *denali,
607 uint32_t int_mask)
608{
609 int i;
610
611 for (i = 0; i < denali->max_banks; ++i)
612 iowrite32(int_mask, denali->flash_reg + INTR_EN(i));
613}
614
615/*
616 * This function only returns when an interrupt that this driver cares about
617 * occurs. This is to reduce the overhead of servicing interrupts
618 */
619static inline uint32_t denali_irq_detected(struct denali_nand_info *denali)
620{
621 return read_interrupt_status(denali) & DENALI_IRQ_ALL;
622}
623
624/* Interrupts are cleared by writing a 1 to the appropriate status bit */
625static inline void clear_interrupt(struct denali_nand_info *denali,
626 uint32_t irq_mask)
627{
628 uint32_t intr_status_reg;
629
630 intr_status_reg = INTR_STATUS(denali->flash_bank);
631
632 iowrite32(irq_mask, denali->flash_reg + intr_status_reg);
633}
634
635static void clear_interrupts(struct denali_nand_info *denali)
636{
637 uint32_t status;
638
639 spin_lock_irq(&denali->irq_lock);
640
641 status = read_interrupt_status(denali);
642 clear_interrupt(denali, status);
643
644 denali->irq_status = 0x0;
645 spin_unlock_irq(&denali->irq_lock);
646}
647
648static uint32_t read_interrupt_status(struct denali_nand_info *denali)
649{
650 uint32_t intr_status_reg;
651
652 intr_status_reg = INTR_STATUS(denali->flash_bank);
653
654 return ioread32(denali->flash_reg + intr_status_reg);
655}
656
657/*
658 * This is the interrupt service routine. It handles all interrupts
659 * sent to this device. Note that on CE4100, this is a shared interrupt.
660 */
661static irqreturn_t denali_isr(int irq, void *dev_id)
662{
663 struct denali_nand_info *denali = dev_id;
664 uint32_t irq_status;
665 irqreturn_t result = IRQ_NONE;
666
667 spin_lock(&denali->irq_lock);
668
669 /* check to see if a valid NAND chip has been selected. */
670 if (is_flash_bank_valid(denali->flash_bank)) {
671 /*
672 * check to see if controller generated the interrupt,
673 * since this is a shared interrupt
674 */
675 irq_status = denali_irq_detected(denali);
676 if (irq_status != 0) {
677 /* handle interrupt */
678 /* first acknowledge it */
679 clear_interrupt(denali, irq_status);
680 /*
681 * store the status in the device context for someone
682 * to read
683 */
684 denali->irq_status |= irq_status;
685 /* notify anyone who cares that it happened */
686 complete(&denali->complete);
687 /* tell the OS that we've handled this */
688 result = IRQ_HANDLED;
689 }
690 }
691 spin_unlock(&denali->irq_lock);
692 return result;
693}
694#define BANK(x) ((x) << 24)
695
696static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
697{
698 unsigned long comp_res;
699 uint32_t intr_status;
700 unsigned long timeout = msecs_to_jiffies(1000);
701
702 do {
703 comp_res =
704 wait_for_completion_timeout(&denali->complete, timeout);
705 spin_lock_irq(&denali->irq_lock);
706 intr_status = denali->irq_status;
707
708 if (intr_status & irq_mask) {
709 denali->irq_status &= ~irq_mask;
710 spin_unlock_irq(&denali->irq_lock);
711 /* our interrupt was detected */
712 break;
713 } else {
714 /*
715 * these are not the interrupts you are looking for -
716 * need to wait again
717 */
718 spin_unlock_irq(&denali->irq_lock);
719 }
720 } while (comp_res != 0);
721
722 if (comp_res == 0) {
723 /* timeout */
724 pr_err("timeout occurred, status = 0x%x, mask = 0x%x\n",
725 intr_status, irq_mask);
726
727 intr_status = 0;
728 }
729 return intr_status;
730}
731
732/*
733 * This helper function setups the registers for ECC and whether or not
734 * the spare area will be transferred.
735 */
736static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
737 bool transfer_spare)
738{
739 int ecc_en_flag, transfer_spare_flag;
740
741 /* set ECC, transfer spare bits if needed */
742 ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
743 transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
744
745 /* Enable spare area/ECC per user's request. */
746 iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
747 iowrite32(transfer_spare_flag,
748 denali->flash_reg + TRANSFER_SPARE_REG);
749}
750
751/*
752 * sends a pipeline command operation to the controller. See the Denali NAND
753 * controller's user guide for more information (section 4.2.3.6).
754 */
755static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
756 bool ecc_en,
757 bool transfer_spare,
758 int access_type,
759 int op)
760{
761 int status = PASS;
762 uint32_t page_count = 1;
763 uint32_t addr, cmd, irq_status, irq_mask;
764
765 if (op == DENALI_READ)
766 irq_mask = INTR_STATUS__LOAD_COMP;
767 else if (op == DENALI_WRITE)
768 irq_mask = 0;
769 else
770 BUG();
771
772 setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
773
774 clear_interrupts(denali);
775
776 addr = BANK(denali->flash_bank) | denali->page;
777
778 if (op == DENALI_WRITE && access_type != SPARE_ACCESS) {
779 cmd = MODE_01 | addr;
780 iowrite32(cmd, denali->flash_mem);
781 } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) {
782 /* read spare area */
783 cmd = MODE_10 | addr;
784 index_addr(denali, cmd, access_type);
785
786 cmd = MODE_01 | addr;
787 iowrite32(cmd, denali->flash_mem);
788 } else if (op == DENALI_READ) {
789 /* setup page read request for access type */
790 cmd = MODE_10 | addr;
791 index_addr(denali, cmd, access_type);
792
793 /*
794 * page 33 of the NAND controller spec indicates we should not
795 * use the pipeline commands in Spare area only mode.
796 * So we don't.
797 */
798 if (access_type == SPARE_ACCESS) {
799 cmd = MODE_01 | addr;
800 iowrite32(cmd, denali->flash_mem);
801 } else {
802 index_addr(denali, cmd,
803 PIPELINE_ACCESS | op | page_count);
804
805 /*
806 * wait for command to be accepted
807 * can always use status0 bit as the
808 * mask is identical for each bank.
809 */
810 irq_status = wait_for_irq(denali, irq_mask);
811
812 if (irq_status == 0) {
813 dev_err(denali->dev,
814 "cmd, page, addr on timeout "
815 "(0x%x, 0x%x, 0x%x)\n",
816 cmd, denali->page, addr);
817 status = FAIL;
818 } else {
819 cmd = MODE_01 | addr;
820 iowrite32(cmd, denali->flash_mem);
821 }
822 }
823 }
824 return status;
825}
826
827/* helper function that simply writes a buffer to the flash */
828static int write_data_to_flash_mem(struct denali_nand_info *denali,
829 const uint8_t *buf,
830 int len)
831{
832 uint32_t *buf32;
833 int i;
834
835 /*
836 * verify that the len is a multiple of 4.
837 * see comment in read_data_from_flash_mem()
838 */
839 BUG_ON((len % 4) != 0);
840
841 /* write the data to the flash memory */
842 buf32 = (uint32_t *)buf;
843 for (i = 0; i < len / 4; i++)
844 iowrite32(*buf32++, denali->flash_mem + 0x10);
845 return i*4; /* intent is to return the number of bytes read */
846}
847
848/* helper function that simply reads a buffer from the flash */
849static int read_data_from_flash_mem(struct denali_nand_info *denali,
850 uint8_t *buf,
851 int len)
852{
853 uint32_t *buf32;
854 int i;
855
856 /*
857 * we assume that len will be a multiple of 4, if not it would be nice
858 * to know about it ASAP rather than have random failures...
859 * This assumption is based on the fact that this function is designed
860 * to be used to read flash pages, which are typically multiples of 4.
861 */
862 BUG_ON((len % 4) != 0);
863
864 /* transfer the data from the flash */
865 buf32 = (uint32_t *)buf;
866 for (i = 0; i < len / 4; i++)
867 *buf32++ = ioread32(denali->flash_mem + 0x10);
868 return i*4; /* intent is to return the number of bytes read */
869}
870
871/* writes OOB data to the device */
872static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
873{
874 struct denali_nand_info *denali = mtd_to_denali(mtd);
875 uint32_t irq_status;
876 uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |
877 INTR_STATUS__PROGRAM_FAIL;
878 int status = 0;
879
880 denali->page = page;
881
882 if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS,
883 DENALI_WRITE) == PASS) {
884 write_data_to_flash_mem(denali, buf, mtd->oobsize);
885
886 /* wait for operation to complete */
887 irq_status = wait_for_irq(denali, irq_mask);
888
889 if (irq_status == 0) {
890 dev_err(denali->dev, "OOB write failed\n");
891 status = -EIO;
892 }
893 } else {
894 dev_err(denali->dev, "unable to send pipeline command\n");
895 status = -EIO;
896 }
897 return status;
898}
899
900/* reads OOB data from the device */
901static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
902{
903 struct denali_nand_info *denali = mtd_to_denali(mtd);
904 uint32_t irq_mask = INTR_STATUS__LOAD_COMP;
905 uint32_t irq_status, addr, cmd;
906
907 denali->page = page;
908
909 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
910 DENALI_READ) == PASS) {
911 read_data_from_flash_mem(denali, buf, mtd->oobsize);
912
913 /*
914 * wait for command to be accepted
915 * can always use status0 bit as the
916 * mask is identical for each bank.
917 */
918 irq_status = wait_for_irq(denali, irq_mask);
919
920 if (irq_status == 0)
921 dev_err(denali->dev, "page on OOB timeout %d\n",
922 denali->page);
923
924 /*
925 * We set the device back to MAIN_ACCESS here as I observed
926 * instability with the controller if you do a block erase
927 * and the last transaction was a SPARE_ACCESS. Block erase
928 * is reliable (according to the MTD test infrastructure)
929 * if you are in MAIN_ACCESS.
930 */
931 addr = BANK(denali->flash_bank) | denali->page;
932 cmd = MODE_10 | addr;
933 index_addr(denali, cmd, MAIN_ACCESS);
934 }
935}
936
937/*
938 * this function examines buffers to see if they contain data that
939 * indicate that the buffer is part of an erased region of flash.
940 */
941static bool is_erased(uint8_t *buf, int len)
942{
943 int i;
944 for (i = 0; i < len; i++)
945 if (buf[i] != 0xFF)
946 return false;
947 return true;
948}
949#define ECC_SECTOR_SIZE 512
950
951#define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12)
952#define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET))
953#define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK)
954#define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE))
955#define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8)
956#define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO)
957
958static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
959 uint32_t irq_status, unsigned int *max_bitflips)
960{
961 bool check_erased_page = false;
962 unsigned int bitflips = 0;
963
964 if (irq_status & INTR_STATUS__ECC_ERR) {
965 /* read the ECC errors. we'll ignore them for now */
966 uint32_t err_address, err_correction_info, err_byte,
967 err_sector, err_device, err_correction_value;
968 denali_set_intr_modes(denali, false);
969
970 do {
971 err_address = ioread32(denali->flash_reg +
972 ECC_ERROR_ADDRESS);
973 err_sector = ECC_SECTOR(err_address);
974 err_byte = ECC_BYTE(err_address);
975
976 err_correction_info = ioread32(denali->flash_reg +
977 ERR_CORRECTION_INFO);
978 err_correction_value =
979 ECC_CORRECTION_VALUE(err_correction_info);
980 err_device = ECC_ERR_DEVICE(err_correction_info);
981
982 if (ECC_ERROR_CORRECTABLE(err_correction_info)) {
983 /*
984 * If err_byte is larger than ECC_SECTOR_SIZE,
985 * means error happened in OOB, so we ignore
986 * it. It's no need for us to correct it
987 * err_device is represented the NAND error
988 * bits are happened in if there are more
989 * than one NAND connected.
990 */
991 if (err_byte < ECC_SECTOR_SIZE) {
992 int offset;
993 offset = (err_sector *
994 ECC_SECTOR_SIZE +
995 err_byte) *
996 denali->devnum +
997 err_device;
998 /* correct the ECC error */
999 buf[offset] ^= err_correction_value;
1000 denali->mtd.ecc_stats.corrected++;
1001 bitflips++;
1002 }
1003 } else {
1004 /*
1005 * if the error is not correctable, need to
1006 * look at the page to see if it is an erased
1007 * page. if so, then it's not a real ECC error
1008 */
1009 check_erased_page = true;
1010 }
1011 } while (!ECC_LAST_ERR(err_correction_info));
1012 /*
1013 * Once handle all ecc errors, controller will triger
1014 * a ECC_TRANSACTION_DONE interrupt, so here just wait
1015 * for a while for this interrupt
1016 */
1017 while (!(read_interrupt_status(denali) &
1018 INTR_STATUS__ECC_TRANSACTION_DONE))
1019 cpu_relax();
1020 clear_interrupts(denali);
1021 denali_set_intr_modes(denali, true);
1022 }
1023 *max_bitflips = bitflips;
1024 return check_erased_page;
1025}
1026
1027/* programs the controller to either enable/disable DMA transfers */
1028static void denali_enable_dma(struct denali_nand_info *denali, bool en)
1029{
1030 iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE);
1031 ioread32(denali->flash_reg + DMA_ENABLE);
1032}
1033
1034/* setups the HW to perform the data DMA */
1035static void denali_setup_dma(struct denali_nand_info *denali, int op)
1036{
1037 uint32_t mode;
1038 const int page_count = 1;
1039 uint32_t addr = denali->buf.dma_buf;
1040
1041 mode = MODE_10 | BANK(denali->flash_bank);
1042
1043 /* DMA is a four step process */
1044
1045 /* 1. setup transfer type and # of pages */
1046 index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
1047
1048 /* 2. set memory high address bits 23:8 */
1049 index_addr(denali, mode | ((addr >> 16) << 8), 0x2200);
1050
1051 /* 3. set memory low address bits 23:8 */
1052 index_addr(denali, mode | ((addr & 0xff) << 8), 0x2300);
1053
1054 /* 4. interrupt when complete, burst len = 64 bytes */
1055 index_addr(denali, mode | 0x14000, 0x2400);
1056}
1057
1058/*
1059 * writes a page. user specifies type, and this function handles the
1060 * configuration details.
1061 */
1062static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
1063 const uint8_t *buf, bool raw_xfer)
1064{
1065 struct denali_nand_info *denali = mtd_to_denali(mtd);
1066
1067 dma_addr_t addr = denali->buf.dma_buf;
1068 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1069
1070 uint32_t irq_status;
1071 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP |
1072 INTR_STATUS__PROGRAM_FAIL;
1073
1074 /*
1075 * if it is a raw xfer, we want to disable ecc and send the spare area.
1076 * !raw_xfer - enable ecc
1077 * raw_xfer - transfer spare
1078 */
1079 setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer);
1080
1081 /* copy buffer into DMA buffer */
1082 memcpy(denali->buf.buf, buf, mtd->writesize);
1083
1084 if (raw_xfer) {
1085 /* transfer the data to the spare area */
1086 memcpy(denali->buf.buf + mtd->writesize,
1087 chip->oob_poi,
1088 mtd->oobsize);
1089 }
1090
1091 dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE);
1092
1093 clear_interrupts(denali);
1094 denali_enable_dma(denali, true);
1095
1096 denali_setup_dma(denali, DENALI_WRITE);
1097
1098 /* wait for operation to complete */
1099 irq_status = wait_for_irq(denali, irq_mask);
1100
1101 if (irq_status == 0) {
1102 dev_err(denali->dev,
1103 "timeout on write_page (type = %d)\n",
1104 raw_xfer);
1105 denali->status = NAND_STATUS_FAIL;
1106 }
1107
1108 denali_enable_dma(denali, false);
1109 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE);
1110
1111 return 0;
1112}
1113
1114/* NAND core entry points */
1115
1116/*
1117 * this is the callback that the NAND core calls to write a page. Since
1118 * writing a page with ECC or without is similar, all the work is done
1119 * by write_page above.
1120 */
1121static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1122 const uint8_t *buf, int oob_required)
1123{
1124 /*
1125 * for regular page writes, we let HW handle all the ECC
1126 * data written to the device.
1127 */
1128 return write_page(mtd, chip, buf, false);
1129}
1130
1131/*
1132 * This is the callback that the NAND core calls to write a page without ECC.
1133 * raw access is similar to ECC page writes, so all the work is done in the
1134 * write_page() function above.
1135 */
1136static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1137 const uint8_t *buf, int oob_required)
1138{
1139 /*
1140 * for raw page writes, we want to disable ECC and simply write
1141 * whatever data is in the buffer.
1142 */
1143 return write_page(mtd, chip, buf, true);
1144}
1145
1146static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1147 int page)
1148{
1149 return write_oob_data(mtd, chip->oob_poi, page);
1150}
1151
1152static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1153 int page)
1154{
1155 read_oob_data(mtd, chip->oob_poi, page);
1156
1157 return 0;
1158}
1159
1160static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1161 uint8_t *buf, int oob_required, int page)
1162{
1163 unsigned int max_bitflips;
1164 struct denali_nand_info *denali = mtd_to_denali(mtd);
1165
1166 dma_addr_t addr = denali->buf.dma_buf;
1167 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1168
1169 uint32_t irq_status;
1170 uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE |
1171 INTR_STATUS__ECC_ERR;
1172 bool check_erased_page = false;
1173
1174 if (page != denali->page) {
1175 dev_err(denali->dev, "IN %s: page %d is not"
1176 " equal to denali->page %d, investigate!!",
1177 __func__, page, denali->page);
1178 BUG();
1179 }
1180
1181 setup_ecc_for_xfer(denali, true, false);
1182
1183 denali_enable_dma(denali, true);
1184 dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
1185
1186 clear_interrupts(denali);
1187 denali_setup_dma(denali, DENALI_READ);
1188
1189 /* wait for operation to complete */
1190 irq_status = wait_for_irq(denali, irq_mask);
1191
1192 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
1193
1194 memcpy(buf, denali->buf.buf, mtd->writesize);
1195
1196 check_erased_page = handle_ecc(denali, buf, irq_status, &max_bitflips);
1197 denali_enable_dma(denali, false);
1198
1199 if (check_erased_page) {
1200 read_oob_data(&denali->mtd, chip->oob_poi, denali->page);
1201
1202 /* check ECC failures that may have occurred on erased pages */
1203 if (check_erased_page) {
1204 if (!is_erased(buf, denali->mtd.writesize))
1205 denali->mtd.ecc_stats.failed++;
1206 if (!is_erased(buf, denali->mtd.oobsize))
1207 denali->mtd.ecc_stats.failed++;
1208 }
1209 }
1210 return max_bitflips;
1211}
1212
1213static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1214 uint8_t *buf, int oob_required, int page)
1215{
1216 struct denali_nand_info *denali = mtd_to_denali(mtd);
1217
1218 dma_addr_t addr = denali->buf.dma_buf;
1219 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1220
1221 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;
1222
1223 if (page != denali->page) {
1224 dev_err(denali->dev, "IN %s: page %d is not"
1225 " equal to denali->page %d, investigate!!",
1226 __func__, page, denali->page);
1227 BUG();
1228 }
1229
1230 setup_ecc_for_xfer(denali, false, true);
1231 denali_enable_dma(denali, true);
1232
1233 dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
1234
1235 clear_interrupts(denali);
1236 denali_setup_dma(denali, DENALI_READ);
1237
1238 /* wait for operation to complete */
1239 wait_for_irq(denali, irq_mask);
1240
1241 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
1242
1243 denali_enable_dma(denali, false);
1244
1245 memcpy(buf, denali->buf.buf, mtd->writesize);
1246 memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize);
1247
1248 return 0;
1249}
1250
1251static uint8_t denali_read_byte(struct mtd_info *mtd)
1252{
1253 struct denali_nand_info *denali = mtd_to_denali(mtd);
1254 uint8_t result = 0xff;
1255
1256 if (denali->buf.head < denali->buf.tail)
1257 result = denali->buf.buf[denali->buf.head++];
1258
1259 return result;
1260}
1261
1262static void denali_select_chip(struct mtd_info *mtd, int chip)
1263{
1264 struct denali_nand_info *denali = mtd_to_denali(mtd);
1265
1266 spin_lock_irq(&denali->irq_lock);
1267 denali->flash_bank = chip;
1268 spin_unlock_irq(&denali->irq_lock);
1269}
1270
1271static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
1272{
1273 struct denali_nand_info *denali = mtd_to_denali(mtd);
1274 int status = denali->status;
1275 denali->status = 0;
1276
1277 return status;
1278}
1279
1280static int denali_erase(struct mtd_info *mtd, int page)
1281{
1282 struct denali_nand_info *denali = mtd_to_denali(mtd);
1283
1284 uint32_t cmd, irq_status;
1285
1286 clear_interrupts(denali);
1287
1288 /* setup page read request for access type */
1289 cmd = MODE_10 | BANK(denali->flash_bank) | page;
1290 index_addr(denali, cmd, 0x1);
1291
1292 /* wait for erase to complete or failure to occur */
1293 irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |
1294 INTR_STATUS__ERASE_FAIL);
1295
1296 return (irq_status & INTR_STATUS__ERASE_FAIL) ? NAND_STATUS_FAIL : PASS;
1297}
1298
1299static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
1300 int page)
1301{
1302 struct denali_nand_info *denali = mtd_to_denali(mtd);
1303 uint32_t addr, id;
1304 int i;
1305
1306 switch (cmd) {
1307 case NAND_CMD_PAGEPROG:
1308 break;
1309 case NAND_CMD_STATUS:
1310 read_status(denali);
1311 break;
1312 case NAND_CMD_READID:
1313 case NAND_CMD_PARAM:
1314 reset_buf(denali);
1315 /*
1316 * sometimes ManufactureId read from register is not right
1317 * e.g. some of Micron MT29F32G08QAA MLC NAND chips
1318 * So here we send READID cmd to NAND insteand
1319 */
1320 addr = MODE_11 | BANK(denali->flash_bank);
1321 index_addr(denali, addr | 0, 0x90);
1322 index_addr(denali, addr | 1, 0);
1323 for (i = 0; i < 8; i++) {
1324 index_addr_read_data(denali,
1325 addr | 2,
1326 &id);
1327 write_byte_to_buf(denali, id);
1328 }
1329 break;
1330 case NAND_CMD_READ0:
1331 case NAND_CMD_SEQIN:
1332 denali->page = page;
1333 break;
1334 case NAND_CMD_RESET:
1335 reset_bank(denali);
1336 break;
1337 case NAND_CMD_READOOB:
1338 /* TODO: Read OOB data */
1339 break;
1340 default:
1341 pr_err(": unsupported command received 0x%x\n", cmd);
1342 break;
1343 }
1344}
1345
1346/* stubs for ECC functions not used by the NAND core */
1347static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data,
1348 uint8_t *ecc_code)
1349{
1350 struct denali_nand_info *denali = mtd_to_denali(mtd);
1351 dev_err(denali->dev,
1352 "denali_ecc_calculate called unexpectedly\n");
1353 BUG();
1354 return -EIO;
1355}
1356
1357static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data,
1358 uint8_t *read_ecc, uint8_t *calc_ecc)
1359{
1360 struct denali_nand_info *denali = mtd_to_denali(mtd);
1361 dev_err(denali->dev,
1362 "denali_ecc_correct called unexpectedly\n");
1363 BUG();
1364 return -EIO;
1365}
1366
1367static void denali_ecc_hwctl(struct mtd_info *mtd, int mode)
1368{
1369 struct denali_nand_info *denali = mtd_to_denali(mtd);
1370 dev_err(denali->dev,
1371 "denali_ecc_hwctl called unexpectedly\n");
1372 BUG();
1373}
1374/* end NAND core entry points */
1375
1376/* Initialization code to bring the device up to a known good state */
1377static void denali_hw_init(struct denali_nand_info *denali)
1378{
1379 /*
1380 * tell driver how many bit controller will skip before
1381 * writing ECC code in OOB, this register may be already
1382 * set by firmware. So we read this value out.
1383 * if this value is 0, just let it be.
1384 */
1385 denali->bbtskipbytes = ioread32(denali->flash_reg +
1386 SPARE_AREA_SKIP_BYTES);
1387 detect_max_banks(denali);
1388 denali_nand_reset(denali);
1389 iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
1390 iowrite32(CHIP_EN_DONT_CARE__FLAG,
1391 denali->flash_reg + CHIP_ENABLE_DONT_CARE);
1392
1393 iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
1394
1395 /* Should set value for these registers when init */
1396 iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
1397 iowrite32(1, denali->flash_reg + ECC_ENABLE);
1398 denali_nand_timing_set(denali);
1399 denali_irq_init(denali);
1400}
1401
1402/*
1403 * Althogh controller spec said SLC ECC is forceb to be 4bit,
1404 * but denali controller in MRST only support 15bit and 8bit ECC
1405 * correction
1406 */
1407#define ECC_8BITS 14
1408static struct nand_ecclayout nand_8bit_oob = {
1409 .eccbytes = 14,
1410};
1411
1412#define ECC_15BITS 26
1413static struct nand_ecclayout nand_15bit_oob = {
1414 .eccbytes = 26,
1415};
1416
1417static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
1418static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
1419
1420static struct nand_bbt_descr bbt_main_descr = {
1421 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1422 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1423 .offs = 8,
1424 .len = 4,
1425 .veroffs = 12,
1426 .maxblocks = 4,
1427 .pattern = bbt_pattern,
1428};
1429
1430static struct nand_bbt_descr bbt_mirror_descr = {
1431 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1432 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1433 .offs = 8,
1434 .len = 4,
1435 .veroffs = 12,
1436 .maxblocks = 4,
1437 .pattern = mirror_pattern,
1438};
1439
1440/* initialize driver data structures */
1441static void denali_drv_init(struct denali_nand_info *denali)
1442{
1443 denali->idx = 0;
1444
1445 /* setup interrupt handler */
1446 /*
1447 * the completion object will be used to notify
1448 * the callee that the interrupt is done
1449 */
1450 init_completion(&denali->complete);
1451
1452 /*
1453 * the spinlock will be used to synchronize the ISR with any
1454 * element that might be access shared data (interrupt status)
1455 */
1456 spin_lock_init(&denali->irq_lock);
1457
1458 /* indicate that MTD has not selected a valid bank yet */
1459 denali->flash_bank = CHIP_SELECT_INVALID;
1460
1461 /* initialize our irq_status variable to indicate no interrupts */
1462 denali->irq_status = 0;
1463}
1464
1465int denali_init(struct denali_nand_info *denali)
1466{
1467 int ret;
1468
1469 if (denali->platform == INTEL_CE4100) {
1470 /*
1471 * Due to a silicon limitation, we can only support
1472 * ONFI timing mode 1 and below.
1473 */
1474 if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
1475 pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n");
1476 return -EINVAL;
1477 }
1478 }
1479
1480 /* allocate a temporary buffer for nand_scan_ident() */
1481 denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE,
1482 GFP_DMA | GFP_KERNEL);
1483 if (!denali->buf.buf)
1484 return -ENOMEM;
1485
1486 denali->mtd.dev.parent = denali->dev;
1487 denali_hw_init(denali);
1488 denali_drv_init(denali);
1489
1490 /*
1491 * denali_isr register is done after all the hardware
1492 * initilization is finished
1493 */
1494 if (request_irq(denali->irq, denali_isr, IRQF_SHARED,
1495 DENALI_NAND_NAME, denali)) {
1496 pr_err("Spectra: Unable to allocate IRQ\n");
1497 return -ENODEV;
1498 }
1499
1500 /* now that our ISR is registered, we can enable interrupts */
1501 denali_set_intr_modes(denali, true);
1502 denali->mtd.name = "denali-nand";
1503 denali->mtd.owner = THIS_MODULE;
1504 denali->mtd.priv = &denali->nand;
1505
1506 /* register the driver with the NAND core subsystem */
1507 denali->nand.select_chip = denali_select_chip;
1508 denali->nand.cmdfunc = denali_cmdfunc;
1509 denali->nand.read_byte = denali_read_byte;
1510 denali->nand.waitfunc = denali_waitfunc;
1511
1512 /*
1513 * scan for NAND devices attached to the controller
1514 * this is the first stage in a two step process to register
1515 * with the nand subsystem
1516 */
1517 if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) {
1518 ret = -ENXIO;
1519 goto failed_req_irq;
1520 }
1521
1522 /* allocate the right size buffer now */
1523 devm_kfree(denali->dev, denali->buf.buf);
1524 denali->buf.buf = devm_kzalloc(denali->dev,
1525 denali->mtd.writesize + denali->mtd.oobsize,
1526 GFP_KERNEL);
1527 if (!denali->buf.buf) {
1528 ret = -ENOMEM;
1529 goto failed_req_irq;
1530 }
1531
1532 /* Is 32-bit DMA supported? */
1533 ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32));
1534 if (ret) {
1535 pr_err("Spectra: no usable DMA configuration\n");
1536 goto failed_req_irq;
1537 }
1538
1539 denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf,
1540 denali->mtd.writesize + denali->mtd.oobsize,
1541 DMA_BIDIRECTIONAL);
1542 if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) {
1543 dev_err(denali->dev, "Spectra: failed to map DMA buffer\n");
1544 ret = -EIO;
1545 goto failed_req_irq;
1546 }
1547
1548 /*
1549 * support for multi nand
1550 * MTD known nothing about multi nand, so we should tell it
1551 * the real pagesize and anything necessery
1552 */
1553 denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED);
1554 denali->nand.chipsize <<= (denali->devnum - 1);
1555 denali->nand.page_shift += (denali->devnum - 1);
1556 denali->nand.pagemask = (denali->nand.chipsize >>
1557 denali->nand.page_shift) - 1;
1558 denali->nand.bbt_erase_shift += (denali->devnum - 1);
1559 denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift;
1560 denali->nand.chip_shift += (denali->devnum - 1);
1561 denali->mtd.writesize <<= (denali->devnum - 1);
1562 denali->mtd.oobsize <<= (denali->devnum - 1);
1563 denali->mtd.erasesize <<= (denali->devnum - 1);
1564 denali->mtd.size = denali->nand.numchips * denali->nand.chipsize;
1565 denali->bbtskipbytes *= denali->devnum;
1566
1567 /*
1568 * second stage of the NAND scan
1569 * this stage requires information regarding ECC and
1570 * bad block management.
1571 */
1572
1573 /* Bad block management */
1574 denali->nand.bbt_td = &bbt_main_descr;
1575 denali->nand.bbt_md = &bbt_mirror_descr;
1576
1577 /* skip the scan for now until we have OOB read and write support */
1578 denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
1579 denali->nand.options |= NAND_SKIP_BBTSCAN;
1580 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
1581
1582 /*
1583 * Denali Controller only support 15bit and 8bit ECC in MRST,
1584 * so just let controller do 15bit ECC for MLC and 8bit ECC for
1585 * SLC if possible.
1586 * */
1587 if (!nand_is_slc(&denali->nand) &&
1588 (denali->mtd.oobsize > (denali->bbtskipbytes +
1589 ECC_15BITS * (denali->mtd.writesize /
1590 ECC_SECTOR_SIZE)))) {
1591 /* if MLC OOB size is large enough, use 15bit ECC*/
1592 denali->nand.ecc.strength = 15;
1593 denali->nand.ecc.layout = &nand_15bit_oob;
1594 denali->nand.ecc.bytes = ECC_15BITS;
1595 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
1596 } else if (denali->mtd.oobsize < (denali->bbtskipbytes +
1597 ECC_8BITS * (denali->mtd.writesize /
1598 ECC_SECTOR_SIZE))) {
1599 pr_err("Your NAND chip OOB is not large enough to \
1600 contain 8bit ECC correction codes");
1601 goto failed_req_irq;
1602 } else {
1603 denali->nand.ecc.strength = 8;
1604 denali->nand.ecc.layout = &nand_8bit_oob;
1605 denali->nand.ecc.bytes = ECC_8BITS;
1606 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
1607 }
1608
1609 denali->nand.ecc.bytes *= denali->devnum;
1610 denali->nand.ecc.strength *= denali->devnum;
1611 denali->nand.ecc.layout->eccbytes *=
1612 denali->mtd.writesize / ECC_SECTOR_SIZE;
1613 denali->nand.ecc.layout->oobfree[0].offset =
1614 denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes;
1615 denali->nand.ecc.layout->oobfree[0].length =
1616 denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes -
1617 denali->bbtskipbytes;
1618
1619 /*
1620 * Let driver know the total blocks number and how many blocks
1621 * contained by each nand chip. blksperchip will help driver to
1622 * know how many blocks is taken by FW.
1623 */
1624 denali->totalblks = denali->mtd.size >>
1625 denali->nand.phys_erase_shift;
1626 denali->blksperchip = denali->totalblks / denali->nand.numchips;
1627
1628 /*
1629 * These functions are required by the NAND core framework, otherwise,
1630 * the NAND core will assert. However, we don't need them, so we'll stub
1631 * them out.
1632 */
1633 denali->nand.ecc.calculate = denali_ecc_calculate;
1634 denali->nand.ecc.correct = denali_ecc_correct;
1635 denali->nand.ecc.hwctl = denali_ecc_hwctl;
1636
1637 /* override the default read operations */
1638 denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum;
1639 denali->nand.ecc.read_page = denali_read_page;
1640 denali->nand.ecc.read_page_raw = denali_read_page_raw;
1641 denali->nand.ecc.write_page = denali_write_page;
1642 denali->nand.ecc.write_page_raw = denali_write_page_raw;
1643 denali->nand.ecc.read_oob = denali_read_oob;
1644 denali->nand.ecc.write_oob = denali_write_oob;
1645 denali->nand.erase = denali_erase;
1646
1647 if (nand_scan_tail(&denali->mtd)) {
1648 ret = -ENXIO;
1649 goto failed_req_irq;
1650 }
1651
1652 ret = mtd_device_register(&denali->mtd, NULL, 0);
1653 if (ret) {
1654 dev_err(denali->dev, "Spectra: Failed to register MTD: %d\n",
1655 ret);
1656 goto failed_req_irq;
1657 }
1658 return 0;
1659
1660failed_req_irq:
1661 denali_irq_cleanup(denali->irq, denali);
1662
1663 return ret;
1664}
1665EXPORT_SYMBOL(denali_init);
1666
1667/* driver exit point */
1668void denali_remove(struct denali_nand_info *denali)
1669{
1670 denali_irq_cleanup(denali->irq, denali);
1671 dma_unmap_single(denali->dev, denali->buf.dma_buf,
1672 denali->mtd.writesize + denali->mtd.oobsize,
1673 DMA_BIDIRECTIONAL);
1674}
1675EXPORT_SYMBOL(denali_remove);
Linux kernel - Deliverables
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