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mxs-dma : rewrite the last parameter of mxs_dma_prep_slave_sg()
[deliverable/linux.git] / drivers / mtd / nand / nand_base.c
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1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
8 *
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
11 *
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
14 *
15 * Credits:
16 * David Woodhouse for adding multichip support
17 *
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
21 * TODO:
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ECC support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
28 *
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
35#include <linux/module.h>
36#include <linux/delay.h>
37#include <linux/errno.h>
38#include <linux/err.h>
39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
42#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h>
44#include <linux/mtd/nand_ecc.h>
45#include <linux/mtd/nand_bch.h>
46#include <linux/interrupt.h>
47#include <linux/bitops.h>
48#include <linux/leds.h>
49#include <linux/io.h>
50#include <linux/mtd/partitions.h>
51
52/* Define default oob placement schemes for large and small page devices */
53static struct nand_ecclayout nand_oob_8 = {
54 .eccbytes = 3,
55 .eccpos = {0, 1, 2},
56 .oobfree = {
57 {.offset = 3,
58 .length = 2},
59 {.offset = 6,
60 .length = 2} }
61};
62
63static struct nand_ecclayout nand_oob_16 = {
64 .eccbytes = 6,
65 .eccpos = {0, 1, 2, 3, 6, 7},
66 .oobfree = {
67 {.offset = 8,
68 . length = 8} }
69};
70
71static struct nand_ecclayout nand_oob_64 = {
72 .eccbytes = 24,
73 .eccpos = {
74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
77 .oobfree = {
78 {.offset = 2,
79 .length = 38} }
80};
81
82static struct nand_ecclayout nand_oob_128 = {
83 .eccbytes = 48,
84 .eccpos = {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
91 .oobfree = {
92 {.offset = 2,
93 .length = 78} }
94};
95
96static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
97 int new_state);
98
99static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
100 struct mtd_oob_ops *ops);
101
102/*
103 * For devices which display every fart in the system on a separate LED. Is
104 * compiled away when LED support is disabled.
105 */
106DEFINE_LED_TRIGGER(nand_led_trigger);
107
108static int check_offs_len(struct mtd_info *mtd,
109 loff_t ofs, uint64_t len)
110{
111 struct nand_chip *chip = mtd->priv;
112 int ret = 0;
113
114 /* Start address must align on block boundary */
115 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
116 pr_debug("%s: unaligned address\n", __func__);
117 ret = -EINVAL;
118 }
119
120 /* Length must align on block boundary */
121 if (len & ((1 << chip->phys_erase_shift) - 1)) {
122 pr_debug("%s: length not block aligned\n", __func__);
123 ret = -EINVAL;
124 }
125
126 return ret;
127}
128
129/**
130 * nand_release_device - [GENERIC] release chip
131 * @mtd: MTD device structure
132 *
133 * Deselect, release chip lock and wake up anyone waiting on the device.
134 */
135static void nand_release_device(struct mtd_info *mtd)
136{
137 struct nand_chip *chip = mtd->priv;
138
139 /* De-select the NAND device */
140 chip->select_chip(mtd, -1);
141
142 /* Release the controller and the chip */
143 spin_lock(&chip->controller->lock);
144 chip->controller->active = NULL;
145 chip->state = FL_READY;
146 wake_up(&chip->controller->wq);
147 spin_unlock(&chip->controller->lock);
148}
149
150/**
151 * nand_read_byte - [DEFAULT] read one byte from the chip
152 * @mtd: MTD device structure
153 *
154 * Default read function for 8bit buswidth
155 */
156static uint8_t nand_read_byte(struct mtd_info *mtd)
157{
158 struct nand_chip *chip = mtd->priv;
159 return readb(chip->IO_ADDR_R);
160}
161
162/**
163 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
164 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
165 * @mtd: MTD device structure
166 *
167 * Default read function for 16bit buswidth with endianness conversion.
168 *
169 */
170static uint8_t nand_read_byte16(struct mtd_info *mtd)
171{
172 struct nand_chip *chip = mtd->priv;
173 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
174}
175
176/**
177 * nand_read_word - [DEFAULT] read one word from the chip
178 * @mtd: MTD device structure
179 *
180 * Default read function for 16bit buswidth without endianness conversion.
181 */
182static u16 nand_read_word(struct mtd_info *mtd)
183{
184 struct nand_chip *chip = mtd->priv;
185 return readw(chip->IO_ADDR_R);
186}
187
188/**
189 * nand_select_chip - [DEFAULT] control CE line
190 * @mtd: MTD device structure
191 * @chipnr: chipnumber to select, -1 for deselect
192 *
193 * Default select function for 1 chip devices.
194 */
195static void nand_select_chip(struct mtd_info *mtd, int chipnr)
196{
197 struct nand_chip *chip = mtd->priv;
198
199 switch (chipnr) {
200 case -1:
201 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
202 break;
203 case 0:
204 break;
205
206 default:
207 BUG();
208 }
209}
210
211/**
212 * nand_write_buf - [DEFAULT] write buffer to chip
213 * @mtd: MTD device structure
214 * @buf: data buffer
215 * @len: number of bytes to write
216 *
217 * Default write function for 8bit buswidth.
218 */
219static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
220{
221 int i;
222 struct nand_chip *chip = mtd->priv;
223
224 for (i = 0; i < len; i++)
225 writeb(buf[i], chip->IO_ADDR_W);
226}
227
228/**
229 * nand_read_buf - [DEFAULT] read chip data into buffer
230 * @mtd: MTD device structure
231 * @buf: buffer to store date
232 * @len: number of bytes to read
233 *
234 * Default read function for 8bit buswidth.
235 */
236static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
237{
238 int i;
239 struct nand_chip *chip = mtd->priv;
240
241 for (i = 0; i < len; i++)
242 buf[i] = readb(chip->IO_ADDR_R);
243}
244
245/**
246 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
247 * @mtd: MTD device structure
248 * @buf: buffer containing the data to compare
249 * @len: number of bytes to compare
250 *
251 * Default verify function for 8bit buswidth.
252 */
253static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
254{
255 int i;
256 struct nand_chip *chip = mtd->priv;
257
258 for (i = 0; i < len; i++)
259 if (buf[i] != readb(chip->IO_ADDR_R))
260 return -EFAULT;
261 return 0;
262}
263
264/**
265 * nand_write_buf16 - [DEFAULT] write buffer to chip
266 * @mtd: MTD device structure
267 * @buf: data buffer
268 * @len: number of bytes to write
269 *
270 * Default write function for 16bit buswidth.
271 */
272static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
273{
274 int i;
275 struct nand_chip *chip = mtd->priv;
276 u16 *p = (u16 *) buf;
277 len >>= 1;
278
279 for (i = 0; i < len; i++)
280 writew(p[i], chip->IO_ADDR_W);
281
282}
283
284/**
285 * nand_read_buf16 - [DEFAULT] read chip data into buffer
286 * @mtd: MTD device structure
287 * @buf: buffer to store date
288 * @len: number of bytes to read
289 *
290 * Default read function for 16bit buswidth.
291 */
292static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
293{
294 int i;
295 struct nand_chip *chip = mtd->priv;
296 u16 *p = (u16 *) buf;
297 len >>= 1;
298
299 for (i = 0; i < len; i++)
300 p[i] = readw(chip->IO_ADDR_R);
301}
302
303/**
304 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
305 * @mtd: MTD device structure
306 * @buf: buffer containing the data to compare
307 * @len: number of bytes to compare
308 *
309 * Default verify function for 16bit buswidth.
310 */
311static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
312{
313 int i;
314 struct nand_chip *chip = mtd->priv;
315 u16 *p = (u16 *) buf;
316 len >>= 1;
317
318 for (i = 0; i < len; i++)
319 if (p[i] != readw(chip->IO_ADDR_R))
320 return -EFAULT;
321
322 return 0;
323}
324
325/**
326 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
327 * @mtd: MTD device structure
328 * @ofs: offset from device start
329 * @getchip: 0, if the chip is already selected
330 *
331 * Check, if the block is bad.
332 */
333static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
334{
335 int page, chipnr, res = 0, i = 0;
336 struct nand_chip *chip = mtd->priv;
337 u16 bad;
338
339 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
340 ofs += mtd->erasesize - mtd->writesize;
341
342 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
343
344 if (getchip) {
345 chipnr = (int)(ofs >> chip->chip_shift);
346
347 nand_get_device(chip, mtd, FL_READING);
348
349 /* Select the NAND device */
350 chip->select_chip(mtd, chipnr);
351 }
352
353 do {
354 if (chip->options & NAND_BUSWIDTH_16) {
355 chip->cmdfunc(mtd, NAND_CMD_READOOB,
356 chip->badblockpos & 0xFE, page);
357 bad = cpu_to_le16(chip->read_word(mtd));
358 if (chip->badblockpos & 0x1)
359 bad >>= 8;
360 else
361 bad &= 0xFF;
362 } else {
363 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
364 page);
365 bad = chip->read_byte(mtd);
366 }
367
368 if (likely(chip->badblockbits == 8))
369 res = bad != 0xFF;
370 else
371 res = hweight8(bad) < chip->badblockbits;
372 ofs += mtd->writesize;
373 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
374 i++;
375 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
376
377 if (getchip)
378 nand_release_device(mtd);
379
380 return res;
381}
382
383/**
384 * nand_default_block_markbad - [DEFAULT] mark a block bad
385 * @mtd: MTD device structure
386 * @ofs: offset from device start
387 *
388 * This is the default implementation, which can be overridden by a hardware
389 * specific driver. We try operations in the following order, according to our
390 * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
391 * (1) erase the affected block, to allow OOB marker to be written cleanly
392 * (2) update in-memory BBT
393 * (3) write bad block marker to OOB area of affected block
394 * (4) update flash-based BBT
395 * Note that we retain the first error encountered in (3) or (4), finish the
396 * procedures, and dump the error in the end.
397*/
398static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
399{
400 struct nand_chip *chip = mtd->priv;
401 uint8_t buf[2] = { 0, 0 };
402 int block, res, ret = 0, i = 0;
403 int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
404
405 if (write_oob) {
406 struct erase_info einfo;
407
408 /* Attempt erase before marking OOB */
409 memset(&einfo, 0, sizeof(einfo));
410 einfo.mtd = mtd;
411 einfo.addr = ofs;
412 einfo.len = 1 << chip->phys_erase_shift;
413 nand_erase_nand(mtd, &einfo, 0);
414 }
415
416 /* Get block number */
417 block = (int)(ofs >> chip->bbt_erase_shift);
418 /* Mark block bad in memory-based BBT */
419 if (chip->bbt)
420 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
421
422 /* Write bad block marker to OOB */
423 if (write_oob) {
424 struct mtd_oob_ops ops;
425 loff_t wr_ofs = ofs;
426
427 nand_get_device(chip, mtd, FL_WRITING);
428
429 ops.datbuf = NULL;
430 ops.oobbuf = buf;
431 ops.ooboffs = chip->badblockpos;
432 if (chip->options & NAND_BUSWIDTH_16) {
433 ops.ooboffs &= ~0x01;
434 ops.len = ops.ooblen = 2;
435 } else {
436 ops.len = ops.ooblen = 1;
437 }
438 ops.mode = MTD_OPS_PLACE_OOB;
439
440 /* Write to first/last page(s) if necessary */
441 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
442 wr_ofs += mtd->erasesize - mtd->writesize;
443 do {
444 res = nand_do_write_oob(mtd, wr_ofs, &ops);
445 if (!ret)
446 ret = res;
447
448 i++;
449 wr_ofs += mtd->writesize;
450 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
451
452 nand_release_device(mtd);
453 }
454
455 /* Update flash-based bad block table */
456 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
457 res = nand_update_bbt(mtd, ofs);
458 if (!ret)
459 ret = res;
460 }
461
462 if (!ret)
463 mtd->ecc_stats.badblocks++;
464
465 return ret;
466}
467
468/**
469 * nand_check_wp - [GENERIC] check if the chip is write protected
470 * @mtd: MTD device structure
471 *
472 * Check, if the device is write protected. The function expects, that the
473 * device is already selected.
474 */
475static int nand_check_wp(struct mtd_info *mtd)
476{
477 struct nand_chip *chip = mtd->priv;
478
479 /* Broken xD cards report WP despite being writable */
480 if (chip->options & NAND_BROKEN_XD)
481 return 0;
482
483 /* Check the WP bit */
484 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
485 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
486}
487
488/**
489 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
490 * @mtd: MTD device structure
491 * @ofs: offset from device start
492 * @getchip: 0, if the chip is already selected
493 * @allowbbt: 1, if its allowed to access the bbt area
494 *
495 * Check, if the block is bad. Either by reading the bad block table or
496 * calling of the scan function.
497 */
498static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
499 int allowbbt)
500{
501 struct nand_chip *chip = mtd->priv;
502
503 if (!chip->bbt)
504 return chip->block_bad(mtd, ofs, getchip);
505
506 /* Return info from the table */
507 return nand_isbad_bbt(mtd, ofs, allowbbt);
508}
509
510/**
511 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
512 * @mtd: MTD device structure
513 * @timeo: Timeout
514 *
515 * Helper function for nand_wait_ready used when needing to wait in interrupt
516 * context.
517 */
518static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
519{
520 struct nand_chip *chip = mtd->priv;
521 int i;
522
523 /* Wait for the device to get ready */
524 for (i = 0; i < timeo; i++) {
525 if (chip->dev_ready(mtd))
526 break;
527 touch_softlockup_watchdog();
528 mdelay(1);
529 }
530}
531
532/* Wait for the ready pin, after a command. The timeout is caught later. */
533void nand_wait_ready(struct mtd_info *mtd)
534{
535 struct nand_chip *chip = mtd->priv;
536 unsigned long timeo = jiffies + 2;
537
538 /* 400ms timeout */
539 if (in_interrupt() || oops_in_progress)
540 return panic_nand_wait_ready(mtd, 400);
541
542 led_trigger_event(nand_led_trigger, LED_FULL);
543 /* Wait until command is processed or timeout occurs */
544 do {
545 if (chip->dev_ready(mtd))
546 break;
547 touch_softlockup_watchdog();
548 } while (time_before(jiffies, timeo));
549 led_trigger_event(nand_led_trigger, LED_OFF);
550}
551EXPORT_SYMBOL_GPL(nand_wait_ready);
552
553/**
554 * nand_command - [DEFAULT] Send command to NAND device
555 * @mtd: MTD device structure
556 * @command: the command to be sent
557 * @column: the column address for this command, -1 if none
558 * @page_addr: the page address for this command, -1 if none
559 *
560 * Send command to NAND device. This function is used for small page devices
561 * (256/512 Bytes per page).
562 */
563static void nand_command(struct mtd_info *mtd, unsigned int command,
564 int column, int page_addr)
565{
566 register struct nand_chip *chip = mtd->priv;
567 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
568
569 /* Write out the command to the device */
570 if (command == NAND_CMD_SEQIN) {
571 int readcmd;
572
573 if (column >= mtd->writesize) {
574 /* OOB area */
575 column -= mtd->writesize;
576 readcmd = NAND_CMD_READOOB;
577 } else if (column < 256) {
578 /* First 256 bytes --> READ0 */
579 readcmd = NAND_CMD_READ0;
580 } else {
581 column -= 256;
582 readcmd = NAND_CMD_READ1;
583 }
584 chip->cmd_ctrl(mtd, readcmd, ctrl);
585 ctrl &= ~NAND_CTRL_CHANGE;
586 }
587 chip->cmd_ctrl(mtd, command, ctrl);
588
589 /* Address cycle, when necessary */
590 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
591 /* Serially input address */
592 if (column != -1) {
593 /* Adjust columns for 16 bit buswidth */
594 if (chip->options & NAND_BUSWIDTH_16)
595 column >>= 1;
596 chip->cmd_ctrl(mtd, column, ctrl);
597 ctrl &= ~NAND_CTRL_CHANGE;
598 }
599 if (page_addr != -1) {
600 chip->cmd_ctrl(mtd, page_addr, ctrl);
601 ctrl &= ~NAND_CTRL_CHANGE;
602 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
603 /* One more address cycle for devices > 32MiB */
604 if (chip->chipsize > (32 << 20))
605 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
606 }
607 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
608
609 /*
610 * Program and erase have their own busy handlers status and sequential
611 * in needs no delay
612 */
613 switch (command) {
614
615 case NAND_CMD_PAGEPROG:
616 case NAND_CMD_ERASE1:
617 case NAND_CMD_ERASE2:
618 case NAND_CMD_SEQIN:
619 case NAND_CMD_STATUS:
620 return;
621
622 case NAND_CMD_RESET:
623 if (chip->dev_ready)
624 break;
625 udelay(chip->chip_delay);
626 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
627 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
628 chip->cmd_ctrl(mtd,
629 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
630 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
631 ;
632 return;
633
634 /* This applies to read commands */
635 default:
636 /*
637 * If we don't have access to the busy pin, we apply the given
638 * command delay
639 */
640 if (!chip->dev_ready) {
641 udelay(chip->chip_delay);
642 return;
643 }
644 }
645 /*
646 * Apply this short delay always to ensure that we do wait tWB in
647 * any case on any machine.
648 */
649 ndelay(100);
650
651 nand_wait_ready(mtd);
652}
653
654/**
655 * nand_command_lp - [DEFAULT] Send command to NAND large page device
656 * @mtd: MTD device structure
657 * @command: the command to be sent
658 * @column: the column address for this command, -1 if none
659 * @page_addr: the page address for this command, -1 if none
660 *
661 * Send command to NAND device. This is the version for the new large page
662 * devices. We don't have the separate regions as we have in the small page
663 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
664 */
665static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
666 int column, int page_addr)
667{
668 register struct nand_chip *chip = mtd->priv;
669
670 /* Emulate NAND_CMD_READOOB */
671 if (command == NAND_CMD_READOOB) {
672 column += mtd->writesize;
673 command = NAND_CMD_READ0;
674 }
675
676 /* Command latch cycle */
677 chip->cmd_ctrl(mtd, command & 0xff,
678 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
679
680 if (column != -1 || page_addr != -1) {
681 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
682
683 /* Serially input address */
684 if (column != -1) {
685 /* Adjust columns for 16 bit buswidth */
686 if (chip->options & NAND_BUSWIDTH_16)
687 column >>= 1;
688 chip->cmd_ctrl(mtd, column, ctrl);
689 ctrl &= ~NAND_CTRL_CHANGE;
690 chip->cmd_ctrl(mtd, column >> 8, ctrl);
691 }
692 if (page_addr != -1) {
693 chip->cmd_ctrl(mtd, page_addr, ctrl);
694 chip->cmd_ctrl(mtd, page_addr >> 8,
695 NAND_NCE | NAND_ALE);
696 /* One more address cycle for devices > 128MiB */
697 if (chip->chipsize > (128 << 20))
698 chip->cmd_ctrl(mtd, page_addr >> 16,
699 NAND_NCE | NAND_ALE);
700 }
701 }
702 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
703
704 /*
705 * Program and erase have their own busy handlers status, sequential
706 * in, and deplete1 need no delay.
707 */
708 switch (command) {
709
710 case NAND_CMD_CACHEDPROG:
711 case NAND_CMD_PAGEPROG:
712 case NAND_CMD_ERASE1:
713 case NAND_CMD_ERASE2:
714 case NAND_CMD_SEQIN:
715 case NAND_CMD_RNDIN:
716 case NAND_CMD_STATUS:
717 case NAND_CMD_DEPLETE1:
718 return;
719
720 case NAND_CMD_STATUS_ERROR:
721 case NAND_CMD_STATUS_ERROR0:
722 case NAND_CMD_STATUS_ERROR1:
723 case NAND_CMD_STATUS_ERROR2:
724 case NAND_CMD_STATUS_ERROR3:
725 /* Read error status commands require only a short delay */
726 udelay(chip->chip_delay);
727 return;
728
729 case NAND_CMD_RESET:
730 if (chip->dev_ready)
731 break;
732 udelay(chip->chip_delay);
733 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
734 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
735 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
736 NAND_NCE | NAND_CTRL_CHANGE);
737 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
738 ;
739 return;
740
741 case NAND_CMD_RNDOUT:
742 /* No ready / busy check necessary */
743 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
744 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
745 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
746 NAND_NCE | NAND_CTRL_CHANGE);
747 return;
748
749 case NAND_CMD_READ0:
750 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
751 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
752 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
753 NAND_NCE | NAND_CTRL_CHANGE);
754
755 /* This applies to read commands */
756 default:
757 /*
758 * If we don't have access to the busy pin, we apply the given
759 * command delay.
760 */
761 if (!chip->dev_ready) {
762 udelay(chip->chip_delay);
763 return;
764 }
765 }
766
767 /*
768 * Apply this short delay always to ensure that we do wait tWB in
769 * any case on any machine.
770 */
771 ndelay(100);
772
773 nand_wait_ready(mtd);
774}
775
776/**
777 * panic_nand_get_device - [GENERIC] Get chip for selected access
778 * @chip: the nand chip descriptor
779 * @mtd: MTD device structure
780 * @new_state: the state which is requested
781 *
782 * Used when in panic, no locks are taken.
783 */
784static void panic_nand_get_device(struct nand_chip *chip,
785 struct mtd_info *mtd, int new_state)
786{
787 /* Hardware controller shared among independent devices */
788 chip->controller->active = chip;
789 chip->state = new_state;
790}
791
792/**
793 * nand_get_device - [GENERIC] Get chip for selected access
794 * @chip: the nand chip descriptor
795 * @mtd: MTD device structure
796 * @new_state: the state which is requested
797 *
798 * Get the device and lock it for exclusive access
799 */
800static int
801nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
802{
803 spinlock_t *lock = &chip->controller->lock;
804 wait_queue_head_t *wq = &chip->controller->wq;
805 DECLARE_WAITQUEUE(wait, current);
806retry:
807 spin_lock(lock);
808
809 /* Hardware controller shared among independent devices */
810 if (!chip->controller->active)
811 chip->controller->active = chip;
812
813 if (chip->controller->active == chip && chip->state == FL_READY) {
814 chip->state = new_state;
815 spin_unlock(lock);
816 return 0;
817 }
818 if (new_state == FL_PM_SUSPENDED) {
819 if (chip->controller->active->state == FL_PM_SUSPENDED) {
820 chip->state = FL_PM_SUSPENDED;
821 spin_unlock(lock);
822 return 0;
823 }
824 }
825 set_current_state(TASK_UNINTERRUPTIBLE);
826 add_wait_queue(wq, &wait);
827 spin_unlock(lock);
828 schedule();
829 remove_wait_queue(wq, &wait);
830 goto retry;
831}
832
833/**
834 * panic_nand_wait - [GENERIC] wait until the command is done
835 * @mtd: MTD device structure
836 * @chip: NAND chip structure
837 * @timeo: timeout
838 *
839 * Wait for command done. This is a helper function for nand_wait used when
840 * we are in interrupt context. May happen when in panic and trying to write
841 * an oops through mtdoops.
842 */
843static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
844 unsigned long timeo)
845{
846 int i;
847 for (i = 0; i < timeo; i++) {
848 if (chip->dev_ready) {
849 if (chip->dev_ready(mtd))
850 break;
851 } else {
852 if (chip->read_byte(mtd) & NAND_STATUS_READY)
853 break;
854 }
855 mdelay(1);
856 }
857}
858
859/**
860 * nand_wait - [DEFAULT] wait until the command is done
861 * @mtd: MTD device structure
862 * @chip: NAND chip structure
863 *
864 * Wait for command done. This applies to erase and program only. Erase can
865 * take up to 400ms and program up to 20ms according to general NAND and
866 * SmartMedia specs.
867 */
868static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
869{
870
871 unsigned long timeo = jiffies;
872 int status, state = chip->state;
873
874 if (state == FL_ERASING)
875 timeo += (HZ * 400) / 1000;
876 else
877 timeo += (HZ * 20) / 1000;
878
879 led_trigger_event(nand_led_trigger, LED_FULL);
880
881 /*
882 * Apply this short delay always to ensure that we do wait tWB in any
883 * case on any machine.
884 */
885 ndelay(100);
886
887 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
888 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
889 else
890 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
891
892 if (in_interrupt() || oops_in_progress)
893 panic_nand_wait(mtd, chip, timeo);
894 else {
895 while (time_before(jiffies, timeo)) {
896 if (chip->dev_ready) {
897 if (chip->dev_ready(mtd))
898 break;
899 } else {
900 if (chip->read_byte(mtd) & NAND_STATUS_READY)
901 break;
902 }
903 cond_resched();
904 }
905 }
906 led_trigger_event(nand_led_trigger, LED_OFF);
907
908 status = (int)chip->read_byte(mtd);
909 return status;
910}
911
912/**
913 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
914 * @mtd: mtd info
915 * @ofs: offset to start unlock from
916 * @len: length to unlock
917 * @invert: when = 0, unlock the range of blocks within the lower and
918 * upper boundary address
919 * when = 1, unlock the range of blocks outside the boundaries
920 * of the lower and upper boundary address
921 *
922 * Returs unlock status.
923 */
924static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
925 uint64_t len, int invert)
926{
927 int ret = 0;
928 int status, page;
929 struct nand_chip *chip = mtd->priv;
930
931 /* Submit address of first page to unlock */
932 page = ofs >> chip->page_shift;
933 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
934
935 /* Submit address of last page to unlock */
936 page = (ofs + len) >> chip->page_shift;
937 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
938 (page | invert) & chip->pagemask);
939
940 /* Call wait ready function */
941 status = chip->waitfunc(mtd, chip);
942 /* See if device thinks it succeeded */
943 if (status & 0x01) {
944 pr_debug("%s: error status = 0x%08x\n",
945 __func__, status);
946 ret = -EIO;
947 }
948
949 return ret;
950}
951
952/**
953 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
954 * @mtd: mtd info
955 * @ofs: offset to start unlock from
956 * @len: length to unlock
957 *
958 * Returns unlock status.
959 */
960int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
961{
962 int ret = 0;
963 int chipnr;
964 struct nand_chip *chip = mtd->priv;
965
966 pr_debug("%s: start = 0x%012llx, len = %llu\n",
967 __func__, (unsigned long long)ofs, len);
968
969 if (check_offs_len(mtd, ofs, len))
970 ret = -EINVAL;
971
972 /* Align to last block address if size addresses end of the device */
973 if (ofs + len == mtd->size)
974 len -= mtd->erasesize;
975
976 nand_get_device(chip, mtd, FL_UNLOCKING);
977
978 /* Shift to get chip number */
979 chipnr = ofs >> chip->chip_shift;
980
981 chip->select_chip(mtd, chipnr);
982
983 /* Check, if it is write protected */
984 if (nand_check_wp(mtd)) {
985 pr_debug("%s: device is write protected!\n",
986 __func__);
987 ret = -EIO;
988 goto out;
989 }
990
991 ret = __nand_unlock(mtd, ofs, len, 0);
992
993out:
994 nand_release_device(mtd);
995
996 return ret;
997}
998EXPORT_SYMBOL(nand_unlock);
999
1000/**
1001 * nand_lock - [REPLACEABLE] locks all blocks present in the device
1002 * @mtd: mtd info
1003 * @ofs: offset to start unlock from
1004 * @len: length to unlock
1005 *
1006 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1007 * have this feature, but it allows only to lock all blocks, not for specified
1008 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1009 * now.
1010 *
1011 * Returns lock status.
1012 */
1013int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1014{
1015 int ret = 0;
1016 int chipnr, status, page;
1017 struct nand_chip *chip = mtd->priv;
1018
1019 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1020 __func__, (unsigned long long)ofs, len);
1021
1022 if (check_offs_len(mtd, ofs, len))
1023 ret = -EINVAL;
1024
1025 nand_get_device(chip, mtd, FL_LOCKING);
1026
1027 /* Shift to get chip number */
1028 chipnr = ofs >> chip->chip_shift;
1029
1030 chip->select_chip(mtd, chipnr);
1031
1032 /* Check, if it is write protected */
1033 if (nand_check_wp(mtd)) {
1034 pr_debug("%s: device is write protected!\n",
1035 __func__);
1036 status = MTD_ERASE_FAILED;
1037 ret = -EIO;
1038 goto out;
1039 }
1040
1041 /* Submit address of first page to lock */
1042 page = ofs >> chip->page_shift;
1043 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1044
1045 /* Call wait ready function */
1046 status = chip->waitfunc(mtd, chip);
1047 /* See if device thinks it succeeded */
1048 if (status & 0x01) {
1049 pr_debug("%s: error status = 0x%08x\n",
1050 __func__, status);
1051 ret = -EIO;
1052 goto out;
1053 }
1054
1055 ret = __nand_unlock(mtd, ofs, len, 0x1);
1056
1057out:
1058 nand_release_device(mtd);
1059
1060 return ret;
1061}
1062EXPORT_SYMBOL(nand_lock);
1063
1064/**
1065 * nand_read_page_raw - [INTERN] read raw page data without ecc
1066 * @mtd: mtd info structure
1067 * @chip: nand chip info structure
1068 * @buf: buffer to store read data
1069 * @page: page number to read
1070 *
1071 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1072 */
1073static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1074 uint8_t *buf, int page)
1075{
1076 chip->read_buf(mtd, buf, mtd->writesize);
1077 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1078 return 0;
1079}
1080
1081/**
1082 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1083 * @mtd: mtd info structure
1084 * @chip: nand chip info structure
1085 * @buf: buffer to store read data
1086 * @page: page number to read
1087 *
1088 * We need a special oob layout and handling even when OOB isn't used.
1089 */
1090static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1091 struct nand_chip *chip,
1092 uint8_t *buf, int page)
1093{
1094 int eccsize = chip->ecc.size;
1095 int eccbytes = chip->ecc.bytes;
1096 uint8_t *oob = chip->oob_poi;
1097 int steps, size;
1098
1099 for (steps = chip->ecc.steps; steps > 0; steps--) {
1100 chip->read_buf(mtd, buf, eccsize);
1101 buf += eccsize;
1102
1103 if (chip->ecc.prepad) {
1104 chip->read_buf(mtd, oob, chip->ecc.prepad);
1105 oob += chip->ecc.prepad;
1106 }
1107
1108 chip->read_buf(mtd, oob, eccbytes);
1109 oob += eccbytes;
1110
1111 if (chip->ecc.postpad) {
1112 chip->read_buf(mtd, oob, chip->ecc.postpad);
1113 oob += chip->ecc.postpad;
1114 }
1115 }
1116
1117 size = mtd->oobsize - (oob - chip->oob_poi);
1118 if (size)
1119 chip->read_buf(mtd, oob, size);
1120
1121 return 0;
1122}
1123
1124/**
1125 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1126 * @mtd: mtd info structure
1127 * @chip: nand chip info structure
1128 * @buf: buffer to store read data
1129 * @page: page number to read
1130 */
1131static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1132 uint8_t *buf, int page)
1133{
1134 int i, eccsize = chip->ecc.size;
1135 int eccbytes = chip->ecc.bytes;
1136 int eccsteps = chip->ecc.steps;
1137 uint8_t *p = buf;
1138 uint8_t *ecc_calc = chip->buffers->ecccalc;
1139 uint8_t *ecc_code = chip->buffers->ecccode;
1140 uint32_t *eccpos = chip->ecc.layout->eccpos;
1141
1142 chip->ecc.read_page_raw(mtd, chip, buf, page);
1143
1144 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1145 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1146
1147 for (i = 0; i < chip->ecc.total; i++)
1148 ecc_code[i] = chip->oob_poi[eccpos[i]];
1149
1150 eccsteps = chip->ecc.steps;
1151 p = buf;
1152
1153 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1154 int stat;
1155
1156 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1157 if (stat < 0)
1158 mtd->ecc_stats.failed++;
1159 else
1160 mtd->ecc_stats.corrected += stat;
1161 }
1162 return 0;
1163}
1164
1165/**
1166 * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
1167 * @mtd: mtd info structure
1168 * @chip: nand chip info structure
1169 * @data_offs: offset of requested data within the page
1170 * @readlen: data length
1171 * @bufpoi: buffer to store read data
1172 */
1173static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1174 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1175{
1176 int start_step, end_step, num_steps;
1177 uint32_t *eccpos = chip->ecc.layout->eccpos;
1178 uint8_t *p;
1179 int data_col_addr, i, gaps = 0;
1180 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1181 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1182 int index = 0;
1183
1184 /* Column address within the page aligned to ECC size (256bytes) */
1185 start_step = data_offs / chip->ecc.size;
1186 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1187 num_steps = end_step - start_step + 1;
1188
1189 /* Data size aligned to ECC ecc.size */
1190 datafrag_len = num_steps * chip->ecc.size;
1191 eccfrag_len = num_steps * chip->ecc.bytes;
1192
1193 data_col_addr = start_step * chip->ecc.size;
1194 /* If we read not a page aligned data */
1195 if (data_col_addr != 0)
1196 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1197
1198 p = bufpoi + data_col_addr;
1199 chip->read_buf(mtd, p, datafrag_len);
1200
1201 /* Calculate ECC */
1202 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1203 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1204
1205 /*
1206 * The performance is faster if we position offsets according to
1207 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1208 */
1209 for (i = 0; i < eccfrag_len - 1; i++) {
1210 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1211 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1212 gaps = 1;
1213 break;
1214 }
1215 }
1216 if (gaps) {
1217 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1218 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1219 } else {
1220 /*
1221 * Send the command to read the particular ECC bytes take care
1222 * about buswidth alignment in read_buf.
1223 */
1224 index = start_step * chip->ecc.bytes;
1225
1226 aligned_pos = eccpos[index] & ~(busw - 1);
1227 aligned_len = eccfrag_len;
1228 if (eccpos[index] & (busw - 1))
1229 aligned_len++;
1230 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1231 aligned_len++;
1232
1233 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1234 mtd->writesize + aligned_pos, -1);
1235 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1236 }
1237
1238 for (i = 0; i < eccfrag_len; i++)
1239 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1240
1241 p = bufpoi + data_col_addr;
1242 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1243 int stat;
1244
1245 stat = chip->ecc.correct(mtd, p,
1246 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1247 if (stat < 0)
1248 mtd->ecc_stats.failed++;
1249 else
1250 mtd->ecc_stats.corrected += stat;
1251 }
1252 return 0;
1253}
1254
1255/**
1256 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1257 * @mtd: mtd info structure
1258 * @chip: nand chip info structure
1259 * @buf: buffer to store read data
1260 * @page: page number to read
1261 *
1262 * Not for syndrome calculating ECC controllers which need a special oob layout.
1263 */
1264static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1265 uint8_t *buf, int page)
1266{
1267 int i, eccsize = chip->ecc.size;
1268 int eccbytes = chip->ecc.bytes;
1269 int eccsteps = chip->ecc.steps;
1270 uint8_t *p = buf;
1271 uint8_t *ecc_calc = chip->buffers->ecccalc;
1272 uint8_t *ecc_code = chip->buffers->ecccode;
1273 uint32_t *eccpos = chip->ecc.layout->eccpos;
1274
1275 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1276 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1277 chip->read_buf(mtd, p, eccsize);
1278 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1279 }
1280 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1281
1282 for (i = 0; i < chip->ecc.total; i++)
1283 ecc_code[i] = chip->oob_poi[eccpos[i]];
1284
1285 eccsteps = chip->ecc.steps;
1286 p = buf;
1287
1288 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1289 int stat;
1290
1291 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1292 if (stat < 0)
1293 mtd->ecc_stats.failed++;
1294 else
1295 mtd->ecc_stats.corrected += stat;
1296 }
1297 return 0;
1298}
1299
1300/**
1301 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1302 * @mtd: mtd info structure
1303 * @chip: nand chip info structure
1304 * @buf: buffer to store read data
1305 * @page: page number to read
1306 *
1307 * Hardware ECC for large page chips, require OOB to be read first. For this
1308 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1309 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1310 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1311 * the data area, by overwriting the NAND manufacturer bad block markings.
1312 */
1313static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1314 struct nand_chip *chip, uint8_t *buf, int page)
1315{
1316 int i, eccsize = chip->ecc.size;
1317 int eccbytes = chip->ecc.bytes;
1318 int eccsteps = chip->ecc.steps;
1319 uint8_t *p = buf;
1320 uint8_t *ecc_code = chip->buffers->ecccode;
1321 uint32_t *eccpos = chip->ecc.layout->eccpos;
1322 uint8_t *ecc_calc = chip->buffers->ecccalc;
1323
1324 /* Read the OOB area first */
1325 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1326 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1327 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1328
1329 for (i = 0; i < chip->ecc.total; i++)
1330 ecc_code[i] = chip->oob_poi[eccpos[i]];
1331
1332 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1333 int stat;
1334
1335 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1336 chip->read_buf(mtd, p, eccsize);
1337 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1338
1339 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1340 if (stat < 0)
1341 mtd->ecc_stats.failed++;
1342 else
1343 mtd->ecc_stats.corrected += stat;
1344 }
1345 return 0;
1346}
1347
1348/**
1349 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1350 * @mtd: mtd info structure
1351 * @chip: nand chip info structure
1352 * @buf: buffer to store read data
1353 * @page: page number to read
1354 *
1355 * The hw generator calculates the error syndrome automatically. Therefore we
1356 * need a special oob layout and handling.
1357 */
1358static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1359 uint8_t *buf, int page)
1360{
1361 int i, eccsize = chip->ecc.size;
1362 int eccbytes = chip->ecc.bytes;
1363 int eccsteps = chip->ecc.steps;
1364 uint8_t *p = buf;
1365 uint8_t *oob = chip->oob_poi;
1366
1367 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1368 int stat;
1369
1370 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1371 chip->read_buf(mtd, p, eccsize);
1372
1373 if (chip->ecc.prepad) {
1374 chip->read_buf(mtd, oob, chip->ecc.prepad);
1375 oob += chip->ecc.prepad;
1376 }
1377
1378 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1379 chip->read_buf(mtd, oob, eccbytes);
1380 stat = chip->ecc.correct(mtd, p, oob, NULL);
1381
1382 if (stat < 0)
1383 mtd->ecc_stats.failed++;
1384 else
1385 mtd->ecc_stats.corrected += stat;
1386
1387 oob += eccbytes;
1388
1389 if (chip->ecc.postpad) {
1390 chip->read_buf(mtd, oob, chip->ecc.postpad);
1391 oob += chip->ecc.postpad;
1392 }
1393 }
1394
1395 /* Calculate remaining oob bytes */
1396 i = mtd->oobsize - (oob - chip->oob_poi);
1397 if (i)
1398 chip->read_buf(mtd, oob, i);
1399
1400 return 0;
1401}
1402
1403/**
1404 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1405 * @chip: nand chip structure
1406 * @oob: oob destination address
1407 * @ops: oob ops structure
1408 * @len: size of oob to transfer
1409 */
1410static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1411 struct mtd_oob_ops *ops, size_t len)
1412{
1413 switch (ops->mode) {
1414
1415 case MTD_OPS_PLACE_OOB:
1416 case MTD_OPS_RAW:
1417 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1418 return oob + len;
1419
1420 case MTD_OPS_AUTO_OOB: {
1421 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1422 uint32_t boffs = 0, roffs = ops->ooboffs;
1423 size_t bytes = 0;
1424
1425 for (; free->length && len; free++, len -= bytes) {
1426 /* Read request not from offset 0? */
1427 if (unlikely(roffs)) {
1428 if (roffs >= free->length) {
1429 roffs -= free->length;
1430 continue;
1431 }
1432 boffs = free->offset + roffs;
1433 bytes = min_t(size_t, len,
1434 (free->length - roffs));
1435 roffs = 0;
1436 } else {
1437 bytes = min_t(size_t, len, free->length);
1438 boffs = free->offset;
1439 }
1440 memcpy(oob, chip->oob_poi + boffs, bytes);
1441 oob += bytes;
1442 }
1443 return oob;
1444 }
1445 default:
1446 BUG();
1447 }
1448 return NULL;
1449}
1450
1451/**
1452 * nand_do_read_ops - [INTERN] Read data with ECC
1453 * @mtd: MTD device structure
1454 * @from: offset to read from
1455 * @ops: oob ops structure
1456 *
1457 * Internal function. Called with chip held.
1458 */
1459static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1460 struct mtd_oob_ops *ops)
1461{
1462 int chipnr, page, realpage, col, bytes, aligned;
1463 struct nand_chip *chip = mtd->priv;
1464 struct mtd_ecc_stats stats;
1465 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1466 int sndcmd = 1;
1467 int ret = 0;
1468 uint32_t readlen = ops->len;
1469 uint32_t oobreadlen = ops->ooblen;
1470 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1471 mtd->oobavail : mtd->oobsize;
1472
1473 uint8_t *bufpoi, *oob, *buf;
1474
1475 stats = mtd->ecc_stats;
1476
1477 chipnr = (int)(from >> chip->chip_shift);
1478 chip->select_chip(mtd, chipnr);
1479
1480 realpage = (int)(from >> chip->page_shift);
1481 page = realpage & chip->pagemask;
1482
1483 col = (int)(from & (mtd->writesize - 1));
1484
1485 buf = ops->datbuf;
1486 oob = ops->oobbuf;
1487
1488 while (1) {
1489 bytes = min(mtd->writesize - col, readlen);
1490 aligned = (bytes == mtd->writesize);
1491
1492 /* Is the current page in the buffer? */
1493 if (realpage != chip->pagebuf || oob) {
1494 bufpoi = aligned ? buf : chip->buffers->databuf;
1495
1496 if (likely(sndcmd)) {
1497 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1498 sndcmd = 0;
1499 }
1500
1501 /* Now read the page into the buffer */
1502 if (unlikely(ops->mode == MTD_OPS_RAW))
1503 ret = chip->ecc.read_page_raw(mtd, chip,
1504 bufpoi, page);
1505 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1506 ret = chip->ecc.read_subpage(mtd, chip,
1507 col, bytes, bufpoi);
1508 else
1509 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1510 page);
1511 if (ret < 0) {
1512 if (!aligned)
1513 /* Invalidate page cache */
1514 chip->pagebuf = -1;
1515 break;
1516 }
1517
1518 /* Transfer not aligned data */
1519 if (!aligned) {
1520 if (!NAND_SUBPAGE_READ(chip) && !oob &&
1521 !(mtd->ecc_stats.failed - stats.failed) &&
1522 (ops->mode != MTD_OPS_RAW))
1523 chip->pagebuf = realpage;
1524 else
1525 /* Invalidate page cache */
1526 chip->pagebuf = -1;
1527 memcpy(buf, chip->buffers->databuf + col, bytes);
1528 }
1529
1530 buf += bytes;
1531
1532 if (unlikely(oob)) {
1533
1534 int toread = min(oobreadlen, max_oobsize);
1535
1536 if (toread) {
1537 oob = nand_transfer_oob(chip,
1538 oob, ops, toread);
1539 oobreadlen -= toread;
1540 }
1541 }
1542
1543 if (!(chip->options & NAND_NO_READRDY)) {
1544 /*
1545 * Apply delay or wait for ready/busy pin. Do
1546 * this before the AUTOINCR check, so no
1547 * problems arise if a chip which does auto
1548 * increment is marked as NOAUTOINCR by the
1549 * board driver.
1550 */
1551 if (!chip->dev_ready)
1552 udelay(chip->chip_delay);
1553 else
1554 nand_wait_ready(mtd);
1555 }
1556 } else {
1557 memcpy(buf, chip->buffers->databuf + col, bytes);
1558 buf += bytes;
1559 }
1560
1561 readlen -= bytes;
1562
1563 if (!readlen)
1564 break;
1565
1566 /* For subsequent reads align to page boundary */
1567 col = 0;
1568 /* Increment page address */
1569 realpage++;
1570
1571 page = realpage & chip->pagemask;
1572 /* Check, if we cross a chip boundary */
1573 if (!page) {
1574 chipnr++;
1575 chip->select_chip(mtd, -1);
1576 chip->select_chip(mtd, chipnr);
1577 }
1578
1579 /*
1580 * Check, if the chip supports auto page increment or if we
1581 * have hit a block boundary.
1582 */
1583 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1584 sndcmd = 1;
1585 }
1586
1587 ops->retlen = ops->len - (size_t) readlen;
1588 if (oob)
1589 ops->oobretlen = ops->ooblen - oobreadlen;
1590
1591 if (ret)
1592 return ret;
1593
1594 if (mtd->ecc_stats.failed - stats.failed)
1595 return -EBADMSG;
1596
1597 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1598}
1599
1600/**
1601 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1602 * @mtd: MTD device structure
1603 * @from: offset to read from
1604 * @len: number of bytes to read
1605 * @retlen: pointer to variable to store the number of read bytes
1606 * @buf: the databuffer to put data
1607 *
1608 * Get hold of the chip and call nand_do_read.
1609 */
1610static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1611 size_t *retlen, uint8_t *buf)
1612{
1613 struct nand_chip *chip = mtd->priv;
1614 struct mtd_oob_ops ops;
1615 int ret;
1616
1617 nand_get_device(chip, mtd, FL_READING);
1618 ops.len = len;
1619 ops.datbuf = buf;
1620 ops.oobbuf = NULL;
1621 ops.mode = 0;
1622 ret = nand_do_read_ops(mtd, from, &ops);
1623 *retlen = ops.retlen;
1624 nand_release_device(mtd);
1625 return ret;
1626}
1627
1628/**
1629 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1630 * @mtd: mtd info structure
1631 * @chip: nand chip info structure
1632 * @page: page number to read
1633 * @sndcmd: flag whether to issue read command or not
1634 */
1635static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1636 int page, int sndcmd)
1637{
1638 if (sndcmd) {
1639 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1640 sndcmd = 0;
1641 }
1642 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1643 return sndcmd;
1644}
1645
1646/**
1647 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1648 * with syndromes
1649 * @mtd: mtd info structure
1650 * @chip: nand chip info structure
1651 * @page: page number to read
1652 * @sndcmd: flag whether to issue read command or not
1653 */
1654static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1655 int page, int sndcmd)
1656{
1657 uint8_t *buf = chip->oob_poi;
1658 int length = mtd->oobsize;
1659 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1660 int eccsize = chip->ecc.size;
1661 uint8_t *bufpoi = buf;
1662 int i, toread, sndrnd = 0, pos;
1663
1664 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1665 for (i = 0; i < chip->ecc.steps; i++) {
1666 if (sndrnd) {
1667 pos = eccsize + i * (eccsize + chunk);
1668 if (mtd->writesize > 512)
1669 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1670 else
1671 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1672 } else
1673 sndrnd = 1;
1674 toread = min_t(int, length, chunk);
1675 chip->read_buf(mtd, bufpoi, toread);
1676 bufpoi += toread;
1677 length -= toread;
1678 }
1679 if (length > 0)
1680 chip->read_buf(mtd, bufpoi, length);
1681
1682 return 1;
1683}
1684
1685/**
1686 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1687 * @mtd: mtd info structure
1688 * @chip: nand chip info structure
1689 * @page: page number to write
1690 */
1691static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1692 int page)
1693{
1694 int status = 0;
1695 const uint8_t *buf = chip->oob_poi;
1696 int length = mtd->oobsize;
1697
1698 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1699 chip->write_buf(mtd, buf, length);
1700 /* Send command to program the OOB data */
1701 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1702
1703 status = chip->waitfunc(mtd, chip);
1704
1705 return status & NAND_STATUS_FAIL ? -EIO : 0;
1706}
1707
1708/**
1709 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1710 * with syndrome - only for large page flash
1711 * @mtd: mtd info structure
1712 * @chip: nand chip info structure
1713 * @page: page number to write
1714 */
1715static int nand_write_oob_syndrome(struct mtd_info *mtd,
1716 struct nand_chip *chip, int page)
1717{
1718 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1719 int eccsize = chip->ecc.size, length = mtd->oobsize;
1720 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1721 const uint8_t *bufpoi = chip->oob_poi;
1722
1723 /*
1724 * data-ecc-data-ecc ... ecc-oob
1725 * or
1726 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1727 */
1728 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1729 pos = steps * (eccsize + chunk);
1730 steps = 0;
1731 } else
1732 pos = eccsize;
1733
1734 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1735 for (i = 0; i < steps; i++) {
1736 if (sndcmd) {
1737 if (mtd->writesize <= 512) {
1738 uint32_t fill = 0xFFFFFFFF;
1739
1740 len = eccsize;
1741 while (len > 0) {
1742 int num = min_t(int, len, 4);
1743 chip->write_buf(mtd, (uint8_t *)&fill,
1744 num);
1745 len -= num;
1746 }
1747 } else {
1748 pos = eccsize + i * (eccsize + chunk);
1749 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1750 }
1751 } else
1752 sndcmd = 1;
1753 len = min_t(int, length, chunk);
1754 chip->write_buf(mtd, bufpoi, len);
1755 bufpoi += len;
1756 length -= len;
1757 }
1758 if (length > 0)
1759 chip->write_buf(mtd, bufpoi, length);
1760
1761 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1762 status = chip->waitfunc(mtd, chip);
1763
1764 return status & NAND_STATUS_FAIL ? -EIO : 0;
1765}
1766
1767/**
1768 * nand_do_read_oob - [INTERN] NAND read out-of-band
1769 * @mtd: MTD device structure
1770 * @from: offset to read from
1771 * @ops: oob operations description structure
1772 *
1773 * NAND read out-of-band data from the spare area.
1774 */
1775static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1776 struct mtd_oob_ops *ops)
1777{
1778 int page, realpage, chipnr, sndcmd = 1;
1779 struct nand_chip *chip = mtd->priv;
1780 struct mtd_ecc_stats stats;
1781 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1782 int readlen = ops->ooblen;
1783 int len;
1784 uint8_t *buf = ops->oobbuf;
1785
1786 pr_debug("%s: from = 0x%08Lx, len = %i\n",
1787 __func__, (unsigned long long)from, readlen);
1788
1789 stats = mtd->ecc_stats;
1790
1791 if (ops->mode == MTD_OPS_AUTO_OOB)
1792 len = chip->ecc.layout->oobavail;
1793 else
1794 len = mtd->oobsize;
1795
1796 if (unlikely(ops->ooboffs >= len)) {
1797 pr_debug("%s: attempt to start read outside oob\n",
1798 __func__);
1799 return -EINVAL;
1800 }
1801
1802 /* Do not allow reads past end of device */
1803 if (unlikely(from >= mtd->size ||
1804 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1805 (from >> chip->page_shift)) * len)) {
1806 pr_debug("%s: attempt to read beyond end of device\n",
1807 __func__);
1808 return -EINVAL;
1809 }
1810
1811 chipnr = (int)(from >> chip->chip_shift);
1812 chip->select_chip(mtd, chipnr);
1813
1814 /* Shift to get page */
1815 realpage = (int)(from >> chip->page_shift);
1816 page = realpage & chip->pagemask;
1817
1818 while (1) {
1819 if (ops->mode == MTD_OPS_RAW)
1820 sndcmd = chip->ecc.read_oob_raw(mtd, chip, page, sndcmd);
1821 else
1822 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1823
1824 len = min(len, readlen);
1825 buf = nand_transfer_oob(chip, buf, ops, len);
1826
1827 if (!(chip->options & NAND_NO_READRDY)) {
1828 /*
1829 * Apply delay or wait for ready/busy pin. Do this
1830 * before the AUTOINCR check, so no problems arise if a
1831 * chip which does auto increment is marked as
1832 * NOAUTOINCR by the board driver.
1833 */
1834 if (!chip->dev_ready)
1835 udelay(chip->chip_delay);
1836 else
1837 nand_wait_ready(mtd);
1838 }
1839
1840 readlen -= len;
1841 if (!readlen)
1842 break;
1843
1844 /* Increment page address */
1845 realpage++;
1846
1847 page = realpage & chip->pagemask;
1848 /* Check, if we cross a chip boundary */
1849 if (!page) {
1850 chipnr++;
1851 chip->select_chip(mtd, -1);
1852 chip->select_chip(mtd, chipnr);
1853 }
1854
1855 /*
1856 * Check, if the chip supports auto page increment or if we
1857 * have hit a block boundary.
1858 */
1859 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1860 sndcmd = 1;
1861 }
1862
1863 ops->oobretlen = ops->ooblen;
1864
1865 if (mtd->ecc_stats.failed - stats.failed)
1866 return -EBADMSG;
1867
1868 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1869}
1870
1871/**
1872 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1873 * @mtd: MTD device structure
1874 * @from: offset to read from
1875 * @ops: oob operation description structure
1876 *
1877 * NAND read data and/or out-of-band data.
1878 */
1879static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1880 struct mtd_oob_ops *ops)
1881{
1882 struct nand_chip *chip = mtd->priv;
1883 int ret = -ENOTSUPP;
1884
1885 ops->retlen = 0;
1886
1887 /* Do not allow reads past end of device */
1888 if (ops->datbuf && (from + ops->len) > mtd->size) {
1889 pr_debug("%s: attempt to read beyond end of device\n",
1890 __func__);
1891 return -EINVAL;
1892 }
1893
1894 nand_get_device(chip, mtd, FL_READING);
1895
1896 switch (ops->mode) {
1897 case MTD_OPS_PLACE_OOB:
1898 case MTD_OPS_AUTO_OOB:
1899 case MTD_OPS_RAW:
1900 break;
1901
1902 default:
1903 goto out;
1904 }
1905
1906 if (!ops->datbuf)
1907 ret = nand_do_read_oob(mtd, from, ops);
1908 else
1909 ret = nand_do_read_ops(mtd, from, ops);
1910
1911out:
1912 nand_release_device(mtd);
1913 return ret;
1914}
1915
1916
1917/**
1918 * nand_write_page_raw - [INTERN] raw page write function
1919 * @mtd: mtd info structure
1920 * @chip: nand chip info structure
1921 * @buf: data buffer
1922 *
1923 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1924 */
1925static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1926 const uint8_t *buf)
1927{
1928 chip->write_buf(mtd, buf, mtd->writesize);
1929 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1930}
1931
1932/**
1933 * nand_write_page_raw_syndrome - [INTERN] raw page write function
1934 * @mtd: mtd info structure
1935 * @chip: nand chip info structure
1936 * @buf: data buffer
1937 *
1938 * We need a special oob layout and handling even when ECC isn't checked.
1939 */
1940static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1941 struct nand_chip *chip,
1942 const uint8_t *buf)
1943{
1944 int eccsize = chip->ecc.size;
1945 int eccbytes = chip->ecc.bytes;
1946 uint8_t *oob = chip->oob_poi;
1947 int steps, size;
1948
1949 for (steps = chip->ecc.steps; steps > 0; steps--) {
1950 chip->write_buf(mtd, buf, eccsize);
1951 buf += eccsize;
1952
1953 if (chip->ecc.prepad) {
1954 chip->write_buf(mtd, oob, chip->ecc.prepad);
1955 oob += chip->ecc.prepad;
1956 }
1957
1958 chip->read_buf(mtd, oob, eccbytes);
1959 oob += eccbytes;
1960
1961 if (chip->ecc.postpad) {
1962 chip->write_buf(mtd, oob, chip->ecc.postpad);
1963 oob += chip->ecc.postpad;
1964 }
1965 }
1966
1967 size = mtd->oobsize - (oob - chip->oob_poi);
1968 if (size)
1969 chip->write_buf(mtd, oob, size);
1970}
1971/**
1972 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1973 * @mtd: mtd info structure
1974 * @chip: nand chip info structure
1975 * @buf: data buffer
1976 */
1977static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1978 const uint8_t *buf)
1979{
1980 int i, eccsize = chip->ecc.size;
1981 int eccbytes = chip->ecc.bytes;
1982 int eccsteps = chip->ecc.steps;
1983 uint8_t *ecc_calc = chip->buffers->ecccalc;
1984 const uint8_t *p = buf;
1985 uint32_t *eccpos = chip->ecc.layout->eccpos;
1986
1987 /* Software ECC calculation */
1988 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1989 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1990
1991 for (i = 0; i < chip->ecc.total; i++)
1992 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1993
1994 chip->ecc.write_page_raw(mtd, chip, buf);
1995}
1996
1997/**
1998 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
1999 * @mtd: mtd info structure
2000 * @chip: nand chip info structure
2001 * @buf: data buffer
2002 */
2003static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2004 const uint8_t *buf)
2005{
2006 int i, eccsize = chip->ecc.size;
2007 int eccbytes = chip->ecc.bytes;
2008 int eccsteps = chip->ecc.steps;
2009 uint8_t *ecc_calc = chip->buffers->ecccalc;
2010 const uint8_t *p = buf;
2011 uint32_t *eccpos = chip->ecc.layout->eccpos;
2012
2013 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2014 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2015 chip->write_buf(mtd, p, eccsize);
2016 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2017 }
2018
2019 for (i = 0; i < chip->ecc.total; i++)
2020 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2021
2022 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2023}
2024
2025/**
2026 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2027 * @mtd: mtd info structure
2028 * @chip: nand chip info structure
2029 * @buf: data buffer
2030 *
2031 * The hw generator calculates the error syndrome automatically. Therefore we
2032 * need a special oob layout and handling.
2033 */
2034static void nand_write_page_syndrome(struct mtd_info *mtd,
2035 struct nand_chip *chip, const uint8_t *buf)
2036{
2037 int i, eccsize = chip->ecc.size;
2038 int eccbytes = chip->ecc.bytes;
2039 int eccsteps = chip->ecc.steps;
2040 const uint8_t *p = buf;
2041 uint8_t *oob = chip->oob_poi;
2042
2043 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2044
2045 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2046 chip->write_buf(mtd, p, eccsize);
2047
2048 if (chip->ecc.prepad) {
2049 chip->write_buf(mtd, oob, chip->ecc.prepad);
2050 oob += chip->ecc.prepad;
2051 }
2052
2053 chip->ecc.calculate(mtd, p, oob);
2054 chip->write_buf(mtd, oob, eccbytes);
2055 oob += eccbytes;
2056
2057 if (chip->ecc.postpad) {
2058 chip->write_buf(mtd, oob, chip->ecc.postpad);
2059 oob += chip->ecc.postpad;
2060 }
2061 }
2062
2063 /* Calculate remaining oob bytes */
2064 i = mtd->oobsize - (oob - chip->oob_poi);
2065 if (i)
2066 chip->write_buf(mtd, oob, i);
2067}
2068
2069/**
2070 * nand_write_page - [REPLACEABLE] write one page
2071 * @mtd: MTD device structure
2072 * @chip: NAND chip descriptor
2073 * @buf: the data to write
2074 * @page: page number to write
2075 * @cached: cached programming
2076 * @raw: use _raw version of write_page
2077 */
2078static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2079 const uint8_t *buf, int page, int cached, int raw)
2080{
2081 int status;
2082
2083 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2084
2085 if (unlikely(raw))
2086 chip->ecc.write_page_raw(mtd, chip, buf);
2087 else
2088 chip->ecc.write_page(mtd, chip, buf);
2089
2090 /*
2091 * Cached progamming disabled for now. Not sure if it's worth the
2092 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2093 */
2094 cached = 0;
2095
2096 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2097
2098 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2099 status = chip->waitfunc(mtd, chip);
2100 /*
2101 * See if operation failed and additional status checks are
2102 * available.
2103 */
2104 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2105 status = chip->errstat(mtd, chip, FL_WRITING, status,
2106 page);
2107
2108 if (status & NAND_STATUS_FAIL)
2109 return -EIO;
2110 } else {
2111 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2112 status = chip->waitfunc(mtd, chip);
2113 }
2114
2115#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2116 /* Send command to read back the data */
2117 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2118
2119 if (chip->verify_buf(mtd, buf, mtd->writesize))
2120 return -EIO;
2121#endif
2122 return 0;
2123}
2124
2125/**
2126 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2127 * @mtd: MTD device structure
2128 * @oob: oob data buffer
2129 * @len: oob data write length
2130 * @ops: oob ops structure
2131 */
2132static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2133 struct mtd_oob_ops *ops)
2134{
2135 struct nand_chip *chip = mtd->priv;
2136
2137 /*
2138 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2139 * data from a previous OOB read.
2140 */
2141 memset(chip->oob_poi, 0xff, mtd->oobsize);
2142
2143 switch (ops->mode) {
2144
2145 case MTD_OPS_PLACE_OOB:
2146 case MTD_OPS_RAW:
2147 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2148 return oob + len;
2149
2150 case MTD_OPS_AUTO_OOB: {
2151 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2152 uint32_t boffs = 0, woffs = ops->ooboffs;
2153 size_t bytes = 0;
2154
2155 for (; free->length && len; free++, len -= bytes) {
2156 /* Write request not from offset 0? */
2157 if (unlikely(woffs)) {
2158 if (woffs >= free->length) {
2159 woffs -= free->length;
2160 continue;
2161 }
2162 boffs = free->offset + woffs;
2163 bytes = min_t(size_t, len,
2164 (free->length - woffs));
2165 woffs = 0;
2166 } else {
2167 bytes = min_t(size_t, len, free->length);
2168 boffs = free->offset;
2169 }
2170 memcpy(chip->oob_poi + boffs, oob, bytes);
2171 oob += bytes;
2172 }
2173 return oob;
2174 }
2175 default:
2176 BUG();
2177 }
2178 return NULL;
2179}
2180
2181#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2182
2183/**
2184 * nand_do_write_ops - [INTERN] NAND write with ECC
2185 * @mtd: MTD device structure
2186 * @to: offset to write to
2187 * @ops: oob operations description structure
2188 *
2189 * NAND write with ECC.
2190 */
2191static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2192 struct mtd_oob_ops *ops)
2193{
2194 int chipnr, realpage, page, blockmask, column;
2195 struct nand_chip *chip = mtd->priv;
2196 uint32_t writelen = ops->len;
2197
2198 uint32_t oobwritelen = ops->ooblen;
2199 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2200 mtd->oobavail : mtd->oobsize;
2201
2202 uint8_t *oob = ops->oobbuf;
2203 uint8_t *buf = ops->datbuf;
2204 int ret, subpage;
2205
2206 ops->retlen = 0;
2207 if (!writelen)
2208 return 0;
2209
2210 /* Reject writes, which are not page aligned */
2211 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2212 pr_notice("%s: attempt to write non page aligned data\n",
2213 __func__);
2214 return -EINVAL;
2215 }
2216
2217 column = to & (mtd->writesize - 1);
2218 subpage = column || (writelen & (mtd->writesize - 1));
2219
2220 if (subpage && oob)
2221 return -EINVAL;
2222
2223 chipnr = (int)(to >> chip->chip_shift);
2224 chip->select_chip(mtd, chipnr);
2225
2226 /* Check, if it is write protected */
2227 if (nand_check_wp(mtd))
2228 return -EIO;
2229
2230 realpage = (int)(to >> chip->page_shift);
2231 page = realpage & chip->pagemask;
2232 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2233
2234 /* Invalidate the page cache, when we write to the cached page */
2235 if (to <= (chip->pagebuf << chip->page_shift) &&
2236 (chip->pagebuf << chip->page_shift) < (to + ops->len))
2237 chip->pagebuf = -1;
2238
2239 /* Don't allow multipage oob writes with offset */
2240 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
2241 return -EINVAL;
2242
2243 while (1) {
2244 int bytes = mtd->writesize;
2245 int cached = writelen > bytes && page != blockmask;
2246 uint8_t *wbuf = buf;
2247
2248 /* Partial page write? */
2249 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2250 cached = 0;
2251 bytes = min_t(int, bytes - column, (int) writelen);
2252 chip->pagebuf = -1;
2253 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2254 memcpy(&chip->buffers->databuf[column], buf, bytes);
2255 wbuf = chip->buffers->databuf;
2256 }
2257
2258 if (unlikely(oob)) {
2259 size_t len = min(oobwritelen, oobmaxlen);
2260 oob = nand_fill_oob(mtd, oob, len, ops);
2261 oobwritelen -= len;
2262 } else {
2263 /* We still need to erase leftover OOB data */
2264 memset(chip->oob_poi, 0xff, mtd->oobsize);
2265 }
2266
2267 ret = chip->write_page(mtd, chip, wbuf, page, cached,
2268 (ops->mode == MTD_OPS_RAW));
2269 if (ret)
2270 break;
2271
2272 writelen -= bytes;
2273 if (!writelen)
2274 break;
2275
2276 column = 0;
2277 buf += bytes;
2278 realpage++;
2279
2280 page = realpage & chip->pagemask;
2281 /* Check, if we cross a chip boundary */
2282 if (!page) {
2283 chipnr++;
2284 chip->select_chip(mtd, -1);
2285 chip->select_chip(mtd, chipnr);
2286 }
2287 }
2288
2289 ops->retlen = ops->len - writelen;
2290 if (unlikely(oob))
2291 ops->oobretlen = ops->ooblen;
2292 return ret;
2293}
2294
2295/**
2296 * panic_nand_write - [MTD Interface] NAND write with ECC
2297 * @mtd: MTD device structure
2298 * @to: offset to write to
2299 * @len: number of bytes to write
2300 * @retlen: pointer to variable to store the number of written bytes
2301 * @buf: the data to write
2302 *
2303 * NAND write with ECC. Used when performing writes in interrupt context, this
2304 * may for example be called by mtdoops when writing an oops while in panic.
2305 */
2306static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2307 size_t *retlen, const uint8_t *buf)
2308{
2309 struct nand_chip *chip = mtd->priv;
2310 struct mtd_oob_ops ops;
2311 int ret;
2312
2313 /* Wait for the device to get ready */
2314 panic_nand_wait(mtd, chip, 400);
2315
2316 /* Grab the device */
2317 panic_nand_get_device(chip, mtd, FL_WRITING);
2318
2319 ops.len = len;
2320 ops.datbuf = (uint8_t *)buf;
2321 ops.oobbuf = NULL;
2322 ops.mode = 0;
2323
2324 ret = nand_do_write_ops(mtd, to, &ops);
2325
2326 *retlen = ops.retlen;
2327 return ret;
2328}
2329
2330/**
2331 * nand_write - [MTD Interface] NAND write with ECC
2332 * @mtd: MTD device structure
2333 * @to: offset to write to
2334 * @len: number of bytes to write
2335 * @retlen: pointer to variable to store the number of written bytes
2336 * @buf: the data to write
2337 *
2338 * NAND write with ECC.
2339 */
2340static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2341 size_t *retlen, const uint8_t *buf)
2342{
2343 struct nand_chip *chip = mtd->priv;
2344 struct mtd_oob_ops ops;
2345 int ret;
2346
2347 nand_get_device(chip, mtd, FL_WRITING);
2348 ops.len = len;
2349 ops.datbuf = (uint8_t *)buf;
2350 ops.oobbuf = NULL;
2351 ops.mode = 0;
2352 ret = nand_do_write_ops(mtd, to, &ops);
2353 *retlen = ops.retlen;
2354 nand_release_device(mtd);
2355 return ret;
2356}
2357
2358/**
2359 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2360 * @mtd: MTD device structure
2361 * @to: offset to write to
2362 * @ops: oob operation description structure
2363 *
2364 * NAND write out-of-band.
2365 */
2366static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2367 struct mtd_oob_ops *ops)
2368{
2369 int chipnr, page, status, len;
2370 struct nand_chip *chip = mtd->priv;
2371
2372 pr_debug("%s: to = 0x%08x, len = %i\n",
2373 __func__, (unsigned int)to, (int)ops->ooblen);
2374
2375 if (ops->mode == MTD_OPS_AUTO_OOB)
2376 len = chip->ecc.layout->oobavail;
2377 else
2378 len = mtd->oobsize;
2379
2380 /* Do not allow write past end of page */
2381 if ((ops->ooboffs + ops->ooblen) > len) {
2382 pr_debug("%s: attempt to write past end of page\n",
2383 __func__);
2384 return -EINVAL;
2385 }
2386
2387 if (unlikely(ops->ooboffs >= len)) {
2388 pr_debug("%s: attempt to start write outside oob\n",
2389 __func__);
2390 return -EINVAL;
2391 }
2392
2393 /* Do not allow write past end of device */
2394 if (unlikely(to >= mtd->size ||
2395 ops->ooboffs + ops->ooblen >
2396 ((mtd->size >> chip->page_shift) -
2397 (to >> chip->page_shift)) * len)) {
2398 pr_debug("%s: attempt to write beyond end of device\n",
2399 __func__);
2400 return -EINVAL;
2401 }
2402
2403 chipnr = (int)(to >> chip->chip_shift);
2404 chip->select_chip(mtd, chipnr);
2405
2406 /* Shift to get page */
2407 page = (int)(to >> chip->page_shift);
2408
2409 /*
2410 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2411 * of my DiskOnChip 2000 test units) will clear the whole data page too
2412 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2413 * it in the doc2000 driver in August 1999. dwmw2.
2414 */
2415 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2416
2417 /* Check, if it is write protected */
2418 if (nand_check_wp(mtd))
2419 return -EROFS;
2420
2421 /* Invalidate the page cache, if we write to the cached page */
2422 if (page == chip->pagebuf)
2423 chip->pagebuf = -1;
2424
2425 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2426
2427 if (ops->mode == MTD_OPS_RAW)
2428 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2429 else
2430 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2431
2432 if (status)
2433 return status;
2434
2435 ops->oobretlen = ops->ooblen;
2436
2437 return 0;
2438}
2439
2440/**
2441 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2442 * @mtd: MTD device structure
2443 * @to: offset to write to
2444 * @ops: oob operation description structure
2445 */
2446static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2447 struct mtd_oob_ops *ops)
2448{
2449 struct nand_chip *chip = mtd->priv;
2450 int ret = -ENOTSUPP;
2451
2452 ops->retlen = 0;
2453
2454 /* Do not allow writes past end of device */
2455 if (ops->datbuf && (to + ops->len) > mtd->size) {
2456 pr_debug("%s: attempt to write beyond end of device\n",
2457 __func__);
2458 return -EINVAL;
2459 }
2460
2461 nand_get_device(chip, mtd, FL_WRITING);
2462
2463 switch (ops->mode) {
2464 case MTD_OPS_PLACE_OOB:
2465 case MTD_OPS_AUTO_OOB:
2466 case MTD_OPS_RAW:
2467 break;
2468
2469 default:
2470 goto out;
2471 }
2472
2473 if (!ops->datbuf)
2474 ret = nand_do_write_oob(mtd, to, ops);
2475 else
2476 ret = nand_do_write_ops(mtd, to, ops);
2477
2478out:
2479 nand_release_device(mtd);
2480 return ret;
2481}
2482
2483/**
2484 * single_erase_cmd - [GENERIC] NAND standard block erase command function
2485 * @mtd: MTD device structure
2486 * @page: the page address of the block which will be erased
2487 *
2488 * Standard erase command for NAND chips.
2489 */
2490static void single_erase_cmd(struct mtd_info *mtd, int page)
2491{
2492 struct nand_chip *chip = mtd->priv;
2493 /* Send commands to erase a block */
2494 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2495 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2496}
2497
2498/**
2499 * multi_erase_cmd - [GENERIC] AND specific block erase command function
2500 * @mtd: MTD device structure
2501 * @page: the page address of the block which will be erased
2502 *
2503 * AND multi block erase command function. Erase 4 consecutive blocks.
2504 */
2505static void multi_erase_cmd(struct mtd_info *mtd, int page)
2506{
2507 struct nand_chip *chip = mtd->priv;
2508 /* Send commands to erase a block */
2509 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2510 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2511 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2512 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2513 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2514}
2515
2516/**
2517 * nand_erase - [MTD Interface] erase block(s)
2518 * @mtd: MTD device structure
2519 * @instr: erase instruction
2520 *
2521 * Erase one ore more blocks.
2522 */
2523static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2524{
2525 return nand_erase_nand(mtd, instr, 0);
2526}
2527
2528#define BBT_PAGE_MASK 0xffffff3f
2529/**
2530 * nand_erase_nand - [INTERN] erase block(s)
2531 * @mtd: MTD device structure
2532 * @instr: erase instruction
2533 * @allowbbt: allow erasing the bbt area
2534 *
2535 * Erase one ore more blocks.
2536 */
2537int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2538 int allowbbt)
2539{
2540 int page, status, pages_per_block, ret, chipnr;
2541 struct nand_chip *chip = mtd->priv;
2542 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
2543 unsigned int bbt_masked_page = 0xffffffff;
2544 loff_t len;
2545
2546 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2547 __func__, (unsigned long long)instr->addr,
2548 (unsigned long long)instr->len);
2549
2550 if (check_offs_len(mtd, instr->addr, instr->len))
2551 return -EINVAL;
2552
2553 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2554
2555 /* Grab the lock and see if the device is available */
2556 nand_get_device(chip, mtd, FL_ERASING);
2557
2558 /* Shift to get first page */
2559 page = (int)(instr->addr >> chip->page_shift);
2560 chipnr = (int)(instr->addr >> chip->chip_shift);
2561
2562 /* Calculate pages in each block */
2563 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2564
2565 /* Select the NAND device */
2566 chip->select_chip(mtd, chipnr);
2567
2568 /* Check, if it is write protected */
2569 if (nand_check_wp(mtd)) {
2570 pr_debug("%s: device is write protected!\n",
2571 __func__);
2572 instr->state = MTD_ERASE_FAILED;
2573 goto erase_exit;
2574 }
2575
2576 /*
2577 * If BBT requires refresh, set the BBT page mask to see if the BBT
2578 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2579 * can not be matched. This is also done when the bbt is actually
2580 * erased to avoid recursive updates.
2581 */
2582 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2583 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2584
2585 /* Loop through the pages */
2586 len = instr->len;
2587
2588 instr->state = MTD_ERASING;
2589
2590 while (len) {
2591 /* Check if we have a bad block, we do not erase bad blocks! */
2592 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2593 chip->page_shift, 0, allowbbt)) {
2594 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2595 __func__, page);
2596 instr->state = MTD_ERASE_FAILED;
2597 goto erase_exit;
2598 }
2599
2600 /*
2601 * Invalidate the page cache, if we erase the block which
2602 * contains the current cached page.
2603 */
2604 if (page <= chip->pagebuf && chip->pagebuf <
2605 (page + pages_per_block))
2606 chip->pagebuf = -1;
2607
2608 chip->erase_cmd(mtd, page & chip->pagemask);
2609
2610 status = chip->waitfunc(mtd, chip);
2611
2612 /*
2613 * See if operation failed and additional status checks are
2614 * available
2615 */
2616 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2617 status = chip->errstat(mtd, chip, FL_ERASING,
2618 status, page);
2619
2620 /* See if block erase succeeded */
2621 if (status & NAND_STATUS_FAIL) {
2622 pr_debug("%s: failed erase, page 0x%08x\n",
2623 __func__, page);
2624 instr->state = MTD_ERASE_FAILED;
2625 instr->fail_addr =
2626 ((loff_t)page << chip->page_shift);
2627 goto erase_exit;
2628 }
2629
2630 /*
2631 * If BBT requires refresh, set the BBT rewrite flag to the
2632 * page being erased.
2633 */
2634 if (bbt_masked_page != 0xffffffff &&
2635 (page & BBT_PAGE_MASK) == bbt_masked_page)
2636 rewrite_bbt[chipnr] =
2637 ((loff_t)page << chip->page_shift);
2638
2639 /* Increment page address and decrement length */
2640 len -= (1 << chip->phys_erase_shift);
2641 page += pages_per_block;
2642
2643 /* Check, if we cross a chip boundary */
2644 if (len && !(page & chip->pagemask)) {
2645 chipnr++;
2646 chip->select_chip(mtd, -1);
2647 chip->select_chip(mtd, chipnr);
2648
2649 /*
2650 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2651 * page mask to see if this BBT should be rewritten.
2652 */
2653 if (bbt_masked_page != 0xffffffff &&
2654 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2655 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2656 BBT_PAGE_MASK;
2657 }
2658 }
2659 instr->state = MTD_ERASE_DONE;
2660
2661erase_exit:
2662
2663 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2664
2665 /* Deselect and wake up anyone waiting on the device */
2666 nand_release_device(mtd);
2667
2668 /* Do call back function */
2669 if (!ret)
2670 mtd_erase_callback(instr);
2671
2672 /*
2673 * If BBT requires refresh and erase was successful, rewrite any
2674 * selected bad block tables.
2675 */
2676 if (bbt_masked_page == 0xffffffff || ret)
2677 return ret;
2678
2679 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2680 if (!rewrite_bbt[chipnr])
2681 continue;
2682 /* Update the BBT for chip */
2683 pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
2684 __func__, chipnr, rewrite_bbt[chipnr],
2685 chip->bbt_td->pages[chipnr]);
2686 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2687 }
2688
2689 /* Return more or less happy */
2690 return ret;
2691}
2692
2693/**
2694 * nand_sync - [MTD Interface] sync
2695 * @mtd: MTD device structure
2696 *
2697 * Sync is actually a wait for chip ready function.
2698 */
2699static void nand_sync(struct mtd_info *mtd)
2700{
2701 struct nand_chip *chip = mtd->priv;
2702
2703 pr_debug("%s: called\n", __func__);
2704
2705 /* Grab the lock and see if the device is available */
2706 nand_get_device(chip, mtd, FL_SYNCING);
2707 /* Release it and go back */
2708 nand_release_device(mtd);
2709}
2710
2711/**
2712 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2713 * @mtd: MTD device structure
2714 * @offs: offset relative to mtd start
2715 */
2716static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2717{
2718 return nand_block_checkbad(mtd, offs, 1, 0);
2719}
2720
2721/**
2722 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2723 * @mtd: MTD device structure
2724 * @ofs: offset relative to mtd start
2725 */
2726static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2727{
2728 struct nand_chip *chip = mtd->priv;
2729 int ret;
2730
2731 ret = nand_block_isbad(mtd, ofs);
2732 if (ret) {
2733 /* If it was bad already, return success and do nothing */
2734 if (ret > 0)
2735 return 0;
2736 return ret;
2737 }
2738
2739 return chip->block_markbad(mtd, ofs);
2740}
2741
2742/**
2743 * nand_suspend - [MTD Interface] Suspend the NAND flash
2744 * @mtd: MTD device structure
2745 */
2746static int nand_suspend(struct mtd_info *mtd)
2747{
2748 struct nand_chip *chip = mtd->priv;
2749
2750 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2751}
2752
2753/**
2754 * nand_resume - [MTD Interface] Resume the NAND flash
2755 * @mtd: MTD device structure
2756 */
2757static void nand_resume(struct mtd_info *mtd)
2758{
2759 struct nand_chip *chip = mtd->priv;
2760
2761 if (chip->state == FL_PM_SUSPENDED)
2762 nand_release_device(mtd);
2763 else
2764 pr_err("%s called for a chip which is not in suspended state\n",
2765 __func__);
2766}
2767
2768/* Set default functions */
2769static void nand_set_defaults(struct nand_chip *chip, int busw)
2770{
2771 /* check for proper chip_delay setup, set 20us if not */
2772 if (!chip->chip_delay)
2773 chip->chip_delay = 20;
2774
2775 /* check, if a user supplied command function given */
2776 if (chip->cmdfunc == NULL)
2777 chip->cmdfunc = nand_command;
2778
2779 /* check, if a user supplied wait function given */
2780 if (chip->waitfunc == NULL)
2781 chip->waitfunc = nand_wait;
2782
2783 if (!chip->select_chip)
2784 chip->select_chip = nand_select_chip;
2785 if (!chip->read_byte)
2786 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2787 if (!chip->read_word)
2788 chip->read_word = nand_read_word;
2789 if (!chip->block_bad)
2790 chip->block_bad = nand_block_bad;
2791 if (!chip->block_markbad)
2792 chip->block_markbad = nand_default_block_markbad;
2793 if (!chip->write_buf)
2794 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2795 if (!chip->read_buf)
2796 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2797 if (!chip->verify_buf)
2798 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2799 if (!chip->scan_bbt)
2800 chip->scan_bbt = nand_default_bbt;
2801
2802 if (!chip->controller) {
2803 chip->controller = &chip->hwcontrol;
2804 spin_lock_init(&chip->controller->lock);
2805 init_waitqueue_head(&chip->controller->wq);
2806 }
2807
2808}
2809
2810/* Sanitize ONFI strings so we can safely print them */
2811static void sanitize_string(uint8_t *s, size_t len)
2812{
2813 ssize_t i;
2814
2815 /* Null terminate */
2816 s[len - 1] = 0;
2817
2818 /* Remove non printable chars */
2819 for (i = 0; i < len - 1; i++) {
2820 if (s[i] < ' ' || s[i] > 127)
2821 s[i] = '?';
2822 }
2823
2824 /* Remove trailing spaces */
2825 strim(s);
2826}
2827
2828static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2829{
2830 int i;
2831 while (len--) {
2832 crc ^= *p++ << 8;
2833 for (i = 0; i < 8; i++)
2834 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2835 }
2836
2837 return crc;
2838}
2839
2840/*
2841 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2842 */
2843static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2844 int *busw)
2845{
2846 struct nand_onfi_params *p = &chip->onfi_params;
2847 int i;
2848 int val;
2849
2850 /* Try ONFI for unknown chip or LP */
2851 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2852 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2853 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2854 return 0;
2855
2856 pr_info("ONFI flash detected\n");
2857 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2858 for (i = 0; i < 3; i++) {
2859 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2860 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2861 le16_to_cpu(p->crc)) {
2862 pr_info("ONFI param page %d valid\n", i);
2863 break;
2864 }
2865 }
2866
2867 if (i == 3)
2868 return 0;
2869
2870 /* Check version */
2871 val = le16_to_cpu(p->revision);
2872 if (val & (1 << 5))
2873 chip->onfi_version = 23;
2874 else if (val & (1 << 4))
2875 chip->onfi_version = 22;
2876 else if (val & (1 << 3))
2877 chip->onfi_version = 21;
2878 else if (val & (1 << 2))
2879 chip->onfi_version = 20;
2880 else if (val & (1 << 1))
2881 chip->onfi_version = 10;
2882 else
2883 chip->onfi_version = 0;
2884
2885 if (!chip->onfi_version) {
2886 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
2887 return 0;
2888 }
2889
2890 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2891 sanitize_string(p->model, sizeof(p->model));
2892 if (!mtd->name)
2893 mtd->name = p->model;
2894 mtd->writesize = le32_to_cpu(p->byte_per_page);
2895 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2896 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2897 chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
2898 *busw = 0;
2899 if (le16_to_cpu(p->features) & 1)
2900 *busw = NAND_BUSWIDTH_16;
2901
2902 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2903 chip->options |= (NAND_NO_READRDY |
2904 NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2905
2906 return 1;
2907}
2908
2909/*
2910 * Get the flash and manufacturer id and lookup if the type is supported.
2911 */
2912static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2913 struct nand_chip *chip,
2914 int busw,
2915 int *maf_id, int *dev_id,
2916 struct nand_flash_dev *type)
2917{
2918 int i, maf_idx;
2919 u8 id_data[8];
2920 int ret;
2921
2922 /* Select the device */
2923 chip->select_chip(mtd, 0);
2924
2925 /*
2926 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2927 * after power-up.
2928 */
2929 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2930
2931 /* Send the command for reading device ID */
2932 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2933
2934 /* Read manufacturer and device IDs */
2935 *maf_id = chip->read_byte(mtd);
2936 *dev_id = chip->read_byte(mtd);
2937
2938 /*
2939 * Try again to make sure, as some systems the bus-hold or other
2940 * interface concerns can cause random data which looks like a
2941 * possibly credible NAND flash to appear. If the two results do
2942 * not match, ignore the device completely.
2943 */
2944
2945 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2946
2947 for (i = 0; i < 2; i++)
2948 id_data[i] = chip->read_byte(mtd);
2949
2950 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
2951 pr_info("%s: second ID read did not match "
2952 "%02x,%02x against %02x,%02x\n", __func__,
2953 *maf_id, *dev_id, id_data[0], id_data[1]);
2954 return ERR_PTR(-ENODEV);
2955 }
2956
2957 if (!type)
2958 type = nand_flash_ids;
2959
2960 for (; type->name != NULL; type++)
2961 if (*dev_id == type->id)
2962 break;
2963
2964 chip->onfi_version = 0;
2965 if (!type->name || !type->pagesize) {
2966 /* Check is chip is ONFI compliant */
2967 ret = nand_flash_detect_onfi(mtd, chip, &busw);
2968 if (ret)
2969 goto ident_done;
2970 }
2971
2972 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2973
2974 /* Read entire ID string */
2975
2976 for (i = 0; i < 8; i++)
2977 id_data[i] = chip->read_byte(mtd);
2978
2979 if (!type->name)
2980 return ERR_PTR(-ENODEV);
2981
2982 if (!mtd->name)
2983 mtd->name = type->name;
2984
2985 chip->chipsize = (uint64_t)type->chipsize << 20;
2986
2987 if (!type->pagesize && chip->init_size) {
2988 /* Set the pagesize, oobsize, erasesize by the driver */
2989 busw = chip->init_size(mtd, chip, id_data);
2990 } else if (!type->pagesize) {
2991 int extid;
2992 /* The 3rd id byte holds MLC / multichip data */
2993 chip->cellinfo = id_data[2];
2994 /* The 4th id byte is the important one */
2995 extid = id_data[3];
2996
2997 /*
2998 * Field definitions are in the following datasheets:
2999 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3000 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
3001 *
3002 * Check for wraparound + Samsung ID + nonzero 6th byte
3003 * to decide what to do.
3004 */
3005 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
3006 id_data[0] == NAND_MFR_SAMSUNG &&
3007 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3008 id_data[5] != 0x00) {
3009 /* Calc pagesize */
3010 mtd->writesize = 2048 << (extid & 0x03);
3011 extid >>= 2;
3012 /* Calc oobsize */
3013 switch (extid & 0x03) {
3014 case 1:
3015 mtd->oobsize = 128;
3016 break;
3017 case 2:
3018 mtd->oobsize = 218;
3019 break;
3020 case 3:
3021 mtd->oobsize = 400;
3022 break;
3023 default:
3024 mtd->oobsize = 436;
3025 break;
3026 }
3027 extid >>= 2;
3028 /* Calc blocksize */
3029 mtd->erasesize = (128 * 1024) <<
3030 (((extid >> 1) & 0x04) | (extid & 0x03));
3031 busw = 0;
3032 } else {
3033 /* Calc pagesize */
3034 mtd->writesize = 1024 << (extid & 0x03);
3035 extid >>= 2;
3036 /* Calc oobsize */
3037 mtd->oobsize = (8 << (extid & 0x01)) *
3038 (mtd->writesize >> 9);
3039 extid >>= 2;
3040 /* Calc blocksize. Blocksize is multiples of 64KiB */
3041 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3042 extid >>= 2;
3043 /* Get buswidth information */
3044 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3045 }
3046 } else {
3047 /*
3048 * Old devices have chip data hardcoded in the device id table.
3049 */
3050 mtd->erasesize = type->erasesize;
3051 mtd->writesize = type->pagesize;
3052 mtd->oobsize = mtd->writesize / 32;
3053 busw = type->options & NAND_BUSWIDTH_16;
3054
3055 /*
3056 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3057 * some Spansion chips have erasesize that conflicts with size
3058 * listed in nand_ids table.
3059 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3060 */
3061 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3062 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3063 id_data[7] == 0x00 && mtd->writesize == 512) {
3064 mtd->erasesize = 128 * 1024;
3065 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3066 }
3067 }
3068 /* Get chip options, preserve non chip based options */
3069 chip->options &= ~NAND_CHIPOPTIONS_MSK;
3070 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3071
3072 /*
3073 * Check if chip is not a Samsung device. Do not clear the
3074 * options for chips which do not have an extended id.
3075 */
3076 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3077 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3078ident_done:
3079
3080 /*
3081 * Set chip as a default. Board drivers can override it, if necessary.
3082 */
3083 chip->options |= NAND_NO_AUTOINCR;
3084
3085 /* Try to identify manufacturer */
3086 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3087 if (nand_manuf_ids[maf_idx].id == *maf_id)
3088 break;
3089 }
3090
3091 /*
3092 * Check, if buswidth is correct. Hardware drivers should set
3093 * chip correct!
3094 */
3095 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3096 pr_info("NAND device: Manufacturer ID:"
3097 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3098 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
3099 pr_warn("NAND bus width %d instead %d bit\n",
3100 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3101 busw ? 16 : 8);
3102 return ERR_PTR(-EINVAL);
3103 }
3104
3105 /* Calculate the address shift from the page size */
3106 chip->page_shift = ffs(mtd->writesize) - 1;
3107 /* Convert chipsize to number of pages per chip -1 */
3108 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3109
3110 chip->bbt_erase_shift = chip->phys_erase_shift =
3111 ffs(mtd->erasesize) - 1;
3112 if (chip->chipsize & 0xffffffff)
3113 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3114 else {
3115 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3116 chip->chip_shift += 32 - 1;
3117 }
3118
3119 chip->badblockbits = 8;
3120
3121 /* Set the bad block position */
3122 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
3123 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3124 else
3125 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3126
3127 /*
3128 * Bad block marker is stored in the last page of each block
3129 * on Samsung and Hynix MLC devices; stored in first two pages
3130 * of each block on Micron devices with 2KiB pages and on
3131 * SLC Samsung, Hynix, Toshiba, AMD/Spansion, and Macronix.
3132 * All others scan only the first page.
3133 */
3134 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3135 (*maf_id == NAND_MFR_SAMSUNG ||
3136 *maf_id == NAND_MFR_HYNIX))
3137 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3138 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3139 (*maf_id == NAND_MFR_SAMSUNG ||
3140 *maf_id == NAND_MFR_HYNIX ||
3141 *maf_id == NAND_MFR_TOSHIBA ||
3142 *maf_id == NAND_MFR_AMD ||
3143 *maf_id == NAND_MFR_MACRONIX)) ||
3144 (mtd->writesize == 2048 &&
3145 *maf_id == NAND_MFR_MICRON))
3146 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3147
3148 /* Check for AND chips with 4 page planes */
3149 if (chip->options & NAND_4PAGE_ARRAY)
3150 chip->erase_cmd = multi_erase_cmd;
3151 else
3152 chip->erase_cmd = single_erase_cmd;
3153
3154 /* Do not replace user supplied command function! */
3155 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3156 chip->cmdfunc = nand_command_lp;
3157
3158 pr_info("NAND device: Manufacturer ID:"
3159 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
3160 nand_manuf_ids[maf_idx].name,
3161 chip->onfi_version ? chip->onfi_params.model : type->name);
3162
3163 return type;
3164}
3165
3166/**
3167 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3168 * @mtd: MTD device structure
3169 * @maxchips: number of chips to scan for
3170 * @table: alternative NAND ID table
3171 *
3172 * This is the first phase of the normal nand_scan() function. It reads the
3173 * flash ID and sets up MTD fields accordingly.
3174 *
3175 * The mtd->owner field must be set to the module of the caller.
3176 */
3177int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3178 struct nand_flash_dev *table)
3179{
3180 int i, busw, nand_maf_id, nand_dev_id;
3181 struct nand_chip *chip = mtd->priv;
3182 struct nand_flash_dev *type;
3183
3184 /* Get buswidth to select the correct functions */
3185 busw = chip->options & NAND_BUSWIDTH_16;
3186 /* Set the default functions */
3187 nand_set_defaults(chip, busw);
3188
3189 /* Read the flash type */
3190 type = nand_get_flash_type(mtd, chip, busw,
3191 &nand_maf_id, &nand_dev_id, table);
3192
3193 if (IS_ERR(type)) {
3194 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3195 pr_warn("No NAND device found\n");
3196 chip->select_chip(mtd, -1);
3197 return PTR_ERR(type);
3198 }
3199
3200 /* Check for a chip array */
3201 for (i = 1; i < maxchips; i++) {
3202 chip->select_chip(mtd, i);
3203 /* See comment in nand_get_flash_type for reset */
3204 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3205 /* Send the command for reading device ID */
3206 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3207 /* Read manufacturer and device IDs */
3208 if (nand_maf_id != chip->read_byte(mtd) ||
3209 nand_dev_id != chip->read_byte(mtd))
3210 break;
3211 }
3212 if (i > 1)
3213 pr_info("%d NAND chips detected\n", i);
3214
3215 /* Store the number of chips and calc total size for mtd */
3216 chip->numchips = i;
3217 mtd->size = i * chip->chipsize;
3218
3219 return 0;
3220}
3221EXPORT_SYMBOL(nand_scan_ident);
3222
3223
3224/**
3225 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3226 * @mtd: MTD device structure
3227 *
3228 * This is the second phase of the normal nand_scan() function. It fills out
3229 * all the uninitialized function pointers with the defaults and scans for a
3230 * bad block table if appropriate.
3231 */
3232int nand_scan_tail(struct mtd_info *mtd)
3233{
3234 int i;
3235 struct nand_chip *chip = mtd->priv;
3236
3237 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3238 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3239 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3240
3241 if (!(chip->options & NAND_OWN_BUFFERS))
3242 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3243 if (!chip->buffers)
3244 return -ENOMEM;
3245
3246 /* Set the internal oob buffer location, just after the page data */
3247 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3248
3249 /*
3250 * If no default placement scheme is given, select an appropriate one.
3251 */
3252 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3253 switch (mtd->oobsize) {
3254 case 8:
3255 chip->ecc.layout = &nand_oob_8;
3256 break;
3257 case 16:
3258 chip->ecc.layout = &nand_oob_16;
3259 break;
3260 case 64:
3261 chip->ecc.layout = &nand_oob_64;
3262 break;
3263 case 128:
3264 chip->ecc.layout = &nand_oob_128;
3265 break;
3266 default:
3267 pr_warn("No oob scheme defined for oobsize %d\n",
3268 mtd->oobsize);
3269 BUG();
3270 }
3271 }
3272
3273 if (!chip->write_page)
3274 chip->write_page = nand_write_page;
3275
3276 /*
3277 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3278 * selected and we have 256 byte pagesize fallback to software ECC
3279 */
3280
3281 switch (chip->ecc.mode) {
3282 case NAND_ECC_HW_OOB_FIRST:
3283 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3284 if (!chip->ecc.calculate || !chip->ecc.correct ||
3285 !chip->ecc.hwctl) {
3286 pr_warn("No ECC functions supplied; "
3287 "hardware ECC not possible\n");
3288 BUG();
3289 }
3290 if (!chip->ecc.read_page)
3291 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3292
3293 case NAND_ECC_HW:
3294 /* Use standard hwecc read page function? */
3295 if (!chip->ecc.read_page)
3296 chip->ecc.read_page = nand_read_page_hwecc;
3297 if (!chip->ecc.write_page)
3298 chip->ecc.write_page = nand_write_page_hwecc;
3299 if (!chip->ecc.read_page_raw)
3300 chip->ecc.read_page_raw = nand_read_page_raw;
3301 if (!chip->ecc.write_page_raw)
3302 chip->ecc.write_page_raw = nand_write_page_raw;
3303 if (!chip->ecc.read_oob)
3304 chip->ecc.read_oob = nand_read_oob_std;
3305 if (!chip->ecc.write_oob)
3306 chip->ecc.write_oob = nand_write_oob_std;
3307
3308 case NAND_ECC_HW_SYNDROME:
3309 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3310 !chip->ecc.hwctl) &&
3311 (!chip->ecc.read_page ||
3312 chip->ecc.read_page == nand_read_page_hwecc ||
3313 !chip->ecc.write_page ||
3314 chip->ecc.write_page == nand_write_page_hwecc)) {
3315 pr_warn("No ECC functions supplied; "
3316 "hardware ECC not possible\n");
3317 BUG();
3318 }
3319 /* Use standard syndrome read/write page function? */
3320 if (!chip->ecc.read_page)
3321 chip->ecc.read_page = nand_read_page_syndrome;
3322 if (!chip->ecc.write_page)
3323 chip->ecc.write_page = nand_write_page_syndrome;
3324 if (!chip->ecc.read_page_raw)
3325 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3326 if (!chip->ecc.write_page_raw)
3327 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3328 if (!chip->ecc.read_oob)
3329 chip->ecc.read_oob = nand_read_oob_syndrome;
3330 if (!chip->ecc.write_oob)
3331 chip->ecc.write_oob = nand_write_oob_syndrome;
3332
3333 if (mtd->writesize >= chip->ecc.size)
3334 break;
3335 pr_warn("%d byte HW ECC not possible on "
3336 "%d byte page size, fallback to SW ECC\n",
3337 chip->ecc.size, mtd->writesize);
3338 chip->ecc.mode = NAND_ECC_SOFT;
3339
3340 case NAND_ECC_SOFT:
3341 chip->ecc.calculate = nand_calculate_ecc;
3342 chip->ecc.correct = nand_correct_data;
3343 chip->ecc.read_page = nand_read_page_swecc;
3344 chip->ecc.read_subpage = nand_read_subpage;
3345 chip->ecc.write_page = nand_write_page_swecc;
3346 chip->ecc.read_page_raw = nand_read_page_raw;
3347 chip->ecc.write_page_raw = nand_write_page_raw;
3348 chip->ecc.read_oob = nand_read_oob_std;
3349 chip->ecc.write_oob = nand_write_oob_std;
3350 if (!chip->ecc.size)
3351 chip->ecc.size = 256;
3352 chip->ecc.bytes = 3;
3353 break;
3354
3355 case NAND_ECC_SOFT_BCH:
3356 if (!mtd_nand_has_bch()) {
3357 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3358 BUG();
3359 }
3360 chip->ecc.calculate = nand_bch_calculate_ecc;
3361 chip->ecc.correct = nand_bch_correct_data;
3362 chip->ecc.read_page = nand_read_page_swecc;
3363 chip->ecc.read_subpage = nand_read_subpage;
3364 chip->ecc.write_page = nand_write_page_swecc;
3365 chip->ecc.read_page_raw = nand_read_page_raw;
3366 chip->ecc.write_page_raw = nand_write_page_raw;
3367 chip->ecc.read_oob = nand_read_oob_std;
3368 chip->ecc.write_oob = nand_write_oob_std;
3369 /*
3370 * Board driver should supply ecc.size and ecc.bytes values to
3371 * select how many bits are correctable; see nand_bch_init()
3372 * for details. Otherwise, default to 4 bits for large page
3373 * devices.
3374 */
3375 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3376 chip->ecc.size = 512;
3377 chip->ecc.bytes = 7;
3378 }
3379 chip->ecc.priv = nand_bch_init(mtd,
3380 chip->ecc.size,
3381 chip->ecc.bytes,
3382 &chip->ecc.layout);
3383 if (!chip->ecc.priv) {
3384 pr_warn("BCH ECC initialization failed!\n");
3385 BUG();
3386 }
3387 break;
3388
3389 case NAND_ECC_NONE:
3390 pr_warn("NAND_ECC_NONE selected by board driver. "
3391 "This is not recommended!\n");
3392 chip->ecc.read_page = nand_read_page_raw;
3393 chip->ecc.write_page = nand_write_page_raw;
3394 chip->ecc.read_oob = nand_read_oob_std;
3395 chip->ecc.read_page_raw = nand_read_page_raw;
3396 chip->ecc.write_page_raw = nand_write_page_raw;
3397 chip->ecc.write_oob = nand_write_oob_std;
3398 chip->ecc.size = mtd->writesize;
3399 chip->ecc.bytes = 0;
3400 break;
3401
3402 default:
3403 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
3404 BUG();
3405 }
3406
3407 /* For many systems, the standard OOB write also works for raw */
3408 if (!chip->ecc.read_oob_raw)
3409 chip->ecc.read_oob_raw = chip->ecc.read_oob;
3410 if (!chip->ecc.write_oob_raw)
3411 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3412
3413 /*
3414 * The number of bytes available for a client to place data into
3415 * the out of band area.
3416 */
3417 chip->ecc.layout->oobavail = 0;
3418 for (i = 0; chip->ecc.layout->oobfree[i].length
3419 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3420 chip->ecc.layout->oobavail +=
3421 chip->ecc.layout->oobfree[i].length;
3422 mtd->oobavail = chip->ecc.layout->oobavail;
3423
3424 /*
3425 * Set the number of read / write steps for one page depending on ECC
3426 * mode.
3427 */
3428 chip->ecc.steps = mtd->writesize / chip->ecc.size;
3429 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3430 pr_warn("Invalid ECC parameters\n");
3431 BUG();
3432 }
3433 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3434
3435 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3436 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3437 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3438 switch (chip->ecc.steps) {
3439 case 2:
3440 mtd->subpage_sft = 1;
3441 break;
3442 case 4:
3443 case 8:
3444 case 16:
3445 mtd->subpage_sft = 2;
3446 break;
3447 }
3448 }
3449 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3450
3451 /* Initialize state */
3452 chip->state = FL_READY;
3453
3454 /* De-select the device */
3455 chip->select_chip(mtd, -1);
3456
3457 /* Invalidate the pagebuffer reference */
3458 chip->pagebuf = -1;
3459
3460 /* Fill in remaining MTD driver data */
3461 mtd->type = MTD_NANDFLASH;
3462 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3463 MTD_CAP_NANDFLASH;
3464 mtd->_erase = nand_erase;
3465 mtd->_point = NULL;
3466 mtd->_unpoint = NULL;
3467 mtd->_read = nand_read;
3468 mtd->_write = nand_write;
3469 mtd->_panic_write = panic_nand_write;
3470 mtd->_read_oob = nand_read_oob;
3471 mtd->_write_oob = nand_write_oob;
3472 mtd->_sync = nand_sync;
3473 mtd->_lock = NULL;
3474 mtd->_unlock = NULL;
3475 mtd->_suspend = nand_suspend;
3476 mtd->_resume = nand_resume;
3477 mtd->_block_isbad = nand_block_isbad;
3478 mtd->_block_markbad = nand_block_markbad;
3479 mtd->writebufsize = mtd->writesize;
3480
3481 /* propagate ecc.layout to mtd_info */
3482 mtd->ecclayout = chip->ecc.layout;
3483
3484 /* Check, if we should skip the bad block table scan */
3485 if (chip->options & NAND_SKIP_BBTSCAN)
3486 return 0;
3487
3488 /* Build bad block table */
3489 return chip->scan_bbt(mtd);
3490}
3491EXPORT_SYMBOL(nand_scan_tail);
3492
3493/*
3494 * is_module_text_address() isn't exported, and it's mostly a pointless
3495 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3496 * to call us from in-kernel code if the core NAND support is modular.
3497 */
3498#ifdef MODULE
3499#define caller_is_module() (1)
3500#else
3501#define caller_is_module() \
3502 is_module_text_address((unsigned long)__builtin_return_address(0))
3503#endif
3504
3505/**
3506 * nand_scan - [NAND Interface] Scan for the NAND device
3507 * @mtd: MTD device structure
3508 * @maxchips: number of chips to scan for
3509 *
3510 * This fills out all the uninitialized function pointers with the defaults.
3511 * The flash ID is read and the mtd/chip structures are filled with the
3512 * appropriate values. The mtd->owner field must be set to the module of the
3513 * caller.
3514 */
3515int nand_scan(struct mtd_info *mtd, int maxchips)
3516{
3517 int ret;
3518
3519 /* Many callers got this wrong, so check for it for a while... */
3520 if (!mtd->owner && caller_is_module()) {
3521 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3522 BUG();
3523 }
3524
3525 ret = nand_scan_ident(mtd, maxchips, NULL);
3526 if (!ret)
3527 ret = nand_scan_tail(mtd);
3528 return ret;
3529}
3530EXPORT_SYMBOL(nand_scan);
3531
3532/**
3533 * nand_release - [NAND Interface] Free resources held by the NAND device
3534 * @mtd: MTD device structure
3535 */
3536void nand_release(struct mtd_info *mtd)
3537{
3538 struct nand_chip *chip = mtd->priv;
3539
3540 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3541 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3542
3543 mtd_device_unregister(mtd);
3544
3545 /* Free bad block table memory */
3546 kfree(chip->bbt);
3547 if (!(chip->options & NAND_OWN_BUFFERS))
3548 kfree(chip->buffers);
3549
3550 /* Free bad block descriptor memory */
3551 if (chip->badblock_pattern && chip->badblock_pattern->options
3552 & NAND_BBT_DYNAMICSTRUCT)
3553 kfree(chip->badblock_pattern);
3554}
3555EXPORT_SYMBOL_GPL(nand_release);
3556
3557static int __init nand_base_init(void)
3558{
3559 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3560 return 0;
3561}
3562
3563static void __exit nand_base_exit(void)
3564{
3565 led_trigger_unregister_simple(nand_led_trigger);
3566}
3567
3568module_init(nand_base_init);
3569module_exit(nand_base_exit);
3570
3571MODULE_LICENSE("GPL");
3572MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3573MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3574MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux kernel - Deliverables
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