| 1 | /* |
| 2 | * Blackfin On-Chip MAC Driver |
| 3 | * |
| 4 | * Copyright 2004-2010 Analog Devices Inc. |
| 5 | * |
| 6 | * Enter bugs at http://blackfin.uclinux.org/ |
| 7 | * |
| 8 | * Licensed under the GPL-2 or later. |
| 9 | */ |
| 10 | |
| 11 | #define DRV_VERSION "1.1" |
| 12 | #define DRV_DESC "Blackfin on-chip Ethernet MAC driver" |
| 13 | |
| 14 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 15 | |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/module.h> |
| 18 | #include <linux/kernel.h> |
| 19 | #include <linux/sched.h> |
| 20 | #include <linux/slab.h> |
| 21 | #include <linux/delay.h> |
| 22 | #include <linux/timer.h> |
| 23 | #include <linux/errno.h> |
| 24 | #include <linux/irq.h> |
| 25 | #include <linux/io.h> |
| 26 | #include <linux/ioport.h> |
| 27 | #include <linux/crc32.h> |
| 28 | #include <linux/device.h> |
| 29 | #include <linux/spinlock.h> |
| 30 | #include <linux/mii.h> |
| 31 | #include <linux/netdevice.h> |
| 32 | #include <linux/etherdevice.h> |
| 33 | #include <linux/ethtool.h> |
| 34 | #include <linux/skbuff.h> |
| 35 | #include <linux/platform_device.h> |
| 36 | |
| 37 | #include <asm/dma.h> |
| 38 | #include <linux/dma-mapping.h> |
| 39 | |
| 40 | #include <asm/div64.h> |
| 41 | #include <asm/dpmc.h> |
| 42 | #include <asm/blackfin.h> |
| 43 | #include <asm/cacheflush.h> |
| 44 | #include <asm/portmux.h> |
| 45 | #include <mach/pll.h> |
| 46 | |
| 47 | #include "bfin_mac.h" |
| 48 | |
| 49 | MODULE_AUTHOR("Bryan Wu, Luke Yang"); |
| 50 | MODULE_LICENSE("GPL"); |
| 51 | MODULE_DESCRIPTION(DRV_DESC); |
| 52 | MODULE_ALIAS("platform:bfin_mac"); |
| 53 | |
| 54 | #if defined(CONFIG_BFIN_MAC_USE_L1) |
| 55 | # define bfin_mac_alloc(dma_handle, size, num) l1_data_sram_zalloc(size*num) |
| 56 | # define bfin_mac_free(dma_handle, ptr, num) l1_data_sram_free(ptr) |
| 57 | #else |
| 58 | # define bfin_mac_alloc(dma_handle, size, num) \ |
| 59 | dma_alloc_coherent(NULL, size*num, dma_handle, GFP_KERNEL) |
| 60 | # define bfin_mac_free(dma_handle, ptr, num) \ |
| 61 | dma_free_coherent(NULL, sizeof(*ptr)*num, ptr, dma_handle) |
| 62 | #endif |
| 63 | |
| 64 | #define PKT_BUF_SZ 1580 |
| 65 | |
| 66 | #define MAX_TIMEOUT_CNT 500 |
| 67 | |
| 68 | /* pointers to maintain transmit list */ |
| 69 | static struct net_dma_desc_tx *tx_list_head; |
| 70 | static struct net_dma_desc_tx *tx_list_tail; |
| 71 | static struct net_dma_desc_rx *rx_list_head; |
| 72 | static struct net_dma_desc_rx *rx_list_tail; |
| 73 | static struct net_dma_desc_rx *current_rx_ptr; |
| 74 | static struct net_dma_desc_tx *current_tx_ptr; |
| 75 | static struct net_dma_desc_tx *tx_desc; |
| 76 | static struct net_dma_desc_rx *rx_desc; |
| 77 | |
| 78 | static void desc_list_free(void) |
| 79 | { |
| 80 | struct net_dma_desc_rx *r; |
| 81 | struct net_dma_desc_tx *t; |
| 82 | int i; |
| 83 | #if !defined(CONFIG_BFIN_MAC_USE_L1) |
| 84 | dma_addr_t dma_handle = 0; |
| 85 | #endif |
| 86 | |
| 87 | if (tx_desc) { |
| 88 | t = tx_list_head; |
| 89 | for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) { |
| 90 | if (t) { |
| 91 | if (t->skb) { |
| 92 | dev_kfree_skb(t->skb); |
| 93 | t->skb = NULL; |
| 94 | } |
| 95 | t = t->next; |
| 96 | } |
| 97 | } |
| 98 | bfin_mac_free(dma_handle, tx_desc, CONFIG_BFIN_TX_DESC_NUM); |
| 99 | } |
| 100 | |
| 101 | if (rx_desc) { |
| 102 | r = rx_list_head; |
| 103 | for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) { |
| 104 | if (r) { |
| 105 | if (r->skb) { |
| 106 | dev_kfree_skb(r->skb); |
| 107 | r->skb = NULL; |
| 108 | } |
| 109 | r = r->next; |
| 110 | } |
| 111 | } |
| 112 | bfin_mac_free(dma_handle, rx_desc, CONFIG_BFIN_RX_DESC_NUM); |
| 113 | } |
| 114 | } |
| 115 | |
| 116 | static int desc_list_init(struct net_device *dev) |
| 117 | { |
| 118 | int i; |
| 119 | struct sk_buff *new_skb; |
| 120 | #if !defined(CONFIG_BFIN_MAC_USE_L1) |
| 121 | /* |
| 122 | * This dma_handle is useless in Blackfin dma_alloc_coherent(). |
| 123 | * The real dma handler is the return value of dma_alloc_coherent(). |
| 124 | */ |
| 125 | dma_addr_t dma_handle; |
| 126 | #endif |
| 127 | |
| 128 | tx_desc = bfin_mac_alloc(&dma_handle, |
| 129 | sizeof(struct net_dma_desc_tx), |
| 130 | CONFIG_BFIN_TX_DESC_NUM); |
| 131 | if (tx_desc == NULL) |
| 132 | goto init_error; |
| 133 | |
| 134 | rx_desc = bfin_mac_alloc(&dma_handle, |
| 135 | sizeof(struct net_dma_desc_rx), |
| 136 | CONFIG_BFIN_RX_DESC_NUM); |
| 137 | if (rx_desc == NULL) |
| 138 | goto init_error; |
| 139 | |
| 140 | /* init tx_list */ |
| 141 | tx_list_head = tx_list_tail = tx_desc; |
| 142 | |
| 143 | for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) { |
| 144 | struct net_dma_desc_tx *t = tx_desc + i; |
| 145 | struct dma_descriptor *a = &(t->desc_a); |
| 146 | struct dma_descriptor *b = &(t->desc_b); |
| 147 | |
| 148 | /* |
| 149 | * disable DMA |
| 150 | * read from memory WNR = 0 |
| 151 | * wordsize is 32 bits |
| 152 | * 6 half words is desc size |
| 153 | * large desc flow |
| 154 | */ |
| 155 | a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; |
| 156 | a->start_addr = (unsigned long)t->packet; |
| 157 | a->x_count = 0; |
| 158 | a->next_dma_desc = b; |
| 159 | |
| 160 | /* |
| 161 | * enabled DMA |
| 162 | * write to memory WNR = 1 |
| 163 | * wordsize is 32 bits |
| 164 | * disable interrupt |
| 165 | * 6 half words is desc size |
| 166 | * large desc flow |
| 167 | */ |
| 168 | b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; |
| 169 | b->start_addr = (unsigned long)(&(t->status)); |
| 170 | b->x_count = 0; |
| 171 | |
| 172 | t->skb = NULL; |
| 173 | tx_list_tail->desc_b.next_dma_desc = a; |
| 174 | tx_list_tail->next = t; |
| 175 | tx_list_tail = t; |
| 176 | } |
| 177 | tx_list_tail->next = tx_list_head; /* tx_list is a circle */ |
| 178 | tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a); |
| 179 | current_tx_ptr = tx_list_head; |
| 180 | |
| 181 | /* init rx_list */ |
| 182 | rx_list_head = rx_list_tail = rx_desc; |
| 183 | |
| 184 | for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) { |
| 185 | struct net_dma_desc_rx *r = rx_desc + i; |
| 186 | struct dma_descriptor *a = &(r->desc_a); |
| 187 | struct dma_descriptor *b = &(r->desc_b); |
| 188 | |
| 189 | /* allocate a new skb for next time receive */ |
| 190 | new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN); |
| 191 | if (!new_skb) |
| 192 | goto init_error; |
| 193 | |
| 194 | skb_reserve(new_skb, NET_IP_ALIGN); |
| 195 | /* Invidate the data cache of skb->data range when it is write back |
| 196 | * cache. It will prevent overwritting the new data from DMA |
| 197 | */ |
| 198 | blackfin_dcache_invalidate_range((unsigned long)new_skb->head, |
| 199 | (unsigned long)new_skb->end); |
| 200 | r->skb = new_skb; |
| 201 | |
| 202 | /* |
| 203 | * enabled DMA |
| 204 | * write to memory WNR = 1 |
| 205 | * wordsize is 32 bits |
| 206 | * disable interrupt |
| 207 | * 6 half words is desc size |
| 208 | * large desc flow |
| 209 | */ |
| 210 | a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; |
| 211 | /* since RXDWA is enabled */ |
| 212 | a->start_addr = (unsigned long)new_skb->data - 2; |
| 213 | a->x_count = 0; |
| 214 | a->next_dma_desc = b; |
| 215 | |
| 216 | /* |
| 217 | * enabled DMA |
| 218 | * write to memory WNR = 1 |
| 219 | * wordsize is 32 bits |
| 220 | * enable interrupt |
| 221 | * 6 half words is desc size |
| 222 | * large desc flow |
| 223 | */ |
| 224 | b->config = DMAEN | WNR | WDSIZE_32 | DI_EN | |
| 225 | NDSIZE_6 | DMAFLOW_LARGE; |
| 226 | b->start_addr = (unsigned long)(&(r->status)); |
| 227 | b->x_count = 0; |
| 228 | |
| 229 | rx_list_tail->desc_b.next_dma_desc = a; |
| 230 | rx_list_tail->next = r; |
| 231 | rx_list_tail = r; |
| 232 | } |
| 233 | rx_list_tail->next = rx_list_head; /* rx_list is a circle */ |
| 234 | rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a); |
| 235 | current_rx_ptr = rx_list_head; |
| 236 | |
| 237 | return 0; |
| 238 | |
| 239 | init_error: |
| 240 | desc_list_free(); |
| 241 | pr_err("kmalloc failed\n"); |
| 242 | return -ENOMEM; |
| 243 | } |
| 244 | |
| 245 | |
| 246 | /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/ |
| 247 | |
| 248 | /* |
| 249 | * MII operations |
| 250 | */ |
| 251 | /* Wait until the previous MDC/MDIO transaction has completed */ |
| 252 | static int bfin_mdio_poll(void) |
| 253 | { |
| 254 | int timeout_cnt = MAX_TIMEOUT_CNT; |
| 255 | |
| 256 | /* poll the STABUSY bit */ |
| 257 | while ((bfin_read_EMAC_STAADD()) & STABUSY) { |
| 258 | udelay(1); |
| 259 | if (timeout_cnt-- < 0) { |
| 260 | pr_err("wait MDC/MDIO transaction to complete timeout\n"); |
| 261 | return -ETIMEDOUT; |
| 262 | } |
| 263 | } |
| 264 | |
| 265 | return 0; |
| 266 | } |
| 267 | |
| 268 | /* Read an off-chip register in a PHY through the MDC/MDIO port */ |
| 269 | static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) |
| 270 | { |
| 271 | int ret; |
| 272 | |
| 273 | ret = bfin_mdio_poll(); |
| 274 | if (ret) |
| 275 | return ret; |
| 276 | |
| 277 | /* read mode */ |
| 278 | bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) | |
| 279 | SET_REGAD((u16) regnum) | |
| 280 | STABUSY); |
| 281 | |
| 282 | ret = bfin_mdio_poll(); |
| 283 | if (ret) |
| 284 | return ret; |
| 285 | |
| 286 | return (int) bfin_read_EMAC_STADAT(); |
| 287 | } |
| 288 | |
| 289 | /* Write an off-chip register in a PHY through the MDC/MDIO port */ |
| 290 | static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, |
| 291 | u16 value) |
| 292 | { |
| 293 | int ret; |
| 294 | |
| 295 | ret = bfin_mdio_poll(); |
| 296 | if (ret) |
| 297 | return ret; |
| 298 | |
| 299 | bfin_write_EMAC_STADAT((u32) value); |
| 300 | |
| 301 | /* write mode */ |
| 302 | bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) | |
| 303 | SET_REGAD((u16) regnum) | |
| 304 | STAOP | |
| 305 | STABUSY); |
| 306 | |
| 307 | return bfin_mdio_poll(); |
| 308 | } |
| 309 | |
| 310 | static void bfin_mac_adjust_link(struct net_device *dev) |
| 311 | { |
| 312 | struct bfin_mac_local *lp = netdev_priv(dev); |
| 313 | struct phy_device *phydev = dev->phydev; |
| 314 | unsigned long flags; |
| 315 | int new_state = 0; |
| 316 | |
| 317 | spin_lock_irqsave(&lp->lock, flags); |
| 318 | if (phydev->link) { |
| 319 | /* Now we make sure that we can be in full duplex mode. |
| 320 | * If not, we operate in half-duplex mode. */ |
| 321 | if (phydev->duplex != lp->old_duplex) { |
| 322 | u32 opmode = bfin_read_EMAC_OPMODE(); |
| 323 | new_state = 1; |
| 324 | |
| 325 | if (phydev->duplex) |
| 326 | opmode |= FDMODE; |
| 327 | else |
| 328 | opmode &= ~(FDMODE); |
| 329 | |
| 330 | bfin_write_EMAC_OPMODE(opmode); |
| 331 | lp->old_duplex = phydev->duplex; |
| 332 | } |
| 333 | |
| 334 | if (phydev->speed != lp->old_speed) { |
| 335 | if (phydev->interface == PHY_INTERFACE_MODE_RMII) { |
| 336 | u32 opmode = bfin_read_EMAC_OPMODE(); |
| 337 | switch (phydev->speed) { |
| 338 | case 10: |
| 339 | opmode |= RMII_10; |
| 340 | break; |
| 341 | case 100: |
| 342 | opmode &= ~RMII_10; |
| 343 | break; |
| 344 | default: |
| 345 | netdev_warn(dev, |
| 346 | "Ack! Speed (%d) is not 10/100!\n", |
| 347 | phydev->speed); |
| 348 | break; |
| 349 | } |
| 350 | bfin_write_EMAC_OPMODE(opmode); |
| 351 | } |
| 352 | |
| 353 | new_state = 1; |
| 354 | lp->old_speed = phydev->speed; |
| 355 | } |
| 356 | |
| 357 | if (!lp->old_link) { |
| 358 | new_state = 1; |
| 359 | lp->old_link = 1; |
| 360 | } |
| 361 | } else if (lp->old_link) { |
| 362 | new_state = 1; |
| 363 | lp->old_link = 0; |
| 364 | lp->old_speed = 0; |
| 365 | lp->old_duplex = -1; |
| 366 | } |
| 367 | |
| 368 | if (new_state) { |
| 369 | u32 opmode = bfin_read_EMAC_OPMODE(); |
| 370 | phy_print_status(phydev); |
| 371 | pr_debug("EMAC_OPMODE = 0x%08x\n", opmode); |
| 372 | } |
| 373 | |
| 374 | spin_unlock_irqrestore(&lp->lock, flags); |
| 375 | } |
| 376 | |
| 377 | /* MDC = 2.5 MHz */ |
| 378 | #define MDC_CLK 2500000 |
| 379 | |
| 380 | static int mii_probe(struct net_device *dev, int phy_mode) |
| 381 | { |
| 382 | struct bfin_mac_local *lp = netdev_priv(dev); |
| 383 | struct phy_device *phydev; |
| 384 | unsigned short sysctl; |
| 385 | u32 sclk, mdc_div; |
| 386 | |
| 387 | /* Enable PHY output early */ |
| 388 | if (!(bfin_read_VR_CTL() & CLKBUFOE)) |
| 389 | bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); |
| 390 | |
| 391 | sclk = get_sclk(); |
| 392 | mdc_div = ((sclk / MDC_CLK) / 2) - 1; |
| 393 | |
| 394 | sysctl = bfin_read_EMAC_SYSCTL(); |
| 395 | sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div); |
| 396 | bfin_write_EMAC_SYSCTL(sysctl); |
| 397 | |
| 398 | phydev = phy_find_first(lp->mii_bus); |
| 399 | if (!phydev) { |
| 400 | netdev_err(dev, "no phy device found\n"); |
| 401 | return -ENODEV; |
| 402 | } |
| 403 | |
| 404 | if (phy_mode != PHY_INTERFACE_MODE_RMII && |
| 405 | phy_mode != PHY_INTERFACE_MODE_MII) { |
| 406 | netdev_err(dev, "invalid phy interface mode\n"); |
| 407 | return -EINVAL; |
| 408 | } |
| 409 | |
| 410 | phydev = phy_connect(dev, phydev_name(phydev), |
| 411 | &bfin_mac_adjust_link, phy_mode); |
| 412 | |
| 413 | if (IS_ERR(phydev)) { |
| 414 | netdev_err(dev, "could not attach PHY\n"); |
| 415 | return PTR_ERR(phydev); |
| 416 | } |
| 417 | |
| 418 | /* mask with MAC supported features */ |
| 419 | phydev->supported &= (SUPPORTED_10baseT_Half |
| 420 | | SUPPORTED_10baseT_Full |
| 421 | | SUPPORTED_100baseT_Half |
| 422 | | SUPPORTED_100baseT_Full |
| 423 | | SUPPORTED_Autoneg |
| 424 | | SUPPORTED_Pause | SUPPORTED_Asym_Pause |
| 425 | | SUPPORTED_MII |
| 426 | | SUPPORTED_TP); |
| 427 | |
| 428 | phydev->advertising = phydev->supported; |
| 429 | |
| 430 | lp->old_link = 0; |
| 431 | lp->old_speed = 0; |
| 432 | lp->old_duplex = -1; |
| 433 | |
| 434 | phy_attached_print(phydev, "mdc_clk=%dHz(mdc_div=%d)@sclk=%dMHz)\n", |
| 435 | MDC_CLK, mdc_div, sclk / 1000000); |
| 436 | |
| 437 | return 0; |
| 438 | } |
| 439 | |
| 440 | /* |
| 441 | * Ethtool support |
| 442 | */ |
| 443 | |
| 444 | /* |
| 445 | * interrupt routine for magic packet wakeup |
| 446 | */ |
| 447 | static irqreturn_t bfin_mac_wake_interrupt(int irq, void *dev_id) |
| 448 | { |
| 449 | return IRQ_HANDLED; |
| 450 | } |
| 451 | |
| 452 | static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev, |
| 453 | struct ethtool_drvinfo *info) |
| 454 | { |
| 455 | strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); |
| 456 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); |
| 457 | strlcpy(info->fw_version, "N/A", sizeof(info->fw_version)); |
| 458 | strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info)); |
| 459 | } |
| 460 | |
| 461 | static void bfin_mac_ethtool_getwol(struct net_device *dev, |
| 462 | struct ethtool_wolinfo *wolinfo) |
| 463 | { |
| 464 | struct bfin_mac_local *lp = netdev_priv(dev); |
| 465 | |
| 466 | wolinfo->supported = WAKE_MAGIC; |
| 467 | wolinfo->wolopts = lp->wol; |
| 468 | } |
| 469 | |
| 470 | static int bfin_mac_ethtool_setwol(struct net_device *dev, |
| 471 | struct ethtool_wolinfo *wolinfo) |
| 472 | { |
| 473 | struct bfin_mac_local *lp = netdev_priv(dev); |
| 474 | int rc; |
| 475 | |
| 476 | if (wolinfo->wolopts & (WAKE_MAGICSECURE | |
| 477 | WAKE_UCAST | |
| 478 | WAKE_MCAST | |
| 479 | WAKE_BCAST | |
| 480 | WAKE_ARP)) |
| 481 | return -EOPNOTSUPP; |
| 482 | |
| 483 | lp->wol = wolinfo->wolopts; |
| 484 | |
| 485 | if (lp->wol && !lp->irq_wake_requested) { |
| 486 | /* register wake irq handler */ |
| 487 | rc = request_irq(IRQ_MAC_WAKEDET, bfin_mac_wake_interrupt, |
| 488 | 0, "EMAC_WAKE", dev); |
| 489 | if (rc) |
| 490 | return rc; |
| 491 | lp->irq_wake_requested = true; |
| 492 | } |
| 493 | |
| 494 | if (!lp->wol && lp->irq_wake_requested) { |
| 495 | free_irq(IRQ_MAC_WAKEDET, dev); |
| 496 | lp->irq_wake_requested = false; |
| 497 | } |
| 498 | |
| 499 | /* Make sure the PHY driver doesn't suspend */ |
| 500 | device_init_wakeup(&dev->dev, lp->wol); |
| 501 | |
| 502 | return 0; |
| 503 | } |
| 504 | |
| 505 | #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP |
| 506 | static int bfin_mac_ethtool_get_ts_info(struct net_device *dev, |
| 507 | struct ethtool_ts_info *info) |
| 508 | { |
| 509 | struct bfin_mac_local *lp = netdev_priv(dev); |
| 510 | |
| 511 | info->so_timestamping = |
| 512 | SOF_TIMESTAMPING_TX_HARDWARE | |
| 513 | SOF_TIMESTAMPING_RX_HARDWARE | |
| 514 | SOF_TIMESTAMPING_RAW_HARDWARE; |
| 515 | info->phc_index = lp->phc_index; |
| 516 | info->tx_types = |
| 517 | (1 << HWTSTAMP_TX_OFF) | |
| 518 | (1 << HWTSTAMP_TX_ON); |
| 519 | info->rx_filters = |
| 520 | (1 << HWTSTAMP_FILTER_NONE) | |
| 521 | (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | |
| 522 | (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | |
| 523 | (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); |
| 524 | return 0; |
| 525 | } |
| 526 | #endif |
| 527 | |
| 528 | static const struct ethtool_ops bfin_mac_ethtool_ops = { |
| 529 | .get_link = ethtool_op_get_link, |
| 530 | .get_drvinfo = bfin_mac_ethtool_getdrvinfo, |
| 531 | .get_wol = bfin_mac_ethtool_getwol, |
| 532 | .set_wol = bfin_mac_ethtool_setwol, |
| 533 | #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP |
| 534 | .get_ts_info = bfin_mac_ethtool_get_ts_info, |
| 535 | #endif |
| 536 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
| 537 | .set_link_ksettings = phy_ethtool_set_link_ksettings, |
| 538 | }; |
| 539 | |
| 540 | /**************************************************************************/ |
| 541 | static void setup_system_regs(struct net_device *dev) |
| 542 | { |
| 543 | struct bfin_mac_local *lp = netdev_priv(dev); |
| 544 | int i; |
| 545 | unsigned short sysctl; |
| 546 | |
| 547 | /* |
| 548 | * Odd word alignment for Receive Frame DMA word |
| 549 | * Configure checksum support and rcve frame word alignment |
| 550 | */ |
| 551 | sysctl = bfin_read_EMAC_SYSCTL(); |
| 552 | /* |
| 553 | * check if interrupt is requested for any PHY, |
| 554 | * enable PHY interrupt only if needed |
| 555 | */ |
| 556 | for (i = 0; i < PHY_MAX_ADDR; ++i) |
| 557 | if (lp->mii_bus->irq[i] != PHY_POLL) |
| 558 | break; |
| 559 | if (i < PHY_MAX_ADDR) |
| 560 | sysctl |= PHYIE; |
| 561 | sysctl |= RXDWA; |
| 562 | #if defined(BFIN_MAC_CSUM_OFFLOAD) |
| 563 | sysctl |= RXCKS; |
| 564 | #else |
| 565 | sysctl &= ~RXCKS; |
| 566 | #endif |
| 567 | bfin_write_EMAC_SYSCTL(sysctl); |
| 568 | |
| 569 | bfin_write_EMAC_MMC_CTL(RSTC | CROLL); |
| 570 | |
| 571 | /* Set vlan regs to let 1522 bytes long packets pass through */ |
| 572 | bfin_write_EMAC_VLAN1(lp->vlan1_mask); |
| 573 | bfin_write_EMAC_VLAN2(lp->vlan2_mask); |
| 574 | |
| 575 | /* Initialize the TX DMA channel registers */ |
| 576 | bfin_write_DMA2_X_COUNT(0); |
| 577 | bfin_write_DMA2_X_MODIFY(4); |
| 578 | bfin_write_DMA2_Y_COUNT(0); |
| 579 | bfin_write_DMA2_Y_MODIFY(0); |
| 580 | |
| 581 | /* Initialize the RX DMA channel registers */ |
| 582 | bfin_write_DMA1_X_COUNT(0); |
| 583 | bfin_write_DMA1_X_MODIFY(4); |
| 584 | bfin_write_DMA1_Y_COUNT(0); |
| 585 | bfin_write_DMA1_Y_MODIFY(0); |
| 586 | } |
| 587 | |
| 588 | static void setup_mac_addr(u8 *mac_addr) |
| 589 | { |
| 590 | u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]); |
| 591 | u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]); |
| 592 | |
| 593 | /* this depends on a little-endian machine */ |
| 594 | bfin_write_EMAC_ADDRLO(addr_low); |
| 595 | bfin_write_EMAC_ADDRHI(addr_hi); |
| 596 | } |
| 597 | |
| 598 | static int bfin_mac_set_mac_address(struct net_device *dev, void *p) |
| 599 | { |
| 600 | struct sockaddr *addr = p; |
| 601 | if (netif_running(dev)) |
| 602 | return -EBUSY; |
| 603 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
| 604 | setup_mac_addr(dev->dev_addr); |
| 605 | return 0; |
| 606 | } |
| 607 | |
| 608 | #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP |
| 609 | #define bfin_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE) |
| 610 | |
| 611 | static u32 bfin_select_phc_clock(u32 input_clk, unsigned int *shift_result) |
| 612 | { |
| 613 | u32 ipn = 1000000000UL / input_clk; |
| 614 | u32 ppn = 1; |
| 615 | unsigned int shift = 0; |
| 616 | |
| 617 | while (ppn <= ipn) { |
| 618 | ppn <<= 1; |
| 619 | shift++; |
| 620 | } |
| 621 | *shift_result = shift; |
| 622 | return 1000000000UL / ppn; |
| 623 | } |
| 624 | |
| 625 | static int bfin_mac_hwtstamp_set(struct net_device *netdev, |
| 626 | struct ifreq *ifr) |
| 627 | { |
| 628 | struct hwtstamp_config config; |
| 629 | struct bfin_mac_local *lp = netdev_priv(netdev); |
| 630 | u16 ptpctl; |
| 631 | u32 ptpfv1, ptpfv2, ptpfv3, ptpfoff; |
| 632 | |
| 633 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) |
| 634 | return -EFAULT; |
| 635 | |
| 636 | pr_debug("%s config flag:0x%x, tx_type:0x%x, rx_filter:0x%x\n", |
| 637 | __func__, config.flags, config.tx_type, config.rx_filter); |
| 638 | |
| 639 | /* reserved for future extensions */ |
| 640 | if (config.flags) |
| 641 | return -EINVAL; |
| 642 | |
| 643 | if ((config.tx_type != HWTSTAMP_TX_OFF) && |
| 644 | (config.tx_type != HWTSTAMP_TX_ON)) |
| 645 | return -ERANGE; |
| 646 | |
| 647 | ptpctl = bfin_read_EMAC_PTP_CTL(); |
| 648 | |
| 649 | switch (config.rx_filter) { |
| 650 | case HWTSTAMP_FILTER_NONE: |
| 651 | /* |
| 652 | * Dont allow any timestamping |
| 653 | */ |
| 654 | ptpfv3 = 0xFFFFFFFF; |
| 655 | bfin_write_EMAC_PTP_FV3(ptpfv3); |
| 656 | break; |
| 657 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: |
| 658 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: |
| 659 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: |
| 660 | /* |
| 661 | * Clear the five comparison mask bits (bits[12:8]) in EMAC_PTP_CTL) |
| 662 | * to enable all the field matches. |
| 663 | */ |
| 664 | ptpctl &= ~0x1F00; |
| 665 | bfin_write_EMAC_PTP_CTL(ptpctl); |
| 666 | /* |
| 667 | * Keep the default values of the EMAC_PTP_FOFF register. |
| 668 | */ |
| 669 | ptpfoff = 0x4A24170C; |
| 670 | bfin_write_EMAC_PTP_FOFF(ptpfoff); |
| 671 | /* |
| 672 | * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2 |
| 673 | * registers. |
| 674 | */ |
| 675 | ptpfv1 = 0x11040800; |
| 676 | bfin_write_EMAC_PTP_FV1(ptpfv1); |
| 677 | ptpfv2 = 0x0140013F; |
| 678 | bfin_write_EMAC_PTP_FV2(ptpfv2); |
| 679 | /* |
| 680 | * The default value (0xFFFC) allows the timestamping of both |
| 681 | * received Sync messages and Delay_Req messages. |
| 682 | */ |
| 683 | ptpfv3 = 0xFFFFFFFC; |
| 684 | bfin_write_EMAC_PTP_FV3(ptpfv3); |
| 685 | |
| 686 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; |
| 687 | break; |
| 688 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: |
| 689 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: |
| 690 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: |
| 691 | /* Clear all five comparison mask bits (bits[12:8]) in the |
| 692 | * EMAC_PTP_CTL register to enable all the field matches. |
| 693 | */ |
| 694 | ptpctl &= ~0x1F00; |
| 695 | bfin_write_EMAC_PTP_CTL(ptpctl); |
| 696 | /* |
| 697 | * Keep the default values of the EMAC_PTP_FOFF register, except set |
| 698 | * the PTPCOF field to 0x2A. |
| 699 | */ |
| 700 | ptpfoff = 0x2A24170C; |
| 701 | bfin_write_EMAC_PTP_FOFF(ptpfoff); |
| 702 | /* |
| 703 | * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2 |
| 704 | * registers. |
| 705 | */ |
| 706 | ptpfv1 = 0x11040800; |
| 707 | bfin_write_EMAC_PTP_FV1(ptpfv1); |
| 708 | ptpfv2 = 0x0140013F; |
| 709 | bfin_write_EMAC_PTP_FV2(ptpfv2); |
| 710 | /* |
| 711 | * To allow the timestamping of Pdelay_Req and Pdelay_Resp, set |
| 712 | * the value to 0xFFF0. |
| 713 | */ |
| 714 | ptpfv3 = 0xFFFFFFF0; |
| 715 | bfin_write_EMAC_PTP_FV3(ptpfv3); |
| 716 | |
| 717 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; |
| 718 | break; |
| 719 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: |
| 720 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: |
| 721 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: |
| 722 | /* |
| 723 | * Clear bits 8 and 12 of the EMAC_PTP_CTL register to enable only the |
| 724 | * EFTM and PTPCM field comparison. |
| 725 | */ |
| 726 | ptpctl &= ~0x1100; |
| 727 | bfin_write_EMAC_PTP_CTL(ptpctl); |
| 728 | /* |
| 729 | * Keep the default values of all the fields of the EMAC_PTP_FOFF |
| 730 | * register, except set the PTPCOF field to 0x0E. |
| 731 | */ |
| 732 | ptpfoff = 0x0E24170C; |
| 733 | bfin_write_EMAC_PTP_FOFF(ptpfoff); |
| 734 | /* |
| 735 | * Program bits [15:0] of the EMAC_PTP_FV1 register to 0x88F7, which |
| 736 | * corresponds to PTP messages on the MAC layer. |
| 737 | */ |
| 738 | ptpfv1 = 0x110488F7; |
| 739 | bfin_write_EMAC_PTP_FV1(ptpfv1); |
| 740 | ptpfv2 = 0x0140013F; |
| 741 | bfin_write_EMAC_PTP_FV2(ptpfv2); |
| 742 | /* |
| 743 | * To allow the timestamping of Pdelay_Req and Pdelay_Resp |
| 744 | * messages, set the value to 0xFFF0. |
| 745 | */ |
| 746 | ptpfv3 = 0xFFFFFFF0; |
| 747 | bfin_write_EMAC_PTP_FV3(ptpfv3); |
| 748 | |
| 749 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; |
| 750 | break; |
| 751 | default: |
| 752 | return -ERANGE; |
| 753 | } |
| 754 | |
| 755 | if (config.tx_type == HWTSTAMP_TX_OFF && |
| 756 | bfin_mac_hwtstamp_is_none(config.rx_filter)) { |
| 757 | ptpctl &= ~PTP_EN; |
| 758 | bfin_write_EMAC_PTP_CTL(ptpctl); |
| 759 | |
| 760 | SSYNC(); |
| 761 | } else { |
| 762 | ptpctl |= PTP_EN; |
| 763 | bfin_write_EMAC_PTP_CTL(ptpctl); |
| 764 | |
| 765 | /* |
| 766 | * clear any existing timestamp |
| 767 | */ |
| 768 | bfin_read_EMAC_PTP_RXSNAPLO(); |
| 769 | bfin_read_EMAC_PTP_RXSNAPHI(); |
| 770 | |
| 771 | bfin_read_EMAC_PTP_TXSNAPLO(); |
| 772 | bfin_read_EMAC_PTP_TXSNAPHI(); |
| 773 | |
| 774 | SSYNC(); |
| 775 | } |
| 776 | |
| 777 | lp->stamp_cfg = config; |
| 778 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? |
| 779 | -EFAULT : 0; |
| 780 | } |
| 781 | |
| 782 | static int bfin_mac_hwtstamp_get(struct net_device *netdev, |
| 783 | struct ifreq *ifr) |
| 784 | { |
| 785 | struct bfin_mac_local *lp = netdev_priv(netdev); |
| 786 | |
| 787 | return copy_to_user(ifr->ifr_data, &lp->stamp_cfg, |
| 788 | sizeof(lp->stamp_cfg)) ? |
| 789 | -EFAULT : 0; |
| 790 | } |
| 791 | |
| 792 | static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb) |
| 793 | { |
| 794 | struct bfin_mac_local *lp = netdev_priv(netdev); |
| 795 | |
| 796 | if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { |
| 797 | int timeout_cnt = MAX_TIMEOUT_CNT; |
| 798 | |
| 799 | /* When doing time stamping, keep the connection to the socket |
| 800 | * a while longer |
| 801 | */ |
| 802 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
| 803 | |
| 804 | /* |
| 805 | * The timestamping is done at the EMAC module's MII/RMII interface |
| 806 | * when the module sees the Start of Frame of an event message packet. This |
| 807 | * interface is the closest possible place to the physical Ethernet transmission |
| 808 | * medium, providing the best timing accuracy. |
| 809 | */ |
| 810 | while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt)) |
| 811 | udelay(1); |
| 812 | if (timeout_cnt == 0) |
| 813 | netdev_err(netdev, "timestamp the TX packet failed\n"); |
| 814 | else { |
| 815 | struct skb_shared_hwtstamps shhwtstamps; |
| 816 | u64 ns; |
| 817 | u64 regval; |
| 818 | |
| 819 | regval = bfin_read_EMAC_PTP_TXSNAPLO(); |
| 820 | regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32; |
| 821 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); |
| 822 | ns = regval << lp->shift; |
| 823 | shhwtstamps.hwtstamp = ns_to_ktime(ns); |
| 824 | skb_tstamp_tx(skb, &shhwtstamps); |
| 825 | } |
| 826 | } |
| 827 | } |
| 828 | |
| 829 | static void bfin_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb) |
| 830 | { |
| 831 | struct bfin_mac_local *lp = netdev_priv(netdev); |
| 832 | u32 valid; |
| 833 | u64 regval, ns; |
| 834 | struct skb_shared_hwtstamps *shhwtstamps; |
| 835 | |
| 836 | if (bfin_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter)) |
| 837 | return; |
| 838 | |
| 839 | valid = bfin_read_EMAC_PTP_ISTAT() & RXEL; |
| 840 | if (!valid) |
| 841 | return; |
| 842 | |
| 843 | shhwtstamps = skb_hwtstamps(skb); |
| 844 | |
| 845 | regval = bfin_read_EMAC_PTP_RXSNAPLO(); |
| 846 | regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32; |
| 847 | ns = regval << lp->shift; |
| 848 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); |
| 849 | shhwtstamps->hwtstamp = ns_to_ktime(ns); |
| 850 | } |
| 851 | |
| 852 | static void bfin_mac_hwtstamp_init(struct net_device *netdev) |
| 853 | { |
| 854 | struct bfin_mac_local *lp = netdev_priv(netdev); |
| 855 | u64 addend, ppb; |
| 856 | u32 input_clk, phc_clk; |
| 857 | |
| 858 | /* Initialize hardware timer */ |
| 859 | input_clk = get_sclk(); |
| 860 | phc_clk = bfin_select_phc_clock(input_clk, &lp->shift); |
| 861 | addend = phc_clk * (1ULL << 32); |
| 862 | do_div(addend, input_clk); |
| 863 | bfin_write_EMAC_PTP_ADDEND((u32)addend); |
| 864 | |
| 865 | lp->addend = addend; |
| 866 | ppb = 1000000000ULL * input_clk; |
| 867 | do_div(ppb, phc_clk); |
| 868 | lp->max_ppb = ppb - 1000000000ULL - 1ULL; |
| 869 | |
| 870 | /* Initialize hwstamp config */ |
| 871 | lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE; |
| 872 | lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF; |
| 873 | } |
| 874 | |
| 875 | static u64 bfin_ptp_time_read(struct bfin_mac_local *lp) |
| 876 | { |
| 877 | u64 ns; |
| 878 | u32 lo, hi; |
| 879 | |
| 880 | lo = bfin_read_EMAC_PTP_TIMELO(); |
| 881 | hi = bfin_read_EMAC_PTP_TIMEHI(); |
| 882 | |
| 883 | ns = ((u64) hi) << 32; |
| 884 | ns |= lo; |
| 885 | ns <<= lp->shift; |
| 886 | |
| 887 | return ns; |
| 888 | } |
| 889 | |
| 890 | static void bfin_ptp_time_write(struct bfin_mac_local *lp, u64 ns) |
| 891 | { |
| 892 | u32 hi, lo; |
| 893 | |
| 894 | ns >>= lp->shift; |
| 895 | hi = ns >> 32; |
| 896 | lo = ns & 0xffffffff; |
| 897 | |
| 898 | bfin_write_EMAC_PTP_TIMELO(lo); |
| 899 | bfin_write_EMAC_PTP_TIMEHI(hi); |
| 900 | } |
| 901 | |
| 902 | /* PTP Hardware Clock operations */ |
| 903 | |
| 904 | static int bfin_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) |
| 905 | { |
| 906 | u64 adj; |
| 907 | u32 diff, addend; |
| 908 | int neg_adj = 0; |
| 909 | struct bfin_mac_local *lp = |
| 910 | container_of(ptp, struct bfin_mac_local, caps); |
| 911 | |
| 912 | if (ppb < 0) { |
| 913 | neg_adj = 1; |
| 914 | ppb = -ppb; |
| 915 | } |
| 916 | addend = lp->addend; |
| 917 | adj = addend; |
| 918 | adj *= ppb; |
| 919 | diff = div_u64(adj, 1000000000ULL); |
| 920 | |
| 921 | addend = neg_adj ? addend - diff : addend + diff; |
| 922 | |
| 923 | bfin_write_EMAC_PTP_ADDEND(addend); |
| 924 | |
| 925 | return 0; |
| 926 | } |
| 927 | |
| 928 | static int bfin_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) |
| 929 | { |
| 930 | s64 now; |
| 931 | unsigned long flags; |
| 932 | struct bfin_mac_local *lp = |
| 933 | container_of(ptp, struct bfin_mac_local, caps); |
| 934 | |
| 935 | spin_lock_irqsave(&lp->phc_lock, flags); |
| 936 | |
| 937 | now = bfin_ptp_time_read(lp); |
| 938 | now += delta; |
| 939 | bfin_ptp_time_write(lp, now); |
| 940 | |
| 941 | spin_unlock_irqrestore(&lp->phc_lock, flags); |
| 942 | |
| 943 | return 0; |
| 944 | } |
| 945 | |
| 946 | static int bfin_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) |
| 947 | { |
| 948 | u64 ns; |
| 949 | unsigned long flags; |
| 950 | struct bfin_mac_local *lp = |
| 951 | container_of(ptp, struct bfin_mac_local, caps); |
| 952 | |
| 953 | spin_lock_irqsave(&lp->phc_lock, flags); |
| 954 | |
| 955 | ns = bfin_ptp_time_read(lp); |
| 956 | |
| 957 | spin_unlock_irqrestore(&lp->phc_lock, flags); |
| 958 | |
| 959 | *ts = ns_to_timespec64(ns); |
| 960 | |
| 961 | return 0; |
| 962 | } |
| 963 | |
| 964 | static int bfin_ptp_settime(struct ptp_clock_info *ptp, |
| 965 | const struct timespec64 *ts) |
| 966 | { |
| 967 | u64 ns; |
| 968 | unsigned long flags; |
| 969 | struct bfin_mac_local *lp = |
| 970 | container_of(ptp, struct bfin_mac_local, caps); |
| 971 | |
| 972 | ns = timespec64_to_ns(ts); |
| 973 | |
| 974 | spin_lock_irqsave(&lp->phc_lock, flags); |
| 975 | |
| 976 | bfin_ptp_time_write(lp, ns); |
| 977 | |
| 978 | spin_unlock_irqrestore(&lp->phc_lock, flags); |
| 979 | |
| 980 | return 0; |
| 981 | } |
| 982 | |
| 983 | static int bfin_ptp_enable(struct ptp_clock_info *ptp, |
| 984 | struct ptp_clock_request *rq, int on) |
| 985 | { |
| 986 | return -EOPNOTSUPP; |
| 987 | } |
| 988 | |
| 989 | static struct ptp_clock_info bfin_ptp_caps = { |
| 990 | .owner = THIS_MODULE, |
| 991 | .name = "BF518 clock", |
| 992 | .max_adj = 0, |
| 993 | .n_alarm = 0, |
| 994 | .n_ext_ts = 0, |
| 995 | .n_per_out = 0, |
| 996 | .n_pins = 0, |
| 997 | .pps = 0, |
| 998 | .adjfreq = bfin_ptp_adjfreq, |
| 999 | .adjtime = bfin_ptp_adjtime, |
| 1000 | .gettime64 = bfin_ptp_gettime, |
| 1001 | .settime64 = bfin_ptp_settime, |
| 1002 | .enable = bfin_ptp_enable, |
| 1003 | }; |
| 1004 | |
| 1005 | static int bfin_phc_init(struct net_device *netdev, struct device *dev) |
| 1006 | { |
| 1007 | struct bfin_mac_local *lp = netdev_priv(netdev); |
| 1008 | |
| 1009 | lp->caps = bfin_ptp_caps; |
| 1010 | lp->caps.max_adj = lp->max_ppb; |
| 1011 | lp->clock = ptp_clock_register(&lp->caps, dev); |
| 1012 | if (IS_ERR(lp->clock)) |
| 1013 | return PTR_ERR(lp->clock); |
| 1014 | |
| 1015 | lp->phc_index = ptp_clock_index(lp->clock); |
| 1016 | spin_lock_init(&lp->phc_lock); |
| 1017 | |
| 1018 | return 0; |
| 1019 | } |
| 1020 | |
| 1021 | static void bfin_phc_release(struct bfin_mac_local *lp) |
| 1022 | { |
| 1023 | ptp_clock_unregister(lp->clock); |
| 1024 | } |
| 1025 | |
| 1026 | #else |
| 1027 | # define bfin_mac_hwtstamp_is_none(cfg) 0 |
| 1028 | # define bfin_mac_hwtstamp_init(dev) |
| 1029 | # define bfin_mac_hwtstamp_set(dev, ifr) (-EOPNOTSUPP) |
| 1030 | # define bfin_mac_hwtstamp_get(dev, ifr) (-EOPNOTSUPP) |
| 1031 | # define bfin_rx_hwtstamp(dev, skb) |
| 1032 | # define bfin_tx_hwtstamp(dev, skb) |
| 1033 | # define bfin_phc_init(netdev, dev) 0 |
| 1034 | # define bfin_phc_release(lp) |
| 1035 | #endif |
| 1036 | |
| 1037 | static inline void _tx_reclaim_skb(void) |
| 1038 | { |
| 1039 | do { |
| 1040 | tx_list_head->desc_a.config &= ~DMAEN; |
| 1041 | tx_list_head->status.status_word = 0; |
| 1042 | if (tx_list_head->skb) { |
| 1043 | dev_consume_skb_any(tx_list_head->skb); |
| 1044 | tx_list_head->skb = NULL; |
| 1045 | } |
| 1046 | tx_list_head = tx_list_head->next; |
| 1047 | |
| 1048 | } while (tx_list_head->status.status_word != 0); |
| 1049 | } |
| 1050 | |
| 1051 | static void tx_reclaim_skb(struct bfin_mac_local *lp) |
| 1052 | { |
| 1053 | int timeout_cnt = MAX_TIMEOUT_CNT; |
| 1054 | |
| 1055 | if (tx_list_head->status.status_word != 0) |
| 1056 | _tx_reclaim_skb(); |
| 1057 | |
| 1058 | if (current_tx_ptr->next == tx_list_head) { |
| 1059 | while (tx_list_head->status.status_word == 0) { |
| 1060 | /* slow down polling to avoid too many queue stop. */ |
| 1061 | udelay(10); |
| 1062 | /* reclaim skb if DMA is not running. */ |
| 1063 | if (!(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)) |
| 1064 | break; |
| 1065 | if (timeout_cnt-- < 0) |
| 1066 | break; |
| 1067 | } |
| 1068 | |
| 1069 | if (timeout_cnt >= 0) |
| 1070 | _tx_reclaim_skb(); |
| 1071 | else |
| 1072 | netif_stop_queue(lp->ndev); |
| 1073 | } |
| 1074 | |
| 1075 | if (current_tx_ptr->next != tx_list_head && |
| 1076 | netif_queue_stopped(lp->ndev)) |
| 1077 | netif_wake_queue(lp->ndev); |
| 1078 | |
| 1079 | if (tx_list_head != current_tx_ptr) { |
| 1080 | /* shorten the timer interval if tx queue is stopped */ |
| 1081 | if (netif_queue_stopped(lp->ndev)) |
| 1082 | lp->tx_reclaim_timer.expires = |
| 1083 | jiffies + (TX_RECLAIM_JIFFIES >> 4); |
| 1084 | else |
| 1085 | lp->tx_reclaim_timer.expires = |
| 1086 | jiffies + TX_RECLAIM_JIFFIES; |
| 1087 | |
| 1088 | mod_timer(&lp->tx_reclaim_timer, |
| 1089 | lp->tx_reclaim_timer.expires); |
| 1090 | } |
| 1091 | |
| 1092 | return; |
| 1093 | } |
| 1094 | |
| 1095 | static void tx_reclaim_skb_timeout(unsigned long lp) |
| 1096 | { |
| 1097 | tx_reclaim_skb((struct bfin_mac_local *)lp); |
| 1098 | } |
| 1099 | |
| 1100 | static int bfin_mac_hard_start_xmit(struct sk_buff *skb, |
| 1101 | struct net_device *dev) |
| 1102 | { |
| 1103 | struct bfin_mac_local *lp = netdev_priv(dev); |
| 1104 | u16 *data; |
| 1105 | u32 data_align = (unsigned long)(skb->data) & 0x3; |
| 1106 | |
| 1107 | current_tx_ptr->skb = skb; |
| 1108 | |
| 1109 | if (data_align == 0x2) { |
| 1110 | /* move skb->data to current_tx_ptr payload */ |
| 1111 | data = (u16 *)(skb->data) - 1; |
| 1112 | *data = (u16)(skb->len); |
| 1113 | /* |
| 1114 | * When transmitting an Ethernet packet, the PTP_TSYNC module requires |
| 1115 | * a DMA_Length_Word field associated with the packet. The lower 12 bits |
| 1116 | * of this field are the length of the packet payload in bytes and the higher |
| 1117 | * 4 bits are the timestamping enable field. |
| 1118 | */ |
| 1119 | if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) |
| 1120 | *data |= 0x1000; |
| 1121 | |
| 1122 | current_tx_ptr->desc_a.start_addr = (u32)data; |
| 1123 | /* this is important! */ |
| 1124 | blackfin_dcache_flush_range((u32)data, |
| 1125 | (u32)((u8 *)data + skb->len + 4)); |
| 1126 | } else { |
| 1127 | *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len); |
| 1128 | /* enable timestamping for the sent packet */ |
| 1129 | if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) |
| 1130 | *((u16 *)(current_tx_ptr->packet)) |= 0x1000; |
| 1131 | memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data, |
| 1132 | skb->len); |
| 1133 | current_tx_ptr->desc_a.start_addr = |
| 1134 | (u32)current_tx_ptr->packet; |
| 1135 | blackfin_dcache_flush_range( |
| 1136 | (u32)current_tx_ptr->packet, |
| 1137 | (u32)(current_tx_ptr->packet + skb->len + 2)); |
| 1138 | } |
| 1139 | |
| 1140 | /* make sure the internal data buffers in the core are drained |
| 1141 | * so that the DMA descriptors are completely written when the |
| 1142 | * DMA engine goes to fetch them below |
| 1143 | */ |
| 1144 | SSYNC(); |
| 1145 | |
| 1146 | /* always clear status buffer before start tx dma */ |
| 1147 | current_tx_ptr->status.status_word = 0; |
| 1148 | |
| 1149 | /* enable this packet's dma */ |
| 1150 | current_tx_ptr->desc_a.config |= DMAEN; |
| 1151 | |
| 1152 | /* tx dma is running, just return */ |
| 1153 | if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN) |
| 1154 | goto out; |
| 1155 | |
| 1156 | /* tx dma is not running */ |
| 1157 | bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a)); |
| 1158 | /* dma enabled, read from memory, size is 6 */ |
| 1159 | bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config); |
| 1160 | /* Turn on the EMAC tx */ |
| 1161 | bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE); |
| 1162 | |
| 1163 | out: |
| 1164 | bfin_tx_hwtstamp(dev, skb); |
| 1165 | |
| 1166 | current_tx_ptr = current_tx_ptr->next; |
| 1167 | dev->stats.tx_packets++; |
| 1168 | dev->stats.tx_bytes += (skb->len); |
| 1169 | |
| 1170 | tx_reclaim_skb(lp); |
| 1171 | |
| 1172 | return NETDEV_TX_OK; |
| 1173 | } |
| 1174 | |
| 1175 | #define IP_HEADER_OFF 0 |
| 1176 | #define RX_ERROR_MASK (RX_LONG | RX_ALIGN | RX_CRC | RX_LEN | \ |
| 1177 | RX_FRAG | RX_ADDR | RX_DMAO | RX_PHY | RX_LATE | RX_RANGE) |
| 1178 | |
| 1179 | static void bfin_mac_rx(struct bfin_mac_local *lp) |
| 1180 | { |
| 1181 | struct net_device *dev = lp->ndev; |
| 1182 | struct sk_buff *skb, *new_skb; |
| 1183 | unsigned short len; |
| 1184 | #if defined(BFIN_MAC_CSUM_OFFLOAD) |
| 1185 | unsigned int i; |
| 1186 | unsigned char fcs[ETH_FCS_LEN + 1]; |
| 1187 | #endif |
| 1188 | |
| 1189 | /* check if frame status word reports an error condition |
| 1190 | * we which case we simply drop the packet |
| 1191 | */ |
| 1192 | if (current_rx_ptr->status.status_word & RX_ERROR_MASK) { |
| 1193 | netdev_notice(dev, "rx: receive error - packet dropped\n"); |
| 1194 | dev->stats.rx_dropped++; |
| 1195 | goto out; |
| 1196 | } |
| 1197 | |
| 1198 | /* allocate a new skb for next time receive */ |
| 1199 | skb = current_rx_ptr->skb; |
| 1200 | |
| 1201 | new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN); |
| 1202 | if (!new_skb) { |
| 1203 | dev->stats.rx_dropped++; |
| 1204 | goto out; |
| 1205 | } |
| 1206 | /* reserve 2 bytes for RXDWA padding */ |
| 1207 | skb_reserve(new_skb, NET_IP_ALIGN); |
| 1208 | /* Invidate the data cache of skb->data range when it is write back |
| 1209 | * cache. It will prevent overwritting the new data from DMA |
| 1210 | */ |
| 1211 | blackfin_dcache_invalidate_range((unsigned long)new_skb->head, |
| 1212 | (unsigned long)new_skb->end); |
| 1213 | |
| 1214 | current_rx_ptr->skb = new_skb; |
| 1215 | current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2; |
| 1216 | |
| 1217 | len = (unsigned short)(current_rx_ptr->status.status_word & RX_FRLEN); |
| 1218 | /* Deduce Ethernet FCS length from Ethernet payload length */ |
| 1219 | len -= ETH_FCS_LEN; |
| 1220 | skb_put(skb, len); |
| 1221 | |
| 1222 | skb->protocol = eth_type_trans(skb, dev); |
| 1223 | |
| 1224 | bfin_rx_hwtstamp(dev, skb); |
| 1225 | |
| 1226 | #if defined(BFIN_MAC_CSUM_OFFLOAD) |
| 1227 | /* Checksum offloading only works for IPv4 packets with the standard IP header |
| 1228 | * length of 20 bytes, because the blackfin MAC checksum calculation is |
| 1229 | * based on that assumption. We must NOT use the calculated checksum if our |
| 1230 | * IP version or header break that assumption. |
| 1231 | */ |
| 1232 | if (skb->data[IP_HEADER_OFF] == 0x45) { |
| 1233 | skb->csum = current_rx_ptr->status.ip_payload_csum; |
| 1234 | /* |
| 1235 | * Deduce Ethernet FCS from hardware generated IP payload checksum. |
| 1236 | * IP checksum is based on 16-bit one's complement algorithm. |
| 1237 | * To deduce a value from checksum is equal to add its inversion. |
| 1238 | * If the IP payload len is odd, the inversed FCS should also |
| 1239 | * begin from odd address and leave first byte zero. |
| 1240 | */ |
| 1241 | if (skb->len % 2) { |
| 1242 | fcs[0] = 0; |
| 1243 | for (i = 0; i < ETH_FCS_LEN; i++) |
| 1244 | fcs[i + 1] = ~skb->data[skb->len + i]; |
| 1245 | skb->csum = csum_partial(fcs, ETH_FCS_LEN + 1, skb->csum); |
| 1246 | } else { |
| 1247 | for (i = 0; i < ETH_FCS_LEN; i++) |
| 1248 | fcs[i] = ~skb->data[skb->len + i]; |
| 1249 | skb->csum = csum_partial(fcs, ETH_FCS_LEN, skb->csum); |
| 1250 | } |
| 1251 | skb->ip_summed = CHECKSUM_COMPLETE; |
| 1252 | } |
| 1253 | #endif |
| 1254 | |
| 1255 | napi_gro_receive(&lp->napi, skb); |
| 1256 | |
| 1257 | dev->stats.rx_packets++; |
| 1258 | dev->stats.rx_bytes += len; |
| 1259 | out: |
| 1260 | current_rx_ptr->status.status_word = 0x00000000; |
| 1261 | current_rx_ptr = current_rx_ptr->next; |
| 1262 | } |
| 1263 | |
| 1264 | static int bfin_mac_poll(struct napi_struct *napi, int budget) |
| 1265 | { |
| 1266 | int i = 0; |
| 1267 | struct bfin_mac_local *lp = container_of(napi, |
| 1268 | struct bfin_mac_local, |
| 1269 | napi); |
| 1270 | |
| 1271 | while (current_rx_ptr->status.status_word != 0 && i < budget) { |
| 1272 | bfin_mac_rx(lp); |
| 1273 | i++; |
| 1274 | } |
| 1275 | |
| 1276 | if (i < budget) { |
| 1277 | napi_complete(napi); |
| 1278 | if (test_and_clear_bit(BFIN_MAC_RX_IRQ_DISABLED, &lp->flags)) |
| 1279 | enable_irq(IRQ_MAC_RX); |
| 1280 | } |
| 1281 | |
| 1282 | return i; |
| 1283 | } |
| 1284 | |
| 1285 | /* interrupt routine to handle rx and error signal */ |
| 1286 | static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id) |
| 1287 | { |
| 1288 | struct bfin_mac_local *lp = netdev_priv(dev_id); |
| 1289 | u32 status; |
| 1290 | |
| 1291 | status = bfin_read_DMA1_IRQ_STATUS(); |
| 1292 | |
| 1293 | bfin_write_DMA1_IRQ_STATUS(status | DMA_DONE | DMA_ERR); |
| 1294 | if (status & DMA_DONE) { |
| 1295 | disable_irq_nosync(IRQ_MAC_RX); |
| 1296 | set_bit(BFIN_MAC_RX_IRQ_DISABLED, &lp->flags); |
| 1297 | napi_schedule(&lp->napi); |
| 1298 | } |
| 1299 | |
| 1300 | return IRQ_HANDLED; |
| 1301 | } |
| 1302 | |
| 1303 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 1304 | static void bfin_mac_poll_controller(struct net_device *dev) |
| 1305 | { |
| 1306 | struct bfin_mac_local *lp = netdev_priv(dev); |
| 1307 | |
| 1308 | bfin_mac_interrupt(IRQ_MAC_RX, dev); |
| 1309 | tx_reclaim_skb(lp); |
| 1310 | } |
| 1311 | #endif /* CONFIG_NET_POLL_CONTROLLER */ |
| 1312 | |
| 1313 | static void bfin_mac_disable(void) |
| 1314 | { |
| 1315 | unsigned int opmode; |
| 1316 | |
| 1317 | opmode = bfin_read_EMAC_OPMODE(); |
| 1318 | opmode &= (~RE); |
| 1319 | opmode &= (~TE); |
| 1320 | /* Turn off the EMAC */ |
| 1321 | bfin_write_EMAC_OPMODE(opmode); |
| 1322 | } |
| 1323 | |
| 1324 | /* |
| 1325 | * Enable Interrupts, Receive, and Transmit |
| 1326 | */ |
| 1327 | static int bfin_mac_enable(struct phy_device *phydev) |
| 1328 | { |
| 1329 | int ret; |
| 1330 | u32 opmode; |
| 1331 | |
| 1332 | pr_debug("%s\n", __func__); |
| 1333 | |
| 1334 | /* Set RX DMA */ |
| 1335 | bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a)); |
| 1336 | bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config); |
| 1337 | |
| 1338 | /* Wait MII done */ |
| 1339 | ret = bfin_mdio_poll(); |
| 1340 | if (ret) |
| 1341 | return ret; |
| 1342 | |
| 1343 | /* We enable only RX here */ |
| 1344 | /* ASTP : Enable Automatic Pad Stripping |
| 1345 | PR : Promiscuous Mode for test |
| 1346 | PSF : Receive frames with total length less than 64 bytes. |
| 1347 | FDMODE : Full Duplex Mode |
| 1348 | LB : Internal Loopback for test |
| 1349 | RE : Receiver Enable */ |
| 1350 | opmode = bfin_read_EMAC_OPMODE(); |
| 1351 | if (opmode & FDMODE) |
| 1352 | opmode |= PSF; |
| 1353 | else |
| 1354 | opmode |= DRO | DC | PSF; |
| 1355 | opmode |= RE; |
| 1356 | |
| 1357 | if (phydev->interface == PHY_INTERFACE_MODE_RMII) { |
| 1358 | opmode |= RMII; /* For Now only 100MBit are supported */ |
| 1359 | #if defined(CONFIG_BF537) || defined(CONFIG_BF536) |
| 1360 | if (__SILICON_REVISION__ < 3) { |
| 1361 | /* |
| 1362 | * This isn't publicly documented (fun times!), but in |
| 1363 | * silicon <=0.2, the RX and TX pins are clocked together. |
| 1364 | * So in order to recv, we must enable the transmit side |
| 1365 | * as well. This will cause a spurious TX interrupt too, |
| 1366 | * but we can easily consume that. |
| 1367 | */ |
| 1368 | opmode |= TE; |
| 1369 | } |
| 1370 | #endif |
| 1371 | } |
| 1372 | |
| 1373 | /* Turn on the EMAC rx */ |
| 1374 | bfin_write_EMAC_OPMODE(opmode); |
| 1375 | |
| 1376 | return 0; |
| 1377 | } |
| 1378 | |
| 1379 | /* Our watchdog timed out. Called by the networking layer */ |
| 1380 | static void bfin_mac_timeout(struct net_device *dev) |
| 1381 | { |
| 1382 | struct bfin_mac_local *lp = netdev_priv(dev); |
| 1383 | |
| 1384 | pr_debug("%s: %s\n", dev->name, __func__); |
| 1385 | |
| 1386 | bfin_mac_disable(); |
| 1387 | |
| 1388 | del_timer(&lp->tx_reclaim_timer); |
| 1389 | |
| 1390 | /* reset tx queue and free skb */ |
| 1391 | while (tx_list_head != current_tx_ptr) { |
| 1392 | tx_list_head->desc_a.config &= ~DMAEN; |
| 1393 | tx_list_head->status.status_word = 0; |
| 1394 | if (tx_list_head->skb) { |
| 1395 | dev_kfree_skb(tx_list_head->skb); |
| 1396 | tx_list_head->skb = NULL; |
| 1397 | } |
| 1398 | tx_list_head = tx_list_head->next; |
| 1399 | } |
| 1400 | |
| 1401 | if (netif_queue_stopped(dev)) |
| 1402 | netif_wake_queue(dev); |
| 1403 | |
| 1404 | bfin_mac_enable(dev->phydev); |
| 1405 | |
| 1406 | /* We can accept TX packets again */ |
| 1407 | netif_trans_update(dev); /* prevent tx timeout */ |
| 1408 | } |
| 1409 | |
| 1410 | static void bfin_mac_multicast_hash(struct net_device *dev) |
| 1411 | { |
| 1412 | u32 emac_hashhi, emac_hashlo; |
| 1413 | struct netdev_hw_addr *ha; |
| 1414 | u32 crc; |
| 1415 | |
| 1416 | emac_hashhi = emac_hashlo = 0; |
| 1417 | |
| 1418 | netdev_for_each_mc_addr(ha, dev) { |
| 1419 | crc = ether_crc(ETH_ALEN, ha->addr); |
| 1420 | crc >>= 26; |
| 1421 | |
| 1422 | if (crc & 0x20) |
| 1423 | emac_hashhi |= 1 << (crc & 0x1f); |
| 1424 | else |
| 1425 | emac_hashlo |= 1 << (crc & 0x1f); |
| 1426 | } |
| 1427 | |
| 1428 | bfin_write_EMAC_HASHHI(emac_hashhi); |
| 1429 | bfin_write_EMAC_HASHLO(emac_hashlo); |
| 1430 | } |
| 1431 | |
| 1432 | /* |
| 1433 | * This routine will, depending on the values passed to it, |
| 1434 | * either make it accept multicast packets, go into |
| 1435 | * promiscuous mode (for TCPDUMP and cousins) or accept |
| 1436 | * a select set of multicast packets |
| 1437 | */ |
| 1438 | static void bfin_mac_set_multicast_list(struct net_device *dev) |
| 1439 | { |
| 1440 | u32 sysctl; |
| 1441 | |
| 1442 | if (dev->flags & IFF_PROMISC) { |
| 1443 | netdev_info(dev, "set promisc mode\n"); |
| 1444 | sysctl = bfin_read_EMAC_OPMODE(); |
| 1445 | sysctl |= PR; |
| 1446 | bfin_write_EMAC_OPMODE(sysctl); |
| 1447 | } else if (dev->flags & IFF_ALLMULTI) { |
| 1448 | /* accept all multicast */ |
| 1449 | sysctl = bfin_read_EMAC_OPMODE(); |
| 1450 | sysctl |= PAM; |
| 1451 | bfin_write_EMAC_OPMODE(sysctl); |
| 1452 | } else if (!netdev_mc_empty(dev)) { |
| 1453 | /* set up multicast hash table */ |
| 1454 | sysctl = bfin_read_EMAC_OPMODE(); |
| 1455 | sysctl |= HM; |
| 1456 | bfin_write_EMAC_OPMODE(sysctl); |
| 1457 | bfin_mac_multicast_hash(dev); |
| 1458 | } else { |
| 1459 | /* clear promisc or multicast mode */ |
| 1460 | sysctl = bfin_read_EMAC_OPMODE(); |
| 1461 | sysctl &= ~(RAF | PAM); |
| 1462 | bfin_write_EMAC_OPMODE(sysctl); |
| 1463 | } |
| 1464 | } |
| 1465 | |
| 1466 | static int bfin_mac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) |
| 1467 | { |
| 1468 | if (!netif_running(netdev)) |
| 1469 | return -EINVAL; |
| 1470 | |
| 1471 | switch (cmd) { |
| 1472 | case SIOCSHWTSTAMP: |
| 1473 | return bfin_mac_hwtstamp_set(netdev, ifr); |
| 1474 | case SIOCGHWTSTAMP: |
| 1475 | return bfin_mac_hwtstamp_get(netdev, ifr); |
| 1476 | default: |
| 1477 | if (netdev->phydev) |
| 1478 | return phy_mii_ioctl(netdev->phydev, ifr, cmd); |
| 1479 | else |
| 1480 | return -EOPNOTSUPP; |
| 1481 | } |
| 1482 | } |
| 1483 | |
| 1484 | /* |
| 1485 | * this puts the device in an inactive state |
| 1486 | */ |
| 1487 | static void bfin_mac_shutdown(struct net_device *dev) |
| 1488 | { |
| 1489 | /* Turn off the EMAC */ |
| 1490 | bfin_write_EMAC_OPMODE(0x00000000); |
| 1491 | /* Turn off the EMAC RX DMA */ |
| 1492 | bfin_write_DMA1_CONFIG(0x0000); |
| 1493 | bfin_write_DMA2_CONFIG(0x0000); |
| 1494 | } |
| 1495 | |
| 1496 | /* |
| 1497 | * Open and Initialize the interface |
| 1498 | * |
| 1499 | * Set up everything, reset the card, etc.. |
| 1500 | */ |
| 1501 | static int bfin_mac_open(struct net_device *dev) |
| 1502 | { |
| 1503 | struct bfin_mac_local *lp = netdev_priv(dev); |
| 1504 | int ret; |
| 1505 | pr_debug("%s: %s\n", dev->name, __func__); |
| 1506 | |
| 1507 | /* |
| 1508 | * Check that the address is valid. If its not, refuse |
| 1509 | * to bring the device up. The user must specify an |
| 1510 | * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx |
| 1511 | */ |
| 1512 | if (!is_valid_ether_addr(dev->dev_addr)) { |
| 1513 | netdev_warn(dev, "no valid ethernet hw addr\n"); |
| 1514 | return -EINVAL; |
| 1515 | } |
| 1516 | |
| 1517 | /* initial rx and tx list */ |
| 1518 | ret = desc_list_init(dev); |
| 1519 | if (ret) |
| 1520 | return ret; |
| 1521 | |
| 1522 | phy_start(dev->phydev); |
| 1523 | setup_system_regs(dev); |
| 1524 | setup_mac_addr(dev->dev_addr); |
| 1525 | |
| 1526 | bfin_mac_disable(); |
| 1527 | ret = bfin_mac_enable(dev->phydev); |
| 1528 | if (ret) |
| 1529 | return ret; |
| 1530 | pr_debug("hardware init finished\n"); |
| 1531 | |
| 1532 | napi_enable(&lp->napi); |
| 1533 | netif_start_queue(dev); |
| 1534 | netif_carrier_on(dev); |
| 1535 | |
| 1536 | return 0; |
| 1537 | } |
| 1538 | |
| 1539 | /* |
| 1540 | * this makes the board clean up everything that it can |
| 1541 | * and not talk to the outside world. Caused by |
| 1542 | * an 'ifconfig ethX down' |
| 1543 | */ |
| 1544 | static int bfin_mac_close(struct net_device *dev) |
| 1545 | { |
| 1546 | struct bfin_mac_local *lp = netdev_priv(dev); |
| 1547 | pr_debug("%s: %s\n", dev->name, __func__); |
| 1548 | |
| 1549 | netif_stop_queue(dev); |
| 1550 | napi_disable(&lp->napi); |
| 1551 | netif_carrier_off(dev); |
| 1552 | |
| 1553 | phy_stop(dev->phydev); |
| 1554 | phy_write(dev->phydev, MII_BMCR, BMCR_PDOWN); |
| 1555 | |
| 1556 | /* clear everything */ |
| 1557 | bfin_mac_shutdown(dev); |
| 1558 | |
| 1559 | /* free the rx/tx buffers */ |
| 1560 | desc_list_free(); |
| 1561 | |
| 1562 | return 0; |
| 1563 | } |
| 1564 | |
| 1565 | static const struct net_device_ops bfin_mac_netdev_ops = { |
| 1566 | .ndo_open = bfin_mac_open, |
| 1567 | .ndo_stop = bfin_mac_close, |
| 1568 | .ndo_start_xmit = bfin_mac_hard_start_xmit, |
| 1569 | .ndo_set_mac_address = bfin_mac_set_mac_address, |
| 1570 | .ndo_tx_timeout = bfin_mac_timeout, |
| 1571 | .ndo_set_rx_mode = bfin_mac_set_multicast_list, |
| 1572 | .ndo_do_ioctl = bfin_mac_ioctl, |
| 1573 | .ndo_validate_addr = eth_validate_addr, |
| 1574 | .ndo_change_mtu = eth_change_mtu, |
| 1575 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 1576 | .ndo_poll_controller = bfin_mac_poll_controller, |
| 1577 | #endif |
| 1578 | }; |
| 1579 | |
| 1580 | static int bfin_mac_probe(struct platform_device *pdev) |
| 1581 | { |
| 1582 | struct net_device *ndev; |
| 1583 | struct bfin_mac_local *lp; |
| 1584 | struct platform_device *pd; |
| 1585 | struct bfin_mii_bus_platform_data *mii_bus_data; |
| 1586 | int rc; |
| 1587 | |
| 1588 | ndev = alloc_etherdev(sizeof(struct bfin_mac_local)); |
| 1589 | if (!ndev) |
| 1590 | return -ENOMEM; |
| 1591 | |
| 1592 | SET_NETDEV_DEV(ndev, &pdev->dev); |
| 1593 | platform_set_drvdata(pdev, ndev); |
| 1594 | lp = netdev_priv(ndev); |
| 1595 | lp->ndev = ndev; |
| 1596 | |
| 1597 | /* Grab the MAC address in the MAC */ |
| 1598 | *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO()); |
| 1599 | *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI()); |
| 1600 | |
| 1601 | /* probe mac */ |
| 1602 | /*todo: how to proble? which is revision_register */ |
| 1603 | bfin_write_EMAC_ADDRLO(0x12345678); |
| 1604 | if (bfin_read_EMAC_ADDRLO() != 0x12345678) { |
| 1605 | dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n"); |
| 1606 | rc = -ENODEV; |
| 1607 | goto out_err_probe_mac; |
| 1608 | } |
| 1609 | |
| 1610 | |
| 1611 | /* |
| 1612 | * Is it valid? (Did bootloader initialize it?) |
| 1613 | * Grab the MAC from the board somehow |
| 1614 | * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c |
| 1615 | */ |
| 1616 | if (!is_valid_ether_addr(ndev->dev_addr)) { |
| 1617 | if (bfin_get_ether_addr(ndev->dev_addr) || |
| 1618 | !is_valid_ether_addr(ndev->dev_addr)) { |
| 1619 | /* Still not valid, get a random one */ |
| 1620 | netdev_warn(ndev, "Setting Ethernet MAC to a random one\n"); |
| 1621 | eth_hw_addr_random(ndev); |
| 1622 | } |
| 1623 | } |
| 1624 | |
| 1625 | setup_mac_addr(ndev->dev_addr); |
| 1626 | |
| 1627 | if (!dev_get_platdata(&pdev->dev)) { |
| 1628 | dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n"); |
| 1629 | rc = -ENODEV; |
| 1630 | goto out_err_probe_mac; |
| 1631 | } |
| 1632 | pd = dev_get_platdata(&pdev->dev); |
| 1633 | lp->mii_bus = platform_get_drvdata(pd); |
| 1634 | if (!lp->mii_bus) { |
| 1635 | dev_err(&pdev->dev, "Cannot get mii_bus!\n"); |
| 1636 | rc = -ENODEV; |
| 1637 | goto out_err_probe_mac; |
| 1638 | } |
| 1639 | lp->mii_bus->priv = ndev; |
| 1640 | mii_bus_data = dev_get_platdata(&pd->dev); |
| 1641 | |
| 1642 | rc = mii_probe(ndev, mii_bus_data->phy_mode); |
| 1643 | if (rc) { |
| 1644 | dev_err(&pdev->dev, "MII Probe failed!\n"); |
| 1645 | goto out_err_mii_probe; |
| 1646 | } |
| 1647 | |
| 1648 | lp->vlan1_mask = ETH_P_8021Q | mii_bus_data->vlan1_mask; |
| 1649 | lp->vlan2_mask = ETH_P_8021Q | mii_bus_data->vlan2_mask; |
| 1650 | |
| 1651 | ndev->netdev_ops = &bfin_mac_netdev_ops; |
| 1652 | ndev->ethtool_ops = &bfin_mac_ethtool_ops; |
| 1653 | |
| 1654 | init_timer(&lp->tx_reclaim_timer); |
| 1655 | lp->tx_reclaim_timer.data = (unsigned long)lp; |
| 1656 | lp->tx_reclaim_timer.function = tx_reclaim_skb_timeout; |
| 1657 | |
| 1658 | lp->flags = 0; |
| 1659 | netif_napi_add(ndev, &lp->napi, bfin_mac_poll, CONFIG_BFIN_RX_DESC_NUM); |
| 1660 | |
| 1661 | spin_lock_init(&lp->lock); |
| 1662 | |
| 1663 | /* now, enable interrupts */ |
| 1664 | /* register irq handler */ |
| 1665 | rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt, |
| 1666 | 0, "EMAC_RX", ndev); |
| 1667 | if (rc) { |
| 1668 | dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n"); |
| 1669 | rc = -EBUSY; |
| 1670 | goto out_err_request_irq; |
| 1671 | } |
| 1672 | |
| 1673 | rc = register_netdev(ndev); |
| 1674 | if (rc) { |
| 1675 | dev_err(&pdev->dev, "Cannot register net device!\n"); |
| 1676 | goto out_err_reg_ndev; |
| 1677 | } |
| 1678 | |
| 1679 | bfin_mac_hwtstamp_init(ndev); |
| 1680 | rc = bfin_phc_init(ndev, &pdev->dev); |
| 1681 | if (rc) { |
| 1682 | dev_err(&pdev->dev, "Cannot register PHC device!\n"); |
| 1683 | goto out_err_phc; |
| 1684 | } |
| 1685 | |
| 1686 | /* now, print out the card info, in a short format.. */ |
| 1687 | netdev_info(ndev, "%s, Version %s\n", DRV_DESC, DRV_VERSION); |
| 1688 | |
| 1689 | return 0; |
| 1690 | |
| 1691 | out_err_phc: |
| 1692 | out_err_reg_ndev: |
| 1693 | free_irq(IRQ_MAC_RX, ndev); |
| 1694 | out_err_request_irq: |
| 1695 | netif_napi_del(&lp->napi); |
| 1696 | out_err_mii_probe: |
| 1697 | mdiobus_unregister(lp->mii_bus); |
| 1698 | mdiobus_free(lp->mii_bus); |
| 1699 | out_err_probe_mac: |
| 1700 | free_netdev(ndev); |
| 1701 | |
| 1702 | return rc; |
| 1703 | } |
| 1704 | |
| 1705 | static int bfin_mac_remove(struct platform_device *pdev) |
| 1706 | { |
| 1707 | struct net_device *ndev = platform_get_drvdata(pdev); |
| 1708 | struct bfin_mac_local *lp = netdev_priv(ndev); |
| 1709 | |
| 1710 | bfin_phc_release(lp); |
| 1711 | |
| 1712 | lp->mii_bus->priv = NULL; |
| 1713 | |
| 1714 | unregister_netdev(ndev); |
| 1715 | |
| 1716 | netif_napi_del(&lp->napi); |
| 1717 | |
| 1718 | free_irq(IRQ_MAC_RX, ndev); |
| 1719 | |
| 1720 | free_netdev(ndev); |
| 1721 | |
| 1722 | return 0; |
| 1723 | } |
| 1724 | |
| 1725 | #ifdef CONFIG_PM |
| 1726 | static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg) |
| 1727 | { |
| 1728 | struct net_device *net_dev = platform_get_drvdata(pdev); |
| 1729 | struct bfin_mac_local *lp = netdev_priv(net_dev); |
| 1730 | |
| 1731 | if (lp->wol) { |
| 1732 | bfin_write_EMAC_OPMODE((bfin_read_EMAC_OPMODE() & ~TE) | RE); |
| 1733 | bfin_write_EMAC_WKUP_CTL(MPKE); |
| 1734 | enable_irq_wake(IRQ_MAC_WAKEDET); |
| 1735 | } else { |
| 1736 | if (netif_running(net_dev)) |
| 1737 | bfin_mac_close(net_dev); |
| 1738 | } |
| 1739 | |
| 1740 | return 0; |
| 1741 | } |
| 1742 | |
| 1743 | static int bfin_mac_resume(struct platform_device *pdev) |
| 1744 | { |
| 1745 | struct net_device *net_dev = platform_get_drvdata(pdev); |
| 1746 | struct bfin_mac_local *lp = netdev_priv(net_dev); |
| 1747 | |
| 1748 | if (lp->wol) { |
| 1749 | bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE); |
| 1750 | bfin_write_EMAC_WKUP_CTL(0); |
| 1751 | disable_irq_wake(IRQ_MAC_WAKEDET); |
| 1752 | } else { |
| 1753 | if (netif_running(net_dev)) |
| 1754 | bfin_mac_open(net_dev); |
| 1755 | } |
| 1756 | |
| 1757 | return 0; |
| 1758 | } |
| 1759 | #else |
| 1760 | #define bfin_mac_suspend NULL |
| 1761 | #define bfin_mac_resume NULL |
| 1762 | #endif /* CONFIG_PM */ |
| 1763 | |
| 1764 | static int bfin_mii_bus_probe(struct platform_device *pdev) |
| 1765 | { |
| 1766 | struct mii_bus *miibus; |
| 1767 | struct bfin_mii_bus_platform_data *mii_bus_pd; |
| 1768 | const unsigned short *pin_req; |
| 1769 | int rc, i; |
| 1770 | |
| 1771 | mii_bus_pd = dev_get_platdata(&pdev->dev); |
| 1772 | if (!mii_bus_pd) { |
| 1773 | dev_err(&pdev->dev, "No peripherals in platform data!\n"); |
| 1774 | return -EINVAL; |
| 1775 | } |
| 1776 | |
| 1777 | /* |
| 1778 | * We are setting up a network card, |
| 1779 | * so set the GPIO pins to Ethernet mode |
| 1780 | */ |
| 1781 | pin_req = mii_bus_pd->mac_peripherals; |
| 1782 | rc = peripheral_request_list(pin_req, KBUILD_MODNAME); |
| 1783 | if (rc) { |
| 1784 | dev_err(&pdev->dev, "Requesting peripherals failed!\n"); |
| 1785 | return rc; |
| 1786 | } |
| 1787 | |
| 1788 | rc = -ENOMEM; |
| 1789 | miibus = mdiobus_alloc(); |
| 1790 | if (miibus == NULL) |
| 1791 | goto out_err_alloc; |
| 1792 | miibus->read = bfin_mdiobus_read; |
| 1793 | miibus->write = bfin_mdiobus_write; |
| 1794 | |
| 1795 | miibus->parent = &pdev->dev; |
| 1796 | miibus->name = "bfin_mii_bus"; |
| 1797 | miibus->phy_mask = mii_bus_pd->phy_mask; |
| 1798 | |
| 1799 | snprintf(miibus->id, MII_BUS_ID_SIZE, "%s-%x", |
| 1800 | pdev->name, pdev->id); |
| 1801 | |
| 1802 | rc = clamp(mii_bus_pd->phydev_number, 0, PHY_MAX_ADDR); |
| 1803 | if (rc != mii_bus_pd->phydev_number) |
| 1804 | dev_err(&pdev->dev, "Invalid number (%i) of phydevs\n", |
| 1805 | mii_bus_pd->phydev_number); |
| 1806 | for (i = 0; i < rc; ++i) { |
| 1807 | unsigned short phyaddr = mii_bus_pd->phydev_data[i].addr; |
| 1808 | if (phyaddr < PHY_MAX_ADDR) |
| 1809 | miibus->irq[phyaddr] = mii_bus_pd->phydev_data[i].irq; |
| 1810 | else |
| 1811 | dev_err(&pdev->dev, |
| 1812 | "Invalid PHY address %i for phydev %i\n", |
| 1813 | phyaddr, i); |
| 1814 | } |
| 1815 | |
| 1816 | rc = mdiobus_register(miibus); |
| 1817 | if (rc) { |
| 1818 | dev_err(&pdev->dev, "Cannot register MDIO bus!\n"); |
| 1819 | goto out_err_irq_alloc; |
| 1820 | } |
| 1821 | |
| 1822 | platform_set_drvdata(pdev, miibus); |
| 1823 | return 0; |
| 1824 | |
| 1825 | out_err_irq_alloc: |
| 1826 | mdiobus_free(miibus); |
| 1827 | out_err_alloc: |
| 1828 | peripheral_free_list(pin_req); |
| 1829 | |
| 1830 | return rc; |
| 1831 | } |
| 1832 | |
| 1833 | static int bfin_mii_bus_remove(struct platform_device *pdev) |
| 1834 | { |
| 1835 | struct mii_bus *miibus = platform_get_drvdata(pdev); |
| 1836 | struct bfin_mii_bus_platform_data *mii_bus_pd = |
| 1837 | dev_get_platdata(&pdev->dev); |
| 1838 | |
| 1839 | mdiobus_unregister(miibus); |
| 1840 | mdiobus_free(miibus); |
| 1841 | peripheral_free_list(mii_bus_pd->mac_peripherals); |
| 1842 | |
| 1843 | return 0; |
| 1844 | } |
| 1845 | |
| 1846 | static struct platform_driver bfin_mii_bus_driver = { |
| 1847 | .probe = bfin_mii_bus_probe, |
| 1848 | .remove = bfin_mii_bus_remove, |
| 1849 | .driver = { |
| 1850 | .name = "bfin_mii_bus", |
| 1851 | }, |
| 1852 | }; |
| 1853 | |
| 1854 | static struct platform_driver bfin_mac_driver = { |
| 1855 | .probe = bfin_mac_probe, |
| 1856 | .remove = bfin_mac_remove, |
| 1857 | .resume = bfin_mac_resume, |
| 1858 | .suspend = bfin_mac_suspend, |
| 1859 | .driver = { |
| 1860 | .name = KBUILD_MODNAME, |
| 1861 | }, |
| 1862 | }; |
| 1863 | |
| 1864 | static struct platform_driver * const drivers[] = { |
| 1865 | &bfin_mii_bus_driver, |
| 1866 | &bfin_mac_driver, |
| 1867 | }; |
| 1868 | |
| 1869 | static int __init bfin_mac_init(void) |
| 1870 | { |
| 1871 | return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); |
| 1872 | } |
| 1873 | |
| 1874 | module_init(bfin_mac_init); |
| 1875 | |
| 1876 | static void __exit bfin_mac_cleanup(void) |
| 1877 | { |
| 1878 | platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); |
| 1879 | } |
| 1880 | |
| 1881 | module_exit(bfin_mac_cleanup); |
| 1882 | |