| 1 | /* |
| 2 | * Linux network driver for Brocade Converged Network Adapter. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms of the GNU General Public License (GPL) Version 2 as |
| 6 | * published by the Free Software Foundation |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, but |
| 9 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 11 | * General Public License for more details. |
| 12 | */ |
| 13 | /* |
| 14 | * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. |
| 15 | * All rights reserved |
| 16 | * www.brocade.com |
| 17 | */ |
| 18 | #ifndef __BNAD_H__ |
| 19 | #define __BNAD_H__ |
| 20 | |
| 21 | #include <linux/rtnetlink.h> |
| 22 | #include <linux/workqueue.h> |
| 23 | #include <linux/ipv6.h> |
| 24 | #include <linux/etherdevice.h> |
| 25 | #include <linux/mutex.h> |
| 26 | #include <linux/firmware.h> |
| 27 | #include <linux/if_vlan.h> |
| 28 | |
| 29 | /* Fix for IA64 */ |
| 30 | #include <asm/checksum.h> |
| 31 | #include <net/ip6_checksum.h> |
| 32 | |
| 33 | #include <net/ip.h> |
| 34 | #include <net/tcp.h> |
| 35 | |
| 36 | #include "bna.h" |
| 37 | |
| 38 | #define BNAD_TXQ_DEPTH 2048 |
| 39 | #define BNAD_RXQ_DEPTH 2048 |
| 40 | |
| 41 | #define BNAD_MAX_TX 1 |
| 42 | #define BNAD_MAX_TXQ_PER_TX 8 /* 8 priority queues */ |
| 43 | #define BNAD_TXQ_NUM 1 |
| 44 | |
| 45 | #define BNAD_MAX_RX 1 |
| 46 | #define BNAD_MAX_RXP_PER_RX 16 |
| 47 | #define BNAD_MAX_RXQ_PER_RXP 2 |
| 48 | |
| 49 | /* |
| 50 | * Control structure pointed to ccb->ctrl, which |
| 51 | * determines the NAPI / LRO behavior CCB |
| 52 | * There is 1:1 corres. between ccb & ctrl |
| 53 | */ |
| 54 | struct bnad_rx_ctrl { |
| 55 | struct bna_ccb *ccb; |
| 56 | struct bnad *bnad; |
| 57 | unsigned long flags; |
| 58 | struct napi_struct napi; |
| 59 | u64 rx_intr_ctr; |
| 60 | u64 rx_poll_ctr; |
| 61 | u64 rx_schedule; |
| 62 | u64 rx_keep_poll; |
| 63 | u64 rx_complete; |
| 64 | }; |
| 65 | |
| 66 | #define BNAD_RXMODE_PROMISC_DEFAULT BNA_RXMODE_PROMISC |
| 67 | |
| 68 | /* |
| 69 | * GLOBAL #defines (CONSTANTS) |
| 70 | */ |
| 71 | #define BNAD_NAME "bna" |
| 72 | #define BNAD_NAME_LEN 64 |
| 73 | |
| 74 | #define BNAD_VERSION "3.2.21.1" |
| 75 | |
| 76 | #define BNAD_MAILBOX_MSIX_INDEX 0 |
| 77 | #define BNAD_MAILBOX_MSIX_VECTORS 1 |
| 78 | #define BNAD_INTX_TX_IB_BITMASK 0x1 |
| 79 | #define BNAD_INTX_RX_IB_BITMASK 0x2 |
| 80 | |
| 81 | #define BNAD_STATS_TIMER_FREQ 1000 /* in msecs */ |
| 82 | #define BNAD_DIM_TIMER_FREQ 1000 /* in msecs */ |
| 83 | |
| 84 | #define BNAD_IOCETH_TIMEOUT 10000 |
| 85 | |
| 86 | #define BNAD_MIN_Q_DEPTH 512 |
| 87 | #define BNAD_MAX_RXQ_DEPTH 2048 |
| 88 | #define BNAD_MAX_TXQ_DEPTH 2048 |
| 89 | |
| 90 | #define BNAD_JUMBO_MTU 9000 |
| 91 | |
| 92 | #define BNAD_NETIF_WAKE_THRESHOLD 8 |
| 93 | |
| 94 | #define BNAD_RXQ_REFILL_THRESHOLD_SHIFT 3 |
| 95 | |
| 96 | /* Bit positions for tcb->flags */ |
| 97 | #define BNAD_TXQ_FREE_SENT 0 |
| 98 | #define BNAD_TXQ_TX_STARTED 1 |
| 99 | |
| 100 | /* Bit positions for rcb->flags */ |
| 101 | #define BNAD_RXQ_STARTED 0 |
| 102 | #define BNAD_RXQ_POST_OK 1 |
| 103 | |
| 104 | /* Resource limits */ |
| 105 | #define BNAD_NUM_TXQ (bnad->num_tx * bnad->num_txq_per_tx) |
| 106 | #define BNAD_NUM_RXP (bnad->num_rx * bnad->num_rxp_per_rx) |
| 107 | |
| 108 | /* |
| 109 | * DATA STRUCTURES |
| 110 | */ |
| 111 | |
| 112 | /* enums */ |
| 113 | enum bnad_intr_source { |
| 114 | BNAD_INTR_TX = 1, |
| 115 | BNAD_INTR_RX = 2 |
| 116 | }; |
| 117 | |
| 118 | enum bnad_link_state { |
| 119 | BNAD_LS_DOWN = 0, |
| 120 | BNAD_LS_UP = 1 |
| 121 | }; |
| 122 | |
| 123 | struct bnad_iocmd_comp { |
| 124 | struct bnad *bnad; |
| 125 | struct completion comp; |
| 126 | int comp_status; |
| 127 | }; |
| 128 | |
| 129 | struct bnad_completion { |
| 130 | struct completion ioc_comp; |
| 131 | struct completion ucast_comp; |
| 132 | struct completion mcast_comp; |
| 133 | struct completion tx_comp; |
| 134 | struct completion rx_comp; |
| 135 | struct completion stats_comp; |
| 136 | struct completion enet_comp; |
| 137 | struct completion mtu_comp; |
| 138 | |
| 139 | u8 ioc_comp_status; |
| 140 | u8 ucast_comp_status; |
| 141 | u8 mcast_comp_status; |
| 142 | u8 tx_comp_status; |
| 143 | u8 rx_comp_status; |
| 144 | u8 stats_comp_status; |
| 145 | u8 port_comp_status; |
| 146 | u8 mtu_comp_status; |
| 147 | }; |
| 148 | |
| 149 | /* Tx Rx Control Stats */ |
| 150 | struct bnad_drv_stats { |
| 151 | u64 netif_queue_stop; |
| 152 | u64 netif_queue_wakeup; |
| 153 | u64 netif_queue_stopped; |
| 154 | u64 tso4; |
| 155 | u64 tso6; |
| 156 | u64 tso_err; |
| 157 | u64 tcpcsum_offload; |
| 158 | u64 udpcsum_offload; |
| 159 | u64 csum_help; |
| 160 | u64 tx_skb_too_short; |
| 161 | u64 tx_skb_stopping; |
| 162 | u64 tx_skb_max_vectors; |
| 163 | u64 tx_skb_mss_too_long; |
| 164 | u64 tx_skb_tso_too_short; |
| 165 | u64 tx_skb_tso_prepare; |
| 166 | u64 tx_skb_non_tso_too_long; |
| 167 | u64 tx_skb_tcp_hdr; |
| 168 | u64 tx_skb_udp_hdr; |
| 169 | u64 tx_skb_csum_err; |
| 170 | u64 tx_skb_headlen_too_long; |
| 171 | u64 tx_skb_headlen_zero; |
| 172 | u64 tx_skb_frag_zero; |
| 173 | u64 tx_skb_len_mismatch; |
| 174 | |
| 175 | u64 hw_stats_updates; |
| 176 | u64 netif_rx_dropped; |
| 177 | |
| 178 | u64 link_toggle; |
| 179 | u64 cee_toggle; |
| 180 | |
| 181 | u64 rxp_info_alloc_failed; |
| 182 | u64 mbox_intr_disabled; |
| 183 | u64 mbox_intr_enabled; |
| 184 | u64 tx_unmap_q_alloc_failed; |
| 185 | u64 rx_unmap_q_alloc_failed; |
| 186 | |
| 187 | u64 rxbuf_alloc_failed; |
| 188 | }; |
| 189 | |
| 190 | /* Complete driver stats */ |
| 191 | struct bnad_stats { |
| 192 | struct bnad_drv_stats drv_stats; |
| 193 | struct bna_stats *bna_stats; |
| 194 | }; |
| 195 | |
| 196 | /* Tx / Rx Resources */ |
| 197 | struct bnad_tx_res_info { |
| 198 | struct bna_res_info res_info[BNA_TX_RES_T_MAX]; |
| 199 | }; |
| 200 | |
| 201 | struct bnad_rx_res_info { |
| 202 | struct bna_res_info res_info[BNA_RX_RES_T_MAX]; |
| 203 | }; |
| 204 | |
| 205 | struct bnad_tx_info { |
| 206 | struct bna_tx *tx; /* 1:1 between tx_info & tx */ |
| 207 | struct bna_tcb *tcb[BNAD_MAX_TXQ_PER_TX]; |
| 208 | u32 tx_id; |
| 209 | struct delayed_work tx_cleanup_work; |
| 210 | } ____cacheline_aligned; |
| 211 | |
| 212 | struct bnad_rx_info { |
| 213 | struct bna_rx *rx; /* 1:1 between rx_info & rx */ |
| 214 | |
| 215 | struct bnad_rx_ctrl rx_ctrl[BNAD_MAX_RXP_PER_RX]; |
| 216 | u32 rx_id; |
| 217 | struct work_struct rx_cleanup_work; |
| 218 | } ____cacheline_aligned; |
| 219 | |
| 220 | struct bnad_tx_vector { |
| 221 | DEFINE_DMA_UNMAP_ADDR(dma_addr); |
| 222 | }; |
| 223 | |
| 224 | struct bnad_tx_unmap { |
| 225 | struct sk_buff *skb; |
| 226 | u32 nvecs; |
| 227 | struct bnad_tx_vector vectors[BFI_TX_MAX_VECTORS_PER_WI]; |
| 228 | }; |
| 229 | |
| 230 | struct bnad_rx_vector { |
| 231 | DEFINE_DMA_UNMAP_ADDR(dma_addr); |
| 232 | u32 len; |
| 233 | }; |
| 234 | |
| 235 | struct bnad_rx_unmap { |
| 236 | struct page *page; |
| 237 | u32 page_offset; |
| 238 | struct sk_buff *skb; |
| 239 | struct bnad_rx_vector vector; |
| 240 | }; |
| 241 | |
| 242 | enum bnad_rxbuf_type { |
| 243 | BNAD_RXBUF_NONE = 0, |
| 244 | BNAD_RXBUF_SKB = 1, |
| 245 | BNAD_RXBUF_PAGE = 2, |
| 246 | BNAD_RXBUF_MULTI = 3 |
| 247 | }; |
| 248 | |
| 249 | #define BNAD_RXBUF_IS_PAGE(_type) ((_type) == BNAD_RXBUF_PAGE) |
| 250 | |
| 251 | struct bnad_rx_unmap_q { |
| 252 | int reuse_pi; |
| 253 | int alloc_order; |
| 254 | u32 map_size; |
| 255 | enum bnad_rxbuf_type type; |
| 256 | struct bnad_rx_unmap unmap[0]; |
| 257 | }; |
| 258 | |
| 259 | /* Bit mask values for bnad->cfg_flags */ |
| 260 | #define BNAD_CF_DIM_ENABLED 0x01 /* DIM */ |
| 261 | #define BNAD_CF_PROMISC 0x02 |
| 262 | #define BNAD_CF_ALLMULTI 0x04 |
| 263 | #define BNAD_CF_DEFAULT 0x08 |
| 264 | #define BNAD_CF_MSIX 0x10 /* If in MSIx mode */ |
| 265 | |
| 266 | /* Defines for run_flags bit-mask */ |
| 267 | /* Set, tested & cleared using xxx_bit() functions */ |
| 268 | /* Values indicated bit positions */ |
| 269 | #define BNAD_RF_CEE_RUNNING 0 |
| 270 | #define BNAD_RF_MTU_SET 1 |
| 271 | #define BNAD_RF_MBOX_IRQ_DISABLED 2 |
| 272 | #define BNAD_RF_NETDEV_REGISTERED 3 |
| 273 | #define BNAD_RF_DIM_TIMER_RUNNING 4 |
| 274 | #define BNAD_RF_STATS_TIMER_RUNNING 5 |
| 275 | #define BNAD_RF_TX_PRIO_SET 6 |
| 276 | |
| 277 | struct bnad { |
| 278 | struct net_device *netdev; |
| 279 | u32 id; |
| 280 | struct list_head list_entry; |
| 281 | |
| 282 | /* Data path */ |
| 283 | struct bnad_tx_info tx_info[BNAD_MAX_TX]; |
| 284 | struct bnad_rx_info rx_info[BNAD_MAX_RX]; |
| 285 | |
| 286 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
| 287 | /* |
| 288 | * These q numbers are global only because |
| 289 | * they are used to calculate MSIx vectors. |
| 290 | * Actually the exact # of queues are per Tx/Rx |
| 291 | * object. |
| 292 | */ |
| 293 | u32 num_tx; |
| 294 | u32 num_rx; |
| 295 | u32 num_txq_per_tx; |
| 296 | u32 num_rxp_per_rx; |
| 297 | |
| 298 | u32 txq_depth; |
| 299 | u32 rxq_depth; |
| 300 | |
| 301 | u8 tx_coalescing_timeo; |
| 302 | u8 rx_coalescing_timeo; |
| 303 | |
| 304 | struct bna_rx_config rx_config[BNAD_MAX_RX] ____cacheline_aligned; |
| 305 | struct bna_tx_config tx_config[BNAD_MAX_TX] ____cacheline_aligned; |
| 306 | |
| 307 | void __iomem *bar0; /* BAR0 address */ |
| 308 | |
| 309 | struct bna bna; |
| 310 | |
| 311 | u32 cfg_flags; |
| 312 | unsigned long run_flags; |
| 313 | |
| 314 | struct pci_dev *pcidev; |
| 315 | u64 mmio_start; |
| 316 | u64 mmio_len; |
| 317 | |
| 318 | u32 msix_num; |
| 319 | struct msix_entry *msix_table; |
| 320 | |
| 321 | struct mutex conf_mutex; |
| 322 | spinlock_t bna_lock ____cacheline_aligned; |
| 323 | |
| 324 | /* Timers */ |
| 325 | struct timer_list ioc_timer; |
| 326 | struct timer_list dim_timer; |
| 327 | struct timer_list stats_timer; |
| 328 | |
| 329 | /* Control path resources, memory & irq */ |
| 330 | struct bna_res_info res_info[BNA_RES_T_MAX]; |
| 331 | struct bna_res_info mod_res_info[BNA_MOD_RES_T_MAX]; |
| 332 | struct bnad_tx_res_info tx_res_info[BNAD_MAX_TX]; |
| 333 | struct bnad_rx_res_info rx_res_info[BNAD_MAX_RX]; |
| 334 | |
| 335 | struct bnad_completion bnad_completions; |
| 336 | |
| 337 | /* Burnt in MAC address */ |
| 338 | mac_t perm_addr; |
| 339 | |
| 340 | struct workqueue_struct *work_q; |
| 341 | |
| 342 | /* Statistics */ |
| 343 | struct bnad_stats stats; |
| 344 | |
| 345 | struct bnad_diag *diag; |
| 346 | |
| 347 | char adapter_name[BNAD_NAME_LEN]; |
| 348 | char port_name[BNAD_NAME_LEN]; |
| 349 | char mbox_irq_name[BNAD_NAME_LEN]; |
| 350 | char wq_name[BNAD_NAME_LEN]; |
| 351 | |
| 352 | /* debugfs specific data */ |
| 353 | char *regdata; |
| 354 | u32 reglen; |
| 355 | struct dentry *bnad_dentry_files[5]; |
| 356 | struct dentry *port_debugfs_root; |
| 357 | }; |
| 358 | |
| 359 | struct bnad_drvinfo { |
| 360 | struct bfa_ioc_attr ioc_attr; |
| 361 | struct bfa_cee_attr cee_attr; |
| 362 | struct bfa_flash_attr flash_attr; |
| 363 | u32 cee_status; |
| 364 | u32 flash_status; |
| 365 | }; |
| 366 | |
| 367 | /* |
| 368 | * EXTERN VARIABLES |
| 369 | */ |
| 370 | extern const struct firmware *bfi_fw; |
| 371 | |
| 372 | /* |
| 373 | * EXTERN PROTOTYPES |
| 374 | */ |
| 375 | u32 *cna_get_firmware_buf(struct pci_dev *pdev); |
| 376 | /* Netdev entry point prototypes */ |
| 377 | void bnad_set_rx_mode(struct net_device *netdev); |
| 378 | struct net_device_stats *bnad_get_netdev_stats(struct net_device *netdev); |
| 379 | int bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr); |
| 380 | int bnad_enable_default_bcast(struct bnad *bnad); |
| 381 | void bnad_restore_vlans(struct bnad *bnad, u32 rx_id); |
| 382 | void bnad_set_ethtool_ops(struct net_device *netdev); |
| 383 | void bnad_cb_completion(void *arg, enum bfa_status status); |
| 384 | |
| 385 | /* Configuration & setup */ |
| 386 | void bnad_tx_coalescing_timeo_set(struct bnad *bnad); |
| 387 | void bnad_rx_coalescing_timeo_set(struct bnad *bnad); |
| 388 | |
| 389 | int bnad_setup_rx(struct bnad *bnad, u32 rx_id); |
| 390 | int bnad_setup_tx(struct bnad *bnad, u32 tx_id); |
| 391 | void bnad_destroy_tx(struct bnad *bnad, u32 tx_id); |
| 392 | void bnad_destroy_rx(struct bnad *bnad, u32 rx_id); |
| 393 | |
| 394 | /* Timer start/stop protos */ |
| 395 | void bnad_dim_timer_start(struct bnad *bnad); |
| 396 | |
| 397 | /* Statistics */ |
| 398 | void bnad_netdev_qstats_fill(struct bnad *bnad, |
| 399 | struct rtnl_link_stats64 *stats); |
| 400 | void bnad_netdev_hwstats_fill(struct bnad *bnad, |
| 401 | struct rtnl_link_stats64 *stats); |
| 402 | |
| 403 | /* Debugfs */ |
| 404 | void bnad_debugfs_init(struct bnad *bnad); |
| 405 | void bnad_debugfs_uninit(struct bnad *bnad); |
| 406 | |
| 407 | /* MACROS */ |
| 408 | /* To set & get the stats counters */ |
| 409 | #define BNAD_UPDATE_CTR(_bnad, _ctr) \ |
| 410 | (((_bnad)->stats.drv_stats._ctr)++) |
| 411 | |
| 412 | #define BNAD_GET_CTR(_bnad, _ctr) ((_bnad)->stats.drv_stats._ctr) |
| 413 | |
| 414 | #define bnad_enable_rx_irq_unsafe(_ccb) \ |
| 415 | { \ |
| 416 | if (likely(test_bit(BNAD_RXQ_STARTED, &(_ccb)->rcb[0]->flags))) {\ |
| 417 | bna_ib_coalescing_timer_set((_ccb)->i_dbell, \ |
| 418 | (_ccb)->rx_coalescing_timeo); \ |
| 419 | bna_ib_ack((_ccb)->i_dbell, 0); \ |
| 420 | } \ |
| 421 | } |
| 422 | |
| 423 | #endif /* __BNAD_H__ */ |