| 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel(R) Gigabit Ethernet Linux driver |
| 4 | Copyright(c) 2007-2011 Intel Corporation. |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
| 23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 25 | |
| 26 | *******************************************************************************/ |
| 27 | |
| 28 | |
| 29 | /* Linux PRO/1000 Ethernet Driver main header file */ |
| 30 | |
| 31 | #ifndef _IGB_H_ |
| 32 | #define _IGB_H_ |
| 33 | |
| 34 | #include "e1000_mac.h" |
| 35 | #include "e1000_82575.h" |
| 36 | |
| 37 | #include <linux/clocksource.h> |
| 38 | #include <linux/timecompare.h> |
| 39 | #include <linux/net_tstamp.h> |
| 40 | #include <linux/bitops.h> |
| 41 | #include <linux/if_vlan.h> |
| 42 | |
| 43 | struct igb_adapter; |
| 44 | |
| 45 | /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */ |
| 46 | #define IGB_START_ITR 648 |
| 47 | |
| 48 | /* TX/RX descriptor defines */ |
| 49 | #define IGB_DEFAULT_TXD 256 |
| 50 | #define IGB_MIN_TXD 80 |
| 51 | #define IGB_MAX_TXD 4096 |
| 52 | |
| 53 | #define IGB_DEFAULT_RXD 256 |
| 54 | #define IGB_MIN_RXD 80 |
| 55 | #define IGB_MAX_RXD 4096 |
| 56 | |
| 57 | #define IGB_DEFAULT_ITR 3 /* dynamic */ |
| 58 | #define IGB_MAX_ITR_USECS 10000 |
| 59 | #define IGB_MIN_ITR_USECS 10 |
| 60 | #define NON_Q_VECTORS 1 |
| 61 | #define MAX_Q_VECTORS 8 |
| 62 | |
| 63 | /* Transmit and receive queues */ |
| 64 | #define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \ |
| 65 | (hw->mac.type > e1000_82575 ? 8 : 4)) |
| 66 | #define IGB_MAX_TX_QUEUES 16 |
| 67 | |
| 68 | #define IGB_MAX_VF_MC_ENTRIES 30 |
| 69 | #define IGB_MAX_VF_FUNCTIONS 8 |
| 70 | #define IGB_MAX_VFTA_ENTRIES 128 |
| 71 | |
| 72 | struct vf_data_storage { |
| 73 | unsigned char vf_mac_addresses[ETH_ALEN]; |
| 74 | u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES]; |
| 75 | u16 num_vf_mc_hashes; |
| 76 | u16 vlans_enabled; |
| 77 | u32 flags; |
| 78 | unsigned long last_nack; |
| 79 | u16 pf_vlan; /* When set, guest VLAN config not allowed. */ |
| 80 | u16 pf_qos; |
| 81 | u16 tx_rate; |
| 82 | }; |
| 83 | |
| 84 | #define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */ |
| 85 | #define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */ |
| 86 | #define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */ |
| 87 | #define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */ |
| 88 | |
| 89 | /* RX descriptor control thresholds. |
| 90 | * PTHRESH - MAC will consider prefetch if it has fewer than this number of |
| 91 | * descriptors available in its onboard memory. |
| 92 | * Setting this to 0 disables RX descriptor prefetch. |
| 93 | * HTHRESH - MAC will only prefetch if there are at least this many descriptors |
| 94 | * available in host memory. |
| 95 | * If PTHRESH is 0, this should also be 0. |
| 96 | * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back |
| 97 | * descriptors until either it has this many to write back, or the |
| 98 | * ITR timer expires. |
| 99 | */ |
| 100 | #define IGB_RX_PTHRESH 8 |
| 101 | #define IGB_RX_HTHRESH 8 |
| 102 | #define IGB_TX_PTHRESH 8 |
| 103 | #define IGB_TX_HTHRESH 1 |
| 104 | #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ |
| 105 | adapter->msix_entries) ? 1 : 4) |
| 106 | #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \ |
| 107 | adapter->msix_entries) ? 1 : 16) |
| 108 | |
| 109 | /* this is the size past which hardware will drop packets when setting LPE=0 */ |
| 110 | #define MAXIMUM_ETHERNET_VLAN_SIZE 1522 |
| 111 | |
| 112 | /* Supported Rx Buffer Sizes */ |
| 113 | #define IGB_RXBUFFER_512 512 |
| 114 | #define IGB_RXBUFFER_16384 16384 |
| 115 | #define IGB_RX_HDR_LEN IGB_RXBUFFER_512 |
| 116 | |
| 117 | /* How many Tx Descriptors do we need to call netif_wake_queue ? */ |
| 118 | #define IGB_TX_QUEUE_WAKE 16 |
| 119 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
| 120 | #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */ |
| 121 | |
| 122 | #define AUTO_ALL_MODES 0 |
| 123 | #define IGB_EEPROM_APME 0x0400 |
| 124 | |
| 125 | #ifndef IGB_MASTER_SLAVE |
| 126 | /* Switch to override PHY master/slave setting */ |
| 127 | #define IGB_MASTER_SLAVE e1000_ms_hw_default |
| 128 | #endif |
| 129 | |
| 130 | #define IGB_MNG_VLAN_NONE -1 |
| 131 | |
| 132 | /* wrapper around a pointer to a socket buffer, |
| 133 | * so a DMA handle can be stored along with the buffer */ |
| 134 | struct igb_buffer { |
| 135 | struct sk_buff *skb; |
| 136 | dma_addr_t dma; |
| 137 | union { |
| 138 | /* TX */ |
| 139 | struct { |
| 140 | unsigned long time_stamp; |
| 141 | u16 length; |
| 142 | u16 next_to_watch; |
| 143 | unsigned int bytecount; |
| 144 | u16 gso_segs; |
| 145 | u8 tx_flags; |
| 146 | u8 mapped_as_page; |
| 147 | }; |
| 148 | /* RX */ |
| 149 | struct { |
| 150 | struct page *page; |
| 151 | dma_addr_t page_dma; |
| 152 | u16 page_offset; |
| 153 | }; |
| 154 | }; |
| 155 | }; |
| 156 | |
| 157 | struct igb_tx_queue_stats { |
| 158 | u64 packets; |
| 159 | u64 bytes; |
| 160 | u64 restart_queue; |
| 161 | u64 restart_queue2; |
| 162 | }; |
| 163 | |
| 164 | struct igb_rx_queue_stats { |
| 165 | u64 packets; |
| 166 | u64 bytes; |
| 167 | u64 drops; |
| 168 | u64 csum_err; |
| 169 | u64 alloc_failed; |
| 170 | }; |
| 171 | |
| 172 | struct igb_q_vector { |
| 173 | struct igb_adapter *adapter; /* backlink */ |
| 174 | struct igb_ring *rx_ring; |
| 175 | struct igb_ring *tx_ring; |
| 176 | struct napi_struct napi; |
| 177 | |
| 178 | u32 eims_value; |
| 179 | u16 cpu; |
| 180 | |
| 181 | u16 itr_val; |
| 182 | u8 set_itr; |
| 183 | void __iomem *itr_register; |
| 184 | |
| 185 | char name[IFNAMSIZ + 9]; |
| 186 | }; |
| 187 | |
| 188 | struct igb_ring { |
| 189 | struct igb_q_vector *q_vector; /* backlink to q_vector */ |
| 190 | struct net_device *netdev; /* back pointer to net_device */ |
| 191 | struct device *dev; /* device pointer for dma mapping */ |
| 192 | struct igb_buffer *buffer_info; /* array of buffer info structs */ |
| 193 | void *desc; /* descriptor ring memory */ |
| 194 | unsigned long flags; /* ring specific flags */ |
| 195 | void __iomem *tail; /* pointer to ring tail register */ |
| 196 | |
| 197 | u16 count; /* number of desc. in the ring */ |
| 198 | u8 queue_index; /* logical index of the ring*/ |
| 199 | u8 reg_idx; /* physical index of the ring */ |
| 200 | u32 size; /* length of desc. ring in bytes */ |
| 201 | |
| 202 | /* everything past this point are written often */ |
| 203 | u16 next_to_clean ____cacheline_aligned_in_smp; |
| 204 | u16 next_to_use; |
| 205 | |
| 206 | unsigned int total_bytes; |
| 207 | unsigned int total_packets; |
| 208 | |
| 209 | union { |
| 210 | /* TX */ |
| 211 | struct { |
| 212 | struct igb_tx_queue_stats tx_stats; |
| 213 | struct u64_stats_sync tx_syncp; |
| 214 | struct u64_stats_sync tx_syncp2; |
| 215 | bool detect_tx_hung; |
| 216 | }; |
| 217 | /* RX */ |
| 218 | struct { |
| 219 | struct igb_rx_queue_stats rx_stats; |
| 220 | struct u64_stats_sync rx_syncp; |
| 221 | }; |
| 222 | }; |
| 223 | /* Items past this point are only used during ring alloc / free */ |
| 224 | dma_addr_t dma; /* phys address of the ring */ |
| 225 | }; |
| 226 | |
| 227 | #define IGB_RING_FLAG_RX_CSUM 0x00000001 /* RX CSUM enabled */ |
| 228 | #define IGB_RING_FLAG_RX_SCTP_CSUM 0x00000002 /* SCTP CSUM offload enabled */ |
| 229 | |
| 230 | #define IGB_RING_FLAG_TX_CTX_IDX 0x00000001 /* HW requires context index */ |
| 231 | |
| 232 | #define IGB_ADVTXD_DCMD (E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS) |
| 233 | |
| 234 | #define IGB_RX_DESC(R, i) \ |
| 235 | (&(((union e1000_adv_rx_desc *)((R)->desc))[i])) |
| 236 | #define IGB_TX_DESC(R, i) \ |
| 237 | (&(((union e1000_adv_tx_desc *)((R)->desc))[i])) |
| 238 | #define IGB_TX_CTXTDESC(R, i) \ |
| 239 | (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i])) |
| 240 | |
| 241 | /* igb_desc_unused - calculate if we have unused descriptors */ |
| 242 | static inline int igb_desc_unused(struct igb_ring *ring) |
| 243 | { |
| 244 | if (ring->next_to_clean > ring->next_to_use) |
| 245 | return ring->next_to_clean - ring->next_to_use - 1; |
| 246 | |
| 247 | return ring->count + ring->next_to_clean - ring->next_to_use - 1; |
| 248 | } |
| 249 | |
| 250 | /* board specific private data structure */ |
| 251 | struct igb_adapter { |
| 252 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
| 253 | |
| 254 | struct net_device *netdev; |
| 255 | |
| 256 | unsigned long state; |
| 257 | unsigned int flags; |
| 258 | |
| 259 | unsigned int num_q_vectors; |
| 260 | struct msix_entry *msix_entries; |
| 261 | |
| 262 | /* Interrupt Throttle Rate */ |
| 263 | u32 rx_itr_setting; |
| 264 | u32 tx_itr_setting; |
| 265 | u16 tx_itr; |
| 266 | u16 rx_itr; |
| 267 | |
| 268 | /* TX */ |
| 269 | u32 tx_timeout_count; |
| 270 | int num_tx_queues; |
| 271 | struct igb_ring *tx_ring[16]; |
| 272 | |
| 273 | /* RX */ |
| 274 | int num_rx_queues; |
| 275 | struct igb_ring *rx_ring[16]; |
| 276 | |
| 277 | u32 max_frame_size; |
| 278 | u32 min_frame_size; |
| 279 | |
| 280 | struct timer_list watchdog_timer; |
| 281 | struct timer_list phy_info_timer; |
| 282 | |
| 283 | u16 mng_vlan_id; |
| 284 | u32 bd_number; |
| 285 | u32 wol; |
| 286 | u32 en_mng_pt; |
| 287 | u16 link_speed; |
| 288 | u16 link_duplex; |
| 289 | |
| 290 | struct work_struct reset_task; |
| 291 | struct work_struct watchdog_task; |
| 292 | bool fc_autoneg; |
| 293 | u8 tx_timeout_factor; |
| 294 | struct timer_list blink_timer; |
| 295 | unsigned long led_status; |
| 296 | |
| 297 | /* OS defined structs */ |
| 298 | struct pci_dev *pdev; |
| 299 | struct cyclecounter cycles; |
| 300 | struct timecounter clock; |
| 301 | struct timecompare compare; |
| 302 | struct hwtstamp_config hwtstamp_config; |
| 303 | |
| 304 | spinlock_t stats64_lock; |
| 305 | struct rtnl_link_stats64 stats64; |
| 306 | |
| 307 | /* structs defined in e1000_hw.h */ |
| 308 | struct e1000_hw hw; |
| 309 | struct e1000_hw_stats stats; |
| 310 | struct e1000_phy_info phy_info; |
| 311 | struct e1000_phy_stats phy_stats; |
| 312 | |
| 313 | u32 test_icr; |
| 314 | struct igb_ring test_tx_ring; |
| 315 | struct igb_ring test_rx_ring; |
| 316 | |
| 317 | int msg_enable; |
| 318 | |
| 319 | struct igb_q_vector *q_vector[MAX_Q_VECTORS]; |
| 320 | u32 eims_enable_mask; |
| 321 | u32 eims_other; |
| 322 | |
| 323 | /* to not mess up cache alignment, always add to the bottom */ |
| 324 | u32 eeprom_wol; |
| 325 | |
| 326 | u16 tx_ring_count; |
| 327 | u16 rx_ring_count; |
| 328 | unsigned int vfs_allocated_count; |
| 329 | struct vf_data_storage *vf_data; |
| 330 | int vf_rate_link_speed; |
| 331 | u32 rss_queues; |
| 332 | u32 wvbr; |
| 333 | }; |
| 334 | |
| 335 | #define IGB_FLAG_HAS_MSI (1 << 0) |
| 336 | #define IGB_FLAG_DCA_ENABLED (1 << 1) |
| 337 | #define IGB_FLAG_QUAD_PORT_A (1 << 2) |
| 338 | #define IGB_FLAG_QUEUE_PAIRS (1 << 3) |
| 339 | #define IGB_FLAG_DMAC (1 << 4) |
| 340 | |
| 341 | /* DMA Coalescing defines */ |
| 342 | #define IGB_MIN_TXPBSIZE 20408 |
| 343 | #define IGB_TX_BUF_4096 4096 |
| 344 | #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */ |
| 345 | |
| 346 | #define IGB_82576_TSYNC_SHIFT 19 |
| 347 | #define IGB_82580_TSYNC_SHIFT 24 |
| 348 | #define IGB_TS_HDR_LEN 16 |
| 349 | enum e1000_state_t { |
| 350 | __IGB_TESTING, |
| 351 | __IGB_RESETTING, |
| 352 | __IGB_DOWN |
| 353 | }; |
| 354 | |
| 355 | enum igb_boards { |
| 356 | board_82575, |
| 357 | }; |
| 358 | |
| 359 | extern char igb_driver_name[]; |
| 360 | extern char igb_driver_version[]; |
| 361 | |
| 362 | extern int igb_up(struct igb_adapter *); |
| 363 | extern void igb_down(struct igb_adapter *); |
| 364 | extern void igb_reinit_locked(struct igb_adapter *); |
| 365 | extern void igb_reset(struct igb_adapter *); |
| 366 | extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8); |
| 367 | extern int igb_setup_tx_resources(struct igb_ring *); |
| 368 | extern int igb_setup_rx_resources(struct igb_ring *); |
| 369 | extern void igb_free_tx_resources(struct igb_ring *); |
| 370 | extern void igb_free_rx_resources(struct igb_ring *); |
| 371 | extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *); |
| 372 | extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *); |
| 373 | extern void igb_setup_tctl(struct igb_adapter *); |
| 374 | extern void igb_setup_rctl(struct igb_adapter *); |
| 375 | extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *); |
| 376 | extern void igb_unmap_and_free_tx_resource(struct igb_ring *, |
| 377 | struct igb_buffer *); |
| 378 | extern void igb_alloc_rx_buffers(struct igb_ring *, u16); |
| 379 | extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *); |
| 380 | extern bool igb_has_link(struct igb_adapter *adapter); |
| 381 | extern void igb_set_ethtool_ops(struct net_device *); |
| 382 | extern void igb_power_up_link(struct igb_adapter *); |
| 383 | |
| 384 | static inline s32 igb_reset_phy(struct e1000_hw *hw) |
| 385 | { |
| 386 | if (hw->phy.ops.reset) |
| 387 | return hw->phy.ops.reset(hw); |
| 388 | |
| 389 | return 0; |
| 390 | } |
| 391 | |
| 392 | static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data) |
| 393 | { |
| 394 | if (hw->phy.ops.read_reg) |
| 395 | return hw->phy.ops.read_reg(hw, offset, data); |
| 396 | |
| 397 | return 0; |
| 398 | } |
| 399 | |
| 400 | static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data) |
| 401 | { |
| 402 | if (hw->phy.ops.write_reg) |
| 403 | return hw->phy.ops.write_reg(hw, offset, data); |
| 404 | |
| 405 | return 0; |
| 406 | } |
| 407 | |
| 408 | static inline s32 igb_get_phy_info(struct e1000_hw *hw) |
| 409 | { |
| 410 | if (hw->phy.ops.get_phy_info) |
| 411 | return hw->phy.ops.get_phy_info(hw); |
| 412 | |
| 413 | return 0; |
| 414 | } |
| 415 | |
| 416 | #endif /* _IGB_H_ */ |