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igb: add support for 1512 PHY
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
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CommitLineData
1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
23
24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/init.h>
29#include <linux/bitops.h>
30#include <linux/vmalloc.h>
31#include <linux/pagemap.h>
32#include <linux/netdevice.h>
33#include <linux/ipv6.h>
34#include <linux/slab.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/net_tstamp.h>
38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if.h>
41#include <linux/if_vlan.h>
42#include <linux/pci.h>
43#include <linux/pci-aspm.h>
44#include <linux/delay.h>
45#include <linux/interrupt.h>
46#include <linux/ip.h>
47#include <linux/tcp.h>
48#include <linux/sctp.h>
49#include <linux/if_ether.h>
50#include <linux/aer.h>
51#include <linux/prefetch.h>
52#include <linux/pm_runtime.h>
53#ifdef CONFIG_IGB_DCA
54#include <linux/dca.h>
55#endif
56#include <linux/i2c.h>
57#include "igb.h"
58
59#define MAJ 5
60#define MIN 3
61#define BUILD 0
62#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
63__stringify(BUILD) "-k"
64char igb_driver_name[] = "igb";
65char igb_driver_version[] = DRV_VERSION;
66static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
68static const char igb_copyright[] =
69 "Copyright (c) 2007-2014 Intel Corporation.";
70
71static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73};
74
75static const struct pci_device_id igb_pci_tbl[] = {
76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113};
114
115MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
117static int igb_setup_all_tx_resources(struct igb_adapter *);
118static int igb_setup_all_rx_resources(struct igb_adapter *);
119static void igb_free_all_tx_resources(struct igb_adapter *);
120static void igb_free_all_rx_resources(struct igb_adapter *);
121static void igb_setup_mrqc(struct igb_adapter *);
122static int igb_probe(struct pci_dev *, const struct pci_device_id *);
123static void igb_remove(struct pci_dev *pdev);
124static int igb_sw_init(struct igb_adapter *);
125static int igb_open(struct net_device *);
126static int igb_close(struct net_device *);
127static void igb_configure(struct igb_adapter *);
128static void igb_configure_tx(struct igb_adapter *);
129static void igb_configure_rx(struct igb_adapter *);
130static void igb_clean_all_tx_rings(struct igb_adapter *);
131static void igb_clean_all_rx_rings(struct igb_adapter *);
132static void igb_clean_tx_ring(struct igb_ring *);
133static void igb_clean_rx_ring(struct igb_ring *);
134static void igb_set_rx_mode(struct net_device *);
135static void igb_update_phy_info(unsigned long);
136static void igb_watchdog(unsigned long);
137static void igb_watchdog_task(struct work_struct *);
138static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
139static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
140 struct rtnl_link_stats64 *stats);
141static int igb_change_mtu(struct net_device *, int);
142static int igb_set_mac(struct net_device *, void *);
143static void igb_set_uta(struct igb_adapter *adapter);
144static irqreturn_t igb_intr(int irq, void *);
145static irqreturn_t igb_intr_msi(int irq, void *);
146static irqreturn_t igb_msix_other(int irq, void *);
147static irqreturn_t igb_msix_ring(int irq, void *);
148#ifdef CONFIG_IGB_DCA
149static void igb_update_dca(struct igb_q_vector *);
150static void igb_setup_dca(struct igb_adapter *);
151#endif /* CONFIG_IGB_DCA */
152static int igb_poll(struct napi_struct *, int);
153static bool igb_clean_tx_irq(struct igb_q_vector *);
154static bool igb_clean_rx_irq(struct igb_q_vector *, int);
155static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156static void igb_tx_timeout(struct net_device *);
157static void igb_reset_task(struct work_struct *);
158static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
160static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
162static void igb_restore_vlan(struct igb_adapter *);
163static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
164static void igb_ping_all_vfs(struct igb_adapter *);
165static void igb_msg_task(struct igb_adapter *);
166static void igb_vmm_control(struct igb_adapter *);
167static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
168static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
169static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
172static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
173static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 bool setting);
175static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
177static void igb_check_vf_rate_limit(struct igb_adapter *);
178
179#ifdef CONFIG_PCI_IOV
180static int igb_vf_configure(struct igb_adapter *adapter, int vf);
181static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
182#endif
183
184#ifdef CONFIG_PM
185#ifdef CONFIG_PM_SLEEP
186static int igb_suspend(struct device *);
187#endif
188static int igb_resume(struct device *);
189static int igb_runtime_suspend(struct device *dev);
190static int igb_runtime_resume(struct device *dev);
191static int igb_runtime_idle(struct device *dev);
192static const struct dev_pm_ops igb_pm_ops = {
193 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
194 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
195 igb_runtime_idle)
196};
197#endif
198static void igb_shutdown(struct pci_dev *);
199static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
200#ifdef CONFIG_IGB_DCA
201static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
202static struct notifier_block dca_notifier = {
203 .notifier_call = igb_notify_dca,
204 .next = NULL,
205 .priority = 0
206};
207#endif
208#ifdef CONFIG_NET_POLL_CONTROLLER
209/* for netdump / net console */
210static void igb_netpoll(struct net_device *);
211#endif
212#ifdef CONFIG_PCI_IOV
213static unsigned int max_vfs;
214module_param(max_vfs, uint, 0);
215MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
216#endif /* CONFIG_PCI_IOV */
217
218static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
219 pci_channel_state_t);
220static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
221static void igb_io_resume(struct pci_dev *);
222
223static const struct pci_error_handlers igb_err_handler = {
224 .error_detected = igb_io_error_detected,
225 .slot_reset = igb_io_slot_reset,
226 .resume = igb_io_resume,
227};
228
229static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
230
231static struct pci_driver igb_driver = {
232 .name = igb_driver_name,
233 .id_table = igb_pci_tbl,
234 .probe = igb_probe,
235 .remove = igb_remove,
236#ifdef CONFIG_PM
237 .driver.pm = &igb_pm_ops,
238#endif
239 .shutdown = igb_shutdown,
240 .sriov_configure = igb_pci_sriov_configure,
241 .err_handler = &igb_err_handler
242};
243
244MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
245MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
246MODULE_LICENSE("GPL");
247MODULE_VERSION(DRV_VERSION);
248
249#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
250static int debug = -1;
251module_param(debug, int, 0);
252MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
253
254struct igb_reg_info {
255 u32 ofs;
256 char *name;
257};
258
259static const struct igb_reg_info igb_reg_info_tbl[] = {
260
261 /* General Registers */
262 {E1000_CTRL, "CTRL"},
263 {E1000_STATUS, "STATUS"},
264 {E1000_CTRL_EXT, "CTRL_EXT"},
265
266 /* Interrupt Registers */
267 {E1000_ICR, "ICR"},
268
269 /* RX Registers */
270 {E1000_RCTL, "RCTL"},
271 {E1000_RDLEN(0), "RDLEN"},
272 {E1000_RDH(0), "RDH"},
273 {E1000_RDT(0), "RDT"},
274 {E1000_RXDCTL(0), "RXDCTL"},
275 {E1000_RDBAL(0), "RDBAL"},
276 {E1000_RDBAH(0), "RDBAH"},
277
278 /* TX Registers */
279 {E1000_TCTL, "TCTL"},
280 {E1000_TDBAL(0), "TDBAL"},
281 {E1000_TDBAH(0), "TDBAH"},
282 {E1000_TDLEN(0), "TDLEN"},
283 {E1000_TDH(0), "TDH"},
284 {E1000_TDT(0), "TDT"},
285 {E1000_TXDCTL(0), "TXDCTL"},
286 {E1000_TDFH, "TDFH"},
287 {E1000_TDFT, "TDFT"},
288 {E1000_TDFHS, "TDFHS"},
289 {E1000_TDFPC, "TDFPC"},
290
291 /* List Terminator */
292 {}
293};
294
295/* igb_regdump - register printout routine */
296static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
297{
298 int n = 0;
299 char rname[16];
300 u32 regs[8];
301
302 switch (reginfo->ofs) {
303 case E1000_RDLEN(0):
304 for (n = 0; n < 4; n++)
305 regs[n] = rd32(E1000_RDLEN(n));
306 break;
307 case E1000_RDH(0):
308 for (n = 0; n < 4; n++)
309 regs[n] = rd32(E1000_RDH(n));
310 break;
311 case E1000_RDT(0):
312 for (n = 0; n < 4; n++)
313 regs[n] = rd32(E1000_RDT(n));
314 break;
315 case E1000_RXDCTL(0):
316 for (n = 0; n < 4; n++)
317 regs[n] = rd32(E1000_RXDCTL(n));
318 break;
319 case E1000_RDBAL(0):
320 for (n = 0; n < 4; n++)
321 regs[n] = rd32(E1000_RDBAL(n));
322 break;
323 case E1000_RDBAH(0):
324 for (n = 0; n < 4; n++)
325 regs[n] = rd32(E1000_RDBAH(n));
326 break;
327 case E1000_TDBAL(0):
328 for (n = 0; n < 4; n++)
329 regs[n] = rd32(E1000_RDBAL(n));
330 break;
331 case E1000_TDBAH(0):
332 for (n = 0; n < 4; n++)
333 regs[n] = rd32(E1000_TDBAH(n));
334 break;
335 case E1000_TDLEN(0):
336 for (n = 0; n < 4; n++)
337 regs[n] = rd32(E1000_TDLEN(n));
338 break;
339 case E1000_TDH(0):
340 for (n = 0; n < 4; n++)
341 regs[n] = rd32(E1000_TDH(n));
342 break;
343 case E1000_TDT(0):
344 for (n = 0; n < 4; n++)
345 regs[n] = rd32(E1000_TDT(n));
346 break;
347 case E1000_TXDCTL(0):
348 for (n = 0; n < 4; n++)
349 regs[n] = rd32(E1000_TXDCTL(n));
350 break;
351 default:
352 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
353 return;
354 }
355
356 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
357 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
358 regs[2], regs[3]);
359}
360
361/* igb_dump - Print registers, Tx-rings and Rx-rings */
362static void igb_dump(struct igb_adapter *adapter)
363{
364 struct net_device *netdev = adapter->netdev;
365 struct e1000_hw *hw = &adapter->hw;
366 struct igb_reg_info *reginfo;
367 struct igb_ring *tx_ring;
368 union e1000_adv_tx_desc *tx_desc;
369 struct my_u0 { u64 a; u64 b; } *u0;
370 struct igb_ring *rx_ring;
371 union e1000_adv_rx_desc *rx_desc;
372 u32 staterr;
373 u16 i, n;
374
375 if (!netif_msg_hw(adapter))
376 return;
377
378 /* Print netdevice Info */
379 if (netdev) {
380 dev_info(&adapter->pdev->dev, "Net device Info\n");
381 pr_info("Device Name state trans_start last_rx\n");
382 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
383 netdev->state, netdev->trans_start, netdev->last_rx);
384 }
385
386 /* Print Registers */
387 dev_info(&adapter->pdev->dev, "Register Dump\n");
388 pr_info(" Register Name Value\n");
389 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
390 reginfo->name; reginfo++) {
391 igb_regdump(hw, reginfo);
392 }
393
394 /* Print TX Ring Summary */
395 if (!netdev || !netif_running(netdev))
396 goto exit;
397
398 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
399 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
400 for (n = 0; n < adapter->num_tx_queues; n++) {
401 struct igb_tx_buffer *buffer_info;
402 tx_ring = adapter->tx_ring[n];
403 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
404 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
405 n, tx_ring->next_to_use, tx_ring->next_to_clean,
406 (u64)dma_unmap_addr(buffer_info, dma),
407 dma_unmap_len(buffer_info, len),
408 buffer_info->next_to_watch,
409 (u64)buffer_info->time_stamp);
410 }
411
412 /* Print TX Rings */
413 if (!netif_msg_tx_done(adapter))
414 goto rx_ring_summary;
415
416 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
417
418 /* Transmit Descriptor Formats
419 *
420 * Advanced Transmit Descriptor
421 * +--------------------------------------------------------------+
422 * 0 | Buffer Address [63:0] |
423 * +--------------------------------------------------------------+
424 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
425 * +--------------------------------------------------------------+
426 * 63 46 45 40 39 38 36 35 32 31 24 15 0
427 */
428
429 for (n = 0; n < adapter->num_tx_queues; n++) {
430 tx_ring = adapter->tx_ring[n];
431 pr_info("------------------------------------\n");
432 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
433 pr_info("------------------------------------\n");
434 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
435
436 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
437 const char *next_desc;
438 struct igb_tx_buffer *buffer_info;
439 tx_desc = IGB_TX_DESC(tx_ring, i);
440 buffer_info = &tx_ring->tx_buffer_info[i];
441 u0 = (struct my_u0 *)tx_desc;
442 if (i == tx_ring->next_to_use &&
443 i == tx_ring->next_to_clean)
444 next_desc = " NTC/U";
445 else if (i == tx_ring->next_to_use)
446 next_desc = " NTU";
447 else if (i == tx_ring->next_to_clean)
448 next_desc = " NTC";
449 else
450 next_desc = "";
451
452 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
453 i, le64_to_cpu(u0->a),
454 le64_to_cpu(u0->b),
455 (u64)dma_unmap_addr(buffer_info, dma),
456 dma_unmap_len(buffer_info, len),
457 buffer_info->next_to_watch,
458 (u64)buffer_info->time_stamp,
459 buffer_info->skb, next_desc);
460
461 if (netif_msg_pktdata(adapter) && buffer_info->skb)
462 print_hex_dump(KERN_INFO, "",
463 DUMP_PREFIX_ADDRESS,
464 16, 1, buffer_info->skb->data,
465 dma_unmap_len(buffer_info, len),
466 true);
467 }
468 }
469
470 /* Print RX Rings Summary */
471rx_ring_summary:
472 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
473 pr_info("Queue [NTU] [NTC]\n");
474 for (n = 0; n < adapter->num_rx_queues; n++) {
475 rx_ring = adapter->rx_ring[n];
476 pr_info(" %5d %5X %5X\n",
477 n, rx_ring->next_to_use, rx_ring->next_to_clean);
478 }
479
480 /* Print RX Rings */
481 if (!netif_msg_rx_status(adapter))
482 goto exit;
483
484 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
485
486 /* Advanced Receive Descriptor (Read) Format
487 * 63 1 0
488 * +-----------------------------------------------------+
489 * 0 | Packet Buffer Address [63:1] |A0/NSE|
490 * +----------------------------------------------+------+
491 * 8 | Header Buffer Address [63:1] | DD |
492 * +-----------------------------------------------------+
493 *
494 *
495 * Advanced Receive Descriptor (Write-Back) Format
496 *
497 * 63 48 47 32 31 30 21 20 17 16 4 3 0
498 * +------------------------------------------------------+
499 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
500 * | Checksum Ident | | | | Type | Type |
501 * +------------------------------------------------------+
502 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
503 * +------------------------------------------------------+
504 * 63 48 47 32 31 20 19 0
505 */
506
507 for (n = 0; n < adapter->num_rx_queues; n++) {
508 rx_ring = adapter->rx_ring[n];
509 pr_info("------------------------------------\n");
510 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
511 pr_info("------------------------------------\n");
512 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
513 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
514
515 for (i = 0; i < rx_ring->count; i++) {
516 const char *next_desc;
517 struct igb_rx_buffer *buffer_info;
518 buffer_info = &rx_ring->rx_buffer_info[i];
519 rx_desc = IGB_RX_DESC(rx_ring, i);
520 u0 = (struct my_u0 *)rx_desc;
521 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
522
523 if (i == rx_ring->next_to_use)
524 next_desc = " NTU";
525 else if (i == rx_ring->next_to_clean)
526 next_desc = " NTC";
527 else
528 next_desc = "";
529
530 if (staterr & E1000_RXD_STAT_DD) {
531 /* Descriptor Done */
532 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
533 "RWB", i,
534 le64_to_cpu(u0->a),
535 le64_to_cpu(u0->b),
536 next_desc);
537 } else {
538 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
539 "R ", i,
540 le64_to_cpu(u0->a),
541 le64_to_cpu(u0->b),
542 (u64)buffer_info->dma,
543 next_desc);
544
545 if (netif_msg_pktdata(adapter) &&
546 buffer_info->dma && buffer_info->page) {
547 print_hex_dump(KERN_INFO, "",
548 DUMP_PREFIX_ADDRESS,
549 16, 1,
550 page_address(buffer_info->page) +
551 buffer_info->page_offset,
552 IGB_RX_BUFSZ, true);
553 }
554 }
555 }
556 }
557
558exit:
559 return;
560}
561
562/**
563 * igb_get_i2c_data - Reads the I2C SDA data bit
564 * @hw: pointer to hardware structure
565 * @i2cctl: Current value of I2CCTL register
566 *
567 * Returns the I2C data bit value
568 **/
569static int igb_get_i2c_data(void *data)
570{
571 struct igb_adapter *adapter = (struct igb_adapter *)data;
572 struct e1000_hw *hw = &adapter->hw;
573 s32 i2cctl = rd32(E1000_I2CPARAMS);
574
575 return !!(i2cctl & E1000_I2C_DATA_IN);
576}
577
578/**
579 * igb_set_i2c_data - Sets the I2C data bit
580 * @data: pointer to hardware structure
581 * @state: I2C data value (0 or 1) to set
582 *
583 * Sets the I2C data bit
584 **/
585static void igb_set_i2c_data(void *data, int state)
586{
587 struct igb_adapter *adapter = (struct igb_adapter *)data;
588 struct e1000_hw *hw = &adapter->hw;
589 s32 i2cctl = rd32(E1000_I2CPARAMS);
590
591 if (state)
592 i2cctl |= E1000_I2C_DATA_OUT;
593 else
594 i2cctl &= ~E1000_I2C_DATA_OUT;
595
596 i2cctl &= ~E1000_I2C_DATA_OE_N;
597 i2cctl |= E1000_I2C_CLK_OE_N;
598 wr32(E1000_I2CPARAMS, i2cctl);
599 wrfl();
600
601}
602
603/**
604 * igb_set_i2c_clk - Sets the I2C SCL clock
605 * @data: pointer to hardware structure
606 * @state: state to set clock
607 *
608 * Sets the I2C clock line to state
609 **/
610static void igb_set_i2c_clk(void *data, int state)
611{
612 struct igb_adapter *adapter = (struct igb_adapter *)data;
613 struct e1000_hw *hw = &adapter->hw;
614 s32 i2cctl = rd32(E1000_I2CPARAMS);
615
616 if (state) {
617 i2cctl |= E1000_I2C_CLK_OUT;
618 i2cctl &= ~E1000_I2C_CLK_OE_N;
619 } else {
620 i2cctl &= ~E1000_I2C_CLK_OUT;
621 i2cctl &= ~E1000_I2C_CLK_OE_N;
622 }
623 wr32(E1000_I2CPARAMS, i2cctl);
624 wrfl();
625}
626
627/**
628 * igb_get_i2c_clk - Gets the I2C SCL clock state
629 * @data: pointer to hardware structure
630 *
631 * Gets the I2C clock state
632 **/
633static int igb_get_i2c_clk(void *data)
634{
635 struct igb_adapter *adapter = (struct igb_adapter *)data;
636 struct e1000_hw *hw = &adapter->hw;
637 s32 i2cctl = rd32(E1000_I2CPARAMS);
638
639 return !!(i2cctl & E1000_I2C_CLK_IN);
640}
641
642static const struct i2c_algo_bit_data igb_i2c_algo = {
643 .setsda = igb_set_i2c_data,
644 .setscl = igb_set_i2c_clk,
645 .getsda = igb_get_i2c_data,
646 .getscl = igb_get_i2c_clk,
647 .udelay = 5,
648 .timeout = 20,
649};
650
651/**
652 * igb_get_hw_dev - return device
653 * @hw: pointer to hardware structure
654 *
655 * used by hardware layer to print debugging information
656 **/
657struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
658{
659 struct igb_adapter *adapter = hw->back;
660 return adapter->netdev;
661}
662
663/**
664 * igb_init_module - Driver Registration Routine
665 *
666 * igb_init_module is the first routine called when the driver is
667 * loaded. All it does is register with the PCI subsystem.
668 **/
669static int __init igb_init_module(void)
670{
671 int ret;
672
673 pr_info("%s - version %s\n",
674 igb_driver_string, igb_driver_version);
675 pr_info("%s\n", igb_copyright);
676
677#ifdef CONFIG_IGB_DCA
678 dca_register_notify(&dca_notifier);
679#endif
680 ret = pci_register_driver(&igb_driver);
681 return ret;
682}
683
684module_init(igb_init_module);
685
686/**
687 * igb_exit_module - Driver Exit Cleanup Routine
688 *
689 * igb_exit_module is called just before the driver is removed
690 * from memory.
691 **/
692static void __exit igb_exit_module(void)
693{
694#ifdef CONFIG_IGB_DCA
695 dca_unregister_notify(&dca_notifier);
696#endif
697 pci_unregister_driver(&igb_driver);
698}
699
700module_exit(igb_exit_module);
701
702#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
703/**
704 * igb_cache_ring_register - Descriptor ring to register mapping
705 * @adapter: board private structure to initialize
706 *
707 * Once we know the feature-set enabled for the device, we'll cache
708 * the register offset the descriptor ring is assigned to.
709 **/
710static void igb_cache_ring_register(struct igb_adapter *adapter)
711{
712 int i = 0, j = 0;
713 u32 rbase_offset = adapter->vfs_allocated_count;
714
715 switch (adapter->hw.mac.type) {
716 case e1000_82576:
717 /* The queues are allocated for virtualization such that VF 0
718 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
719 * In order to avoid collision we start at the first free queue
720 * and continue consuming queues in the same sequence
721 */
722 if (adapter->vfs_allocated_count) {
723 for (; i < adapter->rss_queues; i++)
724 adapter->rx_ring[i]->reg_idx = rbase_offset +
725 Q_IDX_82576(i);
726 }
727 /* Fall through */
728 case e1000_82575:
729 case e1000_82580:
730 case e1000_i350:
731 case e1000_i354:
732 case e1000_i210:
733 case e1000_i211:
734 /* Fall through */
735 default:
736 for (; i < adapter->num_rx_queues; i++)
737 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
738 for (; j < adapter->num_tx_queues; j++)
739 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
740 break;
741 }
742}
743
744u32 igb_rd32(struct e1000_hw *hw, u32 reg)
745{
746 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
747 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
748 u32 value = 0;
749
750 if (E1000_REMOVED(hw_addr))
751 return ~value;
752
753 value = readl(&hw_addr[reg]);
754
755 /* reads should not return all F's */
756 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
757 struct net_device *netdev = igb->netdev;
758 hw->hw_addr = NULL;
759 netif_device_detach(netdev);
760 netdev_err(netdev, "PCIe link lost, device now detached\n");
761 }
762
763 return value;
764}
765
766/**
767 * igb_write_ivar - configure ivar for given MSI-X vector
768 * @hw: pointer to the HW structure
769 * @msix_vector: vector number we are allocating to a given ring
770 * @index: row index of IVAR register to write within IVAR table
771 * @offset: column offset of in IVAR, should be multiple of 8
772 *
773 * This function is intended to handle the writing of the IVAR register
774 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
775 * each containing an cause allocation for an Rx and Tx ring, and a
776 * variable number of rows depending on the number of queues supported.
777 **/
778static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
779 int index, int offset)
780{
781 u32 ivar = array_rd32(E1000_IVAR0, index);
782
783 /* clear any bits that are currently set */
784 ivar &= ~((u32)0xFF << offset);
785
786 /* write vector and valid bit */
787 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
788
789 array_wr32(E1000_IVAR0, index, ivar);
790}
791
792#define IGB_N0_QUEUE -1
793static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
794{
795 struct igb_adapter *adapter = q_vector->adapter;
796 struct e1000_hw *hw = &adapter->hw;
797 int rx_queue = IGB_N0_QUEUE;
798 int tx_queue = IGB_N0_QUEUE;
799 u32 msixbm = 0;
800
801 if (q_vector->rx.ring)
802 rx_queue = q_vector->rx.ring->reg_idx;
803 if (q_vector->tx.ring)
804 tx_queue = q_vector->tx.ring->reg_idx;
805
806 switch (hw->mac.type) {
807 case e1000_82575:
808 /* The 82575 assigns vectors using a bitmask, which matches the
809 * bitmask for the EICR/EIMS/EIMC registers. To assign one
810 * or more queues to a vector, we write the appropriate bits
811 * into the MSIXBM register for that vector.
812 */
813 if (rx_queue > IGB_N0_QUEUE)
814 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
815 if (tx_queue > IGB_N0_QUEUE)
816 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
817 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
818 msixbm |= E1000_EIMS_OTHER;
819 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
820 q_vector->eims_value = msixbm;
821 break;
822 case e1000_82576:
823 /* 82576 uses a table that essentially consists of 2 columns
824 * with 8 rows. The ordering is column-major so we use the
825 * lower 3 bits as the row index, and the 4th bit as the
826 * column offset.
827 */
828 if (rx_queue > IGB_N0_QUEUE)
829 igb_write_ivar(hw, msix_vector,
830 rx_queue & 0x7,
831 (rx_queue & 0x8) << 1);
832 if (tx_queue > IGB_N0_QUEUE)
833 igb_write_ivar(hw, msix_vector,
834 tx_queue & 0x7,
835 ((tx_queue & 0x8) << 1) + 8);
836 q_vector->eims_value = 1 << msix_vector;
837 break;
838 case e1000_82580:
839 case e1000_i350:
840 case e1000_i354:
841 case e1000_i210:
842 case e1000_i211:
843 /* On 82580 and newer adapters the scheme is similar to 82576
844 * however instead of ordering column-major we have things
845 * ordered row-major. So we traverse the table by using
846 * bit 0 as the column offset, and the remaining bits as the
847 * row index.
848 */
849 if (rx_queue > IGB_N0_QUEUE)
850 igb_write_ivar(hw, msix_vector,
851 rx_queue >> 1,
852 (rx_queue & 0x1) << 4);
853 if (tx_queue > IGB_N0_QUEUE)
854 igb_write_ivar(hw, msix_vector,
855 tx_queue >> 1,
856 ((tx_queue & 0x1) << 4) + 8);
857 q_vector->eims_value = 1 << msix_vector;
858 break;
859 default:
860 BUG();
861 break;
862 }
863
864 /* add q_vector eims value to global eims_enable_mask */
865 adapter->eims_enable_mask |= q_vector->eims_value;
866
867 /* configure q_vector to set itr on first interrupt */
868 q_vector->set_itr = 1;
869}
870
871/**
872 * igb_configure_msix - Configure MSI-X hardware
873 * @adapter: board private structure to initialize
874 *
875 * igb_configure_msix sets up the hardware to properly
876 * generate MSI-X interrupts.
877 **/
878static void igb_configure_msix(struct igb_adapter *adapter)
879{
880 u32 tmp;
881 int i, vector = 0;
882 struct e1000_hw *hw = &adapter->hw;
883
884 adapter->eims_enable_mask = 0;
885
886 /* set vector for other causes, i.e. link changes */
887 switch (hw->mac.type) {
888 case e1000_82575:
889 tmp = rd32(E1000_CTRL_EXT);
890 /* enable MSI-X PBA support*/
891 tmp |= E1000_CTRL_EXT_PBA_CLR;
892
893 /* Auto-Mask interrupts upon ICR read. */
894 tmp |= E1000_CTRL_EXT_EIAME;
895 tmp |= E1000_CTRL_EXT_IRCA;
896
897 wr32(E1000_CTRL_EXT, tmp);
898
899 /* enable msix_other interrupt */
900 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
901 adapter->eims_other = E1000_EIMS_OTHER;
902
903 break;
904
905 case e1000_82576:
906 case e1000_82580:
907 case e1000_i350:
908 case e1000_i354:
909 case e1000_i210:
910 case e1000_i211:
911 /* Turn on MSI-X capability first, or our settings
912 * won't stick. And it will take days to debug.
913 */
914 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
915 E1000_GPIE_PBA | E1000_GPIE_EIAME |
916 E1000_GPIE_NSICR);
917
918 /* enable msix_other interrupt */
919 adapter->eims_other = 1 << vector;
920 tmp = (vector++ | E1000_IVAR_VALID) << 8;
921
922 wr32(E1000_IVAR_MISC, tmp);
923 break;
924 default:
925 /* do nothing, since nothing else supports MSI-X */
926 break;
927 } /* switch (hw->mac.type) */
928
929 adapter->eims_enable_mask |= adapter->eims_other;
930
931 for (i = 0; i < adapter->num_q_vectors; i++)
932 igb_assign_vector(adapter->q_vector[i], vector++);
933
934 wrfl();
935}
936
937/**
938 * igb_request_msix - Initialize MSI-X interrupts
939 * @adapter: board private structure to initialize
940 *
941 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
942 * kernel.
943 **/
944static int igb_request_msix(struct igb_adapter *adapter)
945{
946 struct net_device *netdev = adapter->netdev;
947 struct e1000_hw *hw = &adapter->hw;
948 int i, err = 0, vector = 0, free_vector = 0;
949
950 err = request_irq(adapter->msix_entries[vector].vector,
951 igb_msix_other, 0, netdev->name, adapter);
952 if (err)
953 goto err_out;
954
955 for (i = 0; i < adapter->num_q_vectors; i++) {
956 struct igb_q_vector *q_vector = adapter->q_vector[i];
957
958 vector++;
959
960 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
961
962 if (q_vector->rx.ring && q_vector->tx.ring)
963 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
964 q_vector->rx.ring->queue_index);
965 else if (q_vector->tx.ring)
966 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
967 q_vector->tx.ring->queue_index);
968 else if (q_vector->rx.ring)
969 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
970 q_vector->rx.ring->queue_index);
971 else
972 sprintf(q_vector->name, "%s-unused", netdev->name);
973
974 err = request_irq(adapter->msix_entries[vector].vector,
975 igb_msix_ring, 0, q_vector->name,
976 q_vector);
977 if (err)
978 goto err_free;
979 }
980
981 igb_configure_msix(adapter);
982 return 0;
983
984err_free:
985 /* free already assigned IRQs */
986 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
987
988 vector--;
989 for (i = 0; i < vector; i++) {
990 free_irq(adapter->msix_entries[free_vector++].vector,
991 adapter->q_vector[i]);
992 }
993err_out:
994 return err;
995}
996
997/**
998 * igb_free_q_vector - Free memory allocated for specific interrupt vector
999 * @adapter: board private structure to initialize
1000 * @v_idx: Index of vector to be freed
1001 *
1002 * This function frees the memory allocated to the q_vector.
1003 **/
1004static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1005{
1006 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1007
1008 adapter->q_vector[v_idx] = NULL;
1009
1010 /* igb_get_stats64() might access the rings on this vector,
1011 * we must wait a grace period before freeing it.
1012 */
1013 if (q_vector)
1014 kfree_rcu(q_vector, rcu);
1015}
1016
1017/**
1018 * igb_reset_q_vector - Reset config for interrupt vector
1019 * @adapter: board private structure to initialize
1020 * @v_idx: Index of vector to be reset
1021 *
1022 * If NAPI is enabled it will delete any references to the
1023 * NAPI struct. This is preparation for igb_free_q_vector.
1024 **/
1025static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1026{
1027 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1028
1029 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1030 * allocated. So, q_vector is NULL so we should stop here.
1031 */
1032 if (!q_vector)
1033 return;
1034
1035 if (q_vector->tx.ring)
1036 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1037
1038 if (q_vector->rx.ring)
1039 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
1040
1041 netif_napi_del(&q_vector->napi);
1042
1043}
1044
1045static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1046{
1047 int v_idx = adapter->num_q_vectors;
1048
1049 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1050 pci_disable_msix(adapter->pdev);
1051 else if (adapter->flags & IGB_FLAG_HAS_MSI)
1052 pci_disable_msi(adapter->pdev);
1053
1054 while (v_idx--)
1055 igb_reset_q_vector(adapter, v_idx);
1056}
1057
1058/**
1059 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1060 * @adapter: board private structure to initialize
1061 *
1062 * This function frees the memory allocated to the q_vectors. In addition if
1063 * NAPI is enabled it will delete any references to the NAPI struct prior
1064 * to freeing the q_vector.
1065 **/
1066static void igb_free_q_vectors(struct igb_adapter *adapter)
1067{
1068 int v_idx = adapter->num_q_vectors;
1069
1070 adapter->num_tx_queues = 0;
1071 adapter->num_rx_queues = 0;
1072 adapter->num_q_vectors = 0;
1073
1074 while (v_idx--) {
1075 igb_reset_q_vector(adapter, v_idx);
1076 igb_free_q_vector(adapter, v_idx);
1077 }
1078}
1079
1080/**
1081 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1082 * @adapter: board private structure to initialize
1083 *
1084 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1085 * MSI-X interrupts allocated.
1086 */
1087static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1088{
1089 igb_free_q_vectors(adapter);
1090 igb_reset_interrupt_capability(adapter);
1091}
1092
1093/**
1094 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1095 * @adapter: board private structure to initialize
1096 * @msix: boolean value of MSIX capability
1097 *
1098 * Attempt to configure interrupts using the best available
1099 * capabilities of the hardware and kernel.
1100 **/
1101static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1102{
1103 int err;
1104 int numvecs, i;
1105
1106 if (!msix)
1107 goto msi_only;
1108 adapter->flags |= IGB_FLAG_HAS_MSIX;
1109
1110 /* Number of supported queues. */
1111 adapter->num_rx_queues = adapter->rss_queues;
1112 if (adapter->vfs_allocated_count)
1113 adapter->num_tx_queues = 1;
1114 else
1115 adapter->num_tx_queues = adapter->rss_queues;
1116
1117 /* start with one vector for every Rx queue */
1118 numvecs = adapter->num_rx_queues;
1119
1120 /* if Tx handler is separate add 1 for every Tx queue */
1121 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1122 numvecs += adapter->num_tx_queues;
1123
1124 /* store the number of vectors reserved for queues */
1125 adapter->num_q_vectors = numvecs;
1126
1127 /* add 1 vector for link status interrupts */
1128 numvecs++;
1129 for (i = 0; i < numvecs; i++)
1130 adapter->msix_entries[i].entry = i;
1131
1132 err = pci_enable_msix_range(adapter->pdev,
1133 adapter->msix_entries,
1134 numvecs,
1135 numvecs);
1136 if (err > 0)
1137 return;
1138
1139 igb_reset_interrupt_capability(adapter);
1140
1141 /* If we can't do MSI-X, try MSI */
1142msi_only:
1143 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1144#ifdef CONFIG_PCI_IOV
1145 /* disable SR-IOV for non MSI-X configurations */
1146 if (adapter->vf_data) {
1147 struct e1000_hw *hw = &adapter->hw;
1148 /* disable iov and allow time for transactions to clear */
1149 pci_disable_sriov(adapter->pdev);
1150 msleep(500);
1151
1152 kfree(adapter->vf_data);
1153 adapter->vf_data = NULL;
1154 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1155 wrfl();
1156 msleep(100);
1157 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1158 }
1159#endif
1160 adapter->vfs_allocated_count = 0;
1161 adapter->rss_queues = 1;
1162 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1163 adapter->num_rx_queues = 1;
1164 adapter->num_tx_queues = 1;
1165 adapter->num_q_vectors = 1;
1166 if (!pci_enable_msi(adapter->pdev))
1167 adapter->flags |= IGB_FLAG_HAS_MSI;
1168}
1169
1170static void igb_add_ring(struct igb_ring *ring,
1171 struct igb_ring_container *head)
1172{
1173 head->ring = ring;
1174 head->count++;
1175}
1176
1177/**
1178 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1179 * @adapter: board private structure to initialize
1180 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1181 * @v_idx: index of vector in adapter struct
1182 * @txr_count: total number of Tx rings to allocate
1183 * @txr_idx: index of first Tx ring to allocate
1184 * @rxr_count: total number of Rx rings to allocate
1185 * @rxr_idx: index of first Rx ring to allocate
1186 *
1187 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1188 **/
1189static int igb_alloc_q_vector(struct igb_adapter *adapter,
1190 int v_count, int v_idx,
1191 int txr_count, int txr_idx,
1192 int rxr_count, int rxr_idx)
1193{
1194 struct igb_q_vector *q_vector;
1195 struct igb_ring *ring;
1196 int ring_count, size;
1197
1198 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1199 if (txr_count > 1 || rxr_count > 1)
1200 return -ENOMEM;
1201
1202 ring_count = txr_count + rxr_count;
1203 size = sizeof(struct igb_q_vector) +
1204 (sizeof(struct igb_ring) * ring_count);
1205
1206 /* allocate q_vector and rings */
1207 q_vector = adapter->q_vector[v_idx];
1208 if (!q_vector) {
1209 q_vector = kzalloc(size, GFP_KERNEL);
1210 } else if (size > ksize(q_vector)) {
1211 kfree_rcu(q_vector, rcu);
1212 q_vector = kzalloc(size, GFP_KERNEL);
1213 } else {
1214 memset(q_vector, 0, size);
1215 }
1216 if (!q_vector)
1217 return -ENOMEM;
1218
1219 /* initialize NAPI */
1220 netif_napi_add(adapter->netdev, &q_vector->napi,
1221 igb_poll, 64);
1222
1223 /* tie q_vector and adapter together */
1224 adapter->q_vector[v_idx] = q_vector;
1225 q_vector->adapter = adapter;
1226
1227 /* initialize work limits */
1228 q_vector->tx.work_limit = adapter->tx_work_limit;
1229
1230 /* initialize ITR configuration */
1231 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1232 q_vector->itr_val = IGB_START_ITR;
1233
1234 /* initialize pointer to rings */
1235 ring = q_vector->ring;
1236
1237 /* intialize ITR */
1238 if (rxr_count) {
1239 /* rx or rx/tx vector */
1240 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1241 q_vector->itr_val = adapter->rx_itr_setting;
1242 } else {
1243 /* tx only vector */
1244 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1245 q_vector->itr_val = adapter->tx_itr_setting;
1246 }
1247
1248 if (txr_count) {
1249 /* assign generic ring traits */
1250 ring->dev = &adapter->pdev->dev;
1251 ring->netdev = adapter->netdev;
1252
1253 /* configure backlink on ring */
1254 ring->q_vector = q_vector;
1255
1256 /* update q_vector Tx values */
1257 igb_add_ring(ring, &q_vector->tx);
1258
1259 /* For 82575, context index must be unique per ring. */
1260 if (adapter->hw.mac.type == e1000_82575)
1261 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1262
1263 /* apply Tx specific ring traits */
1264 ring->count = adapter->tx_ring_count;
1265 ring->queue_index = txr_idx;
1266
1267 u64_stats_init(&ring->tx_syncp);
1268 u64_stats_init(&ring->tx_syncp2);
1269
1270 /* assign ring to adapter */
1271 adapter->tx_ring[txr_idx] = ring;
1272
1273 /* push pointer to next ring */
1274 ring++;
1275 }
1276
1277 if (rxr_count) {
1278 /* assign generic ring traits */
1279 ring->dev = &adapter->pdev->dev;
1280 ring->netdev = adapter->netdev;
1281
1282 /* configure backlink on ring */
1283 ring->q_vector = q_vector;
1284
1285 /* update q_vector Rx values */
1286 igb_add_ring(ring, &q_vector->rx);
1287
1288 /* set flag indicating ring supports SCTP checksum offload */
1289 if (adapter->hw.mac.type >= e1000_82576)
1290 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1291
1292 /* On i350, i354, i210, and i211, loopback VLAN packets
1293 * have the tag byte-swapped.
1294 */
1295 if (adapter->hw.mac.type >= e1000_i350)
1296 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1297
1298 /* apply Rx specific ring traits */
1299 ring->count = adapter->rx_ring_count;
1300 ring->queue_index = rxr_idx;
1301
1302 u64_stats_init(&ring->rx_syncp);
1303
1304 /* assign ring to adapter */
1305 adapter->rx_ring[rxr_idx] = ring;
1306 }
1307
1308 return 0;
1309}
1310
1311
1312/**
1313 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1314 * @adapter: board private structure to initialize
1315 *
1316 * We allocate one q_vector per queue interrupt. If allocation fails we
1317 * return -ENOMEM.
1318 **/
1319static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1320{
1321 int q_vectors = adapter->num_q_vectors;
1322 int rxr_remaining = adapter->num_rx_queues;
1323 int txr_remaining = adapter->num_tx_queues;
1324 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1325 int err;
1326
1327 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1328 for (; rxr_remaining; v_idx++) {
1329 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1330 0, 0, 1, rxr_idx);
1331
1332 if (err)
1333 goto err_out;
1334
1335 /* update counts and index */
1336 rxr_remaining--;
1337 rxr_idx++;
1338 }
1339 }
1340
1341 for (; v_idx < q_vectors; v_idx++) {
1342 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1343 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1344
1345 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1346 tqpv, txr_idx, rqpv, rxr_idx);
1347
1348 if (err)
1349 goto err_out;
1350
1351 /* update counts and index */
1352 rxr_remaining -= rqpv;
1353 txr_remaining -= tqpv;
1354 rxr_idx++;
1355 txr_idx++;
1356 }
1357
1358 return 0;
1359
1360err_out:
1361 adapter->num_tx_queues = 0;
1362 adapter->num_rx_queues = 0;
1363 adapter->num_q_vectors = 0;
1364
1365 while (v_idx--)
1366 igb_free_q_vector(adapter, v_idx);
1367
1368 return -ENOMEM;
1369}
1370
1371/**
1372 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1373 * @adapter: board private structure to initialize
1374 * @msix: boolean value of MSIX capability
1375 *
1376 * This function initializes the interrupts and allocates all of the queues.
1377 **/
1378static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1379{
1380 struct pci_dev *pdev = adapter->pdev;
1381 int err;
1382
1383 igb_set_interrupt_capability(adapter, msix);
1384
1385 err = igb_alloc_q_vectors(adapter);
1386 if (err) {
1387 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1388 goto err_alloc_q_vectors;
1389 }
1390
1391 igb_cache_ring_register(adapter);
1392
1393 return 0;
1394
1395err_alloc_q_vectors:
1396 igb_reset_interrupt_capability(adapter);
1397 return err;
1398}
1399
1400/**
1401 * igb_request_irq - initialize interrupts
1402 * @adapter: board private structure to initialize
1403 *
1404 * Attempts to configure interrupts using the best available
1405 * capabilities of the hardware and kernel.
1406 **/
1407static int igb_request_irq(struct igb_adapter *adapter)
1408{
1409 struct net_device *netdev = adapter->netdev;
1410 struct pci_dev *pdev = adapter->pdev;
1411 int err = 0;
1412
1413 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1414 err = igb_request_msix(adapter);
1415 if (!err)
1416 goto request_done;
1417 /* fall back to MSI */
1418 igb_free_all_tx_resources(adapter);
1419 igb_free_all_rx_resources(adapter);
1420
1421 igb_clear_interrupt_scheme(adapter);
1422 err = igb_init_interrupt_scheme(adapter, false);
1423 if (err)
1424 goto request_done;
1425
1426 igb_setup_all_tx_resources(adapter);
1427 igb_setup_all_rx_resources(adapter);
1428 igb_configure(adapter);
1429 }
1430
1431 igb_assign_vector(adapter->q_vector[0], 0);
1432
1433 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1434 err = request_irq(pdev->irq, igb_intr_msi, 0,
1435 netdev->name, adapter);
1436 if (!err)
1437 goto request_done;
1438
1439 /* fall back to legacy interrupts */
1440 igb_reset_interrupt_capability(adapter);
1441 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1442 }
1443
1444 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1445 netdev->name, adapter);
1446
1447 if (err)
1448 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1449 err);
1450
1451request_done:
1452 return err;
1453}
1454
1455static void igb_free_irq(struct igb_adapter *adapter)
1456{
1457 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1458 int vector = 0, i;
1459
1460 free_irq(adapter->msix_entries[vector++].vector, adapter);
1461
1462 for (i = 0; i < adapter->num_q_vectors; i++)
1463 free_irq(adapter->msix_entries[vector++].vector,
1464 adapter->q_vector[i]);
1465 } else {
1466 free_irq(adapter->pdev->irq, adapter);
1467 }
1468}
1469
1470/**
1471 * igb_irq_disable - Mask off interrupt generation on the NIC
1472 * @adapter: board private structure
1473 **/
1474static void igb_irq_disable(struct igb_adapter *adapter)
1475{
1476 struct e1000_hw *hw = &adapter->hw;
1477
1478 /* we need to be careful when disabling interrupts. The VFs are also
1479 * mapped into these registers and so clearing the bits can cause
1480 * issues on the VF drivers so we only need to clear what we set
1481 */
1482 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1483 u32 regval = rd32(E1000_EIAM);
1484
1485 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1486 wr32(E1000_EIMC, adapter->eims_enable_mask);
1487 regval = rd32(E1000_EIAC);
1488 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1489 }
1490
1491 wr32(E1000_IAM, 0);
1492 wr32(E1000_IMC, ~0);
1493 wrfl();
1494 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1495 int i;
1496
1497 for (i = 0; i < adapter->num_q_vectors; i++)
1498 synchronize_irq(adapter->msix_entries[i].vector);
1499 } else {
1500 synchronize_irq(adapter->pdev->irq);
1501 }
1502}
1503
1504/**
1505 * igb_irq_enable - Enable default interrupt generation settings
1506 * @adapter: board private structure
1507 **/
1508static void igb_irq_enable(struct igb_adapter *adapter)
1509{
1510 struct e1000_hw *hw = &adapter->hw;
1511
1512 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1513 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1514 u32 regval = rd32(E1000_EIAC);
1515
1516 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1517 regval = rd32(E1000_EIAM);
1518 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1519 wr32(E1000_EIMS, adapter->eims_enable_mask);
1520 if (adapter->vfs_allocated_count) {
1521 wr32(E1000_MBVFIMR, 0xFF);
1522 ims |= E1000_IMS_VMMB;
1523 }
1524 wr32(E1000_IMS, ims);
1525 } else {
1526 wr32(E1000_IMS, IMS_ENABLE_MASK |
1527 E1000_IMS_DRSTA);
1528 wr32(E1000_IAM, IMS_ENABLE_MASK |
1529 E1000_IMS_DRSTA);
1530 }
1531}
1532
1533static void igb_update_mng_vlan(struct igb_adapter *adapter)
1534{
1535 struct e1000_hw *hw = &adapter->hw;
1536 u16 vid = adapter->hw.mng_cookie.vlan_id;
1537 u16 old_vid = adapter->mng_vlan_id;
1538
1539 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1540 /* add VID to filter table */
1541 igb_vfta_set(hw, vid, true);
1542 adapter->mng_vlan_id = vid;
1543 } else {
1544 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1545 }
1546
1547 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1548 (vid != old_vid) &&
1549 !test_bit(old_vid, adapter->active_vlans)) {
1550 /* remove VID from filter table */
1551 igb_vfta_set(hw, old_vid, false);
1552 }
1553}
1554
1555/**
1556 * igb_release_hw_control - release control of the h/w to f/w
1557 * @adapter: address of board private structure
1558 *
1559 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1560 * For ASF and Pass Through versions of f/w this means that the
1561 * driver is no longer loaded.
1562 **/
1563static void igb_release_hw_control(struct igb_adapter *adapter)
1564{
1565 struct e1000_hw *hw = &adapter->hw;
1566 u32 ctrl_ext;
1567
1568 /* Let firmware take over control of h/w */
1569 ctrl_ext = rd32(E1000_CTRL_EXT);
1570 wr32(E1000_CTRL_EXT,
1571 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1572}
1573
1574/**
1575 * igb_get_hw_control - get control of the h/w from f/w
1576 * @adapter: address of board private structure
1577 *
1578 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1579 * For ASF and Pass Through versions of f/w this means that
1580 * the driver is loaded.
1581 **/
1582static void igb_get_hw_control(struct igb_adapter *adapter)
1583{
1584 struct e1000_hw *hw = &adapter->hw;
1585 u32 ctrl_ext;
1586
1587 /* Let firmware know the driver has taken over */
1588 ctrl_ext = rd32(E1000_CTRL_EXT);
1589 wr32(E1000_CTRL_EXT,
1590 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1591}
1592
1593/**
1594 * igb_configure - configure the hardware for RX and TX
1595 * @adapter: private board structure
1596 **/
1597static void igb_configure(struct igb_adapter *adapter)
1598{
1599 struct net_device *netdev = adapter->netdev;
1600 int i;
1601
1602 igb_get_hw_control(adapter);
1603 igb_set_rx_mode(netdev);
1604
1605 igb_restore_vlan(adapter);
1606
1607 igb_setup_tctl(adapter);
1608 igb_setup_mrqc(adapter);
1609 igb_setup_rctl(adapter);
1610
1611 igb_configure_tx(adapter);
1612 igb_configure_rx(adapter);
1613
1614 igb_rx_fifo_flush_82575(&adapter->hw);
1615
1616 /* call igb_desc_unused which always leaves
1617 * at least 1 descriptor unused to make sure
1618 * next_to_use != next_to_clean
1619 */
1620 for (i = 0; i < adapter->num_rx_queues; i++) {
1621 struct igb_ring *ring = adapter->rx_ring[i];
1622 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1623 }
1624}
1625
1626/**
1627 * igb_power_up_link - Power up the phy/serdes link
1628 * @adapter: address of board private structure
1629 **/
1630void igb_power_up_link(struct igb_adapter *adapter)
1631{
1632 igb_reset_phy(&adapter->hw);
1633
1634 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1635 igb_power_up_phy_copper(&adapter->hw);
1636 else
1637 igb_power_up_serdes_link_82575(&adapter->hw);
1638
1639 igb_setup_link(&adapter->hw);
1640}
1641
1642/**
1643 * igb_power_down_link - Power down the phy/serdes link
1644 * @adapter: address of board private structure
1645 */
1646static void igb_power_down_link(struct igb_adapter *adapter)
1647{
1648 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1649 igb_power_down_phy_copper_82575(&adapter->hw);
1650 else
1651 igb_shutdown_serdes_link_82575(&adapter->hw);
1652}
1653
1654/**
1655 * Detect and switch function for Media Auto Sense
1656 * @adapter: address of the board private structure
1657 **/
1658static void igb_check_swap_media(struct igb_adapter *adapter)
1659{
1660 struct e1000_hw *hw = &adapter->hw;
1661 u32 ctrl_ext, connsw;
1662 bool swap_now = false;
1663
1664 ctrl_ext = rd32(E1000_CTRL_EXT);
1665 connsw = rd32(E1000_CONNSW);
1666
1667 /* need to live swap if current media is copper and we have fiber/serdes
1668 * to go to.
1669 */
1670
1671 if ((hw->phy.media_type == e1000_media_type_copper) &&
1672 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1673 swap_now = true;
1674 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1675 /* copper signal takes time to appear */
1676 if (adapter->copper_tries < 4) {
1677 adapter->copper_tries++;
1678 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1679 wr32(E1000_CONNSW, connsw);
1680 return;
1681 } else {
1682 adapter->copper_tries = 0;
1683 if ((connsw & E1000_CONNSW_PHYSD) &&
1684 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1685 swap_now = true;
1686 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1687 wr32(E1000_CONNSW, connsw);
1688 }
1689 }
1690 }
1691
1692 if (!swap_now)
1693 return;
1694
1695 switch (hw->phy.media_type) {
1696 case e1000_media_type_copper:
1697 netdev_info(adapter->netdev,
1698 "MAS: changing media to fiber/serdes\n");
1699 ctrl_ext |=
1700 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1701 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1702 adapter->copper_tries = 0;
1703 break;
1704 case e1000_media_type_internal_serdes:
1705 case e1000_media_type_fiber:
1706 netdev_info(adapter->netdev,
1707 "MAS: changing media to copper\n");
1708 ctrl_ext &=
1709 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1710 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1711 break;
1712 default:
1713 /* shouldn't get here during regular operation */
1714 netdev_err(adapter->netdev,
1715 "AMS: Invalid media type found, returning\n");
1716 break;
1717 }
1718 wr32(E1000_CTRL_EXT, ctrl_ext);
1719}
1720
1721/**
1722 * igb_up - Open the interface and prepare it to handle traffic
1723 * @adapter: board private structure
1724 **/
1725int igb_up(struct igb_adapter *adapter)
1726{
1727 struct e1000_hw *hw = &adapter->hw;
1728 int i;
1729
1730 /* hardware has been reset, we need to reload some things */
1731 igb_configure(adapter);
1732
1733 clear_bit(__IGB_DOWN, &adapter->state);
1734
1735 for (i = 0; i < adapter->num_q_vectors; i++)
1736 napi_enable(&(adapter->q_vector[i]->napi));
1737
1738 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1739 igb_configure_msix(adapter);
1740 else
1741 igb_assign_vector(adapter->q_vector[0], 0);
1742
1743 /* Clear any pending interrupts. */
1744 rd32(E1000_ICR);
1745 igb_irq_enable(adapter);
1746
1747 /* notify VFs that reset has been completed */
1748 if (adapter->vfs_allocated_count) {
1749 u32 reg_data = rd32(E1000_CTRL_EXT);
1750
1751 reg_data |= E1000_CTRL_EXT_PFRSTD;
1752 wr32(E1000_CTRL_EXT, reg_data);
1753 }
1754
1755 netif_tx_start_all_queues(adapter->netdev);
1756
1757 /* start the watchdog. */
1758 hw->mac.get_link_status = 1;
1759 schedule_work(&adapter->watchdog_task);
1760
1761 if ((adapter->flags & IGB_FLAG_EEE) &&
1762 (!hw->dev_spec._82575.eee_disable))
1763 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1764
1765 return 0;
1766}
1767
1768void igb_down(struct igb_adapter *adapter)
1769{
1770 struct net_device *netdev = adapter->netdev;
1771 struct e1000_hw *hw = &adapter->hw;
1772 u32 tctl, rctl;
1773 int i;
1774
1775 /* signal that we're down so the interrupt handler does not
1776 * reschedule our watchdog timer
1777 */
1778 set_bit(__IGB_DOWN, &adapter->state);
1779
1780 /* disable receives in the hardware */
1781 rctl = rd32(E1000_RCTL);
1782 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1783 /* flush and sleep below */
1784
1785 netif_carrier_off(netdev);
1786 netif_tx_stop_all_queues(netdev);
1787
1788 /* disable transmits in the hardware */
1789 tctl = rd32(E1000_TCTL);
1790 tctl &= ~E1000_TCTL_EN;
1791 wr32(E1000_TCTL, tctl);
1792 /* flush both disables and wait for them to finish */
1793 wrfl();
1794 usleep_range(10000, 11000);
1795
1796 igb_irq_disable(adapter);
1797
1798 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1799
1800 for (i = 0; i < adapter->num_q_vectors; i++) {
1801 if (adapter->q_vector[i]) {
1802 napi_synchronize(&adapter->q_vector[i]->napi);
1803 napi_disable(&adapter->q_vector[i]->napi);
1804 }
1805 }
1806
1807 del_timer_sync(&adapter->watchdog_timer);
1808 del_timer_sync(&adapter->phy_info_timer);
1809
1810 /* record the stats before reset*/
1811 spin_lock(&adapter->stats64_lock);
1812 igb_update_stats(adapter, &adapter->stats64);
1813 spin_unlock(&adapter->stats64_lock);
1814
1815 adapter->link_speed = 0;
1816 adapter->link_duplex = 0;
1817
1818 if (!pci_channel_offline(adapter->pdev))
1819 igb_reset(adapter);
1820 igb_clean_all_tx_rings(adapter);
1821 igb_clean_all_rx_rings(adapter);
1822#ifdef CONFIG_IGB_DCA
1823
1824 /* since we reset the hardware DCA settings were cleared */
1825 igb_setup_dca(adapter);
1826#endif
1827}
1828
1829void igb_reinit_locked(struct igb_adapter *adapter)
1830{
1831 WARN_ON(in_interrupt());
1832 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1833 usleep_range(1000, 2000);
1834 igb_down(adapter);
1835 igb_up(adapter);
1836 clear_bit(__IGB_RESETTING, &adapter->state);
1837}
1838
1839/** igb_enable_mas - Media Autosense re-enable after swap
1840 *
1841 * @adapter: adapter struct
1842 **/
1843static void igb_enable_mas(struct igb_adapter *adapter)
1844{
1845 struct e1000_hw *hw = &adapter->hw;
1846 u32 connsw = rd32(E1000_CONNSW);
1847
1848 /* configure for SerDes media detect */
1849 if ((hw->phy.media_type == e1000_media_type_copper) &&
1850 (!(connsw & E1000_CONNSW_SERDESD))) {
1851 connsw |= E1000_CONNSW_ENRGSRC;
1852 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1853 wr32(E1000_CONNSW, connsw);
1854 wrfl();
1855 }
1856}
1857
1858void igb_reset(struct igb_adapter *adapter)
1859{
1860 struct pci_dev *pdev = adapter->pdev;
1861 struct e1000_hw *hw = &adapter->hw;
1862 struct e1000_mac_info *mac = &hw->mac;
1863 struct e1000_fc_info *fc = &hw->fc;
1864 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
1865
1866 /* Repartition Pba for greater than 9k mtu
1867 * To take effect CTRL.RST is required.
1868 */
1869 switch (mac->type) {
1870 case e1000_i350:
1871 case e1000_i354:
1872 case e1000_82580:
1873 pba = rd32(E1000_RXPBS);
1874 pba = igb_rxpbs_adjust_82580(pba);
1875 break;
1876 case e1000_82576:
1877 pba = rd32(E1000_RXPBS);
1878 pba &= E1000_RXPBS_SIZE_MASK_82576;
1879 break;
1880 case e1000_82575:
1881 case e1000_i210:
1882 case e1000_i211:
1883 default:
1884 pba = E1000_PBA_34K;
1885 break;
1886 }
1887
1888 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1889 (mac->type < e1000_82576)) {
1890 /* adjust PBA for jumbo frames */
1891 wr32(E1000_PBA, pba);
1892
1893 /* To maintain wire speed transmits, the Tx FIFO should be
1894 * large enough to accommodate two full transmit packets,
1895 * rounded up to the next 1KB and expressed in KB. Likewise,
1896 * the Rx FIFO should be large enough to accommodate at least
1897 * one full receive packet and is similarly rounded up and
1898 * expressed in KB.
1899 */
1900 pba = rd32(E1000_PBA);
1901 /* upper 16 bits has Tx packet buffer allocation size in KB */
1902 tx_space = pba >> 16;
1903 /* lower 16 bits has Rx packet buffer allocation size in KB */
1904 pba &= 0xffff;
1905 /* the Tx fifo also stores 16 bytes of information about the Tx
1906 * but don't include ethernet FCS because hardware appends it
1907 */
1908 min_tx_space = (adapter->max_frame_size +
1909 sizeof(union e1000_adv_tx_desc) -
1910 ETH_FCS_LEN) * 2;
1911 min_tx_space = ALIGN(min_tx_space, 1024);
1912 min_tx_space >>= 10;
1913 /* software strips receive CRC, so leave room for it */
1914 min_rx_space = adapter->max_frame_size;
1915 min_rx_space = ALIGN(min_rx_space, 1024);
1916 min_rx_space >>= 10;
1917
1918 /* If current Tx allocation is less than the min Tx FIFO size,
1919 * and the min Tx FIFO size is less than the current Rx FIFO
1920 * allocation, take space away from current Rx allocation
1921 */
1922 if (tx_space < min_tx_space &&
1923 ((min_tx_space - tx_space) < pba)) {
1924 pba = pba - (min_tx_space - tx_space);
1925
1926 /* if short on Rx space, Rx wins and must trump Tx
1927 * adjustment
1928 */
1929 if (pba < min_rx_space)
1930 pba = min_rx_space;
1931 }
1932 wr32(E1000_PBA, pba);
1933 }
1934
1935 /* flow control settings */
1936 /* The high water mark must be low enough to fit one full frame
1937 * (or the size used for early receive) above it in the Rx FIFO.
1938 * Set it to the lower of:
1939 * - 90% of the Rx FIFO size, or
1940 * - the full Rx FIFO size minus one full frame
1941 */
1942 hwm = min(((pba << 10) * 9 / 10),
1943 ((pba << 10) - 2 * adapter->max_frame_size));
1944
1945 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
1946 fc->low_water = fc->high_water - 16;
1947 fc->pause_time = 0xFFFF;
1948 fc->send_xon = 1;
1949 fc->current_mode = fc->requested_mode;
1950
1951 /* disable receive for all VFs and wait one second */
1952 if (adapter->vfs_allocated_count) {
1953 int i;
1954
1955 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1956 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1957
1958 /* ping all the active vfs to let them know we are going down */
1959 igb_ping_all_vfs(adapter);
1960
1961 /* disable transmits and receives */
1962 wr32(E1000_VFRE, 0);
1963 wr32(E1000_VFTE, 0);
1964 }
1965
1966 /* Allow time for pending master requests to run */
1967 hw->mac.ops.reset_hw(hw);
1968 wr32(E1000_WUC, 0);
1969
1970 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1971 /* need to resetup here after media swap */
1972 adapter->ei.get_invariants(hw);
1973 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1974 }
1975 if ((mac->type == e1000_82575) &&
1976 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
1977 igb_enable_mas(adapter);
1978 }
1979 if (hw->mac.ops.init_hw(hw))
1980 dev_err(&pdev->dev, "Hardware Error\n");
1981
1982 /* Flow control settings reset on hardware reset, so guarantee flow
1983 * control is off when forcing speed.
1984 */
1985 if (!hw->mac.autoneg)
1986 igb_force_mac_fc(hw);
1987
1988 igb_init_dmac(adapter, pba);
1989#ifdef CONFIG_IGB_HWMON
1990 /* Re-initialize the thermal sensor on i350 devices. */
1991 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1992 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1993 /* If present, re-initialize the external thermal sensor
1994 * interface.
1995 */
1996 if (adapter->ets)
1997 mac->ops.init_thermal_sensor_thresh(hw);
1998 }
1999 }
2000#endif
2001 /* Re-establish EEE setting */
2002 if (hw->phy.media_type == e1000_media_type_copper) {
2003 switch (mac->type) {
2004 case e1000_i350:
2005 case e1000_i210:
2006 case e1000_i211:
2007 igb_set_eee_i350(hw, true, true);
2008 break;
2009 case e1000_i354:
2010 igb_set_eee_i354(hw, true, true);
2011 break;
2012 default:
2013 break;
2014 }
2015 }
2016 if (!netif_running(adapter->netdev))
2017 igb_power_down_link(adapter);
2018
2019 igb_update_mng_vlan(adapter);
2020
2021 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2022 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2023
2024 /* Re-enable PTP, where applicable. */
2025 igb_ptp_reset(adapter);
2026
2027 igb_get_phy_info(hw);
2028}
2029
2030static netdev_features_t igb_fix_features(struct net_device *netdev,
2031 netdev_features_t features)
2032{
2033 /* Since there is no support for separate Rx/Tx vlan accel
2034 * enable/disable make sure Tx flag is always in same state as Rx.
2035 */
2036 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2037 features |= NETIF_F_HW_VLAN_CTAG_TX;
2038 else
2039 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2040
2041 return features;
2042}
2043
2044static int igb_set_features(struct net_device *netdev,
2045 netdev_features_t features)
2046{
2047 netdev_features_t changed = netdev->features ^ features;
2048 struct igb_adapter *adapter = netdev_priv(netdev);
2049
2050 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2051 igb_vlan_mode(netdev, features);
2052
2053 if (!(changed & NETIF_F_RXALL))
2054 return 0;
2055
2056 netdev->features = features;
2057
2058 if (netif_running(netdev))
2059 igb_reinit_locked(adapter);
2060 else
2061 igb_reset(adapter);
2062
2063 return 0;
2064}
2065
2066static const struct net_device_ops igb_netdev_ops = {
2067 .ndo_open = igb_open,
2068 .ndo_stop = igb_close,
2069 .ndo_start_xmit = igb_xmit_frame,
2070 .ndo_get_stats64 = igb_get_stats64,
2071 .ndo_set_rx_mode = igb_set_rx_mode,
2072 .ndo_set_mac_address = igb_set_mac,
2073 .ndo_change_mtu = igb_change_mtu,
2074 .ndo_do_ioctl = igb_ioctl,
2075 .ndo_tx_timeout = igb_tx_timeout,
2076 .ndo_validate_addr = eth_validate_addr,
2077 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2078 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
2079 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2080 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
2081 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
2082 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
2083 .ndo_get_vf_config = igb_ndo_get_vf_config,
2084#ifdef CONFIG_NET_POLL_CONTROLLER
2085 .ndo_poll_controller = igb_netpoll,
2086#endif
2087 .ndo_fix_features = igb_fix_features,
2088 .ndo_set_features = igb_set_features,
2089 .ndo_features_check = passthru_features_check,
2090};
2091
2092/**
2093 * igb_set_fw_version - Configure version string for ethtool
2094 * @adapter: adapter struct
2095 **/
2096void igb_set_fw_version(struct igb_adapter *adapter)
2097{
2098 struct e1000_hw *hw = &adapter->hw;
2099 struct e1000_fw_version fw;
2100
2101 igb_get_fw_version(hw, &fw);
2102
2103 switch (hw->mac.type) {
2104 case e1000_i210:
2105 case e1000_i211:
2106 if (!(igb_get_flash_presence_i210(hw))) {
2107 snprintf(adapter->fw_version,
2108 sizeof(adapter->fw_version),
2109 "%2d.%2d-%d",
2110 fw.invm_major, fw.invm_minor,
2111 fw.invm_img_type);
2112 break;
2113 }
2114 /* fall through */
2115 default:
2116 /* if option is rom valid, display its version too */
2117 if (fw.or_valid) {
2118 snprintf(adapter->fw_version,
2119 sizeof(adapter->fw_version),
2120 "%d.%d, 0x%08x, %d.%d.%d",
2121 fw.eep_major, fw.eep_minor, fw.etrack_id,
2122 fw.or_major, fw.or_build, fw.or_patch);
2123 /* no option rom */
2124 } else if (fw.etrack_id != 0X0000) {
2125 snprintf(adapter->fw_version,
2126 sizeof(adapter->fw_version),
2127 "%d.%d, 0x%08x",
2128 fw.eep_major, fw.eep_minor, fw.etrack_id);
2129 } else {
2130 snprintf(adapter->fw_version,
2131 sizeof(adapter->fw_version),
2132 "%d.%d.%d",
2133 fw.eep_major, fw.eep_minor, fw.eep_build);
2134 }
2135 break;
2136 }
2137}
2138
2139/**
2140 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2141 *
2142 * @adapter: adapter struct
2143 **/
2144static void igb_init_mas(struct igb_adapter *adapter)
2145{
2146 struct e1000_hw *hw = &adapter->hw;
2147 u16 eeprom_data;
2148
2149 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2150 switch (hw->bus.func) {
2151 case E1000_FUNC_0:
2152 if (eeprom_data & IGB_MAS_ENABLE_0) {
2153 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2154 netdev_info(adapter->netdev,
2155 "MAS: Enabling Media Autosense for port %d\n",
2156 hw->bus.func);
2157 }
2158 break;
2159 case E1000_FUNC_1:
2160 if (eeprom_data & IGB_MAS_ENABLE_1) {
2161 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2162 netdev_info(adapter->netdev,
2163 "MAS: Enabling Media Autosense for port %d\n",
2164 hw->bus.func);
2165 }
2166 break;
2167 case E1000_FUNC_2:
2168 if (eeprom_data & IGB_MAS_ENABLE_2) {
2169 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2170 netdev_info(adapter->netdev,
2171 "MAS: Enabling Media Autosense for port %d\n",
2172 hw->bus.func);
2173 }
2174 break;
2175 case E1000_FUNC_3:
2176 if (eeprom_data & IGB_MAS_ENABLE_3) {
2177 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2178 netdev_info(adapter->netdev,
2179 "MAS: Enabling Media Autosense for port %d\n",
2180 hw->bus.func);
2181 }
2182 break;
2183 default:
2184 /* Shouldn't get here */
2185 netdev_err(adapter->netdev,
2186 "MAS: Invalid port configuration, returning\n");
2187 break;
2188 }
2189}
2190
2191/**
2192 * igb_init_i2c - Init I2C interface
2193 * @adapter: pointer to adapter structure
2194 **/
2195static s32 igb_init_i2c(struct igb_adapter *adapter)
2196{
2197 s32 status = 0;
2198
2199 /* I2C interface supported on i350 devices */
2200 if (adapter->hw.mac.type != e1000_i350)
2201 return 0;
2202
2203 /* Initialize the i2c bus which is controlled by the registers.
2204 * This bus will use the i2c_algo_bit structue that implements
2205 * the protocol through toggling of the 4 bits in the register.
2206 */
2207 adapter->i2c_adap.owner = THIS_MODULE;
2208 adapter->i2c_algo = igb_i2c_algo;
2209 adapter->i2c_algo.data = adapter;
2210 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2211 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2212 strlcpy(adapter->i2c_adap.name, "igb BB",
2213 sizeof(adapter->i2c_adap.name));
2214 status = i2c_bit_add_bus(&adapter->i2c_adap);
2215 return status;
2216}
2217
2218/**
2219 * igb_probe - Device Initialization Routine
2220 * @pdev: PCI device information struct
2221 * @ent: entry in igb_pci_tbl
2222 *
2223 * Returns 0 on success, negative on failure
2224 *
2225 * igb_probe initializes an adapter identified by a pci_dev structure.
2226 * The OS initialization, configuring of the adapter private structure,
2227 * and a hardware reset occur.
2228 **/
2229static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2230{
2231 struct net_device *netdev;
2232 struct igb_adapter *adapter;
2233 struct e1000_hw *hw;
2234 u16 eeprom_data = 0;
2235 s32 ret_val;
2236 static int global_quad_port_a; /* global quad port a indication */
2237 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2238 int err, pci_using_dac;
2239 u8 part_str[E1000_PBANUM_LENGTH];
2240
2241 /* Catch broken hardware that put the wrong VF device ID in
2242 * the PCIe SR-IOV capability.
2243 */
2244 if (pdev->is_virtfn) {
2245 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
2246 pci_name(pdev), pdev->vendor, pdev->device);
2247 return -EINVAL;
2248 }
2249
2250 err = pci_enable_device_mem(pdev);
2251 if (err)
2252 return err;
2253
2254 pci_using_dac = 0;
2255 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2256 if (!err) {
2257 pci_using_dac = 1;
2258 } else {
2259 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2260 if (err) {
2261 dev_err(&pdev->dev,
2262 "No usable DMA configuration, aborting\n");
2263 goto err_dma;
2264 }
2265 }
2266
2267 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2268 IORESOURCE_MEM),
2269 igb_driver_name);
2270 if (err)
2271 goto err_pci_reg;
2272
2273 pci_enable_pcie_error_reporting(pdev);
2274
2275 pci_set_master(pdev);
2276 pci_save_state(pdev);
2277
2278 err = -ENOMEM;
2279 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2280 IGB_MAX_TX_QUEUES);
2281 if (!netdev)
2282 goto err_alloc_etherdev;
2283
2284 SET_NETDEV_DEV(netdev, &pdev->dev);
2285
2286 pci_set_drvdata(pdev, netdev);
2287 adapter = netdev_priv(netdev);
2288 adapter->netdev = netdev;
2289 adapter->pdev = pdev;
2290 hw = &adapter->hw;
2291 hw->back = adapter;
2292 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2293
2294 err = -EIO;
2295 hw->hw_addr = pci_iomap(pdev, 0, 0);
2296 if (!hw->hw_addr)
2297 goto err_ioremap;
2298
2299 netdev->netdev_ops = &igb_netdev_ops;
2300 igb_set_ethtool_ops(netdev);
2301 netdev->watchdog_timeo = 5 * HZ;
2302
2303 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2304
2305 netdev->mem_start = pci_resource_start(pdev, 0);
2306 netdev->mem_end = pci_resource_end(pdev, 0);
2307
2308 /* PCI config space info */
2309 hw->vendor_id = pdev->vendor;
2310 hw->device_id = pdev->device;
2311 hw->revision_id = pdev->revision;
2312 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2313 hw->subsystem_device_id = pdev->subsystem_device;
2314
2315 /* Copy the default MAC, PHY and NVM function pointers */
2316 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2317 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2318 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2319 /* Initialize skew-specific constants */
2320 err = ei->get_invariants(hw);
2321 if (err)
2322 goto err_sw_init;
2323
2324 /* setup the private structure */
2325 err = igb_sw_init(adapter);
2326 if (err)
2327 goto err_sw_init;
2328
2329 igb_get_bus_info_pcie(hw);
2330
2331 hw->phy.autoneg_wait_to_complete = false;
2332
2333 /* Copper options */
2334 if (hw->phy.media_type == e1000_media_type_copper) {
2335 hw->phy.mdix = AUTO_ALL_MODES;
2336 hw->phy.disable_polarity_correction = false;
2337 hw->phy.ms_type = e1000_ms_hw_default;
2338 }
2339
2340 if (igb_check_reset_block(hw))
2341 dev_info(&pdev->dev,
2342 "PHY reset is blocked due to SOL/IDER session.\n");
2343
2344 /* features is initialized to 0 in allocation, it might have bits
2345 * set by igb_sw_init so we should use an or instead of an
2346 * assignment.
2347 */
2348 netdev->features |= NETIF_F_SG |
2349 NETIF_F_IP_CSUM |
2350 NETIF_F_IPV6_CSUM |
2351 NETIF_F_TSO |
2352 NETIF_F_TSO6 |
2353 NETIF_F_RXHASH |
2354 NETIF_F_RXCSUM |
2355 NETIF_F_HW_VLAN_CTAG_RX |
2356 NETIF_F_HW_VLAN_CTAG_TX;
2357
2358 /* copy netdev features into list of user selectable features */
2359 netdev->hw_features |= netdev->features;
2360 netdev->hw_features |= NETIF_F_RXALL;
2361
2362 /* set this bit last since it cannot be part of hw_features */
2363 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2364
2365 netdev->vlan_features |= NETIF_F_TSO |
2366 NETIF_F_TSO6 |
2367 NETIF_F_IP_CSUM |
2368 NETIF_F_IPV6_CSUM |
2369 NETIF_F_SG;
2370
2371 netdev->priv_flags |= IFF_SUPP_NOFCS;
2372
2373 if (pci_using_dac) {
2374 netdev->features |= NETIF_F_HIGHDMA;
2375 netdev->vlan_features |= NETIF_F_HIGHDMA;
2376 }
2377
2378 if (hw->mac.type >= e1000_82576) {
2379 netdev->hw_features |= NETIF_F_SCTP_CSUM;
2380 netdev->features |= NETIF_F_SCTP_CSUM;
2381 }
2382
2383 netdev->priv_flags |= IFF_UNICAST_FLT;
2384
2385 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2386
2387 /* before reading the NVM, reset the controller to put the device in a
2388 * known good starting state
2389 */
2390 hw->mac.ops.reset_hw(hw);
2391
2392 /* make sure the NVM is good , i211/i210 parts can have special NVM
2393 * that doesn't contain a checksum
2394 */
2395 switch (hw->mac.type) {
2396 case e1000_i210:
2397 case e1000_i211:
2398 if (igb_get_flash_presence_i210(hw)) {
2399 if (hw->nvm.ops.validate(hw) < 0) {
2400 dev_err(&pdev->dev,
2401 "The NVM Checksum Is Not Valid\n");
2402 err = -EIO;
2403 goto err_eeprom;
2404 }
2405 }
2406 break;
2407 default:
2408 if (hw->nvm.ops.validate(hw) < 0) {
2409 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2410 err = -EIO;
2411 goto err_eeprom;
2412 }
2413 break;
2414 }
2415
2416 /* copy the MAC address out of the NVM */
2417 if (hw->mac.ops.read_mac_addr(hw))
2418 dev_err(&pdev->dev, "NVM Read Error\n");
2419
2420 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2421
2422 if (!is_valid_ether_addr(netdev->dev_addr)) {
2423 dev_err(&pdev->dev, "Invalid MAC Address\n");
2424 err = -EIO;
2425 goto err_eeprom;
2426 }
2427
2428 /* get firmware version for ethtool -i */
2429 igb_set_fw_version(adapter);
2430
2431 /* configure RXPBSIZE and TXPBSIZE */
2432 if (hw->mac.type == e1000_i210) {
2433 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2434 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2435 }
2436
2437 setup_timer(&adapter->watchdog_timer, igb_watchdog,
2438 (unsigned long) adapter);
2439 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2440 (unsigned long) adapter);
2441
2442 INIT_WORK(&adapter->reset_task, igb_reset_task);
2443 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2444
2445 /* Initialize link properties that are user-changeable */
2446 adapter->fc_autoneg = true;
2447 hw->mac.autoneg = true;
2448 hw->phy.autoneg_advertised = 0x2f;
2449
2450 hw->fc.requested_mode = e1000_fc_default;
2451 hw->fc.current_mode = e1000_fc_default;
2452
2453 igb_validate_mdi_setting(hw);
2454
2455 /* By default, support wake on port A */
2456 if (hw->bus.func == 0)
2457 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2458
2459 /* Check the NVM for wake support on non-port A ports */
2460 if (hw->mac.type >= e1000_82580)
2461 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2462 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2463 &eeprom_data);
2464 else if (hw->bus.func == 1)
2465 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2466
2467 if (eeprom_data & IGB_EEPROM_APME)
2468 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2469
2470 /* now that we have the eeprom settings, apply the special cases where
2471 * the eeprom may be wrong or the board simply won't support wake on
2472 * lan on a particular port
2473 */
2474 switch (pdev->device) {
2475 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2476 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2477 break;
2478 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2479 case E1000_DEV_ID_82576_FIBER:
2480 case E1000_DEV_ID_82576_SERDES:
2481 /* Wake events only supported on port A for dual fiber
2482 * regardless of eeprom setting
2483 */
2484 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2485 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2486 break;
2487 case E1000_DEV_ID_82576_QUAD_COPPER:
2488 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2489 /* if quad port adapter, disable WoL on all but port A */
2490 if (global_quad_port_a != 0)
2491 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2492 else
2493 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2494 /* Reset for multiple quad port adapters */
2495 if (++global_quad_port_a == 4)
2496 global_quad_port_a = 0;
2497 break;
2498 default:
2499 /* If the device can't wake, don't set software support */
2500 if (!device_can_wakeup(&adapter->pdev->dev))
2501 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2502 }
2503
2504 /* initialize the wol settings based on the eeprom settings */
2505 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2506 adapter->wol |= E1000_WUFC_MAG;
2507
2508 /* Some vendors want WoL disabled by default, but still supported */
2509 if ((hw->mac.type == e1000_i350) &&
2510 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2511 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2512 adapter->wol = 0;
2513 }
2514
2515 device_set_wakeup_enable(&adapter->pdev->dev,
2516 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2517
2518 /* reset the hardware with the new settings */
2519 igb_reset(adapter);
2520
2521 /* Init the I2C interface */
2522 err = igb_init_i2c(adapter);
2523 if (err) {
2524 dev_err(&pdev->dev, "failed to init i2c interface\n");
2525 goto err_eeprom;
2526 }
2527
2528 /* let the f/w know that the h/w is now under the control of the
2529 * driver.
2530 */
2531 igb_get_hw_control(adapter);
2532
2533 strcpy(netdev->name, "eth%d");
2534 err = register_netdev(netdev);
2535 if (err)
2536 goto err_register;
2537
2538 /* carrier off reporting is important to ethtool even BEFORE open */
2539 netif_carrier_off(netdev);
2540
2541#ifdef CONFIG_IGB_DCA
2542 if (dca_add_requester(&pdev->dev) == 0) {
2543 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2544 dev_info(&pdev->dev, "DCA enabled\n");
2545 igb_setup_dca(adapter);
2546 }
2547
2548#endif
2549#ifdef CONFIG_IGB_HWMON
2550 /* Initialize the thermal sensor on i350 devices. */
2551 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2552 u16 ets_word;
2553
2554 /* Read the NVM to determine if this i350 device supports an
2555 * external thermal sensor.
2556 */
2557 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2558 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2559 adapter->ets = true;
2560 else
2561 adapter->ets = false;
2562 if (igb_sysfs_init(adapter))
2563 dev_err(&pdev->dev,
2564 "failed to allocate sysfs resources\n");
2565 } else {
2566 adapter->ets = false;
2567 }
2568#endif
2569 /* Check if Media Autosense is enabled */
2570 adapter->ei = *ei;
2571 if (hw->dev_spec._82575.mas_capable)
2572 igb_init_mas(adapter);
2573
2574 /* do hw tstamp init after resetting */
2575 igb_ptp_init(adapter);
2576
2577 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2578 /* print bus type/speed/width info, not applicable to i354 */
2579 if (hw->mac.type != e1000_i354) {
2580 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2581 netdev->name,
2582 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2583 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2584 "unknown"),
2585 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2586 "Width x4" :
2587 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2588 "Width x2" :
2589 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2590 "Width x1" : "unknown"), netdev->dev_addr);
2591 }
2592
2593 if ((hw->mac.type >= e1000_i210 ||
2594 igb_get_flash_presence_i210(hw))) {
2595 ret_val = igb_read_part_string(hw, part_str,
2596 E1000_PBANUM_LENGTH);
2597 } else {
2598 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2599 }
2600
2601 if (ret_val)
2602 strcpy(part_str, "Unknown");
2603 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2604 dev_info(&pdev->dev,
2605 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2606 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
2607 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2608 adapter->num_rx_queues, adapter->num_tx_queues);
2609 if (hw->phy.media_type == e1000_media_type_copper) {
2610 switch (hw->mac.type) {
2611 case e1000_i350:
2612 case e1000_i210:
2613 case e1000_i211:
2614 /* Enable EEE for internal copper PHY devices */
2615 err = igb_set_eee_i350(hw, true, true);
2616 if ((!err) &&
2617 (!hw->dev_spec._82575.eee_disable)) {
2618 adapter->eee_advert =
2619 MDIO_EEE_100TX | MDIO_EEE_1000T;
2620 adapter->flags |= IGB_FLAG_EEE;
2621 }
2622 break;
2623 case e1000_i354:
2624 if ((rd32(E1000_CTRL_EXT) &
2625 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2626 err = igb_set_eee_i354(hw, true, true);
2627 if ((!err) &&
2628 (!hw->dev_spec._82575.eee_disable)) {
2629 adapter->eee_advert =
2630 MDIO_EEE_100TX | MDIO_EEE_1000T;
2631 adapter->flags |= IGB_FLAG_EEE;
2632 }
2633 }
2634 break;
2635 default:
2636 break;
2637 }
2638 }
2639 pm_runtime_put_noidle(&pdev->dev);
2640 return 0;
2641
2642err_register:
2643 igb_release_hw_control(adapter);
2644 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
2645err_eeprom:
2646 if (!igb_check_reset_block(hw))
2647 igb_reset_phy(hw);
2648
2649 if (hw->flash_address)
2650 iounmap(hw->flash_address);
2651err_sw_init:
2652 igb_clear_interrupt_scheme(adapter);
2653 pci_iounmap(pdev, hw->hw_addr);
2654err_ioremap:
2655 free_netdev(netdev);
2656err_alloc_etherdev:
2657 pci_release_selected_regions(pdev,
2658 pci_select_bars(pdev, IORESOURCE_MEM));
2659err_pci_reg:
2660err_dma:
2661 pci_disable_device(pdev);
2662 return err;
2663}
2664
2665#ifdef CONFIG_PCI_IOV
2666static int igb_disable_sriov(struct pci_dev *pdev)
2667{
2668 struct net_device *netdev = pci_get_drvdata(pdev);
2669 struct igb_adapter *adapter = netdev_priv(netdev);
2670 struct e1000_hw *hw = &adapter->hw;
2671
2672 /* reclaim resources allocated to VFs */
2673 if (adapter->vf_data) {
2674 /* disable iov and allow time for transactions to clear */
2675 if (pci_vfs_assigned(pdev)) {
2676 dev_warn(&pdev->dev,
2677 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2678 return -EPERM;
2679 } else {
2680 pci_disable_sriov(pdev);
2681 msleep(500);
2682 }
2683
2684 kfree(adapter->vf_data);
2685 adapter->vf_data = NULL;
2686 adapter->vfs_allocated_count = 0;
2687 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2688 wrfl();
2689 msleep(100);
2690 dev_info(&pdev->dev, "IOV Disabled\n");
2691
2692 /* Re-enable DMA Coalescing flag since IOV is turned off */
2693 adapter->flags |= IGB_FLAG_DMAC;
2694 }
2695
2696 return 0;
2697}
2698
2699static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2700{
2701 struct net_device *netdev = pci_get_drvdata(pdev);
2702 struct igb_adapter *adapter = netdev_priv(netdev);
2703 int old_vfs = pci_num_vf(pdev);
2704 int err = 0;
2705 int i;
2706
2707 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
2708 err = -EPERM;
2709 goto out;
2710 }
2711 if (!num_vfs)
2712 goto out;
2713
2714 if (old_vfs) {
2715 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2716 old_vfs, max_vfs);
2717 adapter->vfs_allocated_count = old_vfs;
2718 } else
2719 adapter->vfs_allocated_count = num_vfs;
2720
2721 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2722 sizeof(struct vf_data_storage), GFP_KERNEL);
2723
2724 /* if allocation failed then we do not support SR-IOV */
2725 if (!adapter->vf_data) {
2726 adapter->vfs_allocated_count = 0;
2727 dev_err(&pdev->dev,
2728 "Unable to allocate memory for VF Data Storage\n");
2729 err = -ENOMEM;
2730 goto out;
2731 }
2732
2733 /* only call pci_enable_sriov() if no VFs are allocated already */
2734 if (!old_vfs) {
2735 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2736 if (err)
2737 goto err_out;
2738 }
2739 dev_info(&pdev->dev, "%d VFs allocated\n",
2740 adapter->vfs_allocated_count);
2741 for (i = 0; i < adapter->vfs_allocated_count; i++)
2742 igb_vf_configure(adapter, i);
2743
2744 /* DMA Coalescing is not supported in IOV mode. */
2745 adapter->flags &= ~IGB_FLAG_DMAC;
2746 goto out;
2747
2748err_out:
2749 kfree(adapter->vf_data);
2750 adapter->vf_data = NULL;
2751 adapter->vfs_allocated_count = 0;
2752out:
2753 return err;
2754}
2755
2756#endif
2757/**
2758 * igb_remove_i2c - Cleanup I2C interface
2759 * @adapter: pointer to adapter structure
2760 **/
2761static void igb_remove_i2c(struct igb_adapter *adapter)
2762{
2763 /* free the adapter bus structure */
2764 i2c_del_adapter(&adapter->i2c_adap);
2765}
2766
2767/**
2768 * igb_remove - Device Removal Routine
2769 * @pdev: PCI device information struct
2770 *
2771 * igb_remove is called by the PCI subsystem to alert the driver
2772 * that it should release a PCI device. The could be caused by a
2773 * Hot-Plug event, or because the driver is going to be removed from
2774 * memory.
2775 **/
2776static void igb_remove(struct pci_dev *pdev)
2777{
2778 struct net_device *netdev = pci_get_drvdata(pdev);
2779 struct igb_adapter *adapter = netdev_priv(netdev);
2780 struct e1000_hw *hw = &adapter->hw;
2781
2782 pm_runtime_get_noresume(&pdev->dev);
2783#ifdef CONFIG_IGB_HWMON
2784 igb_sysfs_exit(adapter);
2785#endif
2786 igb_remove_i2c(adapter);
2787 igb_ptp_stop(adapter);
2788 /* The watchdog timer may be rescheduled, so explicitly
2789 * disable watchdog from being rescheduled.
2790 */
2791 set_bit(__IGB_DOWN, &adapter->state);
2792 del_timer_sync(&adapter->watchdog_timer);
2793 del_timer_sync(&adapter->phy_info_timer);
2794
2795 cancel_work_sync(&adapter->reset_task);
2796 cancel_work_sync(&adapter->watchdog_task);
2797
2798#ifdef CONFIG_IGB_DCA
2799 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2800 dev_info(&pdev->dev, "DCA disabled\n");
2801 dca_remove_requester(&pdev->dev);
2802 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2803 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2804 }
2805#endif
2806
2807 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2808 * would have already happened in close and is redundant.
2809 */
2810 igb_release_hw_control(adapter);
2811
2812 unregister_netdev(netdev);
2813
2814 igb_clear_interrupt_scheme(adapter);
2815
2816#ifdef CONFIG_PCI_IOV
2817 igb_disable_sriov(pdev);
2818#endif
2819
2820 pci_iounmap(pdev, hw->hw_addr);
2821 if (hw->flash_address)
2822 iounmap(hw->flash_address);
2823 pci_release_selected_regions(pdev,
2824 pci_select_bars(pdev, IORESOURCE_MEM));
2825
2826 kfree(adapter->shadow_vfta);
2827 free_netdev(netdev);
2828
2829 pci_disable_pcie_error_reporting(pdev);
2830
2831 pci_disable_device(pdev);
2832}
2833
2834/**
2835 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2836 * @adapter: board private structure to initialize
2837 *
2838 * This function initializes the vf specific data storage and then attempts to
2839 * allocate the VFs. The reason for ordering it this way is because it is much
2840 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2841 * the memory for the VFs.
2842 **/
2843static void igb_probe_vfs(struct igb_adapter *adapter)
2844{
2845#ifdef CONFIG_PCI_IOV
2846 struct pci_dev *pdev = adapter->pdev;
2847 struct e1000_hw *hw = &adapter->hw;
2848
2849 /* Virtualization features not supported on i210 family. */
2850 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2851 return;
2852
2853 pci_sriov_set_totalvfs(pdev, 7);
2854 igb_enable_sriov(pdev, max_vfs);
2855
2856#endif /* CONFIG_PCI_IOV */
2857}
2858
2859static void igb_init_queue_configuration(struct igb_adapter *adapter)
2860{
2861 struct e1000_hw *hw = &adapter->hw;
2862 u32 max_rss_queues;
2863
2864 /* Determine the maximum number of RSS queues supported. */
2865 switch (hw->mac.type) {
2866 case e1000_i211:
2867 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2868 break;
2869 case e1000_82575:
2870 case e1000_i210:
2871 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2872 break;
2873 case e1000_i350:
2874 /* I350 cannot do RSS and SR-IOV at the same time */
2875 if (!!adapter->vfs_allocated_count) {
2876 max_rss_queues = 1;
2877 break;
2878 }
2879 /* fall through */
2880 case e1000_82576:
2881 if (!!adapter->vfs_allocated_count) {
2882 max_rss_queues = 2;
2883 break;
2884 }
2885 /* fall through */
2886 case e1000_82580:
2887 case e1000_i354:
2888 default:
2889 max_rss_queues = IGB_MAX_RX_QUEUES;
2890 break;
2891 }
2892
2893 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2894
2895 igb_set_flag_queue_pairs(adapter, max_rss_queues);
2896}
2897
2898void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
2899 const u32 max_rss_queues)
2900{
2901 struct e1000_hw *hw = &adapter->hw;
2902
2903 /* Determine if we need to pair queues. */
2904 switch (hw->mac.type) {
2905 case e1000_82575:
2906 case e1000_i211:
2907 /* Device supports enough interrupts without queue pairing. */
2908 break;
2909 case e1000_82576:
2910 /* If VFs are going to be allocated with RSS queues then we
2911 * should pair the queues in order to conserve interrupts due
2912 * to limited supply.
2913 */
2914 if ((adapter->rss_queues > 1) &&
2915 (adapter->vfs_allocated_count > 6))
2916 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2917 /* fall through */
2918 case e1000_82580:
2919 case e1000_i350:
2920 case e1000_i354:
2921 case e1000_i210:
2922 default:
2923 /* If rss_queues > half of max_rss_queues, pair the queues in
2924 * order to conserve interrupts due to limited supply.
2925 */
2926 if (adapter->rss_queues > (max_rss_queues / 2))
2927 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2928 break;
2929 }
2930}
2931
2932/**
2933 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2934 * @adapter: board private structure to initialize
2935 *
2936 * igb_sw_init initializes the Adapter private data structure.
2937 * Fields are initialized based on PCI device information and
2938 * OS network device settings (MTU size).
2939 **/
2940static int igb_sw_init(struct igb_adapter *adapter)
2941{
2942 struct e1000_hw *hw = &adapter->hw;
2943 struct net_device *netdev = adapter->netdev;
2944 struct pci_dev *pdev = adapter->pdev;
2945
2946 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2947
2948 /* set default ring sizes */
2949 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2950 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2951
2952 /* set default ITR values */
2953 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2954 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2955
2956 /* set default work limits */
2957 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2958
2959 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2960 VLAN_HLEN;
2961 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2962
2963 spin_lock_init(&adapter->stats64_lock);
2964#ifdef CONFIG_PCI_IOV
2965 switch (hw->mac.type) {
2966 case e1000_82576:
2967 case e1000_i350:
2968 if (max_vfs > 7) {
2969 dev_warn(&pdev->dev,
2970 "Maximum of 7 VFs per PF, using max\n");
2971 max_vfs = adapter->vfs_allocated_count = 7;
2972 } else
2973 adapter->vfs_allocated_count = max_vfs;
2974 if (adapter->vfs_allocated_count)
2975 dev_warn(&pdev->dev,
2976 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2977 break;
2978 default:
2979 break;
2980 }
2981#endif /* CONFIG_PCI_IOV */
2982
2983 igb_init_queue_configuration(adapter);
2984
2985 /* Setup and initialize a copy of the hw vlan table array */
2986 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2987 GFP_ATOMIC);
2988
2989 /* This call may decrease the number of queues */
2990 if (igb_init_interrupt_scheme(adapter, true)) {
2991 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2992 return -ENOMEM;
2993 }
2994
2995 igb_probe_vfs(adapter);
2996
2997 /* Explicitly disable IRQ since the NIC can be in any state. */
2998 igb_irq_disable(adapter);
2999
3000 if (hw->mac.type >= e1000_i350)
3001 adapter->flags &= ~IGB_FLAG_DMAC;
3002
3003 set_bit(__IGB_DOWN, &adapter->state);
3004 return 0;
3005}
3006
3007/**
3008 * igb_open - Called when a network interface is made active
3009 * @netdev: network interface device structure
3010 *
3011 * Returns 0 on success, negative value on failure
3012 *
3013 * The open entry point is called when a network interface is made
3014 * active by the system (IFF_UP). At this point all resources needed
3015 * for transmit and receive operations are allocated, the interrupt
3016 * handler is registered with the OS, the watchdog timer is started,
3017 * and the stack is notified that the interface is ready.
3018 **/
3019static int __igb_open(struct net_device *netdev, bool resuming)
3020{
3021 struct igb_adapter *adapter = netdev_priv(netdev);
3022 struct e1000_hw *hw = &adapter->hw;
3023 struct pci_dev *pdev = adapter->pdev;
3024 int err;
3025 int i;
3026
3027 /* disallow open during test */
3028 if (test_bit(__IGB_TESTING, &adapter->state)) {
3029 WARN_ON(resuming);
3030 return -EBUSY;
3031 }
3032
3033 if (!resuming)
3034 pm_runtime_get_sync(&pdev->dev);
3035
3036 netif_carrier_off(netdev);
3037
3038 /* allocate transmit descriptors */
3039 err = igb_setup_all_tx_resources(adapter);
3040 if (err)
3041 goto err_setup_tx;
3042
3043 /* allocate receive descriptors */
3044 err = igb_setup_all_rx_resources(adapter);
3045 if (err)
3046 goto err_setup_rx;
3047
3048 igb_power_up_link(adapter);
3049
3050 /* before we allocate an interrupt, we must be ready to handle it.
3051 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3052 * as soon as we call pci_request_irq, so we have to setup our
3053 * clean_rx handler before we do so.
3054 */
3055 igb_configure(adapter);
3056
3057 err = igb_request_irq(adapter);
3058 if (err)
3059 goto err_req_irq;
3060
3061 /* Notify the stack of the actual queue counts. */
3062 err = netif_set_real_num_tx_queues(adapter->netdev,
3063 adapter->num_tx_queues);
3064 if (err)
3065 goto err_set_queues;
3066
3067 err = netif_set_real_num_rx_queues(adapter->netdev,
3068 adapter->num_rx_queues);
3069 if (err)
3070 goto err_set_queues;
3071
3072 /* From here on the code is the same as igb_up() */
3073 clear_bit(__IGB_DOWN, &adapter->state);
3074
3075 for (i = 0; i < adapter->num_q_vectors; i++)
3076 napi_enable(&(adapter->q_vector[i]->napi));
3077
3078 /* Clear any pending interrupts. */
3079 rd32(E1000_ICR);
3080
3081 igb_irq_enable(adapter);
3082
3083 /* notify VFs that reset has been completed */
3084 if (adapter->vfs_allocated_count) {
3085 u32 reg_data = rd32(E1000_CTRL_EXT);
3086
3087 reg_data |= E1000_CTRL_EXT_PFRSTD;
3088 wr32(E1000_CTRL_EXT, reg_data);
3089 }
3090
3091 netif_tx_start_all_queues(netdev);
3092
3093 if (!resuming)
3094 pm_runtime_put(&pdev->dev);
3095
3096 /* start the watchdog. */
3097 hw->mac.get_link_status = 1;
3098 schedule_work(&adapter->watchdog_task);
3099
3100 return 0;
3101
3102err_set_queues:
3103 igb_free_irq(adapter);
3104err_req_irq:
3105 igb_release_hw_control(adapter);
3106 igb_power_down_link(adapter);
3107 igb_free_all_rx_resources(adapter);
3108err_setup_rx:
3109 igb_free_all_tx_resources(adapter);
3110err_setup_tx:
3111 igb_reset(adapter);
3112 if (!resuming)
3113 pm_runtime_put(&pdev->dev);
3114
3115 return err;
3116}
3117
3118static int igb_open(struct net_device *netdev)
3119{
3120 return __igb_open(netdev, false);
3121}
3122
3123/**
3124 * igb_close - Disables a network interface
3125 * @netdev: network interface device structure
3126 *
3127 * Returns 0, this is not allowed to fail
3128 *
3129 * The close entry point is called when an interface is de-activated
3130 * by the OS. The hardware is still under the driver's control, but
3131 * needs to be disabled. A global MAC reset is issued to stop the
3132 * hardware, and all transmit and receive resources are freed.
3133 **/
3134static int __igb_close(struct net_device *netdev, bool suspending)
3135{
3136 struct igb_adapter *adapter = netdev_priv(netdev);
3137 struct pci_dev *pdev = adapter->pdev;
3138
3139 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3140
3141 if (!suspending)
3142 pm_runtime_get_sync(&pdev->dev);
3143
3144 igb_down(adapter);
3145 igb_free_irq(adapter);
3146
3147 igb_free_all_tx_resources(adapter);
3148 igb_free_all_rx_resources(adapter);
3149
3150 if (!suspending)
3151 pm_runtime_put_sync(&pdev->dev);
3152 return 0;
3153}
3154
3155static int igb_close(struct net_device *netdev)
3156{
3157 return __igb_close(netdev, false);
3158}
3159
3160/**
3161 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3162 * @tx_ring: tx descriptor ring (for a specific queue) to setup
3163 *
3164 * Return 0 on success, negative on failure
3165 **/
3166int igb_setup_tx_resources(struct igb_ring *tx_ring)
3167{
3168 struct device *dev = tx_ring->dev;
3169 int size;
3170
3171 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3172
3173 tx_ring->tx_buffer_info = vzalloc(size);
3174 if (!tx_ring->tx_buffer_info)
3175 goto err;
3176
3177 /* round up to nearest 4K */
3178 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
3179 tx_ring->size = ALIGN(tx_ring->size, 4096);
3180
3181 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3182 &tx_ring->dma, GFP_KERNEL);
3183 if (!tx_ring->desc)
3184 goto err;
3185
3186 tx_ring->next_to_use = 0;
3187 tx_ring->next_to_clean = 0;
3188
3189 return 0;
3190
3191err:
3192 vfree(tx_ring->tx_buffer_info);
3193 tx_ring->tx_buffer_info = NULL;
3194 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
3195 return -ENOMEM;
3196}
3197
3198/**
3199 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3200 * (Descriptors) for all queues
3201 * @adapter: board private structure
3202 *
3203 * Return 0 on success, negative on failure
3204 **/
3205static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3206{
3207 struct pci_dev *pdev = adapter->pdev;
3208 int i, err = 0;
3209
3210 for (i = 0; i < adapter->num_tx_queues; i++) {
3211 err = igb_setup_tx_resources(adapter->tx_ring[i]);
3212 if (err) {
3213 dev_err(&pdev->dev,
3214 "Allocation for Tx Queue %u failed\n", i);
3215 for (i--; i >= 0; i--)
3216 igb_free_tx_resources(adapter->tx_ring[i]);
3217 break;
3218 }
3219 }
3220
3221 return err;
3222}
3223
3224/**
3225 * igb_setup_tctl - configure the transmit control registers
3226 * @adapter: Board private structure
3227 **/
3228void igb_setup_tctl(struct igb_adapter *adapter)
3229{
3230 struct e1000_hw *hw = &adapter->hw;
3231 u32 tctl;
3232
3233 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3234 wr32(E1000_TXDCTL(0), 0);
3235
3236 /* Program the Transmit Control Register */
3237 tctl = rd32(E1000_TCTL);
3238 tctl &= ~E1000_TCTL_CT;
3239 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3240 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3241
3242 igb_config_collision_dist(hw);
3243
3244 /* Enable transmits */
3245 tctl |= E1000_TCTL_EN;
3246
3247 wr32(E1000_TCTL, tctl);
3248}
3249
3250/**
3251 * igb_configure_tx_ring - Configure transmit ring after Reset
3252 * @adapter: board private structure
3253 * @ring: tx ring to configure
3254 *
3255 * Configure a transmit ring after a reset.
3256 **/
3257void igb_configure_tx_ring(struct igb_adapter *adapter,
3258 struct igb_ring *ring)
3259{
3260 struct e1000_hw *hw = &adapter->hw;
3261 u32 txdctl = 0;
3262 u64 tdba = ring->dma;
3263 int reg_idx = ring->reg_idx;
3264
3265 /* disable the queue */
3266 wr32(E1000_TXDCTL(reg_idx), 0);
3267 wrfl();
3268 mdelay(10);
3269
3270 wr32(E1000_TDLEN(reg_idx),
3271 ring->count * sizeof(union e1000_adv_tx_desc));
3272 wr32(E1000_TDBAL(reg_idx),
3273 tdba & 0x00000000ffffffffULL);
3274 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3275
3276 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
3277 wr32(E1000_TDH(reg_idx), 0);
3278 writel(0, ring->tail);
3279
3280 txdctl |= IGB_TX_PTHRESH;
3281 txdctl |= IGB_TX_HTHRESH << 8;
3282 txdctl |= IGB_TX_WTHRESH << 16;
3283
3284 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3285 wr32(E1000_TXDCTL(reg_idx), txdctl);
3286}
3287
3288/**
3289 * igb_configure_tx - Configure transmit Unit after Reset
3290 * @adapter: board private structure
3291 *
3292 * Configure the Tx unit of the MAC after a reset.
3293 **/
3294static void igb_configure_tx(struct igb_adapter *adapter)
3295{
3296 int i;
3297
3298 for (i = 0; i < adapter->num_tx_queues; i++)
3299 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
3300}
3301
3302/**
3303 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3304 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
3305 *
3306 * Returns 0 on success, negative on failure
3307 **/
3308int igb_setup_rx_resources(struct igb_ring *rx_ring)
3309{
3310 struct device *dev = rx_ring->dev;
3311 int size;
3312
3313 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3314
3315 rx_ring->rx_buffer_info = vzalloc(size);
3316 if (!rx_ring->rx_buffer_info)
3317 goto err;
3318
3319 /* Round up to nearest 4K */
3320 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3321 rx_ring->size = ALIGN(rx_ring->size, 4096);
3322
3323 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3324 &rx_ring->dma, GFP_KERNEL);
3325 if (!rx_ring->desc)
3326 goto err;
3327
3328 rx_ring->next_to_alloc = 0;
3329 rx_ring->next_to_clean = 0;
3330 rx_ring->next_to_use = 0;
3331
3332 return 0;
3333
3334err:
3335 vfree(rx_ring->rx_buffer_info);
3336 rx_ring->rx_buffer_info = NULL;
3337 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3338 return -ENOMEM;
3339}
3340
3341/**
3342 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3343 * (Descriptors) for all queues
3344 * @adapter: board private structure
3345 *
3346 * Return 0 on success, negative on failure
3347 **/
3348static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3349{
3350 struct pci_dev *pdev = adapter->pdev;
3351 int i, err = 0;
3352
3353 for (i = 0; i < adapter->num_rx_queues; i++) {
3354 err = igb_setup_rx_resources(adapter->rx_ring[i]);
3355 if (err) {
3356 dev_err(&pdev->dev,
3357 "Allocation for Rx Queue %u failed\n", i);
3358 for (i--; i >= 0; i--)
3359 igb_free_rx_resources(adapter->rx_ring[i]);
3360 break;
3361 }
3362 }
3363
3364 return err;
3365}
3366
3367/**
3368 * igb_setup_mrqc - configure the multiple receive queue control registers
3369 * @adapter: Board private structure
3370 **/
3371static void igb_setup_mrqc(struct igb_adapter *adapter)
3372{
3373 struct e1000_hw *hw = &adapter->hw;
3374 u32 mrqc, rxcsum;
3375 u32 j, num_rx_queues;
3376 u32 rss_key[10];
3377
3378 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3379 for (j = 0; j < 10; j++)
3380 wr32(E1000_RSSRK(j), rss_key[j]);
3381
3382 num_rx_queues = adapter->rss_queues;
3383
3384 switch (hw->mac.type) {
3385 case e1000_82576:
3386 /* 82576 supports 2 RSS queues for SR-IOV */
3387 if (adapter->vfs_allocated_count)
3388 num_rx_queues = 2;
3389 break;
3390 default:
3391 break;
3392 }
3393
3394 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3395 for (j = 0; j < IGB_RETA_SIZE; j++)
3396 adapter->rss_indir_tbl[j] =
3397 (j * num_rx_queues) / IGB_RETA_SIZE;
3398 adapter->rss_indir_tbl_init = num_rx_queues;
3399 }
3400 igb_write_rss_indir_tbl(adapter);
3401
3402 /* Disable raw packet checksumming so that RSS hash is placed in
3403 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3404 * offloads as they are enabled by default
3405 */
3406 rxcsum = rd32(E1000_RXCSUM);
3407 rxcsum |= E1000_RXCSUM_PCSD;
3408
3409 if (adapter->hw.mac.type >= e1000_82576)
3410 /* Enable Receive Checksum Offload for SCTP */
3411 rxcsum |= E1000_RXCSUM_CRCOFL;
3412
3413 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3414 wr32(E1000_RXCSUM, rxcsum);
3415
3416 /* Generate RSS hash based on packet types, TCP/UDP
3417 * port numbers and/or IPv4/v6 src and dst addresses
3418 */
3419 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3420 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3421 E1000_MRQC_RSS_FIELD_IPV6 |
3422 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3423 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3424
3425 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3426 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3427 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3428 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3429
3430 /* If VMDq is enabled then we set the appropriate mode for that, else
3431 * we default to RSS so that an RSS hash is calculated per packet even
3432 * if we are only using one queue
3433 */
3434 if (adapter->vfs_allocated_count) {
3435 if (hw->mac.type > e1000_82575) {
3436 /* Set the default pool for the PF's first queue */
3437 u32 vtctl = rd32(E1000_VT_CTL);
3438
3439 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3440 E1000_VT_CTL_DISABLE_DEF_POOL);
3441 vtctl |= adapter->vfs_allocated_count <<
3442 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3443 wr32(E1000_VT_CTL, vtctl);
3444 }
3445 if (adapter->rss_queues > 1)
3446 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
3447 else
3448 mrqc |= E1000_MRQC_ENABLE_VMDQ;
3449 } else {
3450 if (hw->mac.type != e1000_i211)
3451 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
3452 }
3453 igb_vmm_control(adapter);
3454
3455 wr32(E1000_MRQC, mrqc);
3456}
3457
3458/**
3459 * igb_setup_rctl - configure the receive control registers
3460 * @adapter: Board private structure
3461 **/
3462void igb_setup_rctl(struct igb_adapter *adapter)
3463{
3464 struct e1000_hw *hw = &adapter->hw;
3465 u32 rctl;
3466
3467 rctl = rd32(E1000_RCTL);
3468
3469 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3470 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
3471
3472 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
3473 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3474
3475 /* enable stripping of CRC. It's unlikely this will break BMC
3476 * redirection as it did with e1000. Newer features require
3477 * that the HW strips the CRC.
3478 */
3479 rctl |= E1000_RCTL_SECRC;
3480
3481 /* disable store bad packets and clear size bits. */
3482 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
3483
3484 /* enable LPE to prevent packets larger than max_frame_size */
3485 rctl |= E1000_RCTL_LPE;
3486
3487 /* disable queue 0 to prevent tail write w/o re-config */
3488 wr32(E1000_RXDCTL(0), 0);
3489
3490 /* Attention!!! For SR-IOV PF driver operations you must enable
3491 * queue drop for all VF and PF queues to prevent head of line blocking
3492 * if an un-trusted VF does not provide descriptors to hardware.
3493 */
3494 if (adapter->vfs_allocated_count) {
3495 /* set all queue drop enable bits */
3496 wr32(E1000_QDE, ALL_QUEUES);
3497 }
3498
3499 /* This is useful for sniffing bad packets. */
3500 if (adapter->netdev->features & NETIF_F_RXALL) {
3501 /* UPE and MPE will be handled by normal PROMISC logic
3502 * in e1000e_set_rx_mode
3503 */
3504 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3505 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3506 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3507
3508 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3509 E1000_RCTL_DPF | /* Allow filtered pause */
3510 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3511 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3512 * and that breaks VLANs.
3513 */
3514 }
3515
3516 wr32(E1000_RCTL, rctl);
3517}
3518
3519static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3520 int vfn)
3521{
3522 struct e1000_hw *hw = &adapter->hw;
3523 u32 vmolr;
3524
3525 /* if it isn't the PF check to see if VFs are enabled and
3526 * increase the size to support vlan tags
3527 */
3528 if (vfn < adapter->vfs_allocated_count &&
3529 adapter->vf_data[vfn].vlans_enabled)
3530 size += VLAN_TAG_SIZE;
3531
3532 vmolr = rd32(E1000_VMOLR(vfn));
3533 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3534 vmolr |= size | E1000_VMOLR_LPE;
3535 wr32(E1000_VMOLR(vfn), vmolr);
3536
3537 return 0;
3538}
3539
3540/**
3541 * igb_rlpml_set - set maximum receive packet size
3542 * @adapter: board private structure
3543 *
3544 * Configure maximum receivable packet size.
3545 **/
3546static void igb_rlpml_set(struct igb_adapter *adapter)
3547{
3548 u32 max_frame_size = adapter->max_frame_size;
3549 struct e1000_hw *hw = &adapter->hw;
3550 u16 pf_id = adapter->vfs_allocated_count;
3551
3552 if (pf_id) {
3553 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3554 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
3555 * to our max jumbo frame size, in case we need to enable
3556 * jumbo frames on one of the rings later.
3557 * This will not pass over-length frames into the default
3558 * queue because it's gated by the VMOLR.RLPML.
3559 */
3560 max_frame_size = MAX_JUMBO_FRAME_SIZE;
3561 }
3562
3563 wr32(E1000_RLPML, max_frame_size);
3564}
3565
3566static inline void igb_set_vmolr(struct igb_adapter *adapter,
3567 int vfn, bool aupe)
3568{
3569 struct e1000_hw *hw = &adapter->hw;
3570 u32 vmolr;
3571
3572 /* This register exists only on 82576 and newer so if we are older then
3573 * we should exit and do nothing
3574 */
3575 if (hw->mac.type < e1000_82576)
3576 return;
3577
3578 vmolr = rd32(E1000_VMOLR(vfn));
3579 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3580 if (hw->mac.type == e1000_i350) {
3581 u32 dvmolr;
3582
3583 dvmolr = rd32(E1000_DVMOLR(vfn));
3584 dvmolr |= E1000_DVMOLR_STRVLAN;
3585 wr32(E1000_DVMOLR(vfn), dvmolr);
3586 }
3587 if (aupe)
3588 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3589 else
3590 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3591
3592 /* clear all bits that might not be set */
3593 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3594
3595 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3596 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3597 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
3598 * multicast packets
3599 */
3600 if (vfn <= adapter->vfs_allocated_count)
3601 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3602
3603 wr32(E1000_VMOLR(vfn), vmolr);
3604}
3605
3606/**
3607 * igb_configure_rx_ring - Configure a receive ring after Reset
3608 * @adapter: board private structure
3609 * @ring: receive ring to be configured
3610 *
3611 * Configure the Rx unit of the MAC after a reset.
3612 **/
3613void igb_configure_rx_ring(struct igb_adapter *adapter,
3614 struct igb_ring *ring)
3615{
3616 struct e1000_hw *hw = &adapter->hw;
3617 u64 rdba = ring->dma;
3618 int reg_idx = ring->reg_idx;
3619 u32 srrctl = 0, rxdctl = 0;
3620
3621 /* disable the queue */
3622 wr32(E1000_RXDCTL(reg_idx), 0);
3623
3624 /* Set DMA base address registers */
3625 wr32(E1000_RDBAL(reg_idx),
3626 rdba & 0x00000000ffffffffULL);
3627 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3628 wr32(E1000_RDLEN(reg_idx),
3629 ring->count * sizeof(union e1000_adv_rx_desc));
3630
3631 /* initialize head and tail */
3632 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3633 wr32(E1000_RDH(reg_idx), 0);
3634 writel(0, ring->tail);
3635
3636 /* set descriptor configuration */
3637 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3638 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3639 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3640 if (hw->mac.type >= e1000_82580)
3641 srrctl |= E1000_SRRCTL_TIMESTAMP;
3642 /* Only set Drop Enable if we are supporting multiple queues */
3643 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3644 srrctl |= E1000_SRRCTL_DROP_EN;
3645
3646 wr32(E1000_SRRCTL(reg_idx), srrctl);
3647
3648 /* set filtering for VMDQ pools */
3649 igb_set_vmolr(adapter, reg_idx & 0x7, true);
3650
3651 rxdctl |= IGB_RX_PTHRESH;
3652 rxdctl |= IGB_RX_HTHRESH << 8;
3653 rxdctl |= IGB_RX_WTHRESH << 16;
3654
3655 /* enable receive descriptor fetching */
3656 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3657 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3658}
3659
3660/**
3661 * igb_configure_rx - Configure receive Unit after Reset
3662 * @adapter: board private structure
3663 *
3664 * Configure the Rx unit of the MAC after a reset.
3665 **/
3666static void igb_configure_rx(struct igb_adapter *adapter)
3667{
3668 int i;
3669
3670 /* set UTA to appropriate mode */
3671 igb_set_uta(adapter);
3672
3673 /* set the correct pool for the PF default MAC address in entry 0 */
3674 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3675 adapter->vfs_allocated_count);
3676
3677 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3678 * the Base and Length of the Rx Descriptor Ring
3679 */
3680 for (i = 0; i < adapter->num_rx_queues; i++)
3681 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3682}
3683
3684/**
3685 * igb_free_tx_resources - Free Tx Resources per Queue
3686 * @tx_ring: Tx descriptor ring for a specific queue
3687 *
3688 * Free all transmit software resources
3689 **/
3690void igb_free_tx_resources(struct igb_ring *tx_ring)
3691{
3692 igb_clean_tx_ring(tx_ring);
3693
3694 vfree(tx_ring->tx_buffer_info);
3695 tx_ring->tx_buffer_info = NULL;
3696
3697 /* if not set, then don't free */
3698 if (!tx_ring->desc)
3699 return;
3700
3701 dma_free_coherent(tx_ring->dev, tx_ring->size,
3702 tx_ring->desc, tx_ring->dma);
3703
3704 tx_ring->desc = NULL;
3705}
3706
3707/**
3708 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3709 * @adapter: board private structure
3710 *
3711 * Free all transmit software resources
3712 **/
3713static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3714{
3715 int i;
3716
3717 for (i = 0; i < adapter->num_tx_queues; i++)
3718 if (adapter->tx_ring[i])
3719 igb_free_tx_resources(adapter->tx_ring[i]);
3720}
3721
3722void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3723 struct igb_tx_buffer *tx_buffer)
3724{
3725 if (tx_buffer->skb) {
3726 dev_kfree_skb_any(tx_buffer->skb);
3727 if (dma_unmap_len(tx_buffer, len))
3728 dma_unmap_single(ring->dev,
3729 dma_unmap_addr(tx_buffer, dma),
3730 dma_unmap_len(tx_buffer, len),
3731 DMA_TO_DEVICE);
3732 } else if (dma_unmap_len(tx_buffer, len)) {
3733 dma_unmap_page(ring->dev,
3734 dma_unmap_addr(tx_buffer, dma),
3735 dma_unmap_len(tx_buffer, len),
3736 DMA_TO_DEVICE);
3737 }
3738 tx_buffer->next_to_watch = NULL;
3739 tx_buffer->skb = NULL;
3740 dma_unmap_len_set(tx_buffer, len, 0);
3741 /* buffer_info must be completely set up in the transmit path */
3742}
3743
3744/**
3745 * igb_clean_tx_ring - Free Tx Buffers
3746 * @tx_ring: ring to be cleaned
3747 **/
3748static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3749{
3750 struct igb_tx_buffer *buffer_info;
3751 unsigned long size;
3752 u16 i;
3753
3754 if (!tx_ring->tx_buffer_info)
3755 return;
3756 /* Free all the Tx ring sk_buffs */
3757
3758 for (i = 0; i < tx_ring->count; i++) {
3759 buffer_info = &tx_ring->tx_buffer_info[i];
3760 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3761 }
3762
3763 netdev_tx_reset_queue(txring_txq(tx_ring));
3764
3765 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3766 memset(tx_ring->tx_buffer_info, 0, size);
3767
3768 /* Zero out the descriptor ring */
3769 memset(tx_ring->desc, 0, tx_ring->size);
3770
3771 tx_ring->next_to_use = 0;
3772 tx_ring->next_to_clean = 0;
3773}
3774
3775/**
3776 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3777 * @adapter: board private structure
3778 **/
3779static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3780{
3781 int i;
3782
3783 for (i = 0; i < adapter->num_tx_queues; i++)
3784 if (adapter->tx_ring[i])
3785 igb_clean_tx_ring(adapter->tx_ring[i]);
3786}
3787
3788/**
3789 * igb_free_rx_resources - Free Rx Resources
3790 * @rx_ring: ring to clean the resources from
3791 *
3792 * Free all receive software resources
3793 **/
3794void igb_free_rx_resources(struct igb_ring *rx_ring)
3795{
3796 igb_clean_rx_ring(rx_ring);
3797
3798 vfree(rx_ring->rx_buffer_info);
3799 rx_ring->rx_buffer_info = NULL;
3800
3801 /* if not set, then don't free */
3802 if (!rx_ring->desc)
3803 return;
3804
3805 dma_free_coherent(rx_ring->dev, rx_ring->size,
3806 rx_ring->desc, rx_ring->dma);
3807
3808 rx_ring->desc = NULL;
3809}
3810
3811/**
3812 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3813 * @adapter: board private structure
3814 *
3815 * Free all receive software resources
3816 **/
3817static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3818{
3819 int i;
3820
3821 for (i = 0; i < adapter->num_rx_queues; i++)
3822 if (adapter->rx_ring[i])
3823 igb_free_rx_resources(adapter->rx_ring[i]);
3824}
3825
3826/**
3827 * igb_clean_rx_ring - Free Rx Buffers per Queue
3828 * @rx_ring: ring to free buffers from
3829 **/
3830static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3831{
3832 unsigned long size;
3833 u16 i;
3834
3835 if (rx_ring->skb)
3836 dev_kfree_skb(rx_ring->skb);
3837 rx_ring->skb = NULL;
3838
3839 if (!rx_ring->rx_buffer_info)
3840 return;
3841
3842 /* Free all the Rx ring sk_buffs */
3843 for (i = 0; i < rx_ring->count; i++) {
3844 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3845
3846 if (!buffer_info->page)
3847 continue;
3848
3849 dma_unmap_page(rx_ring->dev,
3850 buffer_info->dma,
3851 PAGE_SIZE,
3852 DMA_FROM_DEVICE);
3853 __free_page(buffer_info->page);
3854
3855 buffer_info->page = NULL;
3856 }
3857
3858 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3859 memset(rx_ring->rx_buffer_info, 0, size);
3860
3861 /* Zero out the descriptor ring */
3862 memset(rx_ring->desc, 0, rx_ring->size);
3863
3864 rx_ring->next_to_alloc = 0;
3865 rx_ring->next_to_clean = 0;
3866 rx_ring->next_to_use = 0;
3867}
3868
3869/**
3870 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3871 * @adapter: board private structure
3872 **/
3873static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3874{
3875 int i;
3876
3877 for (i = 0; i < adapter->num_rx_queues; i++)
3878 if (adapter->rx_ring[i])
3879 igb_clean_rx_ring(adapter->rx_ring[i]);
3880}
3881
3882/**
3883 * igb_set_mac - Change the Ethernet Address of the NIC
3884 * @netdev: network interface device structure
3885 * @p: pointer to an address structure
3886 *
3887 * Returns 0 on success, negative on failure
3888 **/
3889static int igb_set_mac(struct net_device *netdev, void *p)
3890{
3891 struct igb_adapter *adapter = netdev_priv(netdev);
3892 struct e1000_hw *hw = &adapter->hw;
3893 struct sockaddr *addr = p;
3894
3895 if (!is_valid_ether_addr(addr->sa_data))
3896 return -EADDRNOTAVAIL;
3897
3898 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3899 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3900
3901 /* set the correct pool for the new PF MAC address in entry 0 */
3902 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3903 adapter->vfs_allocated_count);
3904
3905 return 0;
3906}
3907
3908/**
3909 * igb_write_mc_addr_list - write multicast addresses to MTA
3910 * @netdev: network interface device structure
3911 *
3912 * Writes multicast address list to the MTA hash table.
3913 * Returns: -ENOMEM on failure
3914 * 0 on no addresses written
3915 * X on writing X addresses to MTA
3916 **/
3917static int igb_write_mc_addr_list(struct net_device *netdev)
3918{
3919 struct igb_adapter *adapter = netdev_priv(netdev);
3920 struct e1000_hw *hw = &adapter->hw;
3921 struct netdev_hw_addr *ha;
3922 u8 *mta_list;
3923 int i;
3924
3925 if (netdev_mc_empty(netdev)) {
3926 /* nothing to program, so clear mc list */
3927 igb_update_mc_addr_list(hw, NULL, 0);
3928 igb_restore_vf_multicasts(adapter);
3929 return 0;
3930 }
3931
3932 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3933 if (!mta_list)
3934 return -ENOMEM;
3935
3936 /* The shared function expects a packed array of only addresses. */
3937 i = 0;
3938 netdev_for_each_mc_addr(ha, netdev)
3939 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3940
3941 igb_update_mc_addr_list(hw, mta_list, i);
3942 kfree(mta_list);
3943
3944 return netdev_mc_count(netdev);
3945}
3946
3947/**
3948 * igb_write_uc_addr_list - write unicast addresses to RAR table
3949 * @netdev: network interface device structure
3950 *
3951 * Writes unicast address list to the RAR table.
3952 * Returns: -ENOMEM on failure/insufficient address space
3953 * 0 on no addresses written
3954 * X on writing X addresses to the RAR table
3955 **/
3956static int igb_write_uc_addr_list(struct net_device *netdev)
3957{
3958 struct igb_adapter *adapter = netdev_priv(netdev);
3959 struct e1000_hw *hw = &adapter->hw;
3960 unsigned int vfn = adapter->vfs_allocated_count;
3961 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3962 int count = 0;
3963
3964 /* return ENOMEM indicating insufficient memory for addresses */
3965 if (netdev_uc_count(netdev) > rar_entries)
3966 return -ENOMEM;
3967
3968 if (!netdev_uc_empty(netdev) && rar_entries) {
3969 struct netdev_hw_addr *ha;
3970
3971 netdev_for_each_uc_addr(ha, netdev) {
3972 if (!rar_entries)
3973 break;
3974 igb_rar_set_qsel(adapter, ha->addr,
3975 rar_entries--,
3976 vfn);
3977 count++;
3978 }
3979 }
3980 /* write the addresses in reverse order to avoid write combining */
3981 for (; rar_entries > 0 ; rar_entries--) {
3982 wr32(E1000_RAH(rar_entries), 0);
3983 wr32(E1000_RAL(rar_entries), 0);
3984 }
3985 wrfl();
3986
3987 return count;
3988}
3989
3990/**
3991 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3992 * @netdev: network interface device structure
3993 *
3994 * The set_rx_mode entry point is called whenever the unicast or multicast
3995 * address lists or the network interface flags are updated. This routine is
3996 * responsible for configuring the hardware for proper unicast, multicast,
3997 * promiscuous mode, and all-multi behavior.
3998 **/
3999static void igb_set_rx_mode(struct net_device *netdev)
4000{
4001 struct igb_adapter *adapter = netdev_priv(netdev);
4002 struct e1000_hw *hw = &adapter->hw;
4003 unsigned int vfn = adapter->vfs_allocated_count;
4004 u32 rctl, vmolr = 0;
4005 int count;
4006
4007 /* Check for Promiscuous and All Multicast modes */
4008 rctl = rd32(E1000_RCTL);
4009
4010 /* clear the effected bits */
4011 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
4012
4013 if (netdev->flags & IFF_PROMISC) {
4014 /* retain VLAN HW filtering if in VT mode */
4015 if (adapter->vfs_allocated_count)
4016 rctl |= E1000_RCTL_VFE;
4017 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
4018 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
4019 } else {
4020 if (netdev->flags & IFF_ALLMULTI) {
4021 rctl |= E1000_RCTL_MPE;
4022 vmolr |= E1000_VMOLR_MPME;
4023 } else {
4024 /* Write addresses to the MTA, if the attempt fails
4025 * then we should just turn on promiscuous mode so
4026 * that we can at least receive multicast traffic
4027 */
4028 count = igb_write_mc_addr_list(netdev);
4029 if (count < 0) {
4030 rctl |= E1000_RCTL_MPE;
4031 vmolr |= E1000_VMOLR_MPME;
4032 } else if (count) {
4033 vmolr |= E1000_VMOLR_ROMPE;
4034 }
4035 }
4036 /* Write addresses to available RAR registers, if there is not
4037 * sufficient space to store all the addresses then enable
4038 * unicast promiscuous mode
4039 */
4040 count = igb_write_uc_addr_list(netdev);
4041 if (count < 0) {
4042 rctl |= E1000_RCTL_UPE;
4043 vmolr |= E1000_VMOLR_ROPE;
4044 }
4045 rctl |= E1000_RCTL_VFE;
4046 }
4047 wr32(E1000_RCTL, rctl);
4048
4049 /* In order to support SR-IOV and eventually VMDq it is necessary to set
4050 * the VMOLR to enable the appropriate modes. Without this workaround
4051 * we will have issues with VLAN tag stripping not being done for frames
4052 * that are only arriving because we are the default pool
4053 */
4054 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
4055 return;
4056
4057 vmolr |= rd32(E1000_VMOLR(vfn)) &
4058 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
4059 wr32(E1000_VMOLR(vfn), vmolr);
4060 igb_restore_vf_multicasts(adapter);
4061}
4062
4063static void igb_check_wvbr(struct igb_adapter *adapter)
4064{
4065 struct e1000_hw *hw = &adapter->hw;
4066 u32 wvbr = 0;
4067
4068 switch (hw->mac.type) {
4069 case e1000_82576:
4070 case e1000_i350:
4071 wvbr = rd32(E1000_WVBR);
4072 if (!wvbr)
4073 return;
4074 break;
4075 default:
4076 break;
4077 }
4078
4079 adapter->wvbr |= wvbr;
4080}
4081
4082#define IGB_STAGGERED_QUEUE_OFFSET 8
4083
4084static void igb_spoof_check(struct igb_adapter *adapter)
4085{
4086 int j;
4087
4088 if (!adapter->wvbr)
4089 return;
4090
4091 for (j = 0; j < adapter->vfs_allocated_count; j++) {
4092 if (adapter->wvbr & (1 << j) ||
4093 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4094 dev_warn(&adapter->pdev->dev,
4095 "Spoof event(s) detected on VF %d\n", j);
4096 adapter->wvbr &=
4097 ~((1 << j) |
4098 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4099 }
4100 }
4101}
4102
4103/* Need to wait a few seconds after link up to get diagnostic information from
4104 * the phy
4105 */
4106static void igb_update_phy_info(unsigned long data)
4107{
4108 struct igb_adapter *adapter = (struct igb_adapter *) data;
4109 igb_get_phy_info(&adapter->hw);
4110}
4111
4112/**
4113 * igb_has_link - check shared code for link and determine up/down
4114 * @adapter: pointer to driver private info
4115 **/
4116bool igb_has_link(struct igb_adapter *adapter)
4117{
4118 struct e1000_hw *hw = &adapter->hw;
4119 bool link_active = false;
4120
4121 /* get_link_status is set on LSC (link status) interrupt or
4122 * rx sequence error interrupt. get_link_status will stay
4123 * false until the e1000_check_for_link establishes link
4124 * for copper adapters ONLY
4125 */
4126 switch (hw->phy.media_type) {
4127 case e1000_media_type_copper:
4128 if (!hw->mac.get_link_status)
4129 return true;
4130 case e1000_media_type_internal_serdes:
4131 hw->mac.ops.check_for_link(hw);
4132 link_active = !hw->mac.get_link_status;
4133 break;
4134 default:
4135 case e1000_media_type_unknown:
4136 break;
4137 }
4138
4139 if (((hw->mac.type == e1000_i210) ||
4140 (hw->mac.type == e1000_i211)) &&
4141 (hw->phy.id == I210_I_PHY_ID)) {
4142 if (!netif_carrier_ok(adapter->netdev)) {
4143 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4144 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4145 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4146 adapter->link_check_timeout = jiffies;
4147 }
4148 }
4149
4150 return link_active;
4151}
4152
4153static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4154{
4155 bool ret = false;
4156 u32 ctrl_ext, thstat;
4157
4158 /* check for thermal sensor event on i350 copper only */
4159 if (hw->mac.type == e1000_i350) {
4160 thstat = rd32(E1000_THSTAT);
4161 ctrl_ext = rd32(E1000_CTRL_EXT);
4162
4163 if ((hw->phy.media_type == e1000_media_type_copper) &&
4164 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
4165 ret = !!(thstat & event);
4166 }
4167
4168 return ret;
4169}
4170
4171/**
4172 * igb_check_lvmmc - check for malformed packets received
4173 * and indicated in LVMMC register
4174 * @adapter: pointer to adapter
4175 **/
4176static void igb_check_lvmmc(struct igb_adapter *adapter)
4177{
4178 struct e1000_hw *hw = &adapter->hw;
4179 u32 lvmmc;
4180
4181 lvmmc = rd32(E1000_LVMMC);
4182 if (lvmmc) {
4183 if (unlikely(net_ratelimit())) {
4184 netdev_warn(adapter->netdev,
4185 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4186 lvmmc);
4187 }
4188 }
4189}
4190
4191/**
4192 * igb_watchdog - Timer Call-back
4193 * @data: pointer to adapter cast into an unsigned long
4194 **/
4195static void igb_watchdog(unsigned long data)
4196{
4197 struct igb_adapter *adapter = (struct igb_adapter *)data;
4198 /* Do the rest outside of interrupt context */
4199 schedule_work(&adapter->watchdog_task);
4200}
4201
4202static void igb_watchdog_task(struct work_struct *work)
4203{
4204 struct igb_adapter *adapter = container_of(work,
4205 struct igb_adapter,
4206 watchdog_task);
4207 struct e1000_hw *hw = &adapter->hw;
4208 struct e1000_phy_info *phy = &hw->phy;
4209 struct net_device *netdev = adapter->netdev;
4210 u32 link;
4211 int i;
4212 u32 connsw;
4213
4214 link = igb_has_link(adapter);
4215
4216 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4217 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4218 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4219 else
4220 link = false;
4221 }
4222
4223 /* Force link down if we have fiber to swap to */
4224 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4225 if (hw->phy.media_type == e1000_media_type_copper) {
4226 connsw = rd32(E1000_CONNSW);
4227 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4228 link = 0;
4229 }
4230 }
4231 if (link) {
4232 /* Perform a reset if the media type changed. */
4233 if (hw->dev_spec._82575.media_changed) {
4234 hw->dev_spec._82575.media_changed = false;
4235 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4236 igb_reset(adapter);
4237 }
4238 /* Cancel scheduled suspend requests. */
4239 pm_runtime_resume(netdev->dev.parent);
4240
4241 if (!netif_carrier_ok(netdev)) {
4242 u32 ctrl;
4243
4244 hw->mac.ops.get_speed_and_duplex(hw,
4245 &adapter->link_speed,
4246 &adapter->link_duplex);
4247
4248 ctrl = rd32(E1000_CTRL);
4249 /* Links status message must follow this format */
4250 netdev_info(netdev,
4251 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4252 netdev->name,
4253 adapter->link_speed,
4254 adapter->link_duplex == FULL_DUPLEX ?
4255 "Full" : "Half",
4256 (ctrl & E1000_CTRL_TFCE) &&
4257 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4258 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4259 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
4260
4261 /* disable EEE if enabled */
4262 if ((adapter->flags & IGB_FLAG_EEE) &&
4263 (adapter->link_duplex == HALF_DUPLEX)) {
4264 dev_info(&adapter->pdev->dev,
4265 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4266 adapter->hw.dev_spec._82575.eee_disable = true;
4267 adapter->flags &= ~IGB_FLAG_EEE;
4268 }
4269
4270 /* check if SmartSpeed worked */
4271 igb_check_downshift(hw);
4272 if (phy->speed_downgraded)
4273 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4274
4275 /* check for thermal sensor event */
4276 if (igb_thermal_sensor_event(hw,
4277 E1000_THSTAT_LINK_THROTTLE))
4278 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
4279
4280 /* adjust timeout factor according to speed/duplex */
4281 adapter->tx_timeout_factor = 1;
4282 switch (adapter->link_speed) {
4283 case SPEED_10:
4284 adapter->tx_timeout_factor = 14;
4285 break;
4286 case SPEED_100:
4287 /* maybe add some timeout factor ? */
4288 break;
4289 }
4290
4291 netif_carrier_on(netdev);
4292
4293 igb_ping_all_vfs(adapter);
4294 igb_check_vf_rate_limit(adapter);
4295
4296 /* link state has changed, schedule phy info update */
4297 if (!test_bit(__IGB_DOWN, &adapter->state))
4298 mod_timer(&adapter->phy_info_timer,
4299 round_jiffies(jiffies + 2 * HZ));
4300 }
4301 } else {
4302 if (netif_carrier_ok(netdev)) {
4303 adapter->link_speed = 0;
4304 adapter->link_duplex = 0;
4305
4306 /* check for thermal sensor event */
4307 if (igb_thermal_sensor_event(hw,
4308 E1000_THSTAT_PWR_DOWN)) {
4309 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
4310 }
4311
4312 /* Links status message must follow this format */
4313 netdev_info(netdev, "igb: %s NIC Link is Down\n",
4314 netdev->name);
4315 netif_carrier_off(netdev);
4316
4317 igb_ping_all_vfs(adapter);
4318
4319 /* link state has changed, schedule phy info update */
4320 if (!test_bit(__IGB_DOWN, &adapter->state))
4321 mod_timer(&adapter->phy_info_timer,
4322 round_jiffies(jiffies + 2 * HZ));
4323
4324 /* link is down, time to check for alternate media */
4325 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4326 igb_check_swap_media(adapter);
4327 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4328 schedule_work(&adapter->reset_task);
4329 /* return immediately */
4330 return;
4331 }
4332 }
4333 pm_schedule_suspend(netdev->dev.parent,
4334 MSEC_PER_SEC * 5);
4335
4336 /* also check for alternate media here */
4337 } else if (!netif_carrier_ok(netdev) &&
4338 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4339 igb_check_swap_media(adapter);
4340 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4341 schedule_work(&adapter->reset_task);
4342 /* return immediately */
4343 return;
4344 }
4345 }
4346 }
4347
4348 spin_lock(&adapter->stats64_lock);
4349 igb_update_stats(adapter, &adapter->stats64);
4350 spin_unlock(&adapter->stats64_lock);
4351
4352 for (i = 0; i < adapter->num_tx_queues; i++) {
4353 struct igb_ring *tx_ring = adapter->tx_ring[i];
4354 if (!netif_carrier_ok(netdev)) {
4355 /* We've lost link, so the controller stops DMA,
4356 * but we've got queued Tx work that's never going
4357 * to get done, so reset controller to flush Tx.
4358 * (Do the reset outside of interrupt context).
4359 */
4360 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4361 adapter->tx_timeout_count++;
4362 schedule_work(&adapter->reset_task);
4363 /* return immediately since reset is imminent */
4364 return;
4365 }
4366 }
4367
4368 /* Force detection of hung controller every watchdog period */
4369 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
4370 }
4371
4372 /* Cause software interrupt to ensure Rx ring is cleaned */
4373 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
4374 u32 eics = 0;
4375
4376 for (i = 0; i < adapter->num_q_vectors; i++)
4377 eics |= adapter->q_vector[i]->eims_value;
4378 wr32(E1000_EICS, eics);
4379 } else {
4380 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4381 }
4382
4383 igb_spoof_check(adapter);
4384 igb_ptp_rx_hang(adapter);
4385
4386 /* Check LVMMC register on i350/i354 only */
4387 if ((adapter->hw.mac.type == e1000_i350) ||
4388 (adapter->hw.mac.type == e1000_i354))
4389 igb_check_lvmmc(adapter);
4390
4391 /* Reset the timer */
4392 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4393 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4394 mod_timer(&adapter->watchdog_timer,
4395 round_jiffies(jiffies + HZ));
4396 else
4397 mod_timer(&adapter->watchdog_timer,
4398 round_jiffies(jiffies + 2 * HZ));
4399 }
4400}
4401
4402enum latency_range {
4403 lowest_latency = 0,
4404 low_latency = 1,
4405 bulk_latency = 2,
4406 latency_invalid = 255
4407};
4408
4409/**
4410 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4411 * @q_vector: pointer to q_vector
4412 *
4413 * Stores a new ITR value based on strictly on packet size. This
4414 * algorithm is less sophisticated than that used in igb_update_itr,
4415 * due to the difficulty of synchronizing statistics across multiple
4416 * receive rings. The divisors and thresholds used by this function
4417 * were determined based on theoretical maximum wire speed and testing
4418 * data, in order to minimize response time while increasing bulk
4419 * throughput.
4420 * This functionality is controlled by ethtool's coalescing settings.
4421 * NOTE: This function is called only when operating in a multiqueue
4422 * receive environment.
4423 **/
4424static void igb_update_ring_itr(struct igb_q_vector *q_vector)
4425{
4426 int new_val = q_vector->itr_val;
4427 int avg_wire_size = 0;
4428 struct igb_adapter *adapter = q_vector->adapter;
4429 unsigned int packets;
4430
4431 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4432 * ints/sec - ITR timer value of 120 ticks.
4433 */
4434 if (adapter->link_speed != SPEED_1000) {
4435 new_val = IGB_4K_ITR;
4436 goto set_itr_val;
4437 }
4438
4439 packets = q_vector->rx.total_packets;
4440 if (packets)
4441 avg_wire_size = q_vector->rx.total_bytes / packets;
4442
4443 packets = q_vector->tx.total_packets;
4444 if (packets)
4445 avg_wire_size = max_t(u32, avg_wire_size,
4446 q_vector->tx.total_bytes / packets);
4447
4448 /* if avg_wire_size isn't set no work was done */
4449 if (!avg_wire_size)
4450 goto clear_counts;
4451
4452 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4453 avg_wire_size += 24;
4454
4455 /* Don't starve jumbo frames */
4456 avg_wire_size = min(avg_wire_size, 3000);
4457
4458 /* Give a little boost to mid-size frames */
4459 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4460 new_val = avg_wire_size / 3;
4461 else
4462 new_val = avg_wire_size / 2;
4463
4464 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4465 if (new_val < IGB_20K_ITR &&
4466 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4467 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4468 new_val = IGB_20K_ITR;
4469
4470set_itr_val:
4471 if (new_val != q_vector->itr_val) {
4472 q_vector->itr_val = new_val;
4473 q_vector->set_itr = 1;
4474 }
4475clear_counts:
4476 q_vector->rx.total_bytes = 0;
4477 q_vector->rx.total_packets = 0;
4478 q_vector->tx.total_bytes = 0;
4479 q_vector->tx.total_packets = 0;
4480}
4481
4482/**
4483 * igb_update_itr - update the dynamic ITR value based on statistics
4484 * @q_vector: pointer to q_vector
4485 * @ring_container: ring info to update the itr for
4486 *
4487 * Stores a new ITR value based on packets and byte
4488 * counts during the last interrupt. The advantage of per interrupt
4489 * computation is faster updates and more accurate ITR for the current
4490 * traffic pattern. Constants in this function were computed
4491 * based on theoretical maximum wire speed and thresholds were set based
4492 * on testing data as well as attempting to minimize response time
4493 * while increasing bulk throughput.
4494 * This functionality is controlled by ethtool's coalescing settings.
4495 * NOTE: These calculations are only valid when operating in a single-
4496 * queue environment.
4497 **/
4498static void igb_update_itr(struct igb_q_vector *q_vector,
4499 struct igb_ring_container *ring_container)
4500{
4501 unsigned int packets = ring_container->total_packets;
4502 unsigned int bytes = ring_container->total_bytes;
4503 u8 itrval = ring_container->itr;
4504
4505 /* no packets, exit with status unchanged */
4506 if (packets == 0)
4507 return;
4508
4509 switch (itrval) {
4510 case lowest_latency:
4511 /* handle TSO and jumbo frames */
4512 if (bytes/packets > 8000)
4513 itrval = bulk_latency;
4514 else if ((packets < 5) && (bytes > 512))
4515 itrval = low_latency;
4516 break;
4517 case low_latency: /* 50 usec aka 20000 ints/s */
4518 if (bytes > 10000) {
4519 /* this if handles the TSO accounting */
4520 if (bytes/packets > 8000)
4521 itrval = bulk_latency;
4522 else if ((packets < 10) || ((bytes/packets) > 1200))
4523 itrval = bulk_latency;
4524 else if ((packets > 35))
4525 itrval = lowest_latency;
4526 } else if (bytes/packets > 2000) {
4527 itrval = bulk_latency;
4528 } else if (packets <= 2 && bytes < 512) {
4529 itrval = lowest_latency;
4530 }
4531 break;
4532 case bulk_latency: /* 250 usec aka 4000 ints/s */
4533 if (bytes > 25000) {
4534 if (packets > 35)
4535 itrval = low_latency;
4536 } else if (bytes < 1500) {
4537 itrval = low_latency;
4538 }
4539 break;
4540 }
4541
4542 /* clear work counters since we have the values we need */
4543 ring_container->total_bytes = 0;
4544 ring_container->total_packets = 0;
4545
4546 /* write updated itr to ring container */
4547 ring_container->itr = itrval;
4548}
4549
4550static void igb_set_itr(struct igb_q_vector *q_vector)
4551{
4552 struct igb_adapter *adapter = q_vector->adapter;
4553 u32 new_itr = q_vector->itr_val;
4554 u8 current_itr = 0;
4555
4556 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4557 if (adapter->link_speed != SPEED_1000) {
4558 current_itr = 0;
4559 new_itr = IGB_4K_ITR;
4560 goto set_itr_now;
4561 }
4562
4563 igb_update_itr(q_vector, &q_vector->tx);
4564 igb_update_itr(q_vector, &q_vector->rx);
4565
4566 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4567
4568 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4569 if (current_itr == lowest_latency &&
4570 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4571 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4572 current_itr = low_latency;
4573
4574 switch (current_itr) {
4575 /* counts and packets in update_itr are dependent on these numbers */
4576 case lowest_latency:
4577 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
4578 break;
4579 case low_latency:
4580 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
4581 break;
4582 case bulk_latency:
4583 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
4584 break;
4585 default:
4586 break;
4587 }
4588
4589set_itr_now:
4590 if (new_itr != q_vector->itr_val) {
4591 /* this attempts to bias the interrupt rate towards Bulk
4592 * by adding intermediate steps when interrupt rate is
4593 * increasing
4594 */
4595 new_itr = new_itr > q_vector->itr_val ?
4596 max((new_itr * q_vector->itr_val) /
4597 (new_itr + (q_vector->itr_val >> 2)),
4598 new_itr) : new_itr;
4599 /* Don't write the value here; it resets the adapter's
4600 * internal timer, and causes us to delay far longer than
4601 * we should between interrupts. Instead, we write the ITR
4602 * value at the beginning of the next interrupt so the timing
4603 * ends up being correct.
4604 */
4605 q_vector->itr_val = new_itr;
4606 q_vector->set_itr = 1;
4607 }
4608}
4609
4610static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4611 u32 type_tucmd, u32 mss_l4len_idx)
4612{
4613 struct e1000_adv_tx_context_desc *context_desc;
4614 u16 i = tx_ring->next_to_use;
4615
4616 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4617
4618 i++;
4619 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4620
4621 /* set bits to identify this as an advanced context descriptor */
4622 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4623
4624 /* For 82575, context index must be unique per ring. */
4625 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4626 mss_l4len_idx |= tx_ring->reg_idx << 4;
4627
4628 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4629 context_desc->seqnum_seed = 0;
4630 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4631 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4632}
4633
4634static int igb_tso(struct igb_ring *tx_ring,
4635 struct igb_tx_buffer *first,
4636 u8 *hdr_len)
4637{
4638 struct sk_buff *skb = first->skb;
4639 u32 vlan_macip_lens, type_tucmd;
4640 u32 mss_l4len_idx, l4len;
4641 int err;
4642
4643 if (skb->ip_summed != CHECKSUM_PARTIAL)
4644 return 0;
4645
4646 if (!skb_is_gso(skb))
4647 return 0;
4648
4649 err = skb_cow_head(skb, 0);
4650 if (err < 0)
4651 return err;
4652
4653 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4654 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4655
4656 if (first->protocol == htons(ETH_P_IP)) {
4657 struct iphdr *iph = ip_hdr(skb);
4658 iph->tot_len = 0;
4659 iph->check = 0;
4660 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4661 iph->daddr, 0,
4662 IPPROTO_TCP,
4663 0);
4664 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4665 first->tx_flags |= IGB_TX_FLAGS_TSO |
4666 IGB_TX_FLAGS_CSUM |
4667 IGB_TX_FLAGS_IPV4;
4668 } else if (skb_is_gso_v6(skb)) {
4669 ipv6_hdr(skb)->payload_len = 0;
4670 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4671 &ipv6_hdr(skb)->daddr,
4672 0, IPPROTO_TCP, 0);
4673 first->tx_flags |= IGB_TX_FLAGS_TSO |
4674 IGB_TX_FLAGS_CSUM;
4675 }
4676
4677 /* compute header lengths */
4678 l4len = tcp_hdrlen(skb);
4679 *hdr_len = skb_transport_offset(skb) + l4len;
4680
4681 /* update gso size and bytecount with header size */
4682 first->gso_segs = skb_shinfo(skb)->gso_segs;
4683 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4684
4685 /* MSS L4LEN IDX */
4686 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4687 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4688
4689 /* VLAN MACLEN IPLEN */
4690 vlan_macip_lens = skb_network_header_len(skb);
4691 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4692 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4693
4694 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4695
4696 return 1;
4697}
4698
4699static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4700{
4701 struct sk_buff *skb = first->skb;
4702 u32 vlan_macip_lens = 0;
4703 u32 mss_l4len_idx = 0;
4704 u32 type_tucmd = 0;
4705
4706 if (skb->ip_summed != CHECKSUM_PARTIAL) {
4707 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4708 return;
4709 } else {
4710 u8 l4_hdr = 0;
4711
4712 switch (first->protocol) {
4713 case htons(ETH_P_IP):
4714 vlan_macip_lens |= skb_network_header_len(skb);
4715 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4716 l4_hdr = ip_hdr(skb)->protocol;
4717 break;
4718 case htons(ETH_P_IPV6):
4719 vlan_macip_lens |= skb_network_header_len(skb);
4720 l4_hdr = ipv6_hdr(skb)->nexthdr;
4721 break;
4722 default:
4723 if (unlikely(net_ratelimit())) {
4724 dev_warn(tx_ring->dev,
4725 "partial checksum but proto=%x!\n",
4726 first->protocol);
4727 }
4728 break;
4729 }
4730
4731 switch (l4_hdr) {
4732 case IPPROTO_TCP:
4733 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4734 mss_l4len_idx = tcp_hdrlen(skb) <<
4735 E1000_ADVTXD_L4LEN_SHIFT;
4736 break;
4737 case IPPROTO_SCTP:
4738 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4739 mss_l4len_idx = sizeof(struct sctphdr) <<
4740 E1000_ADVTXD_L4LEN_SHIFT;
4741 break;
4742 case IPPROTO_UDP:
4743 mss_l4len_idx = sizeof(struct udphdr) <<
4744 E1000_ADVTXD_L4LEN_SHIFT;
4745 break;
4746 default:
4747 if (unlikely(net_ratelimit())) {
4748 dev_warn(tx_ring->dev,
4749 "partial checksum but l4 proto=%x!\n",
4750 l4_hdr);
4751 }
4752 break;
4753 }
4754
4755 /* update TX checksum flag */
4756 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4757 }
4758
4759 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4760 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4761
4762 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4763}
4764
4765#define IGB_SET_FLAG(_input, _flag, _result) \
4766 ((_flag <= _result) ? \
4767 ((u32)(_input & _flag) * (_result / _flag)) : \
4768 ((u32)(_input & _flag) / (_flag / _result)))
4769
4770static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4771{
4772 /* set type for advanced descriptor with frame checksum insertion */
4773 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4774 E1000_ADVTXD_DCMD_DEXT |
4775 E1000_ADVTXD_DCMD_IFCS;
4776
4777 /* set HW vlan bit if vlan is present */
4778 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4779 (E1000_ADVTXD_DCMD_VLE));
4780
4781 /* set segmentation bits for TSO */
4782 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4783 (E1000_ADVTXD_DCMD_TSE));
4784
4785 /* set timestamp bit if present */
4786 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4787 (E1000_ADVTXD_MAC_TSTAMP));
4788
4789 /* insert frame checksum */
4790 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4791
4792 return cmd_type;
4793}
4794
4795static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4796 union e1000_adv_tx_desc *tx_desc,
4797 u32 tx_flags, unsigned int paylen)
4798{
4799 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4800
4801 /* 82575 requires a unique index per ring */
4802 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4803 olinfo_status |= tx_ring->reg_idx << 4;
4804
4805 /* insert L4 checksum */
4806 olinfo_status |= IGB_SET_FLAG(tx_flags,
4807 IGB_TX_FLAGS_CSUM,
4808 (E1000_TXD_POPTS_TXSM << 8));
4809
4810 /* insert IPv4 checksum */
4811 olinfo_status |= IGB_SET_FLAG(tx_flags,
4812 IGB_TX_FLAGS_IPV4,
4813 (E1000_TXD_POPTS_IXSM << 8));
4814
4815 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4816}
4817
4818static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4819{
4820 struct net_device *netdev = tx_ring->netdev;
4821
4822 netif_stop_subqueue(netdev, tx_ring->queue_index);
4823
4824 /* Herbert's original patch had:
4825 * smp_mb__after_netif_stop_queue();
4826 * but since that doesn't exist yet, just open code it.
4827 */
4828 smp_mb();
4829
4830 /* We need to check again in a case another CPU has just
4831 * made room available.
4832 */
4833 if (igb_desc_unused(tx_ring) < size)
4834 return -EBUSY;
4835
4836 /* A reprieve! */
4837 netif_wake_subqueue(netdev, tx_ring->queue_index);
4838
4839 u64_stats_update_begin(&tx_ring->tx_syncp2);
4840 tx_ring->tx_stats.restart_queue2++;
4841 u64_stats_update_end(&tx_ring->tx_syncp2);
4842
4843 return 0;
4844}
4845
4846static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4847{
4848 if (igb_desc_unused(tx_ring) >= size)
4849 return 0;
4850 return __igb_maybe_stop_tx(tx_ring, size);
4851}
4852
4853static void igb_tx_map(struct igb_ring *tx_ring,
4854 struct igb_tx_buffer *first,
4855 const u8 hdr_len)
4856{
4857 struct sk_buff *skb = first->skb;
4858 struct igb_tx_buffer *tx_buffer;
4859 union e1000_adv_tx_desc *tx_desc;
4860 struct skb_frag_struct *frag;
4861 dma_addr_t dma;
4862 unsigned int data_len, size;
4863 u32 tx_flags = first->tx_flags;
4864 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
4865 u16 i = tx_ring->next_to_use;
4866
4867 tx_desc = IGB_TX_DESC(tx_ring, i);
4868
4869 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4870
4871 size = skb_headlen(skb);
4872 data_len = skb->data_len;
4873
4874 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4875
4876 tx_buffer = first;
4877
4878 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4879 if (dma_mapping_error(tx_ring->dev, dma))
4880 goto dma_error;
4881
4882 /* record length, and DMA address */
4883 dma_unmap_len_set(tx_buffer, len, size);
4884 dma_unmap_addr_set(tx_buffer, dma, dma);
4885
4886 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4887
4888 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4889 tx_desc->read.cmd_type_len =
4890 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
4891
4892 i++;
4893 tx_desc++;
4894 if (i == tx_ring->count) {
4895 tx_desc = IGB_TX_DESC(tx_ring, 0);
4896 i = 0;
4897 }
4898 tx_desc->read.olinfo_status = 0;
4899
4900 dma += IGB_MAX_DATA_PER_TXD;
4901 size -= IGB_MAX_DATA_PER_TXD;
4902
4903 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4904 }
4905
4906 if (likely(!data_len))
4907 break;
4908
4909 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
4910
4911 i++;
4912 tx_desc++;
4913 if (i == tx_ring->count) {
4914 tx_desc = IGB_TX_DESC(tx_ring, 0);
4915 i = 0;
4916 }
4917 tx_desc->read.olinfo_status = 0;
4918
4919 size = skb_frag_size(frag);
4920 data_len -= size;
4921
4922 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4923 size, DMA_TO_DEVICE);
4924
4925 tx_buffer = &tx_ring->tx_buffer_info[i];
4926 }
4927
4928 /* write last descriptor with RS and EOP bits */
4929 cmd_type |= size | IGB_TXD_DCMD;
4930 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
4931
4932 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4933
4934 /* set the timestamp */
4935 first->time_stamp = jiffies;
4936
4937 /* Force memory writes to complete before letting h/w know there
4938 * are new descriptors to fetch. (Only applicable for weak-ordered
4939 * memory model archs, such as IA-64).
4940 *
4941 * We also need this memory barrier to make certain all of the
4942 * status bits have been updated before next_to_watch is written.
4943 */
4944 wmb();
4945
4946 /* set next_to_watch value indicating a packet is present */
4947 first->next_to_watch = tx_desc;
4948
4949 i++;
4950 if (i == tx_ring->count)
4951 i = 0;
4952
4953 tx_ring->next_to_use = i;
4954
4955 /* Make sure there is space in the ring for the next send. */
4956 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4957
4958 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
4959 writel(i, tx_ring->tail);
4960
4961 /* we need this if more than one processor can write to our tail
4962 * at a time, it synchronizes IO on IA64/Altix systems
4963 */
4964 mmiowb();
4965 }
4966 return;
4967
4968dma_error:
4969 dev_err(tx_ring->dev, "TX DMA map failed\n");
4970
4971 /* clear dma mappings for failed tx_buffer_info map */
4972 for (;;) {
4973 tx_buffer = &tx_ring->tx_buffer_info[i];
4974 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4975 if (tx_buffer == first)
4976 break;
4977 if (i == 0)
4978 i = tx_ring->count;
4979 i--;
4980 }
4981
4982 tx_ring->next_to_use = i;
4983}
4984
4985netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4986 struct igb_ring *tx_ring)
4987{
4988 struct igb_tx_buffer *first;
4989 int tso;
4990 u32 tx_flags = 0;
4991 unsigned short f;
4992 u16 count = TXD_USE_COUNT(skb_headlen(skb));
4993 __be16 protocol = vlan_get_protocol(skb);
4994 u8 hdr_len = 0;
4995
4996 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4997 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
4998 * + 2 desc gap to keep tail from touching head,
4999 * + 1 desc for context descriptor,
5000 * otherwise try next time
5001 */
5002 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5003 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5004
5005 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
5006 /* this is a hard error */
5007 return NETDEV_TX_BUSY;
5008 }
5009
5010 /* record the location of the first descriptor for this packet */
5011 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5012 first->skb = skb;
5013 first->bytecount = skb->len;
5014 first->gso_segs = 1;
5015
5016 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5017 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
5018
5019 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5020 &adapter->state)) {
5021 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5022 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5023
5024 adapter->ptp_tx_skb = skb_get(skb);
5025 adapter->ptp_tx_start = jiffies;
5026 if (adapter->hw.mac.type == e1000_82576)
5027 schedule_work(&adapter->ptp_tx_work);
5028 }
5029 }
5030
5031 skb_tx_timestamp(skb);
5032
5033 if (skb_vlan_tag_present(skb)) {
5034 tx_flags |= IGB_TX_FLAGS_VLAN;
5035 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
5036 }
5037
5038 /* record initial flags and protocol */
5039 first->tx_flags = tx_flags;
5040 first->protocol = protocol;
5041
5042 tso = igb_tso(tx_ring, first, &hdr_len);
5043 if (tso < 0)
5044 goto out_drop;
5045 else if (!tso)
5046 igb_tx_csum(tx_ring, first);
5047
5048 igb_tx_map(tx_ring, first, hdr_len);
5049
5050 return NETDEV_TX_OK;
5051
5052out_drop:
5053 igb_unmap_and_free_tx_resource(tx_ring, first);
5054
5055 return NETDEV_TX_OK;
5056}
5057
5058static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5059 struct sk_buff *skb)
5060{
5061 unsigned int r_idx = skb->queue_mapping;
5062
5063 if (r_idx >= adapter->num_tx_queues)
5064 r_idx = r_idx % adapter->num_tx_queues;
5065
5066 return adapter->tx_ring[r_idx];
5067}
5068
5069static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5070 struct net_device *netdev)
5071{
5072 struct igb_adapter *adapter = netdev_priv(netdev);
5073
5074 if (test_bit(__IGB_DOWN, &adapter->state)) {
5075 dev_kfree_skb_any(skb);
5076 return NETDEV_TX_OK;
5077 }
5078
5079 if (skb->len <= 0) {
5080 dev_kfree_skb_any(skb);
5081 return NETDEV_TX_OK;
5082 }
5083
5084 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
5085 * in order to meet this minimum size requirement.
5086 */
5087 if (skb_put_padto(skb, 17))
5088 return NETDEV_TX_OK;
5089
5090 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
5091}
5092
5093/**
5094 * igb_tx_timeout - Respond to a Tx Hang
5095 * @netdev: network interface device structure
5096 **/
5097static void igb_tx_timeout(struct net_device *netdev)
5098{
5099 struct igb_adapter *adapter = netdev_priv(netdev);
5100 struct e1000_hw *hw = &adapter->hw;
5101
5102 /* Do the reset outside of interrupt context */
5103 adapter->tx_timeout_count++;
5104
5105 if (hw->mac.type >= e1000_82580)
5106 hw->dev_spec._82575.global_device_reset = true;
5107
5108 schedule_work(&adapter->reset_task);
5109 wr32(E1000_EICS,
5110 (adapter->eims_enable_mask & ~adapter->eims_other));
5111}
5112
5113static void igb_reset_task(struct work_struct *work)
5114{
5115 struct igb_adapter *adapter;
5116 adapter = container_of(work, struct igb_adapter, reset_task);
5117
5118 igb_dump(adapter);
5119 netdev_err(adapter->netdev, "Reset adapter\n");
5120 igb_reinit_locked(adapter);
5121}
5122
5123/**
5124 * igb_get_stats64 - Get System Network Statistics
5125 * @netdev: network interface device structure
5126 * @stats: rtnl_link_stats64 pointer
5127 **/
5128static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
5129 struct rtnl_link_stats64 *stats)
5130{
5131 struct igb_adapter *adapter = netdev_priv(netdev);
5132
5133 spin_lock(&adapter->stats64_lock);
5134 igb_update_stats(adapter, &adapter->stats64);
5135 memcpy(stats, &adapter->stats64, sizeof(*stats));
5136 spin_unlock(&adapter->stats64_lock);
5137
5138 return stats;
5139}
5140
5141/**
5142 * igb_change_mtu - Change the Maximum Transfer Unit
5143 * @netdev: network interface device structure
5144 * @new_mtu: new value for maximum frame size
5145 *
5146 * Returns 0 on success, negative on failure
5147 **/
5148static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5149{
5150 struct igb_adapter *adapter = netdev_priv(netdev);
5151 struct pci_dev *pdev = adapter->pdev;
5152 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
5153
5154 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
5155 dev_err(&pdev->dev, "Invalid MTU setting\n");
5156 return -EINVAL;
5157 }
5158
5159#define MAX_STD_JUMBO_FRAME_SIZE 9238
5160 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
5161 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
5162 return -EINVAL;
5163 }
5164
5165 /* adjust max frame to be at least the size of a standard frame */
5166 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5167 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5168
5169 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
5170 usleep_range(1000, 2000);
5171
5172 /* igb_down has a dependency on max_frame_size */
5173 adapter->max_frame_size = max_frame;
5174
5175 if (netif_running(netdev))
5176 igb_down(adapter);
5177
5178 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
5179 netdev->mtu, new_mtu);
5180 netdev->mtu = new_mtu;
5181
5182 if (netif_running(netdev))
5183 igb_up(adapter);
5184 else
5185 igb_reset(adapter);
5186
5187 clear_bit(__IGB_RESETTING, &adapter->state);
5188
5189 return 0;
5190}
5191
5192/**
5193 * igb_update_stats - Update the board statistics counters
5194 * @adapter: board private structure
5195 **/
5196void igb_update_stats(struct igb_adapter *adapter,
5197 struct rtnl_link_stats64 *net_stats)
5198{
5199 struct e1000_hw *hw = &adapter->hw;
5200 struct pci_dev *pdev = adapter->pdev;
5201 u32 reg, mpc;
5202 int i;
5203 u64 bytes, packets;
5204 unsigned int start;
5205 u64 _bytes, _packets;
5206
5207 /* Prevent stats update while adapter is being reset, or if the pci
5208 * connection is down.
5209 */
5210 if (adapter->link_speed == 0)
5211 return;
5212 if (pci_channel_offline(pdev))
5213 return;
5214
5215 bytes = 0;
5216 packets = 0;
5217
5218 rcu_read_lock();
5219 for (i = 0; i < adapter->num_rx_queues; i++) {
5220 struct igb_ring *ring = adapter->rx_ring[i];
5221 u32 rqdpc = rd32(E1000_RQDPC(i));
5222 if (hw->mac.type >= e1000_i210)
5223 wr32(E1000_RQDPC(i), 0);
5224
5225 if (rqdpc) {
5226 ring->rx_stats.drops += rqdpc;
5227 net_stats->rx_fifo_errors += rqdpc;
5228 }
5229
5230 do {
5231 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
5232 _bytes = ring->rx_stats.bytes;
5233 _packets = ring->rx_stats.packets;
5234 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
5235 bytes += _bytes;
5236 packets += _packets;
5237 }
5238
5239 net_stats->rx_bytes = bytes;
5240 net_stats->rx_packets = packets;
5241
5242 bytes = 0;
5243 packets = 0;
5244 for (i = 0; i < adapter->num_tx_queues; i++) {
5245 struct igb_ring *ring = adapter->tx_ring[i];
5246 do {
5247 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
5248 _bytes = ring->tx_stats.bytes;
5249 _packets = ring->tx_stats.packets;
5250 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
5251 bytes += _bytes;
5252 packets += _packets;
5253 }
5254 net_stats->tx_bytes = bytes;
5255 net_stats->tx_packets = packets;
5256 rcu_read_unlock();
5257
5258 /* read stats registers */
5259 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5260 adapter->stats.gprc += rd32(E1000_GPRC);
5261 adapter->stats.gorc += rd32(E1000_GORCL);
5262 rd32(E1000_GORCH); /* clear GORCL */
5263 adapter->stats.bprc += rd32(E1000_BPRC);
5264 adapter->stats.mprc += rd32(E1000_MPRC);
5265 adapter->stats.roc += rd32(E1000_ROC);
5266
5267 adapter->stats.prc64 += rd32(E1000_PRC64);
5268 adapter->stats.prc127 += rd32(E1000_PRC127);
5269 adapter->stats.prc255 += rd32(E1000_PRC255);
5270 adapter->stats.prc511 += rd32(E1000_PRC511);
5271 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5272 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5273 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5274 adapter->stats.sec += rd32(E1000_SEC);
5275
5276 mpc = rd32(E1000_MPC);
5277 adapter->stats.mpc += mpc;
5278 net_stats->rx_fifo_errors += mpc;
5279 adapter->stats.scc += rd32(E1000_SCC);
5280 adapter->stats.ecol += rd32(E1000_ECOL);
5281 adapter->stats.mcc += rd32(E1000_MCC);
5282 adapter->stats.latecol += rd32(E1000_LATECOL);
5283 adapter->stats.dc += rd32(E1000_DC);
5284 adapter->stats.rlec += rd32(E1000_RLEC);
5285 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5286 adapter->stats.xontxc += rd32(E1000_XONTXC);
5287 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5288 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5289 adapter->stats.fcruc += rd32(E1000_FCRUC);
5290 adapter->stats.gptc += rd32(E1000_GPTC);
5291 adapter->stats.gotc += rd32(E1000_GOTCL);
5292 rd32(E1000_GOTCH); /* clear GOTCL */
5293 adapter->stats.rnbc += rd32(E1000_RNBC);
5294 adapter->stats.ruc += rd32(E1000_RUC);
5295 adapter->stats.rfc += rd32(E1000_RFC);
5296 adapter->stats.rjc += rd32(E1000_RJC);
5297 adapter->stats.tor += rd32(E1000_TORH);
5298 adapter->stats.tot += rd32(E1000_TOTH);
5299 adapter->stats.tpr += rd32(E1000_TPR);
5300
5301 adapter->stats.ptc64 += rd32(E1000_PTC64);
5302 adapter->stats.ptc127 += rd32(E1000_PTC127);
5303 adapter->stats.ptc255 += rd32(E1000_PTC255);
5304 adapter->stats.ptc511 += rd32(E1000_PTC511);
5305 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5306 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5307
5308 adapter->stats.mptc += rd32(E1000_MPTC);
5309 adapter->stats.bptc += rd32(E1000_BPTC);
5310
5311 adapter->stats.tpt += rd32(E1000_TPT);
5312 adapter->stats.colc += rd32(E1000_COLC);
5313
5314 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
5315 /* read internal phy specific stats */
5316 reg = rd32(E1000_CTRL_EXT);
5317 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5318 adapter->stats.rxerrc += rd32(E1000_RXERRC);
5319
5320 /* this stat has invalid values on i210/i211 */
5321 if ((hw->mac.type != e1000_i210) &&
5322 (hw->mac.type != e1000_i211))
5323 adapter->stats.tncrs += rd32(E1000_TNCRS);
5324 }
5325
5326 adapter->stats.tsctc += rd32(E1000_TSCTC);
5327 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5328
5329 adapter->stats.iac += rd32(E1000_IAC);
5330 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5331 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5332 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5333 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5334 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5335 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5336 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5337 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5338
5339 /* Fill out the OS statistics structure */
5340 net_stats->multicast = adapter->stats.mprc;
5341 net_stats->collisions = adapter->stats.colc;
5342
5343 /* Rx Errors */
5344
5345 /* RLEC on some newer hardware can be incorrect so build
5346 * our own version based on RUC and ROC
5347 */
5348 net_stats->rx_errors = adapter->stats.rxerrc +
5349 adapter->stats.crcerrs + adapter->stats.algnerrc +
5350 adapter->stats.ruc + adapter->stats.roc +
5351 adapter->stats.cexterr;
5352 net_stats->rx_length_errors = adapter->stats.ruc +
5353 adapter->stats.roc;
5354 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5355 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5356 net_stats->rx_missed_errors = adapter->stats.mpc;
5357
5358 /* Tx Errors */
5359 net_stats->tx_errors = adapter->stats.ecol +
5360 adapter->stats.latecol;
5361 net_stats->tx_aborted_errors = adapter->stats.ecol;
5362 net_stats->tx_window_errors = adapter->stats.latecol;
5363 net_stats->tx_carrier_errors = adapter->stats.tncrs;
5364
5365 /* Tx Dropped needs to be maintained elsewhere */
5366
5367 /* Management Stats */
5368 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5369 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5370 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
5371
5372 /* OS2BMC Stats */
5373 reg = rd32(E1000_MANC);
5374 if (reg & E1000_MANC_EN_BMC2OS) {
5375 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5376 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5377 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5378 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5379 }
5380}
5381
5382static void igb_tsync_interrupt(struct igb_adapter *adapter)
5383{
5384 struct e1000_hw *hw = &adapter->hw;
5385 struct ptp_clock_event event;
5386 struct timespec ts;
5387 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
5388
5389 if (tsicr & TSINTR_SYS_WRAP) {
5390 event.type = PTP_CLOCK_PPS;
5391 if (adapter->ptp_caps.pps)
5392 ptp_clock_event(adapter->ptp_clock, &event);
5393 else
5394 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5395 ack |= TSINTR_SYS_WRAP;
5396 }
5397
5398 if (tsicr & E1000_TSICR_TXTS) {
5399 /* retrieve hardware timestamp */
5400 schedule_work(&adapter->ptp_tx_work);
5401 ack |= E1000_TSICR_TXTS;
5402 }
5403
5404 if (tsicr & TSINTR_TT0) {
5405 spin_lock(&adapter->tmreg_lock);
5406 ts = timespec_add(adapter->perout[0].start,
5407 adapter->perout[0].period);
5408 wr32(E1000_TRGTTIML0, ts.tv_nsec);
5409 wr32(E1000_TRGTTIMH0, ts.tv_sec);
5410 tsauxc = rd32(E1000_TSAUXC);
5411 tsauxc |= TSAUXC_EN_TT0;
5412 wr32(E1000_TSAUXC, tsauxc);
5413 adapter->perout[0].start = ts;
5414 spin_unlock(&adapter->tmreg_lock);
5415 ack |= TSINTR_TT0;
5416 }
5417
5418 if (tsicr & TSINTR_TT1) {
5419 spin_lock(&adapter->tmreg_lock);
5420 ts = timespec_add(adapter->perout[1].start,
5421 adapter->perout[1].period);
5422 wr32(E1000_TRGTTIML1, ts.tv_nsec);
5423 wr32(E1000_TRGTTIMH1, ts.tv_sec);
5424 tsauxc = rd32(E1000_TSAUXC);
5425 tsauxc |= TSAUXC_EN_TT1;
5426 wr32(E1000_TSAUXC, tsauxc);
5427 adapter->perout[1].start = ts;
5428 spin_unlock(&adapter->tmreg_lock);
5429 ack |= TSINTR_TT1;
5430 }
5431
5432 if (tsicr & TSINTR_AUTT0) {
5433 nsec = rd32(E1000_AUXSTMPL0);
5434 sec = rd32(E1000_AUXSTMPH0);
5435 event.type = PTP_CLOCK_EXTTS;
5436 event.index = 0;
5437 event.timestamp = sec * 1000000000ULL + nsec;
5438 ptp_clock_event(adapter->ptp_clock, &event);
5439 ack |= TSINTR_AUTT0;
5440 }
5441
5442 if (tsicr & TSINTR_AUTT1) {
5443 nsec = rd32(E1000_AUXSTMPL1);
5444 sec = rd32(E1000_AUXSTMPH1);
5445 event.type = PTP_CLOCK_EXTTS;
5446 event.index = 1;
5447 event.timestamp = sec * 1000000000ULL + nsec;
5448 ptp_clock_event(adapter->ptp_clock, &event);
5449 ack |= TSINTR_AUTT1;
5450 }
5451
5452 /* acknowledge the interrupts */
5453 wr32(E1000_TSICR, ack);
5454}
5455
5456static irqreturn_t igb_msix_other(int irq, void *data)
5457{
5458 struct igb_adapter *adapter = data;
5459 struct e1000_hw *hw = &adapter->hw;
5460 u32 icr = rd32(E1000_ICR);
5461 /* reading ICR causes bit 31 of EICR to be cleared */
5462
5463 if (icr & E1000_ICR_DRSTA)
5464 schedule_work(&adapter->reset_task);
5465
5466 if (icr & E1000_ICR_DOUTSYNC) {
5467 /* HW is reporting DMA is out of sync */
5468 adapter->stats.doosync++;
5469 /* The DMA Out of Sync is also indication of a spoof event
5470 * in IOV mode. Check the Wrong VM Behavior register to
5471 * see if it is really a spoof event.
5472 */
5473 igb_check_wvbr(adapter);
5474 }
5475
5476 /* Check for a mailbox event */
5477 if (icr & E1000_ICR_VMMB)
5478 igb_msg_task(adapter);
5479
5480 if (icr & E1000_ICR_LSC) {
5481 hw->mac.get_link_status = 1;
5482 /* guard against interrupt when we're going down */
5483 if (!test_bit(__IGB_DOWN, &adapter->state))
5484 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5485 }
5486
5487 if (icr & E1000_ICR_TS)
5488 igb_tsync_interrupt(adapter);
5489
5490 wr32(E1000_EIMS, adapter->eims_other);
5491
5492 return IRQ_HANDLED;
5493}
5494
5495static void igb_write_itr(struct igb_q_vector *q_vector)
5496{
5497 struct igb_adapter *adapter = q_vector->adapter;
5498 u32 itr_val = q_vector->itr_val & 0x7FFC;
5499
5500 if (!q_vector->set_itr)
5501 return;
5502
5503 if (!itr_val)
5504 itr_val = 0x4;
5505
5506 if (adapter->hw.mac.type == e1000_82575)
5507 itr_val |= itr_val << 16;
5508 else
5509 itr_val |= E1000_EITR_CNT_IGNR;
5510
5511 writel(itr_val, q_vector->itr_register);
5512 q_vector->set_itr = 0;
5513}
5514
5515static irqreturn_t igb_msix_ring(int irq, void *data)
5516{
5517 struct igb_q_vector *q_vector = data;
5518
5519 /* Write the ITR value calculated from the previous interrupt. */
5520 igb_write_itr(q_vector);
5521
5522 napi_schedule(&q_vector->napi);
5523
5524 return IRQ_HANDLED;
5525}
5526
5527#ifdef CONFIG_IGB_DCA
5528static void igb_update_tx_dca(struct igb_adapter *adapter,
5529 struct igb_ring *tx_ring,
5530 int cpu)
5531{
5532 struct e1000_hw *hw = &adapter->hw;
5533 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5534
5535 if (hw->mac.type != e1000_82575)
5536 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5537
5538 /* We can enable relaxed ordering for reads, but not writes when
5539 * DCA is enabled. This is due to a known issue in some chipsets
5540 * which will cause the DCA tag to be cleared.
5541 */
5542 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5543 E1000_DCA_TXCTRL_DATA_RRO_EN |
5544 E1000_DCA_TXCTRL_DESC_DCA_EN;
5545
5546 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5547}
5548
5549static void igb_update_rx_dca(struct igb_adapter *adapter,
5550 struct igb_ring *rx_ring,
5551 int cpu)
5552{
5553 struct e1000_hw *hw = &adapter->hw;
5554 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5555
5556 if (hw->mac.type != e1000_82575)
5557 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5558
5559 /* We can enable relaxed ordering for reads, but not writes when
5560 * DCA is enabled. This is due to a known issue in some chipsets
5561 * which will cause the DCA tag to be cleared.
5562 */
5563 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5564 E1000_DCA_RXCTRL_DESC_DCA_EN;
5565
5566 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5567}
5568
5569static void igb_update_dca(struct igb_q_vector *q_vector)
5570{
5571 struct igb_adapter *adapter = q_vector->adapter;
5572 int cpu = get_cpu();
5573
5574 if (q_vector->cpu == cpu)
5575 goto out_no_update;
5576
5577 if (q_vector->tx.ring)
5578 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5579
5580 if (q_vector->rx.ring)
5581 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5582
5583 q_vector->cpu = cpu;
5584out_no_update:
5585 put_cpu();
5586}
5587
5588static void igb_setup_dca(struct igb_adapter *adapter)
5589{
5590 struct e1000_hw *hw = &adapter->hw;
5591 int i;
5592
5593 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
5594 return;
5595
5596 /* Always use CB2 mode, difference is masked in the CB driver. */
5597 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5598
5599 for (i = 0; i < adapter->num_q_vectors; i++) {
5600 adapter->q_vector[i]->cpu = -1;
5601 igb_update_dca(adapter->q_vector[i]);
5602 }
5603}
5604
5605static int __igb_notify_dca(struct device *dev, void *data)
5606{
5607 struct net_device *netdev = dev_get_drvdata(dev);
5608 struct igb_adapter *adapter = netdev_priv(netdev);
5609 struct pci_dev *pdev = adapter->pdev;
5610 struct e1000_hw *hw = &adapter->hw;
5611 unsigned long event = *(unsigned long *)data;
5612
5613 switch (event) {
5614 case DCA_PROVIDER_ADD:
5615 /* if already enabled, don't do it again */
5616 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
5617 break;
5618 if (dca_add_requester(dev) == 0) {
5619 adapter->flags |= IGB_FLAG_DCA_ENABLED;
5620 dev_info(&pdev->dev, "DCA enabled\n");
5621 igb_setup_dca(adapter);
5622 break;
5623 }
5624 /* Fall Through since DCA is disabled. */
5625 case DCA_PROVIDER_REMOVE:
5626 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
5627 /* without this a class_device is left
5628 * hanging around in the sysfs model
5629 */
5630 dca_remove_requester(dev);
5631 dev_info(&pdev->dev, "DCA disabled\n");
5632 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
5633 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
5634 }
5635 break;
5636 }
5637
5638 return 0;
5639}
5640
5641static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5642 void *p)
5643{
5644 int ret_val;
5645
5646 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5647 __igb_notify_dca);
5648
5649 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5650}
5651#endif /* CONFIG_IGB_DCA */
5652
5653#ifdef CONFIG_PCI_IOV
5654static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5655{
5656 unsigned char mac_addr[ETH_ALEN];
5657
5658 eth_zero_addr(mac_addr);
5659 igb_set_vf_mac(adapter, vf, mac_addr);
5660
5661 /* By default spoof check is enabled for all VFs */
5662 adapter->vf_data[vf].spoofchk_enabled = true;
5663
5664 return 0;
5665}
5666
5667#endif
5668static void igb_ping_all_vfs(struct igb_adapter *adapter)
5669{
5670 struct e1000_hw *hw = &adapter->hw;
5671 u32 ping;
5672 int i;
5673
5674 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5675 ping = E1000_PF_CONTROL_MSG;
5676 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5677 ping |= E1000_VT_MSGTYPE_CTS;
5678 igb_write_mbx(hw, &ping, 1, i);
5679 }
5680}
5681
5682static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5683{
5684 struct e1000_hw *hw = &adapter->hw;
5685 u32 vmolr = rd32(E1000_VMOLR(vf));
5686 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5687
5688 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5689 IGB_VF_FLAG_MULTI_PROMISC);
5690 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5691
5692 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5693 vmolr |= E1000_VMOLR_MPME;
5694 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5695 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5696 } else {
5697 /* if we have hashes and we are clearing a multicast promisc
5698 * flag we need to write the hashes to the MTA as this step
5699 * was previously skipped
5700 */
5701 if (vf_data->num_vf_mc_hashes > 30) {
5702 vmolr |= E1000_VMOLR_MPME;
5703 } else if (vf_data->num_vf_mc_hashes) {
5704 int j;
5705
5706 vmolr |= E1000_VMOLR_ROMPE;
5707 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5708 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5709 }
5710 }
5711
5712 wr32(E1000_VMOLR(vf), vmolr);
5713
5714 /* there are flags left unprocessed, likely not supported */
5715 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5716 return -EINVAL;
5717
5718 return 0;
5719}
5720
5721static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5722 u32 *msgbuf, u32 vf)
5723{
5724 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5725 u16 *hash_list = (u16 *)&msgbuf[1];
5726 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5727 int i;
5728
5729 /* salt away the number of multicast addresses assigned
5730 * to this VF for later use to restore when the PF multi cast
5731 * list changes
5732 */
5733 vf_data->num_vf_mc_hashes = n;
5734
5735 /* only up to 30 hash values supported */
5736 if (n > 30)
5737 n = 30;
5738
5739 /* store the hashes for later use */
5740 for (i = 0; i < n; i++)
5741 vf_data->vf_mc_hashes[i] = hash_list[i];
5742
5743 /* Flush and reset the mta with the new values */
5744 igb_set_rx_mode(adapter->netdev);
5745
5746 return 0;
5747}
5748
5749static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5750{
5751 struct e1000_hw *hw = &adapter->hw;
5752 struct vf_data_storage *vf_data;
5753 int i, j;
5754
5755 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5756 u32 vmolr = rd32(E1000_VMOLR(i));
5757
5758 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5759
5760 vf_data = &adapter->vf_data[i];
5761
5762 if ((vf_data->num_vf_mc_hashes > 30) ||
5763 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5764 vmolr |= E1000_VMOLR_MPME;
5765 } else if (vf_data->num_vf_mc_hashes) {
5766 vmolr |= E1000_VMOLR_ROMPE;
5767 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5768 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5769 }
5770 wr32(E1000_VMOLR(i), vmolr);
5771 }
5772}
5773
5774static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5775{
5776 struct e1000_hw *hw = &adapter->hw;
5777 u32 pool_mask, reg, vid;
5778 int i;
5779
5780 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5781
5782 /* Find the vlan filter for this id */
5783 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5784 reg = rd32(E1000_VLVF(i));
5785
5786 /* remove the vf from the pool */
5787 reg &= ~pool_mask;
5788
5789 /* if pool is empty then remove entry from vfta */
5790 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5791 (reg & E1000_VLVF_VLANID_ENABLE)) {
5792 reg = 0;
5793 vid = reg & E1000_VLVF_VLANID_MASK;
5794 igb_vfta_set(hw, vid, false);
5795 }
5796
5797 wr32(E1000_VLVF(i), reg);
5798 }
5799
5800 adapter->vf_data[vf].vlans_enabled = 0;
5801}
5802
5803static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5804{
5805 struct e1000_hw *hw = &adapter->hw;
5806 u32 reg, i;
5807
5808 /* The vlvf table only exists on 82576 hardware and newer */
5809 if (hw->mac.type < e1000_82576)
5810 return -1;
5811
5812 /* we only need to do this if VMDq is enabled */
5813 if (!adapter->vfs_allocated_count)
5814 return -1;
5815
5816 /* Find the vlan filter for this id */
5817 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5818 reg = rd32(E1000_VLVF(i));
5819 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5820 vid == (reg & E1000_VLVF_VLANID_MASK))
5821 break;
5822 }
5823
5824 if (add) {
5825 if (i == E1000_VLVF_ARRAY_SIZE) {
5826 /* Did not find a matching VLAN ID entry that was
5827 * enabled. Search for a free filter entry, i.e.
5828 * one without the enable bit set
5829 */
5830 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5831 reg = rd32(E1000_VLVF(i));
5832 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5833 break;
5834 }
5835 }
5836 if (i < E1000_VLVF_ARRAY_SIZE) {
5837 /* Found an enabled/available entry */
5838 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5839
5840 /* if !enabled we need to set this up in vfta */
5841 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5842 /* add VID to filter table */
5843 igb_vfta_set(hw, vid, true);
5844 reg |= E1000_VLVF_VLANID_ENABLE;
5845 }
5846 reg &= ~E1000_VLVF_VLANID_MASK;
5847 reg |= vid;
5848 wr32(E1000_VLVF(i), reg);
5849
5850 /* do not modify RLPML for PF devices */
5851 if (vf >= adapter->vfs_allocated_count)
5852 return 0;
5853
5854 if (!adapter->vf_data[vf].vlans_enabled) {
5855 u32 size;
5856
5857 reg = rd32(E1000_VMOLR(vf));
5858 size = reg & E1000_VMOLR_RLPML_MASK;
5859 size += 4;
5860 reg &= ~E1000_VMOLR_RLPML_MASK;
5861 reg |= size;
5862 wr32(E1000_VMOLR(vf), reg);
5863 }
5864
5865 adapter->vf_data[vf].vlans_enabled++;
5866 }
5867 } else {
5868 if (i < E1000_VLVF_ARRAY_SIZE) {
5869 /* remove vf from the pool */
5870 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5871 /* if pool is empty then remove entry from vfta */
5872 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5873 reg = 0;
5874 igb_vfta_set(hw, vid, false);
5875 }
5876 wr32(E1000_VLVF(i), reg);
5877
5878 /* do not modify RLPML for PF devices */
5879 if (vf >= adapter->vfs_allocated_count)
5880 return 0;
5881
5882 adapter->vf_data[vf].vlans_enabled--;
5883 if (!adapter->vf_data[vf].vlans_enabled) {
5884 u32 size;
5885
5886 reg = rd32(E1000_VMOLR(vf));
5887 size = reg & E1000_VMOLR_RLPML_MASK;
5888 size -= 4;
5889 reg &= ~E1000_VMOLR_RLPML_MASK;
5890 reg |= size;
5891 wr32(E1000_VMOLR(vf), reg);
5892 }
5893 }
5894 }
5895 return 0;
5896}
5897
5898static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5899{
5900 struct e1000_hw *hw = &adapter->hw;
5901
5902 if (vid)
5903 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5904 else
5905 wr32(E1000_VMVIR(vf), 0);
5906}
5907
5908static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5909 int vf, u16 vlan, u8 qos)
5910{
5911 int err = 0;
5912 struct igb_adapter *adapter = netdev_priv(netdev);
5913
5914 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5915 return -EINVAL;
5916 if (vlan || qos) {
5917 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5918 if (err)
5919 goto out;
5920 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5921 igb_set_vmolr(adapter, vf, !vlan);
5922 adapter->vf_data[vf].pf_vlan = vlan;
5923 adapter->vf_data[vf].pf_qos = qos;
5924 dev_info(&adapter->pdev->dev,
5925 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5926 if (test_bit(__IGB_DOWN, &adapter->state)) {
5927 dev_warn(&adapter->pdev->dev,
5928 "The VF VLAN has been set, but the PF device is not up.\n");
5929 dev_warn(&adapter->pdev->dev,
5930 "Bring the PF device up before attempting to use the VF device.\n");
5931 }
5932 } else {
5933 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5934 false, vf);
5935 igb_set_vmvir(adapter, vlan, vf);
5936 igb_set_vmolr(adapter, vf, true);
5937 adapter->vf_data[vf].pf_vlan = 0;
5938 adapter->vf_data[vf].pf_qos = 0;
5939 }
5940out:
5941 return err;
5942}
5943
5944static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5945{
5946 struct e1000_hw *hw = &adapter->hw;
5947 int i;
5948 u32 reg;
5949
5950 /* Find the vlan filter for this id */
5951 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5952 reg = rd32(E1000_VLVF(i));
5953 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5954 vid == (reg & E1000_VLVF_VLANID_MASK))
5955 break;
5956 }
5957
5958 if (i >= E1000_VLVF_ARRAY_SIZE)
5959 i = -1;
5960
5961 return i;
5962}
5963
5964static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5965{
5966 struct e1000_hw *hw = &adapter->hw;
5967 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5968 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5969 int err = 0;
5970
5971 /* If in promiscuous mode we need to make sure the PF also has
5972 * the VLAN filter set.
5973 */
5974 if (add && (adapter->netdev->flags & IFF_PROMISC))
5975 err = igb_vlvf_set(adapter, vid, add,
5976 adapter->vfs_allocated_count);
5977 if (err)
5978 goto out;
5979
5980 err = igb_vlvf_set(adapter, vid, add, vf);
5981
5982 if (err)
5983 goto out;
5984
5985 /* Go through all the checks to see if the VLAN filter should
5986 * be wiped completely.
5987 */
5988 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5989 u32 vlvf, bits;
5990 int regndx = igb_find_vlvf_entry(adapter, vid);
5991
5992 if (regndx < 0)
5993 goto out;
5994 /* See if any other pools are set for this VLAN filter
5995 * entry other than the PF.
5996 */
5997 vlvf = bits = rd32(E1000_VLVF(regndx));
5998 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5999 adapter->vfs_allocated_count);
6000 /* If the filter was removed then ensure PF pool bit
6001 * is cleared if the PF only added itself to the pool
6002 * because the PF is in promiscuous mode.
6003 */
6004 if ((vlvf & VLAN_VID_MASK) == vid &&
6005 !test_bit(vid, adapter->active_vlans) &&
6006 !bits)
6007 igb_vlvf_set(adapter, vid, add,
6008 adapter->vfs_allocated_count);
6009 }
6010
6011out:
6012 return err;
6013}
6014
6015static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
6016{
6017 /* clear flags - except flag that indicates PF has set the MAC */
6018 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
6019 adapter->vf_data[vf].last_nack = jiffies;
6020
6021 /* reset offloads to defaults */
6022 igb_set_vmolr(adapter, vf, true);
6023
6024 /* reset vlans for device */
6025 igb_clear_vf_vfta(adapter, vf);
6026 if (adapter->vf_data[vf].pf_vlan)
6027 igb_ndo_set_vf_vlan(adapter->netdev, vf,
6028 adapter->vf_data[vf].pf_vlan,
6029 adapter->vf_data[vf].pf_qos);
6030 else
6031 igb_clear_vf_vfta(adapter, vf);
6032
6033 /* reset multicast table array for vf */
6034 adapter->vf_data[vf].num_vf_mc_hashes = 0;
6035
6036 /* Flush and reset the mta with the new values */
6037 igb_set_rx_mode(adapter->netdev);
6038}
6039
6040static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6041{
6042 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6043
6044 /* clear mac address as we were hotplug removed/added */
6045 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
6046 eth_zero_addr(vf_mac);
6047
6048 /* process remaining reset events */
6049 igb_vf_reset(adapter, vf);
6050}
6051
6052static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
6053{
6054 struct e1000_hw *hw = &adapter->hw;
6055 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6056 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
6057 u32 reg, msgbuf[3];
6058 u8 *addr = (u8 *)(&msgbuf[1]);
6059
6060 /* process all the same items cleared in a function level reset */
6061 igb_vf_reset(adapter, vf);
6062
6063 /* set vf mac address */
6064 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
6065
6066 /* enable transmit and receive for vf */
6067 reg = rd32(E1000_VFTE);
6068 wr32(E1000_VFTE, reg | (1 << vf));
6069 reg = rd32(E1000_VFRE);
6070 wr32(E1000_VFRE, reg | (1 << vf));
6071
6072 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
6073
6074 /* reply to reset with ack and vf mac address */
6075 if (!is_zero_ether_addr(vf_mac)) {
6076 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6077 memcpy(addr, vf_mac, ETH_ALEN);
6078 } else {
6079 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
6080 }
6081 igb_write_mbx(hw, msgbuf, 3, vf);
6082}
6083
6084static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6085{
6086 /* The VF MAC Address is stored in a packed array of bytes
6087 * starting at the second 32 bit word of the msg array
6088 */
6089 unsigned char *addr = (char *)&msg[1];
6090 int err = -1;
6091
6092 if (is_valid_ether_addr(addr))
6093 err = igb_set_vf_mac(adapter, vf, addr);
6094
6095 return err;
6096}
6097
6098static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6099{
6100 struct e1000_hw *hw = &adapter->hw;
6101 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6102 u32 msg = E1000_VT_MSGTYPE_NACK;
6103
6104 /* if device isn't clear to send it shouldn't be reading either */
6105 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6106 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
6107 igb_write_mbx(hw, &msg, 1, vf);
6108 vf_data->last_nack = jiffies;
6109 }
6110}
6111
6112static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
6113{
6114 struct pci_dev *pdev = adapter->pdev;
6115 u32 msgbuf[E1000_VFMAILBOX_SIZE];
6116 struct e1000_hw *hw = &adapter->hw;
6117 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6118 s32 retval;
6119
6120 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
6121
6122 if (retval) {
6123 /* if receive failed revoke VF CTS stats and restart init */
6124 dev_err(&pdev->dev, "Error receiving message from VF\n");
6125 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6126 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6127 return;
6128 goto out;
6129 }
6130
6131 /* this is a message we already processed, do nothing */
6132 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
6133 return;
6134
6135 /* until the vf completes a reset it should not be
6136 * allowed to start any configuration.
6137 */
6138 if (msgbuf[0] == E1000_VF_RESET) {
6139 igb_vf_reset_msg(adapter, vf);
6140 return;
6141 }
6142
6143 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
6144 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6145 return;
6146 retval = -1;
6147 goto out;
6148 }
6149
6150 switch ((msgbuf[0] & 0xFFFF)) {
6151 case E1000_VF_SET_MAC_ADDR:
6152 retval = -EINVAL;
6153 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6154 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6155 else
6156 dev_warn(&pdev->dev,
6157 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6158 vf);
6159 break;
6160 case E1000_VF_SET_PROMISC:
6161 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6162 break;
6163 case E1000_VF_SET_MULTICAST:
6164 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6165 break;
6166 case E1000_VF_SET_LPE:
6167 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6168 break;
6169 case E1000_VF_SET_VLAN:
6170 retval = -1;
6171 if (vf_data->pf_vlan)
6172 dev_warn(&pdev->dev,
6173 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6174 vf);
6175 else
6176 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
6177 break;
6178 default:
6179 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
6180 retval = -1;
6181 break;
6182 }
6183
6184 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6185out:
6186 /* notify the VF of the results of what it sent us */
6187 if (retval)
6188 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6189 else
6190 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6191
6192 igb_write_mbx(hw, msgbuf, 1, vf);
6193}
6194
6195static void igb_msg_task(struct igb_adapter *adapter)
6196{
6197 struct e1000_hw *hw = &adapter->hw;
6198 u32 vf;
6199
6200 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6201 /* process any reset requests */
6202 if (!igb_check_for_rst(hw, vf))
6203 igb_vf_reset_event(adapter, vf);
6204
6205 /* process any messages pending */
6206 if (!igb_check_for_msg(hw, vf))
6207 igb_rcv_msg_from_vf(adapter, vf);
6208
6209 /* process any acks */
6210 if (!igb_check_for_ack(hw, vf))
6211 igb_rcv_ack_from_vf(adapter, vf);
6212 }
6213}
6214
6215/**
6216 * igb_set_uta - Set unicast filter table address
6217 * @adapter: board private structure
6218 *
6219 * The unicast table address is a register array of 32-bit registers.
6220 * The table is meant to be used in a way similar to how the MTA is used
6221 * however due to certain limitations in the hardware it is necessary to
6222 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6223 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
6224 **/
6225static void igb_set_uta(struct igb_adapter *adapter)
6226{
6227 struct e1000_hw *hw = &adapter->hw;
6228 int i;
6229
6230 /* The UTA table only exists on 82576 hardware and newer */
6231 if (hw->mac.type < e1000_82576)
6232 return;
6233
6234 /* we only need to do this if VMDq is enabled */
6235 if (!adapter->vfs_allocated_count)
6236 return;
6237
6238 for (i = 0; i < hw->mac.uta_reg_count; i++)
6239 array_wr32(E1000_UTA, i, ~0);
6240}
6241
6242/**
6243 * igb_intr_msi - Interrupt Handler
6244 * @irq: interrupt number
6245 * @data: pointer to a network interface device structure
6246 **/
6247static irqreturn_t igb_intr_msi(int irq, void *data)
6248{
6249 struct igb_adapter *adapter = data;
6250 struct igb_q_vector *q_vector = adapter->q_vector[0];
6251 struct e1000_hw *hw = &adapter->hw;
6252 /* read ICR disables interrupts using IAM */
6253 u32 icr = rd32(E1000_ICR);
6254
6255 igb_write_itr(q_vector);
6256
6257 if (icr & E1000_ICR_DRSTA)
6258 schedule_work(&adapter->reset_task);
6259
6260 if (icr & E1000_ICR_DOUTSYNC) {
6261 /* HW is reporting DMA is out of sync */
6262 adapter->stats.doosync++;
6263 }
6264
6265 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6266 hw->mac.get_link_status = 1;
6267 if (!test_bit(__IGB_DOWN, &adapter->state))
6268 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6269 }
6270
6271 if (icr & E1000_ICR_TS)
6272 igb_tsync_interrupt(adapter);
6273
6274 napi_schedule(&q_vector->napi);
6275
6276 return IRQ_HANDLED;
6277}
6278
6279/**
6280 * igb_intr - Legacy Interrupt Handler
6281 * @irq: interrupt number
6282 * @data: pointer to a network interface device structure
6283 **/
6284static irqreturn_t igb_intr(int irq, void *data)
6285{
6286 struct igb_adapter *adapter = data;
6287 struct igb_q_vector *q_vector = adapter->q_vector[0];
6288 struct e1000_hw *hw = &adapter->hw;
6289 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
6290 * need for the IMC write
6291 */
6292 u32 icr = rd32(E1000_ICR);
6293
6294 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
6295 * not set, then the adapter didn't send an interrupt
6296 */
6297 if (!(icr & E1000_ICR_INT_ASSERTED))
6298 return IRQ_NONE;
6299
6300 igb_write_itr(q_vector);
6301
6302 if (icr & E1000_ICR_DRSTA)
6303 schedule_work(&adapter->reset_task);
6304
6305 if (icr & E1000_ICR_DOUTSYNC) {
6306 /* HW is reporting DMA is out of sync */
6307 adapter->stats.doosync++;
6308 }
6309
6310 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6311 hw->mac.get_link_status = 1;
6312 /* guard against interrupt when we're going down */
6313 if (!test_bit(__IGB_DOWN, &adapter->state))
6314 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6315 }
6316
6317 if (icr & E1000_ICR_TS)
6318 igb_tsync_interrupt(adapter);
6319
6320 napi_schedule(&q_vector->napi);
6321
6322 return IRQ_HANDLED;
6323}
6324
6325static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
6326{
6327 struct igb_adapter *adapter = q_vector->adapter;
6328 struct e1000_hw *hw = &adapter->hw;
6329
6330 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6331 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6332 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6333 igb_set_itr(q_vector);
6334 else
6335 igb_update_ring_itr(q_vector);
6336 }
6337
6338 if (!test_bit(__IGB_DOWN, &adapter->state)) {
6339 if (adapter->flags & IGB_FLAG_HAS_MSIX)
6340 wr32(E1000_EIMS, q_vector->eims_value);
6341 else
6342 igb_irq_enable(adapter);
6343 }
6344}
6345
6346/**
6347 * igb_poll - NAPI Rx polling callback
6348 * @napi: napi polling structure
6349 * @budget: count of how many packets we should handle
6350 **/
6351static int igb_poll(struct napi_struct *napi, int budget)
6352{
6353 struct igb_q_vector *q_vector = container_of(napi,
6354 struct igb_q_vector,
6355 napi);
6356 bool clean_complete = true;
6357
6358#ifdef CONFIG_IGB_DCA
6359 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6360 igb_update_dca(q_vector);
6361#endif
6362 if (q_vector->tx.ring)
6363 clean_complete = igb_clean_tx_irq(q_vector);
6364
6365 if (q_vector->rx.ring)
6366 clean_complete &= igb_clean_rx_irq(q_vector, budget);
6367
6368 /* If all work not completed, return budget and keep polling */
6369 if (!clean_complete)
6370 return budget;
6371
6372 /* If not enough Rx work done, exit the polling mode */
6373 napi_complete(napi);
6374 igb_ring_irq_enable(q_vector);
6375
6376 return 0;
6377}
6378
6379/**
6380 * igb_clean_tx_irq - Reclaim resources after transmit completes
6381 * @q_vector: pointer to q_vector containing needed info
6382 *
6383 * returns true if ring is completely cleaned
6384 **/
6385static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
6386{
6387 struct igb_adapter *adapter = q_vector->adapter;
6388 struct igb_ring *tx_ring = q_vector->tx.ring;
6389 struct igb_tx_buffer *tx_buffer;
6390 union e1000_adv_tx_desc *tx_desc;
6391 unsigned int total_bytes = 0, total_packets = 0;
6392 unsigned int budget = q_vector->tx.work_limit;
6393 unsigned int i = tx_ring->next_to_clean;
6394
6395 if (test_bit(__IGB_DOWN, &adapter->state))
6396 return true;
6397
6398 tx_buffer = &tx_ring->tx_buffer_info[i];
6399 tx_desc = IGB_TX_DESC(tx_ring, i);
6400 i -= tx_ring->count;
6401
6402 do {
6403 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
6404
6405 /* if next_to_watch is not set then there is no work pending */
6406 if (!eop_desc)
6407 break;
6408
6409 /* prevent any other reads prior to eop_desc */
6410 read_barrier_depends();
6411
6412 /* if DD is not set pending work has not been completed */
6413 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6414 break;
6415
6416 /* clear next_to_watch to prevent false hangs */
6417 tx_buffer->next_to_watch = NULL;
6418
6419 /* update the statistics for this packet */
6420 total_bytes += tx_buffer->bytecount;
6421 total_packets += tx_buffer->gso_segs;
6422
6423 /* free the skb */
6424 dev_consume_skb_any(tx_buffer->skb);
6425
6426 /* unmap skb header data */
6427 dma_unmap_single(tx_ring->dev,
6428 dma_unmap_addr(tx_buffer, dma),
6429 dma_unmap_len(tx_buffer, len),
6430 DMA_TO_DEVICE);
6431
6432 /* clear tx_buffer data */
6433 tx_buffer->skb = NULL;
6434 dma_unmap_len_set(tx_buffer, len, 0);
6435
6436 /* clear last DMA location and unmap remaining buffers */
6437 while (tx_desc != eop_desc) {
6438 tx_buffer++;
6439 tx_desc++;
6440 i++;
6441 if (unlikely(!i)) {
6442 i -= tx_ring->count;
6443 tx_buffer = tx_ring->tx_buffer_info;
6444 tx_desc = IGB_TX_DESC(tx_ring, 0);
6445 }
6446
6447 /* unmap any remaining paged data */
6448 if (dma_unmap_len(tx_buffer, len)) {
6449 dma_unmap_page(tx_ring->dev,
6450 dma_unmap_addr(tx_buffer, dma),
6451 dma_unmap_len(tx_buffer, len),
6452 DMA_TO_DEVICE);
6453 dma_unmap_len_set(tx_buffer, len, 0);
6454 }
6455 }
6456
6457 /* move us one more past the eop_desc for start of next pkt */
6458 tx_buffer++;
6459 tx_desc++;
6460 i++;
6461 if (unlikely(!i)) {
6462 i -= tx_ring->count;
6463 tx_buffer = tx_ring->tx_buffer_info;
6464 tx_desc = IGB_TX_DESC(tx_ring, 0);
6465 }
6466
6467 /* issue prefetch for next Tx descriptor */
6468 prefetch(tx_desc);
6469
6470 /* update budget accounting */
6471 budget--;
6472 } while (likely(budget));
6473
6474 netdev_tx_completed_queue(txring_txq(tx_ring),
6475 total_packets, total_bytes);
6476 i += tx_ring->count;
6477 tx_ring->next_to_clean = i;
6478 u64_stats_update_begin(&tx_ring->tx_syncp);
6479 tx_ring->tx_stats.bytes += total_bytes;
6480 tx_ring->tx_stats.packets += total_packets;
6481 u64_stats_update_end(&tx_ring->tx_syncp);
6482 q_vector->tx.total_bytes += total_bytes;
6483 q_vector->tx.total_packets += total_packets;
6484
6485 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
6486 struct e1000_hw *hw = &adapter->hw;
6487
6488 /* Detect a transmit hang in hardware, this serializes the
6489 * check with the clearing of time_stamp and movement of i
6490 */
6491 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
6492 if (tx_buffer->next_to_watch &&
6493 time_after(jiffies, tx_buffer->time_stamp +
6494 (adapter->tx_timeout_factor * HZ)) &&
6495 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
6496
6497 /* detected Tx unit hang */
6498 dev_err(tx_ring->dev,
6499 "Detected Tx Unit Hang\n"
6500 " Tx Queue <%d>\n"
6501 " TDH <%x>\n"
6502 " TDT <%x>\n"
6503 " next_to_use <%x>\n"
6504 " next_to_clean <%x>\n"
6505 "buffer_info[next_to_clean]\n"
6506 " time_stamp <%lx>\n"
6507 " next_to_watch <%p>\n"
6508 " jiffies <%lx>\n"
6509 " desc.status <%x>\n",
6510 tx_ring->queue_index,
6511 rd32(E1000_TDH(tx_ring->reg_idx)),
6512 readl(tx_ring->tail),
6513 tx_ring->next_to_use,
6514 tx_ring->next_to_clean,
6515 tx_buffer->time_stamp,
6516 tx_buffer->next_to_watch,
6517 jiffies,
6518 tx_buffer->next_to_watch->wb.status);
6519 netif_stop_subqueue(tx_ring->netdev,
6520 tx_ring->queue_index);
6521
6522 /* we are about to reset, no point in enabling stuff */
6523 return true;
6524 }
6525 }
6526
6527#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6528 if (unlikely(total_packets &&
6529 netif_carrier_ok(tx_ring->netdev) &&
6530 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
6531 /* Make sure that anybody stopping the queue after this
6532 * sees the new next_to_clean.
6533 */
6534 smp_mb();
6535 if (__netif_subqueue_stopped(tx_ring->netdev,
6536 tx_ring->queue_index) &&
6537 !(test_bit(__IGB_DOWN, &adapter->state))) {
6538 netif_wake_subqueue(tx_ring->netdev,
6539 tx_ring->queue_index);
6540
6541 u64_stats_update_begin(&tx_ring->tx_syncp);
6542 tx_ring->tx_stats.restart_queue++;
6543 u64_stats_update_end(&tx_ring->tx_syncp);
6544 }
6545 }
6546
6547 return !!budget;
6548}
6549
6550/**
6551 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6552 * @rx_ring: rx descriptor ring to store buffers on
6553 * @old_buff: donor buffer to have page reused
6554 *
6555 * Synchronizes page for reuse by the adapter
6556 **/
6557static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6558 struct igb_rx_buffer *old_buff)
6559{
6560 struct igb_rx_buffer *new_buff;
6561 u16 nta = rx_ring->next_to_alloc;
6562
6563 new_buff = &rx_ring->rx_buffer_info[nta];
6564
6565 /* update, and store next to alloc */
6566 nta++;
6567 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6568
6569 /* transfer page from old buffer to new buffer */
6570 *new_buff = *old_buff;
6571
6572 /* sync the buffer for use by the device */
6573 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6574 old_buff->page_offset,
6575 IGB_RX_BUFSZ,
6576 DMA_FROM_DEVICE);
6577}
6578
6579static inline bool igb_page_is_reserved(struct page *page)
6580{
6581 return (page_to_nid(page) != numa_mem_id()) || page->pfmemalloc;
6582}
6583
6584static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6585 struct page *page,
6586 unsigned int truesize)
6587{
6588 /* avoid re-using remote pages */
6589 if (unlikely(igb_page_is_reserved(page)))
6590 return false;
6591
6592#if (PAGE_SIZE < 8192)
6593 /* if we are only owner of page we can reuse it */
6594 if (unlikely(page_count(page) != 1))
6595 return false;
6596
6597 /* flip page offset to other buffer */
6598 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6599#else
6600 /* move offset up to the next cache line */
6601 rx_buffer->page_offset += truesize;
6602
6603 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6604 return false;
6605#endif
6606
6607 /* Even if we own the page, we are not allowed to use atomic_set()
6608 * This would break get_page_unless_zero() users.
6609 */
6610 atomic_inc(&page->_count);
6611
6612 return true;
6613}
6614
6615/**
6616 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6617 * @rx_ring: rx descriptor ring to transact packets on
6618 * @rx_buffer: buffer containing page to add
6619 * @rx_desc: descriptor containing length of buffer written by hardware
6620 * @skb: sk_buff to place the data into
6621 *
6622 * This function will add the data contained in rx_buffer->page to the skb.
6623 * This is done either through a direct copy if the data in the buffer is
6624 * less than the skb header size, otherwise it will just attach the page as
6625 * a frag to the skb.
6626 *
6627 * The function will then update the page offset if necessary and return
6628 * true if the buffer can be reused by the adapter.
6629 **/
6630static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6631 struct igb_rx_buffer *rx_buffer,
6632 union e1000_adv_rx_desc *rx_desc,
6633 struct sk_buff *skb)
6634{
6635 struct page *page = rx_buffer->page;
6636 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6637 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6638#if (PAGE_SIZE < 8192)
6639 unsigned int truesize = IGB_RX_BUFSZ;
6640#else
6641 unsigned int truesize = SKB_DATA_ALIGN(size);
6642#endif
6643 unsigned int pull_len;
6644
6645 if (unlikely(skb_is_nonlinear(skb)))
6646 goto add_tail_frag;
6647
6648 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
6649 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6650 va += IGB_TS_HDR_LEN;
6651 size -= IGB_TS_HDR_LEN;
6652 }
6653
6654 if (likely(size <= IGB_RX_HDR_LEN)) {
6655 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6656
6657 /* page is not reserved, we can reuse buffer as-is */
6658 if (likely(!igb_page_is_reserved(page)))
6659 return true;
6660
6661 /* this page cannot be reused so discard it */
6662 __free_page(page);
6663 return false;
6664 }
6665
6666 /* we need the header to contain the greater of either ETH_HLEN or
6667 * 60 bytes if the skb->len is less than 60 for skb_pad.
6668 */
6669 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6670
6671 /* align pull length to size of long to optimize memcpy performance */
6672 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long)));
6673
6674 /* update all of the pointers */
6675 va += pull_len;
6676 size -= pull_len;
6677
6678add_tail_frag:
6679 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6680 (unsigned long)va & ~PAGE_MASK, size, truesize);
6681
6682 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6683}
6684
6685static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6686 union e1000_adv_rx_desc *rx_desc,
6687 struct sk_buff *skb)
6688{
6689 struct igb_rx_buffer *rx_buffer;
6690 struct page *page;
6691
6692 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6693 page = rx_buffer->page;
6694 prefetchw(page);
6695
6696 if (likely(!skb)) {
6697 void *page_addr = page_address(page) +
6698 rx_buffer->page_offset;
6699
6700 /* prefetch first cache line of first page */
6701 prefetch(page_addr);
6702#if L1_CACHE_BYTES < 128
6703 prefetch(page_addr + L1_CACHE_BYTES);
6704#endif
6705
6706 /* allocate a skb to store the frags */
6707 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
6708 if (unlikely(!skb)) {
6709 rx_ring->rx_stats.alloc_failed++;
6710 return NULL;
6711 }
6712
6713 /* we will be copying header into skb->data in
6714 * pskb_may_pull so it is in our interest to prefetch
6715 * it now to avoid a possible cache miss
6716 */
6717 prefetchw(skb->data);
6718 }
6719
6720 /* we are reusing so sync this buffer for CPU use */
6721 dma_sync_single_range_for_cpu(rx_ring->dev,
6722 rx_buffer->dma,
6723 rx_buffer->page_offset,
6724 IGB_RX_BUFSZ,
6725 DMA_FROM_DEVICE);
6726
6727 /* pull page into skb */
6728 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6729 /* hand second half of page back to the ring */
6730 igb_reuse_rx_page(rx_ring, rx_buffer);
6731 } else {
6732 /* we are not reusing the buffer so unmap it */
6733 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6734 PAGE_SIZE, DMA_FROM_DEVICE);
6735 }
6736
6737 /* clear contents of rx_buffer */
6738 rx_buffer->page = NULL;
6739
6740 return skb;
6741}
6742
6743static inline void igb_rx_checksum(struct igb_ring *ring,
6744 union e1000_adv_rx_desc *rx_desc,
6745 struct sk_buff *skb)
6746{
6747 skb_checksum_none_assert(skb);
6748
6749 /* Ignore Checksum bit is set */
6750 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6751 return;
6752
6753 /* Rx checksum disabled via ethtool */
6754 if (!(ring->netdev->features & NETIF_F_RXCSUM))
6755 return;
6756
6757 /* TCP/UDP checksum error bit is set */
6758 if (igb_test_staterr(rx_desc,
6759 E1000_RXDEXT_STATERR_TCPE |
6760 E1000_RXDEXT_STATERR_IPE)) {
6761 /* work around errata with sctp packets where the TCPE aka
6762 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6763 * packets, (aka let the stack check the crc32c)
6764 */
6765 if (!((skb->len == 60) &&
6766 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6767 u64_stats_update_begin(&ring->rx_syncp);
6768 ring->rx_stats.csum_err++;
6769 u64_stats_update_end(&ring->rx_syncp);
6770 }
6771 /* let the stack verify checksum errors */
6772 return;
6773 }
6774 /* It must be a TCP or UDP packet with a valid checksum */
6775 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6776 E1000_RXD_STAT_UDPCS))
6777 skb->ip_summed = CHECKSUM_UNNECESSARY;
6778
6779 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6780 le32_to_cpu(rx_desc->wb.upper.status_error));
6781}
6782
6783static inline void igb_rx_hash(struct igb_ring *ring,
6784 union e1000_adv_rx_desc *rx_desc,
6785 struct sk_buff *skb)
6786{
6787 if (ring->netdev->features & NETIF_F_RXHASH)
6788 skb_set_hash(skb,
6789 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6790 PKT_HASH_TYPE_L3);
6791}
6792
6793/**
6794 * igb_is_non_eop - process handling of non-EOP buffers
6795 * @rx_ring: Rx ring being processed
6796 * @rx_desc: Rx descriptor for current buffer
6797 * @skb: current socket buffer containing buffer in progress
6798 *
6799 * This function updates next to clean. If the buffer is an EOP buffer
6800 * this function exits returning false, otherwise it will place the
6801 * sk_buff in the next buffer to be chained and return true indicating
6802 * that this is in fact a non-EOP buffer.
6803 **/
6804static bool igb_is_non_eop(struct igb_ring *rx_ring,
6805 union e1000_adv_rx_desc *rx_desc)
6806{
6807 u32 ntc = rx_ring->next_to_clean + 1;
6808
6809 /* fetch, update, and store next to clean */
6810 ntc = (ntc < rx_ring->count) ? ntc : 0;
6811 rx_ring->next_to_clean = ntc;
6812
6813 prefetch(IGB_RX_DESC(rx_ring, ntc));
6814
6815 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6816 return false;
6817
6818 return true;
6819}
6820
6821/**
6822 * igb_cleanup_headers - Correct corrupted or empty headers
6823 * @rx_ring: rx descriptor ring packet is being transacted on
6824 * @rx_desc: pointer to the EOP Rx descriptor
6825 * @skb: pointer to current skb being fixed
6826 *
6827 * Address the case where we are pulling data in on pages only
6828 * and as such no data is present in the skb header.
6829 *
6830 * In addition if skb is not at least 60 bytes we need to pad it so that
6831 * it is large enough to qualify as a valid Ethernet frame.
6832 *
6833 * Returns true if an error was encountered and skb was freed.
6834 **/
6835static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6836 union e1000_adv_rx_desc *rx_desc,
6837 struct sk_buff *skb)
6838{
6839 if (unlikely((igb_test_staterr(rx_desc,
6840 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6841 struct net_device *netdev = rx_ring->netdev;
6842 if (!(netdev->features & NETIF_F_RXALL)) {
6843 dev_kfree_skb_any(skb);
6844 return true;
6845 }
6846 }
6847
6848 /* if eth_skb_pad returns an error the skb was freed */
6849 if (eth_skb_pad(skb))
6850 return true;
6851
6852 return false;
6853}
6854
6855/**
6856 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6857 * @rx_ring: rx descriptor ring packet is being transacted on
6858 * @rx_desc: pointer to the EOP Rx descriptor
6859 * @skb: pointer to current skb being populated
6860 *
6861 * This function checks the ring, descriptor, and packet information in
6862 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6863 * other fields within the skb.
6864 **/
6865static void igb_process_skb_fields(struct igb_ring *rx_ring,
6866 union e1000_adv_rx_desc *rx_desc,
6867 struct sk_buff *skb)
6868{
6869 struct net_device *dev = rx_ring->netdev;
6870
6871 igb_rx_hash(rx_ring, rx_desc, skb);
6872
6873 igb_rx_checksum(rx_ring, rx_desc, skb);
6874
6875 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6876 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6877 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
6878
6879 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
6880 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6881 u16 vid;
6882
6883 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6884 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6885 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6886 else
6887 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6888
6889 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
6890 }
6891
6892 skb_record_rx_queue(skb, rx_ring->queue_index);
6893
6894 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6895}
6896
6897static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6898{
6899 struct igb_ring *rx_ring = q_vector->rx.ring;
6900 struct sk_buff *skb = rx_ring->skb;
6901 unsigned int total_bytes = 0, total_packets = 0;
6902 u16 cleaned_count = igb_desc_unused(rx_ring);
6903
6904 while (likely(total_packets < budget)) {
6905 union e1000_adv_rx_desc *rx_desc;
6906
6907 /* return some buffers to hardware, one at a time is too slow */
6908 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6909 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6910 cleaned_count = 0;
6911 }
6912
6913 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6914
6915 if (!rx_desc->wb.upper.status_error)
6916 break;
6917
6918 /* This memory barrier is needed to keep us from reading
6919 * any other fields out of the rx_desc until we know the
6920 * descriptor has been written back
6921 */
6922 dma_rmb();
6923
6924 /* retrieve a buffer from the ring */
6925 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6926
6927 /* exit if we failed to retrieve a buffer */
6928 if (!skb)
6929 break;
6930
6931 cleaned_count++;
6932
6933 /* fetch next buffer in frame if non-eop */
6934 if (igb_is_non_eop(rx_ring, rx_desc))
6935 continue;
6936
6937 /* verify the packet layout is correct */
6938 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6939 skb = NULL;
6940 continue;
6941 }
6942
6943 /* probably a little skewed due to removing CRC */
6944 total_bytes += skb->len;
6945
6946 /* populate checksum, timestamp, VLAN, and protocol */
6947 igb_process_skb_fields(rx_ring, rx_desc, skb);
6948
6949 napi_gro_receive(&q_vector->napi, skb);
6950
6951 /* reset skb pointer */
6952 skb = NULL;
6953
6954 /* update budget accounting */
6955 total_packets++;
6956 }
6957
6958 /* place incomplete frames back on ring for completion */
6959 rx_ring->skb = skb;
6960
6961 u64_stats_update_begin(&rx_ring->rx_syncp);
6962 rx_ring->rx_stats.packets += total_packets;
6963 rx_ring->rx_stats.bytes += total_bytes;
6964 u64_stats_update_end(&rx_ring->rx_syncp);
6965 q_vector->rx.total_packets += total_packets;
6966 q_vector->rx.total_bytes += total_bytes;
6967
6968 if (cleaned_count)
6969 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6970
6971 return total_packets < budget;
6972}
6973
6974static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
6975 struct igb_rx_buffer *bi)
6976{
6977 struct page *page = bi->page;
6978 dma_addr_t dma;
6979
6980 /* since we are recycling buffers we should seldom need to alloc */
6981 if (likely(page))
6982 return true;
6983
6984 /* alloc new page for storage */
6985 page = dev_alloc_page();
6986 if (unlikely(!page)) {
6987 rx_ring->rx_stats.alloc_failed++;
6988 return false;
6989 }
6990
6991 /* map page for use */
6992 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
6993
6994 /* if mapping failed free memory back to system since
6995 * there isn't much point in holding memory we can't use
6996 */
6997 if (dma_mapping_error(rx_ring->dev, dma)) {
6998 __free_page(page);
6999
7000 rx_ring->rx_stats.alloc_failed++;
7001 return false;
7002 }
7003
7004 bi->dma = dma;
7005 bi->page = page;
7006 bi->page_offset = 0;
7007
7008 return true;
7009}
7010
7011/**
7012 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7013 * @adapter: address of board private structure
7014 **/
7015void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
7016{
7017 union e1000_adv_rx_desc *rx_desc;
7018 struct igb_rx_buffer *bi;
7019 u16 i = rx_ring->next_to_use;
7020
7021 /* nothing to do */
7022 if (!cleaned_count)
7023 return;
7024
7025 rx_desc = IGB_RX_DESC(rx_ring, i);
7026 bi = &rx_ring->rx_buffer_info[i];
7027 i -= rx_ring->count;
7028
7029 do {
7030 if (!igb_alloc_mapped_page(rx_ring, bi))
7031 break;
7032
7033 /* Refresh the desc even if buffer_addrs didn't change
7034 * because each write-back erases this info.
7035 */
7036 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
7037
7038 rx_desc++;
7039 bi++;
7040 i++;
7041 if (unlikely(!i)) {
7042 rx_desc = IGB_RX_DESC(rx_ring, 0);
7043 bi = rx_ring->rx_buffer_info;
7044 i -= rx_ring->count;
7045 }
7046
7047 /* clear the status bits for the next_to_use descriptor */
7048 rx_desc->wb.upper.status_error = 0;
7049
7050 cleaned_count--;
7051 } while (cleaned_count);
7052
7053 i += rx_ring->count;
7054
7055 if (rx_ring->next_to_use != i) {
7056 /* record the next descriptor to use */
7057 rx_ring->next_to_use = i;
7058
7059 /* update next to alloc since we have filled the ring */
7060 rx_ring->next_to_alloc = i;
7061
7062 /* Force memory writes to complete before letting h/w
7063 * know there are new descriptors to fetch. (Only
7064 * applicable for weak-ordered memory model archs,
7065 * such as IA-64).
7066 */
7067 wmb();
7068 writel(i, rx_ring->tail);
7069 }
7070}
7071
7072/**
7073 * igb_mii_ioctl -
7074 * @netdev:
7075 * @ifreq:
7076 * @cmd:
7077 **/
7078static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7079{
7080 struct igb_adapter *adapter = netdev_priv(netdev);
7081 struct mii_ioctl_data *data = if_mii(ifr);
7082
7083 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7084 return -EOPNOTSUPP;
7085
7086 switch (cmd) {
7087 case SIOCGMIIPHY:
7088 data->phy_id = adapter->hw.phy.addr;
7089 break;
7090 case SIOCGMIIREG:
7091 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
7092 &data->val_out))
7093 return -EIO;
7094 break;
7095 case SIOCSMIIREG:
7096 default:
7097 return -EOPNOTSUPP;
7098 }
7099 return 0;
7100}
7101
7102/**
7103 * igb_ioctl -
7104 * @netdev:
7105 * @ifreq:
7106 * @cmd:
7107 **/
7108static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7109{
7110 switch (cmd) {
7111 case SIOCGMIIPHY:
7112 case SIOCGMIIREG:
7113 case SIOCSMIIREG:
7114 return igb_mii_ioctl(netdev, ifr, cmd);
7115 case SIOCGHWTSTAMP:
7116 return igb_ptp_get_ts_config(netdev, ifr);
7117 case SIOCSHWTSTAMP:
7118 return igb_ptp_set_ts_config(netdev, ifr);
7119 default:
7120 return -EOPNOTSUPP;
7121 }
7122}
7123
7124void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7125{
7126 struct igb_adapter *adapter = hw->back;
7127
7128 pci_read_config_word(adapter->pdev, reg, value);
7129}
7130
7131void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7132{
7133 struct igb_adapter *adapter = hw->back;
7134
7135 pci_write_config_word(adapter->pdev, reg, *value);
7136}
7137
7138s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7139{
7140 struct igb_adapter *adapter = hw->back;
7141
7142 if (pcie_capability_read_word(adapter->pdev, reg, value))
7143 return -E1000_ERR_CONFIG;
7144
7145 return 0;
7146}
7147
7148s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7149{
7150 struct igb_adapter *adapter = hw->back;
7151
7152 if (pcie_capability_write_word(adapter->pdev, reg, *value))
7153 return -E1000_ERR_CONFIG;
7154
7155 return 0;
7156}
7157
7158static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
7159{
7160 struct igb_adapter *adapter = netdev_priv(netdev);
7161 struct e1000_hw *hw = &adapter->hw;
7162 u32 ctrl, rctl;
7163 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
7164
7165 if (enable) {
7166 /* enable VLAN tag insert/strip */
7167 ctrl = rd32(E1000_CTRL);
7168 ctrl |= E1000_CTRL_VME;
7169 wr32(E1000_CTRL, ctrl);
7170
7171 /* Disable CFI check */
7172 rctl = rd32(E1000_RCTL);
7173 rctl &= ~E1000_RCTL_CFIEN;
7174 wr32(E1000_RCTL, rctl);
7175 } else {
7176 /* disable VLAN tag insert/strip */
7177 ctrl = rd32(E1000_CTRL);
7178 ctrl &= ~E1000_CTRL_VME;
7179 wr32(E1000_CTRL, ctrl);
7180 }
7181
7182 igb_rlpml_set(adapter);
7183}
7184
7185static int igb_vlan_rx_add_vid(struct net_device *netdev,
7186 __be16 proto, u16 vid)
7187{
7188 struct igb_adapter *adapter = netdev_priv(netdev);
7189 struct e1000_hw *hw = &adapter->hw;
7190 int pf_id = adapter->vfs_allocated_count;
7191
7192 /* attempt to add filter to vlvf array */
7193 igb_vlvf_set(adapter, vid, true, pf_id);
7194
7195 /* add the filter since PF can receive vlans w/o entry in vlvf */
7196 igb_vfta_set(hw, vid, true);
7197
7198 set_bit(vid, adapter->active_vlans);
7199
7200 return 0;
7201}
7202
7203static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7204 __be16 proto, u16 vid)
7205{
7206 struct igb_adapter *adapter = netdev_priv(netdev);
7207 struct e1000_hw *hw = &adapter->hw;
7208 int pf_id = adapter->vfs_allocated_count;
7209 s32 err;
7210
7211 /* remove vlan from VLVF table array */
7212 err = igb_vlvf_set(adapter, vid, false, pf_id);
7213
7214 /* if vid was not present in VLVF just remove it from table */
7215 if (err)
7216 igb_vfta_set(hw, vid, false);
7217
7218 clear_bit(vid, adapter->active_vlans);
7219
7220 return 0;
7221}
7222
7223static void igb_restore_vlan(struct igb_adapter *adapter)
7224{
7225 u16 vid;
7226
7227 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7228
7229 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
7230 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
7231}
7232
7233int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
7234{
7235 struct pci_dev *pdev = adapter->pdev;
7236 struct e1000_mac_info *mac = &adapter->hw.mac;
7237
7238 mac->autoneg = 0;
7239
7240 /* Make sure dplx is at most 1 bit and lsb of speed is not set
7241 * for the switch() below to work
7242 */
7243 if ((spd & 1) || (dplx & ~1))
7244 goto err_inval;
7245
7246 /* Fiber NIC's only allow 1000 gbps Full duplex
7247 * and 100Mbps Full duplex for 100baseFx sfp
7248 */
7249 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7250 switch (spd + dplx) {
7251 case SPEED_10 + DUPLEX_HALF:
7252 case SPEED_10 + DUPLEX_FULL:
7253 case SPEED_100 + DUPLEX_HALF:
7254 goto err_inval;
7255 default:
7256 break;
7257 }
7258 }
7259
7260 switch (spd + dplx) {
7261 case SPEED_10 + DUPLEX_HALF:
7262 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7263 break;
7264 case SPEED_10 + DUPLEX_FULL:
7265 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7266 break;
7267 case SPEED_100 + DUPLEX_HALF:
7268 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7269 break;
7270 case SPEED_100 + DUPLEX_FULL:
7271 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7272 break;
7273 case SPEED_1000 + DUPLEX_FULL:
7274 mac->autoneg = 1;
7275 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7276 break;
7277 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7278 default:
7279 goto err_inval;
7280 }
7281
7282 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7283 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7284
7285 return 0;
7286
7287err_inval:
7288 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7289 return -EINVAL;
7290}
7291
7292static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7293 bool runtime)
7294{
7295 struct net_device *netdev = pci_get_drvdata(pdev);
7296 struct igb_adapter *adapter = netdev_priv(netdev);
7297 struct e1000_hw *hw = &adapter->hw;
7298 u32 ctrl, rctl, status;
7299 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
7300#ifdef CONFIG_PM
7301 int retval = 0;
7302#endif
7303
7304 netif_device_detach(netdev);
7305
7306 if (netif_running(netdev))
7307 __igb_close(netdev, true);
7308
7309 igb_clear_interrupt_scheme(adapter);
7310
7311#ifdef CONFIG_PM
7312 retval = pci_save_state(pdev);
7313 if (retval)
7314 return retval;
7315#endif
7316
7317 status = rd32(E1000_STATUS);
7318 if (status & E1000_STATUS_LU)
7319 wufc &= ~E1000_WUFC_LNKC;
7320
7321 if (wufc) {
7322 igb_setup_rctl(adapter);
7323 igb_set_rx_mode(netdev);
7324
7325 /* turn on all-multi mode if wake on multicast is enabled */
7326 if (wufc & E1000_WUFC_MC) {
7327 rctl = rd32(E1000_RCTL);
7328 rctl |= E1000_RCTL_MPE;
7329 wr32(E1000_RCTL, rctl);
7330 }
7331
7332 ctrl = rd32(E1000_CTRL);
7333 /* advertise wake from D3Cold */
7334 #define E1000_CTRL_ADVD3WUC 0x00100000
7335 /* phy power management enable */
7336 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7337 ctrl |= E1000_CTRL_ADVD3WUC;
7338 wr32(E1000_CTRL, ctrl);
7339
7340 /* Allow time for pending master requests to run */
7341 igb_disable_pcie_master(hw);
7342
7343 wr32(E1000_WUC, E1000_WUC_PME_EN);
7344 wr32(E1000_WUFC, wufc);
7345 } else {
7346 wr32(E1000_WUC, 0);
7347 wr32(E1000_WUFC, 0);
7348 }
7349
7350 *enable_wake = wufc || adapter->en_mng_pt;
7351 if (!*enable_wake)
7352 igb_power_down_link(adapter);
7353 else
7354 igb_power_up_link(adapter);
7355
7356 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7357 * would have already happened in close and is redundant.
7358 */
7359 igb_release_hw_control(adapter);
7360
7361 pci_disable_device(pdev);
7362
7363 return 0;
7364}
7365
7366#ifdef CONFIG_PM
7367#ifdef CONFIG_PM_SLEEP
7368static int igb_suspend(struct device *dev)
7369{
7370 int retval;
7371 bool wake;
7372 struct pci_dev *pdev = to_pci_dev(dev);
7373
7374 retval = __igb_shutdown(pdev, &wake, 0);
7375 if (retval)
7376 return retval;
7377
7378 if (wake) {
7379 pci_prepare_to_sleep(pdev);
7380 } else {
7381 pci_wake_from_d3(pdev, false);
7382 pci_set_power_state(pdev, PCI_D3hot);
7383 }
7384
7385 return 0;
7386}
7387#endif /* CONFIG_PM_SLEEP */
7388
7389static int igb_resume(struct device *dev)
7390{
7391 struct pci_dev *pdev = to_pci_dev(dev);
7392 struct net_device *netdev = pci_get_drvdata(pdev);
7393 struct igb_adapter *adapter = netdev_priv(netdev);
7394 struct e1000_hw *hw = &adapter->hw;
7395 u32 err;
7396
7397 pci_set_power_state(pdev, PCI_D0);
7398 pci_restore_state(pdev);
7399 pci_save_state(pdev);
7400
7401 if (!pci_device_is_present(pdev))
7402 return -ENODEV;
7403 err = pci_enable_device_mem(pdev);
7404 if (err) {
7405 dev_err(&pdev->dev,
7406 "igb: Cannot enable PCI device from suspend\n");
7407 return err;
7408 }
7409 pci_set_master(pdev);
7410
7411 pci_enable_wake(pdev, PCI_D3hot, 0);
7412 pci_enable_wake(pdev, PCI_D3cold, 0);
7413
7414 if (igb_init_interrupt_scheme(adapter, true)) {
7415 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7416 return -ENOMEM;
7417 }
7418
7419 igb_reset(adapter);
7420
7421 /* let the f/w know that the h/w is now under the control of the
7422 * driver.
7423 */
7424 igb_get_hw_control(adapter);
7425
7426 wr32(E1000_WUS, ~0);
7427
7428 if (netdev->flags & IFF_UP) {
7429 rtnl_lock();
7430 err = __igb_open(netdev, true);
7431 rtnl_unlock();
7432 if (err)
7433 return err;
7434 }
7435
7436 netif_device_attach(netdev);
7437 return 0;
7438}
7439
7440static int igb_runtime_idle(struct device *dev)
7441{
7442 struct pci_dev *pdev = to_pci_dev(dev);
7443 struct net_device *netdev = pci_get_drvdata(pdev);
7444 struct igb_adapter *adapter = netdev_priv(netdev);
7445
7446 if (!igb_has_link(adapter))
7447 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7448
7449 return -EBUSY;
7450}
7451
7452static int igb_runtime_suspend(struct device *dev)
7453{
7454 struct pci_dev *pdev = to_pci_dev(dev);
7455 int retval;
7456 bool wake;
7457
7458 retval = __igb_shutdown(pdev, &wake, 1);
7459 if (retval)
7460 return retval;
7461
7462 if (wake) {
7463 pci_prepare_to_sleep(pdev);
7464 } else {
7465 pci_wake_from_d3(pdev, false);
7466 pci_set_power_state(pdev, PCI_D3hot);
7467 }
7468
7469 return 0;
7470}
7471
7472static int igb_runtime_resume(struct device *dev)
7473{
7474 return igb_resume(dev);
7475}
7476#endif /* CONFIG_PM */
7477
7478static void igb_shutdown(struct pci_dev *pdev)
7479{
7480 bool wake;
7481
7482 __igb_shutdown(pdev, &wake, 0);
7483
7484 if (system_state == SYSTEM_POWER_OFF) {
7485 pci_wake_from_d3(pdev, wake);
7486 pci_set_power_state(pdev, PCI_D3hot);
7487 }
7488}
7489
7490#ifdef CONFIG_PCI_IOV
7491static int igb_sriov_reinit(struct pci_dev *dev)
7492{
7493 struct net_device *netdev = pci_get_drvdata(dev);
7494 struct igb_adapter *adapter = netdev_priv(netdev);
7495 struct pci_dev *pdev = adapter->pdev;
7496
7497 rtnl_lock();
7498
7499 if (netif_running(netdev))
7500 igb_close(netdev);
7501 else
7502 igb_reset(adapter);
7503
7504 igb_clear_interrupt_scheme(adapter);
7505
7506 igb_init_queue_configuration(adapter);
7507
7508 if (igb_init_interrupt_scheme(adapter, true)) {
7509 rtnl_unlock();
7510 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7511 return -ENOMEM;
7512 }
7513
7514 if (netif_running(netdev))
7515 igb_open(netdev);
7516
7517 rtnl_unlock();
7518
7519 return 0;
7520}
7521
7522static int igb_pci_disable_sriov(struct pci_dev *dev)
7523{
7524 int err = igb_disable_sriov(dev);
7525
7526 if (!err)
7527 err = igb_sriov_reinit(dev);
7528
7529 return err;
7530}
7531
7532static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7533{
7534 int err = igb_enable_sriov(dev, num_vfs);
7535
7536 if (err)
7537 goto out;
7538
7539 err = igb_sriov_reinit(dev);
7540 if (!err)
7541 return num_vfs;
7542
7543out:
7544 return err;
7545}
7546
7547#endif
7548static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7549{
7550#ifdef CONFIG_PCI_IOV
7551 if (num_vfs == 0)
7552 return igb_pci_disable_sriov(dev);
7553 else
7554 return igb_pci_enable_sriov(dev, num_vfs);
7555#endif
7556 return 0;
7557}
7558
7559#ifdef CONFIG_NET_POLL_CONTROLLER
7560/* Polling 'interrupt' - used by things like netconsole to send skbs
7561 * without having to re-enable interrupts. It's not called while
7562 * the interrupt routine is executing.
7563 */
7564static void igb_netpoll(struct net_device *netdev)
7565{
7566 struct igb_adapter *adapter = netdev_priv(netdev);
7567 struct e1000_hw *hw = &adapter->hw;
7568 struct igb_q_vector *q_vector;
7569 int i;
7570
7571 for (i = 0; i < adapter->num_q_vectors; i++) {
7572 q_vector = adapter->q_vector[i];
7573 if (adapter->flags & IGB_FLAG_HAS_MSIX)
7574 wr32(E1000_EIMC, q_vector->eims_value);
7575 else
7576 igb_irq_disable(adapter);
7577 napi_schedule(&q_vector->napi);
7578 }
7579}
7580#endif /* CONFIG_NET_POLL_CONTROLLER */
7581
7582/**
7583 * igb_io_error_detected - called when PCI error is detected
7584 * @pdev: Pointer to PCI device
7585 * @state: The current pci connection state
7586 *
7587 * This function is called after a PCI bus error affecting
7588 * this device has been detected.
7589 **/
7590static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7591 pci_channel_state_t state)
7592{
7593 struct net_device *netdev = pci_get_drvdata(pdev);
7594 struct igb_adapter *adapter = netdev_priv(netdev);
7595
7596 netif_device_detach(netdev);
7597
7598 if (state == pci_channel_io_perm_failure)
7599 return PCI_ERS_RESULT_DISCONNECT;
7600
7601 if (netif_running(netdev))
7602 igb_down(adapter);
7603 pci_disable_device(pdev);
7604
7605 /* Request a slot slot reset. */
7606 return PCI_ERS_RESULT_NEED_RESET;
7607}
7608
7609/**
7610 * igb_io_slot_reset - called after the pci bus has been reset.
7611 * @pdev: Pointer to PCI device
7612 *
7613 * Restart the card from scratch, as if from a cold-boot. Implementation
7614 * resembles the first-half of the igb_resume routine.
7615 **/
7616static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7617{
7618 struct net_device *netdev = pci_get_drvdata(pdev);
7619 struct igb_adapter *adapter = netdev_priv(netdev);
7620 struct e1000_hw *hw = &adapter->hw;
7621 pci_ers_result_t result;
7622 int err;
7623
7624 if (pci_enable_device_mem(pdev)) {
7625 dev_err(&pdev->dev,
7626 "Cannot re-enable PCI device after reset.\n");
7627 result = PCI_ERS_RESULT_DISCONNECT;
7628 } else {
7629 pci_set_master(pdev);
7630 pci_restore_state(pdev);
7631 pci_save_state(pdev);
7632
7633 pci_enable_wake(pdev, PCI_D3hot, 0);
7634 pci_enable_wake(pdev, PCI_D3cold, 0);
7635
7636 igb_reset(adapter);
7637 wr32(E1000_WUS, ~0);
7638 result = PCI_ERS_RESULT_RECOVERED;
7639 }
7640
7641 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7642 if (err) {
7643 dev_err(&pdev->dev,
7644 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7645 err);
7646 /* non-fatal, continue */
7647 }
7648
7649 return result;
7650}
7651
7652/**
7653 * igb_io_resume - called when traffic can start flowing again.
7654 * @pdev: Pointer to PCI device
7655 *
7656 * This callback is called when the error recovery driver tells us that
7657 * its OK to resume normal operation. Implementation resembles the
7658 * second-half of the igb_resume routine.
7659 */
7660static void igb_io_resume(struct pci_dev *pdev)
7661{
7662 struct net_device *netdev = pci_get_drvdata(pdev);
7663 struct igb_adapter *adapter = netdev_priv(netdev);
7664
7665 if (netif_running(netdev)) {
7666 if (igb_up(adapter)) {
7667 dev_err(&pdev->dev, "igb_up failed after reset\n");
7668 return;
7669 }
7670 }
7671
7672 netif_device_attach(netdev);
7673
7674 /* let the f/w know that the h/w is now under the control of the
7675 * driver.
7676 */
7677 igb_get_hw_control(adapter);
7678}
7679
7680static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7681 u8 qsel)
7682{
7683 u32 rar_low, rar_high;
7684 struct e1000_hw *hw = &adapter->hw;
7685
7686 /* HW expects these in little endian so we reverse the byte order
7687 * from network order (big endian) to little endian
7688 */
7689 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7690 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7691 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7692
7693 /* Indicate to hardware the Address is Valid. */
7694 rar_high |= E1000_RAH_AV;
7695
7696 if (hw->mac.type == e1000_82575)
7697 rar_high |= E1000_RAH_POOL_1 * qsel;
7698 else
7699 rar_high |= E1000_RAH_POOL_1 << qsel;
7700
7701 wr32(E1000_RAL(index), rar_low);
7702 wrfl();
7703 wr32(E1000_RAH(index), rar_high);
7704 wrfl();
7705}
7706
7707static int igb_set_vf_mac(struct igb_adapter *adapter,
7708 int vf, unsigned char *mac_addr)
7709{
7710 struct e1000_hw *hw = &adapter->hw;
7711 /* VF MAC addresses start at end of receive addresses and moves
7712 * towards the first, as a result a collision should not be possible
7713 */
7714 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7715
7716 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7717
7718 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7719
7720 return 0;
7721}
7722
7723static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7724{
7725 struct igb_adapter *adapter = netdev_priv(netdev);
7726 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7727 return -EINVAL;
7728 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7729 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7730 dev_info(&adapter->pdev->dev,
7731 "Reload the VF driver to make this change effective.");
7732 if (test_bit(__IGB_DOWN, &adapter->state)) {
7733 dev_warn(&adapter->pdev->dev,
7734 "The VF MAC address has been set, but the PF device is not up.\n");
7735 dev_warn(&adapter->pdev->dev,
7736 "Bring the PF device up before attempting to use the VF device.\n");
7737 }
7738 return igb_set_vf_mac(adapter, vf, mac);
7739}
7740
7741static int igb_link_mbps(int internal_link_speed)
7742{
7743 switch (internal_link_speed) {
7744 case SPEED_100:
7745 return 100;
7746 case SPEED_1000:
7747 return 1000;
7748 default:
7749 return 0;
7750 }
7751}
7752
7753static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7754 int link_speed)
7755{
7756 int rf_dec, rf_int;
7757 u32 bcnrc_val;
7758
7759 if (tx_rate != 0) {
7760 /* Calculate the rate factor values to set */
7761 rf_int = link_speed / tx_rate;
7762 rf_dec = (link_speed - (rf_int * tx_rate));
7763 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7764 tx_rate;
7765
7766 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7767 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7768 E1000_RTTBCNRC_RF_INT_MASK);
7769 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7770 } else {
7771 bcnrc_val = 0;
7772 }
7773
7774 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7775 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7776 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7777 */
7778 wr32(E1000_RTTBCNRM, 0x14);
7779 wr32(E1000_RTTBCNRC, bcnrc_val);
7780}
7781
7782static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7783{
7784 int actual_link_speed, i;
7785 bool reset_rate = false;
7786
7787 /* VF TX rate limit was not set or not supported */
7788 if ((adapter->vf_rate_link_speed == 0) ||
7789 (adapter->hw.mac.type != e1000_82576))
7790 return;
7791
7792 actual_link_speed = igb_link_mbps(adapter->link_speed);
7793 if (actual_link_speed != adapter->vf_rate_link_speed) {
7794 reset_rate = true;
7795 adapter->vf_rate_link_speed = 0;
7796 dev_info(&adapter->pdev->dev,
7797 "Link speed has been changed. VF Transmit rate is disabled\n");
7798 }
7799
7800 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7801 if (reset_rate)
7802 adapter->vf_data[i].tx_rate = 0;
7803
7804 igb_set_vf_rate_limit(&adapter->hw, i,
7805 adapter->vf_data[i].tx_rate,
7806 actual_link_speed);
7807 }
7808}
7809
7810static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7811 int min_tx_rate, int max_tx_rate)
7812{
7813 struct igb_adapter *adapter = netdev_priv(netdev);
7814 struct e1000_hw *hw = &adapter->hw;
7815 int actual_link_speed;
7816
7817 if (hw->mac.type != e1000_82576)
7818 return -EOPNOTSUPP;
7819
7820 if (min_tx_rate)
7821 return -EINVAL;
7822
7823 actual_link_speed = igb_link_mbps(adapter->link_speed);
7824 if ((vf >= adapter->vfs_allocated_count) ||
7825 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7826 (max_tx_rate < 0) ||
7827 (max_tx_rate > actual_link_speed))
7828 return -EINVAL;
7829
7830 adapter->vf_rate_link_speed = actual_link_speed;
7831 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7832 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
7833
7834 return 0;
7835}
7836
7837static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7838 bool setting)
7839{
7840 struct igb_adapter *adapter = netdev_priv(netdev);
7841 struct e1000_hw *hw = &adapter->hw;
7842 u32 reg_val, reg_offset;
7843
7844 if (!adapter->vfs_allocated_count)
7845 return -EOPNOTSUPP;
7846
7847 if (vf >= adapter->vfs_allocated_count)
7848 return -EINVAL;
7849
7850 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7851 reg_val = rd32(reg_offset);
7852 if (setting)
7853 reg_val |= ((1 << vf) |
7854 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7855 else
7856 reg_val &= ~((1 << vf) |
7857 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7858 wr32(reg_offset, reg_val);
7859
7860 adapter->vf_data[vf].spoofchk_enabled = setting;
7861 return 0;
7862}
7863
7864static int igb_ndo_get_vf_config(struct net_device *netdev,
7865 int vf, struct ifla_vf_info *ivi)
7866{
7867 struct igb_adapter *adapter = netdev_priv(netdev);
7868 if (vf >= adapter->vfs_allocated_count)
7869 return -EINVAL;
7870 ivi->vf = vf;
7871 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7872 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
7873 ivi->min_tx_rate = 0;
7874 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7875 ivi->qos = adapter->vf_data[vf].pf_qos;
7876 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
7877 return 0;
7878}
7879
7880static void igb_vmm_control(struct igb_adapter *adapter)
7881{
7882 struct e1000_hw *hw = &adapter->hw;
7883 u32 reg;
7884
7885 switch (hw->mac.type) {
7886 case e1000_82575:
7887 case e1000_i210:
7888 case e1000_i211:
7889 case e1000_i354:
7890 default:
7891 /* replication is not supported for 82575 */
7892 return;
7893 case e1000_82576:
7894 /* notify HW that the MAC is adding vlan tags */
7895 reg = rd32(E1000_DTXCTL);
7896 reg |= E1000_DTXCTL_VLAN_ADDED;
7897 wr32(E1000_DTXCTL, reg);
7898 /* Fall through */
7899 case e1000_82580:
7900 /* enable replication vlan tag stripping */
7901 reg = rd32(E1000_RPLOLR);
7902 reg |= E1000_RPLOLR_STRVLAN;
7903 wr32(E1000_RPLOLR, reg);
7904 /* Fall through */
7905 case e1000_i350:
7906 /* none of the above registers are supported by i350 */
7907 break;
7908 }
7909
7910 if (adapter->vfs_allocated_count) {
7911 igb_vmdq_set_loopback_pf(hw, true);
7912 igb_vmdq_set_replication_pf(hw, true);
7913 igb_vmdq_set_anti_spoofing_pf(hw, true,
7914 adapter->vfs_allocated_count);
7915 } else {
7916 igb_vmdq_set_loopback_pf(hw, false);
7917 igb_vmdq_set_replication_pf(hw, false);
7918 }
7919}
7920
7921static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7922{
7923 struct e1000_hw *hw = &adapter->hw;
7924 u32 dmac_thr;
7925 u16 hwm;
7926
7927 if (hw->mac.type > e1000_82580) {
7928 if (adapter->flags & IGB_FLAG_DMAC) {
7929 u32 reg;
7930
7931 /* force threshold to 0. */
7932 wr32(E1000_DMCTXTH, 0);
7933
7934 /* DMA Coalescing high water mark needs to be greater
7935 * than the Rx threshold. Set hwm to PBA - max frame
7936 * size in 16B units, capping it at PBA - 6KB.
7937 */
7938 hwm = 64 * pba - adapter->max_frame_size / 16;
7939 if (hwm < 64 * (pba - 6))
7940 hwm = 64 * (pba - 6);
7941 reg = rd32(E1000_FCRTC);
7942 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7943 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7944 & E1000_FCRTC_RTH_COAL_MASK);
7945 wr32(E1000_FCRTC, reg);
7946
7947 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
7948 * frame size, capping it at PBA - 10KB.
7949 */
7950 dmac_thr = pba - adapter->max_frame_size / 512;
7951 if (dmac_thr < pba - 10)
7952 dmac_thr = pba - 10;
7953 reg = rd32(E1000_DMACR);
7954 reg &= ~E1000_DMACR_DMACTHR_MASK;
7955 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7956 & E1000_DMACR_DMACTHR_MASK);
7957
7958 /* transition to L0x or L1 if available..*/
7959 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7960
7961 /* watchdog timer= +-1000 usec in 32usec intervals */
7962 reg |= (1000 >> 5);
7963
7964 /* Disable BMC-to-OS Watchdog Enable */
7965 if (hw->mac.type != e1000_i354)
7966 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7967
7968 wr32(E1000_DMACR, reg);
7969
7970 /* no lower threshold to disable
7971 * coalescing(smart fifb)-UTRESH=0
7972 */
7973 wr32(E1000_DMCRTRH, 0);
7974
7975 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7976
7977 wr32(E1000_DMCTLX, reg);
7978
7979 /* free space in tx packet buffer to wake from
7980 * DMA coal
7981 */
7982 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7983 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7984
7985 /* make low power state decision controlled
7986 * by DMA coal
7987 */
7988 reg = rd32(E1000_PCIEMISC);
7989 reg &= ~E1000_PCIEMISC_LX_DECISION;
7990 wr32(E1000_PCIEMISC, reg);
7991 } /* endif adapter->dmac is not disabled */
7992 } else if (hw->mac.type == e1000_82580) {
7993 u32 reg = rd32(E1000_PCIEMISC);
7994
7995 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7996 wr32(E1000_DMACR, 0);
7997 }
7998}
7999
8000/**
8001 * igb_read_i2c_byte - Reads 8 bit word over I2C
8002 * @hw: pointer to hardware structure
8003 * @byte_offset: byte offset to read
8004 * @dev_addr: device address
8005 * @data: value read
8006 *
8007 * Performs byte read operation over I2C interface at
8008 * a specified device address.
8009 **/
8010s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8011 u8 dev_addr, u8 *data)
8012{
8013 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8014 struct i2c_client *this_client = adapter->i2c_client;
8015 s32 status;
8016 u16 swfw_mask = 0;
8017
8018 if (!this_client)
8019 return E1000_ERR_I2C;
8020
8021 swfw_mask = E1000_SWFW_PHY0_SM;
8022
8023 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8024 return E1000_ERR_SWFW_SYNC;
8025
8026 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8027 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8028
8029 if (status < 0)
8030 return E1000_ERR_I2C;
8031 else {
8032 *data = status;
8033 return 0;
8034 }
8035}
8036
8037/**
8038 * igb_write_i2c_byte - Writes 8 bit word over I2C
8039 * @hw: pointer to hardware structure
8040 * @byte_offset: byte offset to write
8041 * @dev_addr: device address
8042 * @data: value to write
8043 *
8044 * Performs byte write operation over I2C interface at
8045 * a specified device address.
8046 **/
8047s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8048 u8 dev_addr, u8 data)
8049{
8050 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8051 struct i2c_client *this_client = adapter->i2c_client;
8052 s32 status;
8053 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8054
8055 if (!this_client)
8056 return E1000_ERR_I2C;
8057
8058 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8059 return E1000_ERR_SWFW_SYNC;
8060 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8061 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8062
8063 if (status)
8064 return E1000_ERR_I2C;
8065 else
8066 return 0;
8067
8068}
8069
8070int igb_reinit_queues(struct igb_adapter *adapter)
8071{
8072 struct net_device *netdev = adapter->netdev;
8073 struct pci_dev *pdev = adapter->pdev;
8074 int err = 0;
8075
8076 if (netif_running(netdev))
8077 igb_close(netdev);
8078
8079 igb_reset_interrupt_capability(adapter);
8080
8081 if (igb_init_interrupt_scheme(adapter, true)) {
8082 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8083 return -ENOMEM;
8084 }
8085
8086 if (netif_running(netdev))
8087 err = igb_open(netdev);
8088
8089 return err;
8090}
8091/* igb_main.c */
Linux kernel - Deliverables
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