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DMA-API: net: intel/e1000e: fix 32-bit DMA mask handling
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
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1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
33#include <linux/bitops.h>
34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
37#include <linux/ipv6.h>
38#include <linux/slab.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/net_tstamp.h>
42#include <linux/mii.h>
43#include <linux/ethtool.h>
44#include <linux/if.h>
45#include <linux/if_vlan.h>
46#include <linux/pci.h>
47#include <linux/pci-aspm.h>
48#include <linux/delay.h>
49#include <linux/interrupt.h>
50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
53#include <linux/if_ether.h>
54#include <linux/aer.h>
55#include <linux/prefetch.h>
56#include <linux/pm_runtime.h>
57#ifdef CONFIG_IGB_DCA
58#include <linux/dca.h>
59#endif
60#include <linux/i2c.h>
61#include "igb.h"
62
63#define MAJ 5
64#define MIN 0
65#define BUILD 5
66#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
67__stringify(BUILD) "-k"
68char igb_driver_name[] = "igb";
69char igb_driver_version[] = DRV_VERSION;
70static const char igb_driver_string[] =
71 "Intel(R) Gigabit Ethernet Network Driver";
72static const char igb_copyright[] =
73 "Copyright (c) 2007-2013 Intel Corporation.";
74
75static const struct e1000_info *igb_info_tbl[] = {
76 [board_82575] = &e1000_82575_info,
77};
78
79static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
114 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
115 /* required last entry */
116 {0, }
117};
118
119MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
120
121void igb_reset(struct igb_adapter *);
122static int igb_setup_all_tx_resources(struct igb_adapter *);
123static int igb_setup_all_rx_resources(struct igb_adapter *);
124static void igb_free_all_tx_resources(struct igb_adapter *);
125static void igb_free_all_rx_resources(struct igb_adapter *);
126static void igb_setup_mrqc(struct igb_adapter *);
127static int igb_probe(struct pci_dev *, const struct pci_device_id *);
128static void igb_remove(struct pci_dev *pdev);
129static int igb_sw_init(struct igb_adapter *);
130static int igb_open(struct net_device *);
131static int igb_close(struct net_device *);
132static void igb_configure(struct igb_adapter *);
133static void igb_configure_tx(struct igb_adapter *);
134static void igb_configure_rx(struct igb_adapter *);
135static void igb_clean_all_tx_rings(struct igb_adapter *);
136static void igb_clean_all_rx_rings(struct igb_adapter *);
137static void igb_clean_tx_ring(struct igb_ring *);
138static void igb_clean_rx_ring(struct igb_ring *);
139static void igb_set_rx_mode(struct net_device *);
140static void igb_update_phy_info(unsigned long);
141static void igb_watchdog(unsigned long);
142static void igb_watchdog_task(struct work_struct *);
143static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
144static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
145 struct rtnl_link_stats64 *stats);
146static int igb_change_mtu(struct net_device *, int);
147static int igb_set_mac(struct net_device *, void *);
148static void igb_set_uta(struct igb_adapter *adapter);
149static irqreturn_t igb_intr(int irq, void *);
150static irqreturn_t igb_intr_msi(int irq, void *);
151static irqreturn_t igb_msix_other(int irq, void *);
152static irqreturn_t igb_msix_ring(int irq, void *);
153#ifdef CONFIG_IGB_DCA
154static void igb_update_dca(struct igb_q_vector *);
155static void igb_setup_dca(struct igb_adapter *);
156#endif /* CONFIG_IGB_DCA */
157static int igb_poll(struct napi_struct *, int);
158static bool igb_clean_tx_irq(struct igb_q_vector *);
159static bool igb_clean_rx_irq(struct igb_q_vector *, int);
160static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
161static void igb_tx_timeout(struct net_device *);
162static void igb_reset_task(struct work_struct *);
163static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
164static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
165static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
166static void igb_restore_vlan(struct igb_adapter *);
167static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
168static void igb_ping_all_vfs(struct igb_adapter *);
169static void igb_msg_task(struct igb_adapter *);
170static void igb_vmm_control(struct igb_adapter *);
171static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
172static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
173static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
174static int igb_ndo_set_vf_vlan(struct net_device *netdev,
175 int vf, u16 vlan, u8 qos);
176static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
177static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
178 bool setting);
179static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
180 struct ifla_vf_info *ivi);
181static void igb_check_vf_rate_limit(struct igb_adapter *);
182
183#ifdef CONFIG_PCI_IOV
184static int igb_vf_configure(struct igb_adapter *adapter, int vf);
185#endif
186
187#ifdef CONFIG_PM
188#ifdef CONFIG_PM_SLEEP
189static int igb_suspend(struct device *);
190#endif
191static int igb_resume(struct device *);
192#ifdef CONFIG_PM_RUNTIME
193static int igb_runtime_suspend(struct device *dev);
194static int igb_runtime_resume(struct device *dev);
195static int igb_runtime_idle(struct device *dev);
196#endif
197static const struct dev_pm_ops igb_pm_ops = {
198 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
199 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
200 igb_runtime_idle)
201};
202#endif
203static void igb_shutdown(struct pci_dev *);
204static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
205#ifdef CONFIG_IGB_DCA
206static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
207static struct notifier_block dca_notifier = {
208 .notifier_call = igb_notify_dca,
209 .next = NULL,
210 .priority = 0
211};
212#endif
213#ifdef CONFIG_NET_POLL_CONTROLLER
214/* for netdump / net console */
215static void igb_netpoll(struct net_device *);
216#endif
217#ifdef CONFIG_PCI_IOV
218static unsigned int max_vfs = 0;
219module_param(max_vfs, uint, 0);
220MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
221 "per physical function");
222#endif /* CONFIG_PCI_IOV */
223
224static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
225 pci_channel_state_t);
226static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
227static void igb_io_resume(struct pci_dev *);
228
229static const struct pci_error_handlers igb_err_handler = {
230 .error_detected = igb_io_error_detected,
231 .slot_reset = igb_io_slot_reset,
232 .resume = igb_io_resume,
233};
234
235static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
236
237static struct pci_driver igb_driver = {
238 .name = igb_driver_name,
239 .id_table = igb_pci_tbl,
240 .probe = igb_probe,
241 .remove = igb_remove,
242#ifdef CONFIG_PM
243 .driver.pm = &igb_pm_ops,
244#endif
245 .shutdown = igb_shutdown,
246 .sriov_configure = igb_pci_sriov_configure,
247 .err_handler = &igb_err_handler
248};
249
250MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
251MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
252MODULE_LICENSE("GPL");
253MODULE_VERSION(DRV_VERSION);
254
255#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
256static int debug = -1;
257module_param(debug, int, 0);
258MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
259
260struct igb_reg_info {
261 u32 ofs;
262 char *name;
263};
264
265static const struct igb_reg_info igb_reg_info_tbl[] = {
266
267 /* General Registers */
268 {E1000_CTRL, "CTRL"},
269 {E1000_STATUS, "STATUS"},
270 {E1000_CTRL_EXT, "CTRL_EXT"},
271
272 /* Interrupt Registers */
273 {E1000_ICR, "ICR"},
274
275 /* RX Registers */
276 {E1000_RCTL, "RCTL"},
277 {E1000_RDLEN(0), "RDLEN"},
278 {E1000_RDH(0), "RDH"},
279 {E1000_RDT(0), "RDT"},
280 {E1000_RXDCTL(0), "RXDCTL"},
281 {E1000_RDBAL(0), "RDBAL"},
282 {E1000_RDBAH(0), "RDBAH"},
283
284 /* TX Registers */
285 {E1000_TCTL, "TCTL"},
286 {E1000_TDBAL(0), "TDBAL"},
287 {E1000_TDBAH(0), "TDBAH"},
288 {E1000_TDLEN(0), "TDLEN"},
289 {E1000_TDH(0), "TDH"},
290 {E1000_TDT(0), "TDT"},
291 {E1000_TXDCTL(0), "TXDCTL"},
292 {E1000_TDFH, "TDFH"},
293 {E1000_TDFT, "TDFT"},
294 {E1000_TDFHS, "TDFHS"},
295 {E1000_TDFPC, "TDFPC"},
296
297 /* List Terminator */
298 {}
299};
300
301/* igb_regdump - register printout routine */
302static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
303{
304 int n = 0;
305 char rname[16];
306 u32 regs[8];
307
308 switch (reginfo->ofs) {
309 case E1000_RDLEN(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDLEN(n));
312 break;
313 case E1000_RDH(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDH(n));
316 break;
317 case E1000_RDT(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RDT(n));
320 break;
321 case E1000_RXDCTL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RXDCTL(n));
324 break;
325 case E1000_RDBAL(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAL(n));
328 break;
329 case E1000_RDBAH(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAH(n));
332 break;
333 case E1000_TDBAL(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_RDBAL(n));
336 break;
337 case E1000_TDBAH(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDBAH(n));
340 break;
341 case E1000_TDLEN(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDLEN(n));
344 break;
345 case E1000_TDH(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDH(n));
348 break;
349 case E1000_TDT(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TDT(n));
352 break;
353 case E1000_TXDCTL(0):
354 for (n = 0; n < 4; n++)
355 regs[n] = rd32(E1000_TXDCTL(n));
356 break;
357 default:
358 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
359 return;
360 }
361
362 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
363 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
364 regs[2], regs[3]);
365}
366
367/* igb_dump - Print registers, Tx-rings and Rx-rings */
368static void igb_dump(struct igb_adapter *adapter)
369{
370 struct net_device *netdev = adapter->netdev;
371 struct e1000_hw *hw = &adapter->hw;
372 struct igb_reg_info *reginfo;
373 struct igb_ring *tx_ring;
374 union e1000_adv_tx_desc *tx_desc;
375 struct my_u0 { u64 a; u64 b; } *u0;
376 struct igb_ring *rx_ring;
377 union e1000_adv_rx_desc *rx_desc;
378 u32 staterr;
379 u16 i, n;
380
381 if (!netif_msg_hw(adapter))
382 return;
383
384 /* Print netdevice Info */
385 if (netdev) {
386 dev_info(&adapter->pdev->dev, "Net device Info\n");
387 pr_info("Device Name state trans_start "
388 "last_rx\n");
389 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
390 netdev->state, netdev->trans_start, netdev->last_rx);
391 }
392
393 /* Print Registers */
394 dev_info(&adapter->pdev->dev, "Register Dump\n");
395 pr_info(" Register Name Value\n");
396 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
397 reginfo->name; reginfo++) {
398 igb_regdump(hw, reginfo);
399 }
400
401 /* Print TX Ring Summary */
402 if (!netdev || !netif_running(netdev))
403 goto exit;
404
405 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
406 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
407 for (n = 0; n < adapter->num_tx_queues; n++) {
408 struct igb_tx_buffer *buffer_info;
409 tx_ring = adapter->tx_ring[n];
410 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
411 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
412 n, tx_ring->next_to_use, tx_ring->next_to_clean,
413 (u64)dma_unmap_addr(buffer_info, dma),
414 dma_unmap_len(buffer_info, len),
415 buffer_info->next_to_watch,
416 (u64)buffer_info->time_stamp);
417 }
418
419 /* Print TX Rings */
420 if (!netif_msg_tx_done(adapter))
421 goto rx_ring_summary;
422
423 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
424
425 /* Transmit Descriptor Formats
426 *
427 * Advanced Transmit Descriptor
428 * +--------------------------------------------------------------+
429 * 0 | Buffer Address [63:0] |
430 * +--------------------------------------------------------------+
431 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
432 * +--------------------------------------------------------------+
433 * 63 46 45 40 39 38 36 35 32 31 24 15 0
434 */
435
436 for (n = 0; n < adapter->num_tx_queues; n++) {
437 tx_ring = adapter->tx_ring[n];
438 pr_info("------------------------------------\n");
439 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
440 pr_info("------------------------------------\n");
441 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
442 "[bi->dma ] leng ntw timestamp "
443 "bi->skb\n");
444
445 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
446 const char *next_desc;
447 struct igb_tx_buffer *buffer_info;
448 tx_desc = IGB_TX_DESC(tx_ring, i);
449 buffer_info = &tx_ring->tx_buffer_info[i];
450 u0 = (struct my_u0 *)tx_desc;
451 if (i == tx_ring->next_to_use &&
452 i == tx_ring->next_to_clean)
453 next_desc = " NTC/U";
454 else if (i == tx_ring->next_to_use)
455 next_desc = " NTU";
456 else if (i == tx_ring->next_to_clean)
457 next_desc = " NTC";
458 else
459 next_desc = "";
460
461 pr_info("T [0x%03X] %016llX %016llX %016llX"
462 " %04X %p %016llX %p%s\n", i,
463 le64_to_cpu(u0->a),
464 le64_to_cpu(u0->b),
465 (u64)dma_unmap_addr(buffer_info, dma),
466 dma_unmap_len(buffer_info, len),
467 buffer_info->next_to_watch,
468 (u64)buffer_info->time_stamp,
469 buffer_info->skb, next_desc);
470
471 if (netif_msg_pktdata(adapter) && buffer_info->skb)
472 print_hex_dump(KERN_INFO, "",
473 DUMP_PREFIX_ADDRESS,
474 16, 1, buffer_info->skb->data,
475 dma_unmap_len(buffer_info, len),
476 true);
477 }
478 }
479
480 /* Print RX Rings Summary */
481rx_ring_summary:
482 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
483 pr_info("Queue [NTU] [NTC]\n");
484 for (n = 0; n < adapter->num_rx_queues; n++) {
485 rx_ring = adapter->rx_ring[n];
486 pr_info(" %5d %5X %5X\n",
487 n, rx_ring->next_to_use, rx_ring->next_to_clean);
488 }
489
490 /* Print RX Rings */
491 if (!netif_msg_rx_status(adapter))
492 goto exit;
493
494 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
495
496 /* Advanced Receive Descriptor (Read) Format
497 * 63 1 0
498 * +-----------------------------------------------------+
499 * 0 | Packet Buffer Address [63:1] |A0/NSE|
500 * +----------------------------------------------+------+
501 * 8 | Header Buffer Address [63:1] | DD |
502 * +-----------------------------------------------------+
503 *
504 *
505 * Advanced Receive Descriptor (Write-Back) Format
506 *
507 * 63 48 47 32 31 30 21 20 17 16 4 3 0
508 * +------------------------------------------------------+
509 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
510 * | Checksum Ident | | | | Type | Type |
511 * +------------------------------------------------------+
512 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
513 * +------------------------------------------------------+
514 * 63 48 47 32 31 20 19 0
515 */
516
517 for (n = 0; n < adapter->num_rx_queues; n++) {
518 rx_ring = adapter->rx_ring[n];
519 pr_info("------------------------------------\n");
520 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
521 pr_info("------------------------------------\n");
522 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
523 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
524 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
525 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
526
527 for (i = 0; i < rx_ring->count; i++) {
528 const char *next_desc;
529 struct igb_rx_buffer *buffer_info;
530 buffer_info = &rx_ring->rx_buffer_info[i];
531 rx_desc = IGB_RX_DESC(rx_ring, i);
532 u0 = (struct my_u0 *)rx_desc;
533 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
534
535 if (i == rx_ring->next_to_use)
536 next_desc = " NTU";
537 else if (i == rx_ring->next_to_clean)
538 next_desc = " NTC";
539 else
540 next_desc = "";
541
542 if (staterr & E1000_RXD_STAT_DD) {
543 /* Descriptor Done */
544 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
545 "RWB", i,
546 le64_to_cpu(u0->a),
547 le64_to_cpu(u0->b),
548 next_desc);
549 } else {
550 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
551 "R ", i,
552 le64_to_cpu(u0->a),
553 le64_to_cpu(u0->b),
554 (u64)buffer_info->dma,
555 next_desc);
556
557 if (netif_msg_pktdata(adapter) &&
558 buffer_info->dma && buffer_info->page) {
559 print_hex_dump(KERN_INFO, "",
560 DUMP_PREFIX_ADDRESS,
561 16, 1,
562 page_address(buffer_info->page) +
563 buffer_info->page_offset,
564 IGB_RX_BUFSZ, true);
565 }
566 }
567 }
568 }
569
570exit:
571 return;
572}
573
574/**
575 * igb_get_i2c_data - Reads the I2C SDA data bit
576 * @hw: pointer to hardware structure
577 * @i2cctl: Current value of I2CCTL register
578 *
579 * Returns the I2C data bit value
580 **/
581static int igb_get_i2c_data(void *data)
582{
583 struct igb_adapter *adapter = (struct igb_adapter *)data;
584 struct e1000_hw *hw = &adapter->hw;
585 s32 i2cctl = rd32(E1000_I2CPARAMS);
586
587 return ((i2cctl & E1000_I2C_DATA_IN) != 0);
588}
589
590/**
591 * igb_set_i2c_data - Sets the I2C data bit
592 * @data: pointer to hardware structure
593 * @state: I2C data value (0 or 1) to set
594 *
595 * Sets the I2C data bit
596 **/
597static void igb_set_i2c_data(void *data, int state)
598{
599 struct igb_adapter *adapter = (struct igb_adapter *)data;
600 struct e1000_hw *hw = &adapter->hw;
601 s32 i2cctl = rd32(E1000_I2CPARAMS);
602
603 if (state)
604 i2cctl |= E1000_I2C_DATA_OUT;
605 else
606 i2cctl &= ~E1000_I2C_DATA_OUT;
607
608 i2cctl &= ~E1000_I2C_DATA_OE_N;
609 i2cctl |= E1000_I2C_CLK_OE_N;
610 wr32(E1000_I2CPARAMS, i2cctl);
611 wrfl();
612
613}
614
615/**
616 * igb_set_i2c_clk - Sets the I2C SCL clock
617 * @data: pointer to hardware structure
618 * @state: state to set clock
619 *
620 * Sets the I2C clock line to state
621 **/
622static void igb_set_i2c_clk(void *data, int state)
623{
624 struct igb_adapter *adapter = (struct igb_adapter *)data;
625 struct e1000_hw *hw = &adapter->hw;
626 s32 i2cctl = rd32(E1000_I2CPARAMS);
627
628 if (state) {
629 i2cctl |= E1000_I2C_CLK_OUT;
630 i2cctl &= ~E1000_I2C_CLK_OE_N;
631 } else {
632 i2cctl &= ~E1000_I2C_CLK_OUT;
633 i2cctl &= ~E1000_I2C_CLK_OE_N;
634 }
635 wr32(E1000_I2CPARAMS, i2cctl);
636 wrfl();
637}
638
639/**
640 * igb_get_i2c_clk - Gets the I2C SCL clock state
641 * @data: pointer to hardware structure
642 *
643 * Gets the I2C clock state
644 **/
645static int igb_get_i2c_clk(void *data)
646{
647 struct igb_adapter *adapter = (struct igb_adapter *)data;
648 struct e1000_hw *hw = &adapter->hw;
649 s32 i2cctl = rd32(E1000_I2CPARAMS);
650
651 return ((i2cctl & E1000_I2C_CLK_IN) != 0);
652}
653
654static const struct i2c_algo_bit_data igb_i2c_algo = {
655 .setsda = igb_set_i2c_data,
656 .setscl = igb_set_i2c_clk,
657 .getsda = igb_get_i2c_data,
658 .getscl = igb_get_i2c_clk,
659 .udelay = 5,
660 .timeout = 20,
661};
662
663/**
664 * igb_get_hw_dev - return device
665 * @hw: pointer to hardware structure
666 *
667 * used by hardware layer to print debugging information
668 **/
669struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
670{
671 struct igb_adapter *adapter = hw->back;
672 return adapter->netdev;
673}
674
675/**
676 * igb_init_module - Driver Registration Routine
677 *
678 * igb_init_module is the first routine called when the driver is
679 * loaded. All it does is register with the PCI subsystem.
680 **/
681static int __init igb_init_module(void)
682{
683 int ret;
684 pr_info("%s - version %s\n",
685 igb_driver_string, igb_driver_version);
686
687 pr_info("%s\n", igb_copyright);
688
689#ifdef CONFIG_IGB_DCA
690 dca_register_notify(&dca_notifier);
691#endif
692 ret = pci_register_driver(&igb_driver);
693 return ret;
694}
695
696module_init(igb_init_module);
697
698/**
699 * igb_exit_module - Driver Exit Cleanup Routine
700 *
701 * igb_exit_module is called just before the driver is removed
702 * from memory.
703 **/
704static void __exit igb_exit_module(void)
705{
706#ifdef CONFIG_IGB_DCA
707 dca_unregister_notify(&dca_notifier);
708#endif
709 pci_unregister_driver(&igb_driver);
710}
711
712module_exit(igb_exit_module);
713
714#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
715/**
716 * igb_cache_ring_register - Descriptor ring to register mapping
717 * @adapter: board private structure to initialize
718 *
719 * Once we know the feature-set enabled for the device, we'll cache
720 * the register offset the descriptor ring is assigned to.
721 **/
722static void igb_cache_ring_register(struct igb_adapter *adapter)
723{
724 int i = 0, j = 0;
725 u32 rbase_offset = adapter->vfs_allocated_count;
726
727 switch (adapter->hw.mac.type) {
728 case e1000_82576:
729 /* The queues are allocated for virtualization such that VF 0
730 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
731 * In order to avoid collision we start at the first free queue
732 * and continue consuming queues in the same sequence
733 */
734 if (adapter->vfs_allocated_count) {
735 for (; i < adapter->rss_queues; i++)
736 adapter->rx_ring[i]->reg_idx = rbase_offset +
737 Q_IDX_82576(i);
738 }
739 case e1000_82575:
740 case e1000_82580:
741 case e1000_i350:
742 case e1000_i354:
743 case e1000_i210:
744 case e1000_i211:
745 default:
746 for (; i < adapter->num_rx_queues; i++)
747 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
748 for (; j < adapter->num_tx_queues; j++)
749 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
750 break;
751 }
752}
753
754/**
755 * igb_write_ivar - configure ivar for given MSI-X vector
756 * @hw: pointer to the HW structure
757 * @msix_vector: vector number we are allocating to a given ring
758 * @index: row index of IVAR register to write within IVAR table
759 * @offset: column offset of in IVAR, should be multiple of 8
760 *
761 * This function is intended to handle the writing of the IVAR register
762 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
763 * each containing an cause allocation for an Rx and Tx ring, and a
764 * variable number of rows depending on the number of queues supported.
765 **/
766static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
767 int index, int offset)
768{
769 u32 ivar = array_rd32(E1000_IVAR0, index);
770
771 /* clear any bits that are currently set */
772 ivar &= ~((u32)0xFF << offset);
773
774 /* write vector and valid bit */
775 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
776
777 array_wr32(E1000_IVAR0, index, ivar);
778}
779
780#define IGB_N0_QUEUE -1
781static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
782{
783 struct igb_adapter *adapter = q_vector->adapter;
784 struct e1000_hw *hw = &adapter->hw;
785 int rx_queue = IGB_N0_QUEUE;
786 int tx_queue = IGB_N0_QUEUE;
787 u32 msixbm = 0;
788
789 if (q_vector->rx.ring)
790 rx_queue = q_vector->rx.ring->reg_idx;
791 if (q_vector->tx.ring)
792 tx_queue = q_vector->tx.ring->reg_idx;
793
794 switch (hw->mac.type) {
795 case e1000_82575:
796 /* The 82575 assigns vectors using a bitmask, which matches the
797 * bitmask for the EICR/EIMS/EIMC registers. To assign one
798 * or more queues to a vector, we write the appropriate bits
799 * into the MSIXBM register for that vector.
800 */
801 if (rx_queue > IGB_N0_QUEUE)
802 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
803 if (tx_queue > IGB_N0_QUEUE)
804 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
805 if (!adapter->msix_entries && msix_vector == 0)
806 msixbm |= E1000_EIMS_OTHER;
807 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
808 q_vector->eims_value = msixbm;
809 break;
810 case e1000_82576:
811 /* 82576 uses a table that essentially consists of 2 columns
812 * with 8 rows. The ordering is column-major so we use the
813 * lower 3 bits as the row index, and the 4th bit as the
814 * column offset.
815 */
816 if (rx_queue > IGB_N0_QUEUE)
817 igb_write_ivar(hw, msix_vector,
818 rx_queue & 0x7,
819 (rx_queue & 0x8) << 1);
820 if (tx_queue > IGB_N0_QUEUE)
821 igb_write_ivar(hw, msix_vector,
822 tx_queue & 0x7,
823 ((tx_queue & 0x8) << 1) + 8);
824 q_vector->eims_value = 1 << msix_vector;
825 break;
826 case e1000_82580:
827 case e1000_i350:
828 case e1000_i354:
829 case e1000_i210:
830 case e1000_i211:
831 /* On 82580 and newer adapters the scheme is similar to 82576
832 * however instead of ordering column-major we have things
833 * ordered row-major. So we traverse the table by using
834 * bit 0 as the column offset, and the remaining bits as the
835 * row index.
836 */
837 if (rx_queue > IGB_N0_QUEUE)
838 igb_write_ivar(hw, msix_vector,
839 rx_queue >> 1,
840 (rx_queue & 0x1) << 4);
841 if (tx_queue > IGB_N0_QUEUE)
842 igb_write_ivar(hw, msix_vector,
843 tx_queue >> 1,
844 ((tx_queue & 0x1) << 4) + 8);
845 q_vector->eims_value = 1 << msix_vector;
846 break;
847 default:
848 BUG();
849 break;
850 }
851
852 /* add q_vector eims value to global eims_enable_mask */
853 adapter->eims_enable_mask |= q_vector->eims_value;
854
855 /* configure q_vector to set itr on first interrupt */
856 q_vector->set_itr = 1;
857}
858
859/**
860 * igb_configure_msix - Configure MSI-X hardware
861 * @adapter: board private structure to initialize
862 *
863 * igb_configure_msix sets up the hardware to properly
864 * generate MSI-X interrupts.
865 **/
866static void igb_configure_msix(struct igb_adapter *adapter)
867{
868 u32 tmp;
869 int i, vector = 0;
870 struct e1000_hw *hw = &adapter->hw;
871
872 adapter->eims_enable_mask = 0;
873
874 /* set vector for other causes, i.e. link changes */
875 switch (hw->mac.type) {
876 case e1000_82575:
877 tmp = rd32(E1000_CTRL_EXT);
878 /* enable MSI-X PBA support*/
879 tmp |= E1000_CTRL_EXT_PBA_CLR;
880
881 /* Auto-Mask interrupts upon ICR read. */
882 tmp |= E1000_CTRL_EXT_EIAME;
883 tmp |= E1000_CTRL_EXT_IRCA;
884
885 wr32(E1000_CTRL_EXT, tmp);
886
887 /* enable msix_other interrupt */
888 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
889 adapter->eims_other = E1000_EIMS_OTHER;
890
891 break;
892
893 case e1000_82576:
894 case e1000_82580:
895 case e1000_i350:
896 case e1000_i354:
897 case e1000_i210:
898 case e1000_i211:
899 /* Turn on MSI-X capability first, or our settings
900 * won't stick. And it will take days to debug.
901 */
902 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
903 E1000_GPIE_PBA | E1000_GPIE_EIAME |
904 E1000_GPIE_NSICR);
905
906 /* enable msix_other interrupt */
907 adapter->eims_other = 1 << vector;
908 tmp = (vector++ | E1000_IVAR_VALID) << 8;
909
910 wr32(E1000_IVAR_MISC, tmp);
911 break;
912 default:
913 /* do nothing, since nothing else supports MSI-X */
914 break;
915 } /* switch (hw->mac.type) */
916
917 adapter->eims_enable_mask |= adapter->eims_other;
918
919 for (i = 0; i < adapter->num_q_vectors; i++)
920 igb_assign_vector(adapter->q_vector[i], vector++);
921
922 wrfl();
923}
924
925/**
926 * igb_request_msix - Initialize MSI-X interrupts
927 * @adapter: board private structure to initialize
928 *
929 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
930 * kernel.
931 **/
932static int igb_request_msix(struct igb_adapter *adapter)
933{
934 struct net_device *netdev = adapter->netdev;
935 struct e1000_hw *hw = &adapter->hw;
936 int i, err = 0, vector = 0, free_vector = 0;
937
938 err = request_irq(adapter->msix_entries[vector].vector,
939 igb_msix_other, 0, netdev->name, adapter);
940 if (err)
941 goto err_out;
942
943 for (i = 0; i < adapter->num_q_vectors; i++) {
944 struct igb_q_vector *q_vector = adapter->q_vector[i];
945
946 vector++;
947
948 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
949
950 if (q_vector->rx.ring && q_vector->tx.ring)
951 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
952 q_vector->rx.ring->queue_index);
953 else if (q_vector->tx.ring)
954 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
955 q_vector->tx.ring->queue_index);
956 else if (q_vector->rx.ring)
957 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
958 q_vector->rx.ring->queue_index);
959 else
960 sprintf(q_vector->name, "%s-unused", netdev->name);
961
962 err = request_irq(adapter->msix_entries[vector].vector,
963 igb_msix_ring, 0, q_vector->name,
964 q_vector);
965 if (err)
966 goto err_free;
967 }
968
969 igb_configure_msix(adapter);
970 return 0;
971
972err_free:
973 /* free already assigned IRQs */
974 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
975
976 vector--;
977 for (i = 0; i < vector; i++) {
978 free_irq(adapter->msix_entries[free_vector++].vector,
979 adapter->q_vector[i]);
980 }
981err_out:
982 return err;
983}
984
985static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
986{
987 if (adapter->msix_entries) {
988 pci_disable_msix(adapter->pdev);
989 kfree(adapter->msix_entries);
990 adapter->msix_entries = NULL;
991 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
992 pci_disable_msi(adapter->pdev);
993 }
994}
995
996/**
997 * igb_free_q_vector - Free memory allocated for specific interrupt vector
998 * @adapter: board private structure to initialize
999 * @v_idx: Index of vector to be freed
1000 *
1001 * This function frees the memory allocated to the q_vector. In addition if
1002 * NAPI is enabled it will delete any references to the NAPI struct prior
1003 * to freeing the q_vector.
1004 **/
1005static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1006{
1007 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1008
1009 if (q_vector->tx.ring)
1010 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1011
1012 if (q_vector->rx.ring)
1013 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1014
1015 adapter->q_vector[v_idx] = NULL;
1016 netif_napi_del(&q_vector->napi);
1017
1018 /* igb_get_stats64() might access the rings on this vector,
1019 * we must wait a grace period before freeing it.
1020 */
1021 kfree_rcu(q_vector, rcu);
1022}
1023
1024/**
1025 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1026 * @adapter: board private structure to initialize
1027 *
1028 * This function frees the memory allocated to the q_vectors. In addition if
1029 * NAPI is enabled it will delete any references to the NAPI struct prior
1030 * to freeing the q_vector.
1031 **/
1032static void igb_free_q_vectors(struct igb_adapter *adapter)
1033{
1034 int v_idx = adapter->num_q_vectors;
1035
1036 adapter->num_tx_queues = 0;
1037 adapter->num_rx_queues = 0;
1038 adapter->num_q_vectors = 0;
1039
1040 while (v_idx--)
1041 igb_free_q_vector(adapter, v_idx);
1042}
1043
1044/**
1045 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1046 * @adapter: board private structure to initialize
1047 *
1048 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1049 * MSI-X interrupts allocated.
1050 */
1051static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1052{
1053 igb_free_q_vectors(adapter);
1054 igb_reset_interrupt_capability(adapter);
1055}
1056
1057/**
1058 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1059 * @adapter: board private structure to initialize
1060 * @msix: boolean value of MSIX capability
1061 *
1062 * Attempt to configure interrupts using the best available
1063 * capabilities of the hardware and kernel.
1064 **/
1065static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1066{
1067 int err;
1068 int numvecs, i;
1069
1070 if (!msix)
1071 goto msi_only;
1072
1073 /* Number of supported queues. */
1074 adapter->num_rx_queues = adapter->rss_queues;
1075 if (adapter->vfs_allocated_count)
1076 adapter->num_tx_queues = 1;
1077 else
1078 adapter->num_tx_queues = adapter->rss_queues;
1079
1080 /* start with one vector for every Rx queue */
1081 numvecs = adapter->num_rx_queues;
1082
1083 /* if Tx handler is separate add 1 for every Tx queue */
1084 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1085 numvecs += adapter->num_tx_queues;
1086
1087 /* store the number of vectors reserved for queues */
1088 adapter->num_q_vectors = numvecs;
1089
1090 /* add 1 vector for link status interrupts */
1091 numvecs++;
1092 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1093 GFP_KERNEL);
1094
1095 if (!adapter->msix_entries)
1096 goto msi_only;
1097
1098 for (i = 0; i < numvecs; i++)
1099 adapter->msix_entries[i].entry = i;
1100
1101 err = pci_enable_msix(adapter->pdev,
1102 adapter->msix_entries,
1103 numvecs);
1104 if (err == 0)
1105 return;
1106
1107 igb_reset_interrupt_capability(adapter);
1108
1109 /* If we can't do MSI-X, try MSI */
1110msi_only:
1111#ifdef CONFIG_PCI_IOV
1112 /* disable SR-IOV for non MSI-X configurations */
1113 if (adapter->vf_data) {
1114 struct e1000_hw *hw = &adapter->hw;
1115 /* disable iov and allow time for transactions to clear */
1116 pci_disable_sriov(adapter->pdev);
1117 msleep(500);
1118
1119 kfree(adapter->vf_data);
1120 adapter->vf_data = NULL;
1121 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1122 wrfl();
1123 msleep(100);
1124 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1125 }
1126#endif
1127 adapter->vfs_allocated_count = 0;
1128 adapter->rss_queues = 1;
1129 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1130 adapter->num_rx_queues = 1;
1131 adapter->num_tx_queues = 1;
1132 adapter->num_q_vectors = 1;
1133 if (!pci_enable_msi(adapter->pdev))
1134 adapter->flags |= IGB_FLAG_HAS_MSI;
1135}
1136
1137static void igb_add_ring(struct igb_ring *ring,
1138 struct igb_ring_container *head)
1139{
1140 head->ring = ring;
1141 head->count++;
1142}
1143
1144/**
1145 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1146 * @adapter: board private structure to initialize
1147 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1148 * @v_idx: index of vector in adapter struct
1149 * @txr_count: total number of Tx rings to allocate
1150 * @txr_idx: index of first Tx ring to allocate
1151 * @rxr_count: total number of Rx rings to allocate
1152 * @rxr_idx: index of first Rx ring to allocate
1153 *
1154 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1155 **/
1156static int igb_alloc_q_vector(struct igb_adapter *adapter,
1157 int v_count, int v_idx,
1158 int txr_count, int txr_idx,
1159 int rxr_count, int rxr_idx)
1160{
1161 struct igb_q_vector *q_vector;
1162 struct igb_ring *ring;
1163 int ring_count, size;
1164
1165 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1166 if (txr_count > 1 || rxr_count > 1)
1167 return -ENOMEM;
1168
1169 ring_count = txr_count + rxr_count;
1170 size = sizeof(struct igb_q_vector) +
1171 (sizeof(struct igb_ring) * ring_count);
1172
1173 /* allocate q_vector and rings */
1174 q_vector = kzalloc(size, GFP_KERNEL);
1175 if (!q_vector)
1176 return -ENOMEM;
1177
1178 /* initialize NAPI */
1179 netif_napi_add(adapter->netdev, &q_vector->napi,
1180 igb_poll, 64);
1181
1182 /* tie q_vector and adapter together */
1183 adapter->q_vector[v_idx] = q_vector;
1184 q_vector->adapter = adapter;
1185
1186 /* initialize work limits */
1187 q_vector->tx.work_limit = adapter->tx_work_limit;
1188
1189 /* initialize ITR configuration */
1190 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1191 q_vector->itr_val = IGB_START_ITR;
1192
1193 /* initialize pointer to rings */
1194 ring = q_vector->ring;
1195
1196 /* intialize ITR */
1197 if (rxr_count) {
1198 /* rx or rx/tx vector */
1199 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1200 q_vector->itr_val = adapter->rx_itr_setting;
1201 } else {
1202 /* tx only vector */
1203 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1204 q_vector->itr_val = adapter->tx_itr_setting;
1205 }
1206
1207 if (txr_count) {
1208 /* assign generic ring traits */
1209 ring->dev = &adapter->pdev->dev;
1210 ring->netdev = adapter->netdev;
1211
1212 /* configure backlink on ring */
1213 ring->q_vector = q_vector;
1214
1215 /* update q_vector Tx values */
1216 igb_add_ring(ring, &q_vector->tx);
1217
1218 /* For 82575, context index must be unique per ring. */
1219 if (adapter->hw.mac.type == e1000_82575)
1220 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1221
1222 /* apply Tx specific ring traits */
1223 ring->count = adapter->tx_ring_count;
1224 ring->queue_index = txr_idx;
1225
1226 /* assign ring to adapter */
1227 adapter->tx_ring[txr_idx] = ring;
1228
1229 /* push pointer to next ring */
1230 ring++;
1231 }
1232
1233 if (rxr_count) {
1234 /* assign generic ring traits */
1235 ring->dev = &adapter->pdev->dev;
1236 ring->netdev = adapter->netdev;
1237
1238 /* configure backlink on ring */
1239 ring->q_vector = q_vector;
1240
1241 /* update q_vector Rx values */
1242 igb_add_ring(ring, &q_vector->rx);
1243
1244 /* set flag indicating ring supports SCTP checksum offload */
1245 if (adapter->hw.mac.type >= e1000_82576)
1246 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1247
1248 /*
1249 * On i350, i354, i210, and i211, loopback VLAN packets
1250 * have the tag byte-swapped.
1251 */
1252 if (adapter->hw.mac.type >= e1000_i350)
1253 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1254
1255 /* apply Rx specific ring traits */
1256 ring->count = adapter->rx_ring_count;
1257 ring->queue_index = rxr_idx;
1258
1259 /* assign ring to adapter */
1260 adapter->rx_ring[rxr_idx] = ring;
1261 }
1262
1263 return 0;
1264}
1265
1266
1267/**
1268 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1269 * @adapter: board private structure to initialize
1270 *
1271 * We allocate one q_vector per queue interrupt. If allocation fails we
1272 * return -ENOMEM.
1273 **/
1274static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1275{
1276 int q_vectors = adapter->num_q_vectors;
1277 int rxr_remaining = adapter->num_rx_queues;
1278 int txr_remaining = adapter->num_tx_queues;
1279 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1280 int err;
1281
1282 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1283 for (; rxr_remaining; v_idx++) {
1284 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1285 0, 0, 1, rxr_idx);
1286
1287 if (err)
1288 goto err_out;
1289
1290 /* update counts and index */
1291 rxr_remaining--;
1292 rxr_idx++;
1293 }
1294 }
1295
1296 for (; v_idx < q_vectors; v_idx++) {
1297 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1298 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1299 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1300 tqpv, txr_idx, rqpv, rxr_idx);
1301
1302 if (err)
1303 goto err_out;
1304
1305 /* update counts and index */
1306 rxr_remaining -= rqpv;
1307 txr_remaining -= tqpv;
1308 rxr_idx++;
1309 txr_idx++;
1310 }
1311
1312 return 0;
1313
1314err_out:
1315 adapter->num_tx_queues = 0;
1316 adapter->num_rx_queues = 0;
1317 adapter->num_q_vectors = 0;
1318
1319 while (v_idx--)
1320 igb_free_q_vector(adapter, v_idx);
1321
1322 return -ENOMEM;
1323}
1324
1325/**
1326 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1327 * @adapter: board private structure to initialize
1328 * @msix: boolean value of MSIX capability
1329 *
1330 * This function initializes the interrupts and allocates all of the queues.
1331 **/
1332static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1333{
1334 struct pci_dev *pdev = adapter->pdev;
1335 int err;
1336
1337 igb_set_interrupt_capability(adapter, msix);
1338
1339 err = igb_alloc_q_vectors(adapter);
1340 if (err) {
1341 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1342 goto err_alloc_q_vectors;
1343 }
1344
1345 igb_cache_ring_register(adapter);
1346
1347 return 0;
1348
1349err_alloc_q_vectors:
1350 igb_reset_interrupt_capability(adapter);
1351 return err;
1352}
1353
1354/**
1355 * igb_request_irq - initialize interrupts
1356 * @adapter: board private structure to initialize
1357 *
1358 * Attempts to configure interrupts using the best available
1359 * capabilities of the hardware and kernel.
1360 **/
1361static int igb_request_irq(struct igb_adapter *adapter)
1362{
1363 struct net_device *netdev = adapter->netdev;
1364 struct pci_dev *pdev = adapter->pdev;
1365 int err = 0;
1366
1367 if (adapter->msix_entries) {
1368 err = igb_request_msix(adapter);
1369 if (!err)
1370 goto request_done;
1371 /* fall back to MSI */
1372 igb_free_all_tx_resources(adapter);
1373 igb_free_all_rx_resources(adapter);
1374
1375 igb_clear_interrupt_scheme(adapter);
1376 err = igb_init_interrupt_scheme(adapter, false);
1377 if (err)
1378 goto request_done;
1379
1380 igb_setup_all_tx_resources(adapter);
1381 igb_setup_all_rx_resources(adapter);
1382 igb_configure(adapter);
1383 }
1384
1385 igb_assign_vector(adapter->q_vector[0], 0);
1386
1387 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1388 err = request_irq(pdev->irq, igb_intr_msi, 0,
1389 netdev->name, adapter);
1390 if (!err)
1391 goto request_done;
1392
1393 /* fall back to legacy interrupts */
1394 igb_reset_interrupt_capability(adapter);
1395 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1396 }
1397
1398 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1399 netdev->name, adapter);
1400
1401 if (err)
1402 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1403 err);
1404
1405request_done:
1406 return err;
1407}
1408
1409static void igb_free_irq(struct igb_adapter *adapter)
1410{
1411 if (adapter->msix_entries) {
1412 int vector = 0, i;
1413
1414 free_irq(adapter->msix_entries[vector++].vector, adapter);
1415
1416 for (i = 0; i < adapter->num_q_vectors; i++)
1417 free_irq(adapter->msix_entries[vector++].vector,
1418 adapter->q_vector[i]);
1419 } else {
1420 free_irq(adapter->pdev->irq, adapter);
1421 }
1422}
1423
1424/**
1425 * igb_irq_disable - Mask off interrupt generation on the NIC
1426 * @adapter: board private structure
1427 **/
1428static void igb_irq_disable(struct igb_adapter *adapter)
1429{
1430 struct e1000_hw *hw = &adapter->hw;
1431
1432 /* we need to be careful when disabling interrupts. The VFs are also
1433 * mapped into these registers and so clearing the bits can cause
1434 * issues on the VF drivers so we only need to clear what we set
1435 */
1436 if (adapter->msix_entries) {
1437 u32 regval = rd32(E1000_EIAM);
1438 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1439 wr32(E1000_EIMC, adapter->eims_enable_mask);
1440 regval = rd32(E1000_EIAC);
1441 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1442 }
1443
1444 wr32(E1000_IAM, 0);
1445 wr32(E1000_IMC, ~0);
1446 wrfl();
1447 if (adapter->msix_entries) {
1448 int i;
1449 for (i = 0; i < adapter->num_q_vectors; i++)
1450 synchronize_irq(adapter->msix_entries[i].vector);
1451 } else {
1452 synchronize_irq(adapter->pdev->irq);
1453 }
1454}
1455
1456/**
1457 * igb_irq_enable - Enable default interrupt generation settings
1458 * @adapter: board private structure
1459 **/
1460static void igb_irq_enable(struct igb_adapter *adapter)
1461{
1462 struct e1000_hw *hw = &adapter->hw;
1463
1464 if (adapter->msix_entries) {
1465 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1466 u32 regval = rd32(E1000_EIAC);
1467 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1468 regval = rd32(E1000_EIAM);
1469 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1470 wr32(E1000_EIMS, adapter->eims_enable_mask);
1471 if (adapter->vfs_allocated_count) {
1472 wr32(E1000_MBVFIMR, 0xFF);
1473 ims |= E1000_IMS_VMMB;
1474 }
1475 wr32(E1000_IMS, ims);
1476 } else {
1477 wr32(E1000_IMS, IMS_ENABLE_MASK |
1478 E1000_IMS_DRSTA);
1479 wr32(E1000_IAM, IMS_ENABLE_MASK |
1480 E1000_IMS_DRSTA);
1481 }
1482}
1483
1484static void igb_update_mng_vlan(struct igb_adapter *adapter)
1485{
1486 struct e1000_hw *hw = &adapter->hw;
1487 u16 vid = adapter->hw.mng_cookie.vlan_id;
1488 u16 old_vid = adapter->mng_vlan_id;
1489
1490 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1491 /* add VID to filter table */
1492 igb_vfta_set(hw, vid, true);
1493 adapter->mng_vlan_id = vid;
1494 } else {
1495 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1496 }
1497
1498 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1499 (vid != old_vid) &&
1500 !test_bit(old_vid, adapter->active_vlans)) {
1501 /* remove VID from filter table */
1502 igb_vfta_set(hw, old_vid, false);
1503 }
1504}
1505
1506/**
1507 * igb_release_hw_control - release control of the h/w to f/w
1508 * @adapter: address of board private structure
1509 *
1510 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1511 * For ASF and Pass Through versions of f/w this means that the
1512 * driver is no longer loaded.
1513 **/
1514static void igb_release_hw_control(struct igb_adapter *adapter)
1515{
1516 struct e1000_hw *hw = &adapter->hw;
1517 u32 ctrl_ext;
1518
1519 /* Let firmware take over control of h/w */
1520 ctrl_ext = rd32(E1000_CTRL_EXT);
1521 wr32(E1000_CTRL_EXT,
1522 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1523}
1524
1525/**
1526 * igb_get_hw_control - get control of the h/w from f/w
1527 * @adapter: address of board private structure
1528 *
1529 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1530 * For ASF and Pass Through versions of f/w this means that
1531 * the driver is loaded.
1532 **/
1533static void igb_get_hw_control(struct igb_adapter *adapter)
1534{
1535 struct e1000_hw *hw = &adapter->hw;
1536 u32 ctrl_ext;
1537
1538 /* Let firmware know the driver has taken over */
1539 ctrl_ext = rd32(E1000_CTRL_EXT);
1540 wr32(E1000_CTRL_EXT,
1541 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1542}
1543
1544/**
1545 * igb_configure - configure the hardware for RX and TX
1546 * @adapter: private board structure
1547 **/
1548static void igb_configure(struct igb_adapter *adapter)
1549{
1550 struct net_device *netdev = adapter->netdev;
1551 int i;
1552
1553 igb_get_hw_control(adapter);
1554 igb_set_rx_mode(netdev);
1555
1556 igb_restore_vlan(adapter);
1557
1558 igb_setup_tctl(adapter);
1559 igb_setup_mrqc(adapter);
1560 igb_setup_rctl(adapter);
1561
1562 igb_configure_tx(adapter);
1563 igb_configure_rx(adapter);
1564
1565 igb_rx_fifo_flush_82575(&adapter->hw);
1566
1567 /* call igb_desc_unused which always leaves
1568 * at least 1 descriptor unused to make sure
1569 * next_to_use != next_to_clean
1570 */
1571 for (i = 0; i < adapter->num_rx_queues; i++) {
1572 struct igb_ring *ring = adapter->rx_ring[i];
1573 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1574 }
1575}
1576
1577/**
1578 * igb_power_up_link - Power up the phy/serdes link
1579 * @adapter: address of board private structure
1580 **/
1581void igb_power_up_link(struct igb_adapter *adapter)
1582{
1583 igb_reset_phy(&adapter->hw);
1584
1585 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1586 igb_power_up_phy_copper(&adapter->hw);
1587 else
1588 igb_power_up_serdes_link_82575(&adapter->hw);
1589}
1590
1591/**
1592 * igb_power_down_link - Power down the phy/serdes link
1593 * @adapter: address of board private structure
1594 */
1595static void igb_power_down_link(struct igb_adapter *adapter)
1596{
1597 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1598 igb_power_down_phy_copper_82575(&adapter->hw);
1599 else
1600 igb_shutdown_serdes_link_82575(&adapter->hw);
1601}
1602
1603/**
1604 * igb_up - Open the interface and prepare it to handle traffic
1605 * @adapter: board private structure
1606 **/
1607int igb_up(struct igb_adapter *adapter)
1608{
1609 struct e1000_hw *hw = &adapter->hw;
1610 int i;
1611
1612 /* hardware has been reset, we need to reload some things */
1613 igb_configure(adapter);
1614
1615 clear_bit(__IGB_DOWN, &adapter->state);
1616
1617 for (i = 0; i < adapter->num_q_vectors; i++)
1618 napi_enable(&(adapter->q_vector[i]->napi));
1619
1620 if (adapter->msix_entries)
1621 igb_configure_msix(adapter);
1622 else
1623 igb_assign_vector(adapter->q_vector[0], 0);
1624
1625 /* Clear any pending interrupts. */
1626 rd32(E1000_ICR);
1627 igb_irq_enable(adapter);
1628
1629 /* notify VFs that reset has been completed */
1630 if (adapter->vfs_allocated_count) {
1631 u32 reg_data = rd32(E1000_CTRL_EXT);
1632 reg_data |= E1000_CTRL_EXT_PFRSTD;
1633 wr32(E1000_CTRL_EXT, reg_data);
1634 }
1635
1636 netif_tx_start_all_queues(adapter->netdev);
1637
1638 /* start the watchdog. */
1639 hw->mac.get_link_status = 1;
1640 schedule_work(&adapter->watchdog_task);
1641
1642 return 0;
1643}
1644
1645void igb_down(struct igb_adapter *adapter)
1646{
1647 struct net_device *netdev = adapter->netdev;
1648 struct e1000_hw *hw = &adapter->hw;
1649 u32 tctl, rctl;
1650 int i;
1651
1652 /* signal that we're down so the interrupt handler does not
1653 * reschedule our watchdog timer
1654 */
1655 set_bit(__IGB_DOWN, &adapter->state);
1656
1657 /* disable receives in the hardware */
1658 rctl = rd32(E1000_RCTL);
1659 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1660 /* flush and sleep below */
1661
1662 netif_tx_stop_all_queues(netdev);
1663
1664 /* disable transmits in the hardware */
1665 tctl = rd32(E1000_TCTL);
1666 tctl &= ~E1000_TCTL_EN;
1667 wr32(E1000_TCTL, tctl);
1668 /* flush both disables and wait for them to finish */
1669 wrfl();
1670 msleep(10);
1671
1672 igb_irq_disable(adapter);
1673
1674 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1675
1676 for (i = 0; i < adapter->num_q_vectors; i++) {
1677 napi_synchronize(&(adapter->q_vector[i]->napi));
1678 napi_disable(&(adapter->q_vector[i]->napi));
1679 }
1680
1681
1682 del_timer_sync(&adapter->watchdog_timer);
1683 del_timer_sync(&adapter->phy_info_timer);
1684
1685 netif_carrier_off(netdev);
1686
1687 /* record the stats before reset*/
1688 spin_lock(&adapter->stats64_lock);
1689 igb_update_stats(adapter, &adapter->stats64);
1690 spin_unlock(&adapter->stats64_lock);
1691
1692 adapter->link_speed = 0;
1693 adapter->link_duplex = 0;
1694
1695 if (!pci_channel_offline(adapter->pdev))
1696 igb_reset(adapter);
1697 igb_clean_all_tx_rings(adapter);
1698 igb_clean_all_rx_rings(adapter);
1699#ifdef CONFIG_IGB_DCA
1700
1701 /* since we reset the hardware DCA settings were cleared */
1702 igb_setup_dca(adapter);
1703#endif
1704}
1705
1706void igb_reinit_locked(struct igb_adapter *adapter)
1707{
1708 WARN_ON(in_interrupt());
1709 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1710 msleep(1);
1711 igb_down(adapter);
1712 igb_up(adapter);
1713 clear_bit(__IGB_RESETTING, &adapter->state);
1714}
1715
1716void igb_reset(struct igb_adapter *adapter)
1717{
1718 struct pci_dev *pdev = adapter->pdev;
1719 struct e1000_hw *hw = &adapter->hw;
1720 struct e1000_mac_info *mac = &hw->mac;
1721 struct e1000_fc_info *fc = &hw->fc;
1722 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
1723
1724 /* Repartition Pba for greater than 9k mtu
1725 * To take effect CTRL.RST is required.
1726 */
1727 switch (mac->type) {
1728 case e1000_i350:
1729 case e1000_i354:
1730 case e1000_82580:
1731 pba = rd32(E1000_RXPBS);
1732 pba = igb_rxpbs_adjust_82580(pba);
1733 break;
1734 case e1000_82576:
1735 pba = rd32(E1000_RXPBS);
1736 pba &= E1000_RXPBS_SIZE_MASK_82576;
1737 break;
1738 case e1000_82575:
1739 case e1000_i210:
1740 case e1000_i211:
1741 default:
1742 pba = E1000_PBA_34K;
1743 break;
1744 }
1745
1746 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1747 (mac->type < e1000_82576)) {
1748 /* adjust PBA for jumbo frames */
1749 wr32(E1000_PBA, pba);
1750
1751 /* To maintain wire speed transmits, the Tx FIFO should be
1752 * large enough to accommodate two full transmit packets,
1753 * rounded up to the next 1KB and expressed in KB. Likewise,
1754 * the Rx FIFO should be large enough to accommodate at least
1755 * one full receive packet and is similarly rounded up and
1756 * expressed in KB.
1757 */
1758 pba = rd32(E1000_PBA);
1759 /* upper 16 bits has Tx packet buffer allocation size in KB */
1760 tx_space = pba >> 16;
1761 /* lower 16 bits has Rx packet buffer allocation size in KB */
1762 pba &= 0xffff;
1763 /* the Tx fifo also stores 16 bytes of information about the Tx
1764 * but don't include ethernet FCS because hardware appends it
1765 */
1766 min_tx_space = (adapter->max_frame_size +
1767 sizeof(union e1000_adv_tx_desc) -
1768 ETH_FCS_LEN) * 2;
1769 min_tx_space = ALIGN(min_tx_space, 1024);
1770 min_tx_space >>= 10;
1771 /* software strips receive CRC, so leave room for it */
1772 min_rx_space = adapter->max_frame_size;
1773 min_rx_space = ALIGN(min_rx_space, 1024);
1774 min_rx_space >>= 10;
1775
1776 /* If current Tx allocation is less than the min Tx FIFO size,
1777 * and the min Tx FIFO size is less than the current Rx FIFO
1778 * allocation, take space away from current Rx allocation
1779 */
1780 if (tx_space < min_tx_space &&
1781 ((min_tx_space - tx_space) < pba)) {
1782 pba = pba - (min_tx_space - tx_space);
1783
1784 /* if short on Rx space, Rx wins and must trump Tx
1785 * adjustment
1786 */
1787 if (pba < min_rx_space)
1788 pba = min_rx_space;
1789 }
1790 wr32(E1000_PBA, pba);
1791 }
1792
1793 /* flow control settings */
1794 /* The high water mark must be low enough to fit one full frame
1795 * (or the size used for early receive) above it in the Rx FIFO.
1796 * Set it to the lower of:
1797 * - 90% of the Rx FIFO size, or
1798 * - the full Rx FIFO size minus one full frame
1799 */
1800 hwm = min(((pba << 10) * 9 / 10),
1801 ((pba << 10) - 2 * adapter->max_frame_size));
1802
1803 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
1804 fc->low_water = fc->high_water - 16;
1805 fc->pause_time = 0xFFFF;
1806 fc->send_xon = 1;
1807 fc->current_mode = fc->requested_mode;
1808
1809 /* disable receive for all VFs and wait one second */
1810 if (adapter->vfs_allocated_count) {
1811 int i;
1812 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1813 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1814
1815 /* ping all the active vfs to let them know we are going down */
1816 igb_ping_all_vfs(adapter);
1817
1818 /* disable transmits and receives */
1819 wr32(E1000_VFRE, 0);
1820 wr32(E1000_VFTE, 0);
1821 }
1822
1823 /* Allow time for pending master requests to run */
1824 hw->mac.ops.reset_hw(hw);
1825 wr32(E1000_WUC, 0);
1826
1827 if (hw->mac.ops.init_hw(hw))
1828 dev_err(&pdev->dev, "Hardware Error\n");
1829
1830 /* Flow control settings reset on hardware reset, so guarantee flow
1831 * control is off when forcing speed.
1832 */
1833 if (!hw->mac.autoneg)
1834 igb_force_mac_fc(hw);
1835
1836 igb_init_dmac(adapter, pba);
1837#ifdef CONFIG_IGB_HWMON
1838 /* Re-initialize the thermal sensor on i350 devices. */
1839 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1840 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1841 /* If present, re-initialize the external thermal sensor
1842 * interface.
1843 */
1844 if (adapter->ets)
1845 mac->ops.init_thermal_sensor_thresh(hw);
1846 }
1847 }
1848#endif
1849 if (!netif_running(adapter->netdev))
1850 igb_power_down_link(adapter);
1851
1852 igb_update_mng_vlan(adapter);
1853
1854 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1855 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1856
1857 /* Re-enable PTP, where applicable. */
1858 igb_ptp_reset(adapter);
1859
1860 igb_get_phy_info(hw);
1861}
1862
1863static netdev_features_t igb_fix_features(struct net_device *netdev,
1864 netdev_features_t features)
1865{
1866 /* Since there is no support for separate Rx/Tx vlan accel
1867 * enable/disable make sure Tx flag is always in same state as Rx.
1868 */
1869 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1870 features |= NETIF_F_HW_VLAN_CTAG_TX;
1871 else
1872 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
1873
1874 return features;
1875}
1876
1877static int igb_set_features(struct net_device *netdev,
1878 netdev_features_t features)
1879{
1880 netdev_features_t changed = netdev->features ^ features;
1881 struct igb_adapter *adapter = netdev_priv(netdev);
1882
1883 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
1884 igb_vlan_mode(netdev, features);
1885
1886 if (!(changed & NETIF_F_RXALL))
1887 return 0;
1888
1889 netdev->features = features;
1890
1891 if (netif_running(netdev))
1892 igb_reinit_locked(adapter);
1893 else
1894 igb_reset(adapter);
1895
1896 return 0;
1897}
1898
1899static const struct net_device_ops igb_netdev_ops = {
1900 .ndo_open = igb_open,
1901 .ndo_stop = igb_close,
1902 .ndo_start_xmit = igb_xmit_frame,
1903 .ndo_get_stats64 = igb_get_stats64,
1904 .ndo_set_rx_mode = igb_set_rx_mode,
1905 .ndo_set_mac_address = igb_set_mac,
1906 .ndo_change_mtu = igb_change_mtu,
1907 .ndo_do_ioctl = igb_ioctl,
1908 .ndo_tx_timeout = igb_tx_timeout,
1909 .ndo_validate_addr = eth_validate_addr,
1910 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1911 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1912 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1913 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1914 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1915 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
1916 .ndo_get_vf_config = igb_ndo_get_vf_config,
1917#ifdef CONFIG_NET_POLL_CONTROLLER
1918 .ndo_poll_controller = igb_netpoll,
1919#endif
1920 .ndo_fix_features = igb_fix_features,
1921 .ndo_set_features = igb_set_features,
1922};
1923
1924/**
1925 * igb_set_fw_version - Configure version string for ethtool
1926 * @adapter: adapter struct
1927 **/
1928void igb_set_fw_version(struct igb_adapter *adapter)
1929{
1930 struct e1000_hw *hw = &adapter->hw;
1931 struct e1000_fw_version fw;
1932
1933 igb_get_fw_version(hw, &fw);
1934
1935 switch (hw->mac.type) {
1936 case e1000_i210:
1937 case e1000_i211:
1938 if (!(igb_get_flash_presence_i210(hw))) {
1939 snprintf(adapter->fw_version,
1940 sizeof(adapter->fw_version),
1941 "%2d.%2d-%d",
1942 fw.invm_major, fw.invm_minor,
1943 fw.invm_img_type);
1944 break;
1945 }
1946 /* fall through */
1947 default:
1948 /* if option is rom valid, display its version too */
1949 if (fw.or_valid) {
1950 snprintf(adapter->fw_version,
1951 sizeof(adapter->fw_version),
1952 "%d.%d, 0x%08x, %d.%d.%d",
1953 fw.eep_major, fw.eep_minor, fw.etrack_id,
1954 fw.or_major, fw.or_build, fw.or_patch);
1955 /* no option rom */
1956 } else if (fw.etrack_id != 0X0000) {
1957 snprintf(adapter->fw_version,
1958 sizeof(adapter->fw_version),
1959 "%d.%d, 0x%08x",
1960 fw.eep_major, fw.eep_minor, fw.etrack_id);
1961 } else {
1962 snprintf(adapter->fw_version,
1963 sizeof(adapter->fw_version),
1964 "%d.%d.%d",
1965 fw.eep_major, fw.eep_minor, fw.eep_build);
1966 }
1967 break;
1968 }
1969 return;
1970}
1971
1972/**
1973 * igb_init_i2c - Init I2C interface
1974 * @adapter: pointer to adapter structure
1975 **/
1976static s32 igb_init_i2c(struct igb_adapter *adapter)
1977{
1978 s32 status = E1000_SUCCESS;
1979
1980 /* I2C interface supported on i350 devices */
1981 if (adapter->hw.mac.type != e1000_i350)
1982 return E1000_SUCCESS;
1983
1984 /* Initialize the i2c bus which is controlled by the registers.
1985 * This bus will use the i2c_algo_bit structue that implements
1986 * the protocol through toggling of the 4 bits in the register.
1987 */
1988 adapter->i2c_adap.owner = THIS_MODULE;
1989 adapter->i2c_algo = igb_i2c_algo;
1990 adapter->i2c_algo.data = adapter;
1991 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
1992 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
1993 strlcpy(adapter->i2c_adap.name, "igb BB",
1994 sizeof(adapter->i2c_adap.name));
1995 status = i2c_bit_add_bus(&adapter->i2c_adap);
1996 return status;
1997}
1998
1999/**
2000 * igb_probe - Device Initialization Routine
2001 * @pdev: PCI device information struct
2002 * @ent: entry in igb_pci_tbl
2003 *
2004 * Returns 0 on success, negative on failure
2005 *
2006 * igb_probe initializes an adapter identified by a pci_dev structure.
2007 * The OS initialization, configuring of the adapter private structure,
2008 * and a hardware reset occur.
2009 **/
2010static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2011{
2012 struct net_device *netdev;
2013 struct igb_adapter *adapter;
2014 struct e1000_hw *hw;
2015 u16 eeprom_data = 0;
2016 s32 ret_val;
2017 static int global_quad_port_a; /* global quad port a indication */
2018 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2019 unsigned long mmio_start, mmio_len;
2020 int err, pci_using_dac;
2021 u8 part_str[E1000_PBANUM_LENGTH];
2022
2023 /* Catch broken hardware that put the wrong VF device ID in
2024 * the PCIe SR-IOV capability.
2025 */
2026 if (pdev->is_virtfn) {
2027 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
2028 pci_name(pdev), pdev->vendor, pdev->device);
2029 return -EINVAL;
2030 }
2031
2032 err = pci_enable_device_mem(pdev);
2033 if (err)
2034 return err;
2035
2036 pci_using_dac = 0;
2037 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
2038 if (!err) {
2039 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
2040 if (!err)
2041 pci_using_dac = 1;
2042 } else {
2043 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
2044 if (err) {
2045 err = dma_set_coherent_mask(&pdev->dev,
2046 DMA_BIT_MASK(32));
2047 if (err) {
2048 dev_err(&pdev->dev,
2049 "No usable DMA configuration, aborting\n");
2050 goto err_dma;
2051 }
2052 }
2053 }
2054
2055 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2056 IORESOURCE_MEM),
2057 igb_driver_name);
2058 if (err)
2059 goto err_pci_reg;
2060
2061 pci_enable_pcie_error_reporting(pdev);
2062
2063 pci_set_master(pdev);
2064 pci_save_state(pdev);
2065
2066 err = -ENOMEM;
2067 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2068 IGB_MAX_TX_QUEUES);
2069 if (!netdev)
2070 goto err_alloc_etherdev;
2071
2072 SET_NETDEV_DEV(netdev, &pdev->dev);
2073
2074 pci_set_drvdata(pdev, netdev);
2075 adapter = netdev_priv(netdev);
2076 adapter->netdev = netdev;
2077 adapter->pdev = pdev;
2078 hw = &adapter->hw;
2079 hw->back = adapter;
2080 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2081
2082 mmio_start = pci_resource_start(pdev, 0);
2083 mmio_len = pci_resource_len(pdev, 0);
2084
2085 err = -EIO;
2086 hw->hw_addr = ioremap(mmio_start, mmio_len);
2087 if (!hw->hw_addr)
2088 goto err_ioremap;
2089
2090 netdev->netdev_ops = &igb_netdev_ops;
2091 igb_set_ethtool_ops(netdev);
2092 netdev->watchdog_timeo = 5 * HZ;
2093
2094 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2095
2096 netdev->mem_start = mmio_start;
2097 netdev->mem_end = mmio_start + mmio_len;
2098
2099 /* PCI config space info */
2100 hw->vendor_id = pdev->vendor;
2101 hw->device_id = pdev->device;
2102 hw->revision_id = pdev->revision;
2103 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2104 hw->subsystem_device_id = pdev->subsystem_device;
2105
2106 /* Copy the default MAC, PHY and NVM function pointers */
2107 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2108 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2109 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2110 /* Initialize skew-specific constants */
2111 err = ei->get_invariants(hw);
2112 if (err)
2113 goto err_sw_init;
2114
2115 /* setup the private structure */
2116 err = igb_sw_init(adapter);
2117 if (err)
2118 goto err_sw_init;
2119
2120 igb_get_bus_info_pcie(hw);
2121
2122 hw->phy.autoneg_wait_to_complete = false;
2123
2124 /* Copper options */
2125 if (hw->phy.media_type == e1000_media_type_copper) {
2126 hw->phy.mdix = AUTO_ALL_MODES;
2127 hw->phy.disable_polarity_correction = false;
2128 hw->phy.ms_type = e1000_ms_hw_default;
2129 }
2130
2131 if (igb_check_reset_block(hw))
2132 dev_info(&pdev->dev,
2133 "PHY reset is blocked due to SOL/IDER session.\n");
2134
2135 /* features is initialized to 0 in allocation, it might have bits
2136 * set by igb_sw_init so we should use an or instead of an
2137 * assignment.
2138 */
2139 netdev->features |= NETIF_F_SG |
2140 NETIF_F_IP_CSUM |
2141 NETIF_F_IPV6_CSUM |
2142 NETIF_F_TSO |
2143 NETIF_F_TSO6 |
2144 NETIF_F_RXHASH |
2145 NETIF_F_RXCSUM |
2146 NETIF_F_HW_VLAN_CTAG_RX |
2147 NETIF_F_HW_VLAN_CTAG_TX;
2148
2149 /* copy netdev features into list of user selectable features */
2150 netdev->hw_features |= netdev->features;
2151 netdev->hw_features |= NETIF_F_RXALL;
2152
2153 /* set this bit last since it cannot be part of hw_features */
2154 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2155
2156 netdev->vlan_features |= NETIF_F_TSO |
2157 NETIF_F_TSO6 |
2158 NETIF_F_IP_CSUM |
2159 NETIF_F_IPV6_CSUM |
2160 NETIF_F_SG;
2161
2162 netdev->priv_flags |= IFF_SUPP_NOFCS;
2163
2164 if (pci_using_dac) {
2165 netdev->features |= NETIF_F_HIGHDMA;
2166 netdev->vlan_features |= NETIF_F_HIGHDMA;
2167 }
2168
2169 if (hw->mac.type >= e1000_82576) {
2170 netdev->hw_features |= NETIF_F_SCTP_CSUM;
2171 netdev->features |= NETIF_F_SCTP_CSUM;
2172 }
2173
2174 netdev->priv_flags |= IFF_UNICAST_FLT;
2175
2176 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2177
2178 /* before reading the NVM, reset the controller to put the device in a
2179 * known good starting state
2180 */
2181 hw->mac.ops.reset_hw(hw);
2182
2183 /* make sure the NVM is good , i211/i210 parts can have special NVM
2184 * that doesn't contain a checksum
2185 */
2186 switch (hw->mac.type) {
2187 case e1000_i210:
2188 case e1000_i211:
2189 if (igb_get_flash_presence_i210(hw)) {
2190 if (hw->nvm.ops.validate(hw) < 0) {
2191 dev_err(&pdev->dev,
2192 "The NVM Checksum Is Not Valid\n");
2193 err = -EIO;
2194 goto err_eeprom;
2195 }
2196 }
2197 break;
2198 default:
2199 if (hw->nvm.ops.validate(hw) < 0) {
2200 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2201 err = -EIO;
2202 goto err_eeprom;
2203 }
2204 break;
2205 }
2206
2207 /* copy the MAC address out of the NVM */
2208 if (hw->mac.ops.read_mac_addr(hw))
2209 dev_err(&pdev->dev, "NVM Read Error\n");
2210
2211 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2212
2213 if (!is_valid_ether_addr(netdev->dev_addr)) {
2214 dev_err(&pdev->dev, "Invalid MAC Address\n");
2215 err = -EIO;
2216 goto err_eeprom;
2217 }
2218
2219 /* get firmware version for ethtool -i */
2220 igb_set_fw_version(adapter);
2221
2222 setup_timer(&adapter->watchdog_timer, igb_watchdog,
2223 (unsigned long) adapter);
2224 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2225 (unsigned long) adapter);
2226
2227 INIT_WORK(&adapter->reset_task, igb_reset_task);
2228 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2229
2230 /* Initialize link properties that are user-changeable */
2231 adapter->fc_autoneg = true;
2232 hw->mac.autoneg = true;
2233 hw->phy.autoneg_advertised = 0x2f;
2234
2235 hw->fc.requested_mode = e1000_fc_default;
2236 hw->fc.current_mode = e1000_fc_default;
2237
2238 igb_validate_mdi_setting(hw);
2239
2240 /* By default, support wake on port A */
2241 if (hw->bus.func == 0)
2242 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2243
2244 /* Check the NVM for wake support on non-port A ports */
2245 if (hw->mac.type >= e1000_82580)
2246 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2247 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2248 &eeprom_data);
2249 else if (hw->bus.func == 1)
2250 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2251
2252 if (eeprom_data & IGB_EEPROM_APME)
2253 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2254
2255 /* now that we have the eeprom settings, apply the special cases where
2256 * the eeprom may be wrong or the board simply won't support wake on
2257 * lan on a particular port
2258 */
2259 switch (pdev->device) {
2260 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2261 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2262 break;
2263 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2264 case E1000_DEV_ID_82576_FIBER:
2265 case E1000_DEV_ID_82576_SERDES:
2266 /* Wake events only supported on port A for dual fiber
2267 * regardless of eeprom setting
2268 */
2269 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2270 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2271 break;
2272 case E1000_DEV_ID_82576_QUAD_COPPER:
2273 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2274 /* if quad port adapter, disable WoL on all but port A */
2275 if (global_quad_port_a != 0)
2276 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2277 else
2278 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2279 /* Reset for multiple quad port adapters */
2280 if (++global_quad_port_a == 4)
2281 global_quad_port_a = 0;
2282 break;
2283 default:
2284 /* If the device can't wake, don't set software support */
2285 if (!device_can_wakeup(&adapter->pdev->dev))
2286 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2287 }
2288
2289 /* initialize the wol settings based on the eeprom settings */
2290 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2291 adapter->wol |= E1000_WUFC_MAG;
2292
2293 /* Some vendors want WoL disabled by default, but still supported */
2294 if ((hw->mac.type == e1000_i350) &&
2295 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2296 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2297 adapter->wol = 0;
2298 }
2299
2300 device_set_wakeup_enable(&adapter->pdev->dev,
2301 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2302
2303 /* reset the hardware with the new settings */
2304 igb_reset(adapter);
2305
2306 /* Init the I2C interface */
2307 err = igb_init_i2c(adapter);
2308 if (err) {
2309 dev_err(&pdev->dev, "failed to init i2c interface\n");
2310 goto err_eeprom;
2311 }
2312
2313 /* let the f/w know that the h/w is now under the control of the
2314 * driver. */
2315 igb_get_hw_control(adapter);
2316
2317 strcpy(netdev->name, "eth%d");
2318 err = register_netdev(netdev);
2319 if (err)
2320 goto err_register;
2321
2322 /* carrier off reporting is important to ethtool even BEFORE open */
2323 netif_carrier_off(netdev);
2324
2325#ifdef CONFIG_IGB_DCA
2326 if (dca_add_requester(&pdev->dev) == 0) {
2327 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2328 dev_info(&pdev->dev, "DCA enabled\n");
2329 igb_setup_dca(adapter);
2330 }
2331
2332#endif
2333#ifdef CONFIG_IGB_HWMON
2334 /* Initialize the thermal sensor on i350 devices. */
2335 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2336 u16 ets_word;
2337
2338 /* Read the NVM to determine if this i350 device supports an
2339 * external thermal sensor.
2340 */
2341 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2342 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2343 adapter->ets = true;
2344 else
2345 adapter->ets = false;
2346 if (igb_sysfs_init(adapter))
2347 dev_err(&pdev->dev,
2348 "failed to allocate sysfs resources\n");
2349 } else {
2350 adapter->ets = false;
2351 }
2352#endif
2353 /* do hw tstamp init after resetting */
2354 igb_ptp_init(adapter);
2355
2356 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2357 /* print bus type/speed/width info, not applicable to i354 */
2358 if (hw->mac.type != e1000_i354) {
2359 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2360 netdev->name,
2361 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2362 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2363 "unknown"),
2364 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2365 "Width x4" :
2366 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2367 "Width x2" :
2368 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2369 "Width x1" : "unknown"), netdev->dev_addr);
2370 }
2371
2372 if ((hw->mac.type >= e1000_i210 ||
2373 igb_get_flash_presence_i210(hw))) {
2374 ret_val = igb_read_part_string(hw, part_str,
2375 E1000_PBANUM_LENGTH);
2376 } else {
2377 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2378 }
2379
2380 if (ret_val)
2381 strcpy(part_str, "Unknown");
2382 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2383 dev_info(&pdev->dev,
2384 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2385 adapter->msix_entries ? "MSI-X" :
2386 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2387 adapter->num_rx_queues, adapter->num_tx_queues);
2388 switch (hw->mac.type) {
2389 case e1000_i350:
2390 case e1000_i210:
2391 case e1000_i211:
2392 igb_set_eee_i350(hw);
2393 break;
2394 case e1000_i354:
2395 if (hw->phy.media_type == e1000_media_type_copper) {
2396 if ((rd32(E1000_CTRL_EXT) &
2397 E1000_CTRL_EXT_LINK_MODE_SGMII))
2398 igb_set_eee_i354(hw);
2399 }
2400 break;
2401 default:
2402 break;
2403 }
2404
2405 pm_runtime_put_noidle(&pdev->dev);
2406 return 0;
2407
2408err_register:
2409 igb_release_hw_control(adapter);
2410 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
2411err_eeprom:
2412 if (!igb_check_reset_block(hw))
2413 igb_reset_phy(hw);
2414
2415 if (hw->flash_address)
2416 iounmap(hw->flash_address);
2417err_sw_init:
2418 igb_clear_interrupt_scheme(adapter);
2419 iounmap(hw->hw_addr);
2420err_ioremap:
2421 free_netdev(netdev);
2422err_alloc_etherdev:
2423 pci_release_selected_regions(pdev,
2424 pci_select_bars(pdev, IORESOURCE_MEM));
2425err_pci_reg:
2426err_dma:
2427 pci_disable_device(pdev);
2428 return err;
2429}
2430
2431#ifdef CONFIG_PCI_IOV
2432static int igb_disable_sriov(struct pci_dev *pdev)
2433{
2434 struct net_device *netdev = pci_get_drvdata(pdev);
2435 struct igb_adapter *adapter = netdev_priv(netdev);
2436 struct e1000_hw *hw = &adapter->hw;
2437
2438 /* reclaim resources allocated to VFs */
2439 if (adapter->vf_data) {
2440 /* disable iov and allow time for transactions to clear */
2441 if (pci_vfs_assigned(pdev)) {
2442 dev_warn(&pdev->dev,
2443 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2444 return -EPERM;
2445 } else {
2446 pci_disable_sriov(pdev);
2447 msleep(500);
2448 }
2449
2450 kfree(adapter->vf_data);
2451 adapter->vf_data = NULL;
2452 adapter->vfs_allocated_count = 0;
2453 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2454 wrfl();
2455 msleep(100);
2456 dev_info(&pdev->dev, "IOV Disabled\n");
2457
2458 /* Re-enable DMA Coalescing flag since IOV is turned off */
2459 adapter->flags |= IGB_FLAG_DMAC;
2460 }
2461
2462 return 0;
2463}
2464
2465static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2466{
2467 struct net_device *netdev = pci_get_drvdata(pdev);
2468 struct igb_adapter *adapter = netdev_priv(netdev);
2469 int old_vfs = pci_num_vf(pdev);
2470 int err = 0;
2471 int i;
2472
2473 if (!adapter->msix_entries) {
2474 err = -EPERM;
2475 goto out;
2476 }
2477
2478 if (!num_vfs)
2479 goto out;
2480 else if (old_vfs && old_vfs == num_vfs)
2481 goto out;
2482 else if (old_vfs && old_vfs != num_vfs)
2483 err = igb_disable_sriov(pdev);
2484
2485 if (err)
2486 goto out;
2487
2488 if (num_vfs > 7) {
2489 err = -EPERM;
2490 goto out;
2491 }
2492
2493 adapter->vfs_allocated_count = num_vfs;
2494
2495 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2496 sizeof(struct vf_data_storage), GFP_KERNEL);
2497
2498 /* if allocation failed then we do not support SR-IOV */
2499 if (!adapter->vf_data) {
2500 adapter->vfs_allocated_count = 0;
2501 dev_err(&pdev->dev,
2502 "Unable to allocate memory for VF Data Storage\n");
2503 err = -ENOMEM;
2504 goto out;
2505 }
2506
2507 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2508 if (err)
2509 goto err_out;
2510
2511 dev_info(&pdev->dev, "%d VFs allocated\n",
2512 adapter->vfs_allocated_count);
2513 for (i = 0; i < adapter->vfs_allocated_count; i++)
2514 igb_vf_configure(adapter, i);
2515
2516 /* DMA Coalescing is not supported in IOV mode. */
2517 adapter->flags &= ~IGB_FLAG_DMAC;
2518 goto out;
2519
2520err_out:
2521 kfree(adapter->vf_data);
2522 adapter->vf_data = NULL;
2523 adapter->vfs_allocated_count = 0;
2524out:
2525 return err;
2526}
2527
2528#endif
2529/**
2530 * igb_remove_i2c - Cleanup I2C interface
2531 * @adapter: pointer to adapter structure
2532 **/
2533static void igb_remove_i2c(struct igb_adapter *adapter)
2534{
2535 /* free the adapter bus structure */
2536 i2c_del_adapter(&adapter->i2c_adap);
2537}
2538
2539/**
2540 * igb_remove - Device Removal Routine
2541 * @pdev: PCI device information struct
2542 *
2543 * igb_remove is called by the PCI subsystem to alert the driver
2544 * that it should release a PCI device. The could be caused by a
2545 * Hot-Plug event, or because the driver is going to be removed from
2546 * memory.
2547 **/
2548static void igb_remove(struct pci_dev *pdev)
2549{
2550 struct net_device *netdev = pci_get_drvdata(pdev);
2551 struct igb_adapter *adapter = netdev_priv(netdev);
2552 struct e1000_hw *hw = &adapter->hw;
2553
2554 pm_runtime_get_noresume(&pdev->dev);
2555#ifdef CONFIG_IGB_HWMON
2556 igb_sysfs_exit(adapter);
2557#endif
2558 igb_remove_i2c(adapter);
2559 igb_ptp_stop(adapter);
2560 /* The watchdog timer may be rescheduled, so explicitly
2561 * disable watchdog from being rescheduled.
2562 */
2563 set_bit(__IGB_DOWN, &adapter->state);
2564 del_timer_sync(&adapter->watchdog_timer);
2565 del_timer_sync(&adapter->phy_info_timer);
2566
2567 cancel_work_sync(&adapter->reset_task);
2568 cancel_work_sync(&adapter->watchdog_task);
2569
2570#ifdef CONFIG_IGB_DCA
2571 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2572 dev_info(&pdev->dev, "DCA disabled\n");
2573 dca_remove_requester(&pdev->dev);
2574 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2575 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2576 }
2577#endif
2578
2579 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2580 * would have already happened in close and is redundant.
2581 */
2582 igb_release_hw_control(adapter);
2583
2584 unregister_netdev(netdev);
2585
2586 igb_clear_interrupt_scheme(adapter);
2587
2588#ifdef CONFIG_PCI_IOV
2589 igb_disable_sriov(pdev);
2590#endif
2591
2592 iounmap(hw->hw_addr);
2593 if (hw->flash_address)
2594 iounmap(hw->flash_address);
2595 pci_release_selected_regions(pdev,
2596 pci_select_bars(pdev, IORESOURCE_MEM));
2597
2598 kfree(adapter->shadow_vfta);
2599 free_netdev(netdev);
2600
2601 pci_disable_pcie_error_reporting(pdev);
2602
2603 pci_disable_device(pdev);
2604}
2605
2606/**
2607 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2608 * @adapter: board private structure to initialize
2609 *
2610 * This function initializes the vf specific data storage and then attempts to
2611 * allocate the VFs. The reason for ordering it this way is because it is much
2612 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2613 * the memory for the VFs.
2614 **/
2615static void igb_probe_vfs(struct igb_adapter *adapter)
2616{
2617#ifdef CONFIG_PCI_IOV
2618 struct pci_dev *pdev = adapter->pdev;
2619 struct e1000_hw *hw = &adapter->hw;
2620
2621 /* Virtualization features not supported on i210 family. */
2622 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2623 return;
2624
2625 pci_sriov_set_totalvfs(pdev, 7);
2626 igb_enable_sriov(pdev, max_vfs);
2627
2628#endif /* CONFIG_PCI_IOV */
2629}
2630
2631static void igb_init_queue_configuration(struct igb_adapter *adapter)
2632{
2633 struct e1000_hw *hw = &adapter->hw;
2634 u32 max_rss_queues;
2635
2636 /* Determine the maximum number of RSS queues supported. */
2637 switch (hw->mac.type) {
2638 case e1000_i211:
2639 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2640 break;
2641 case e1000_82575:
2642 case e1000_i210:
2643 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2644 break;
2645 case e1000_i350:
2646 /* I350 cannot do RSS and SR-IOV at the same time */
2647 if (!!adapter->vfs_allocated_count) {
2648 max_rss_queues = 1;
2649 break;
2650 }
2651 /* fall through */
2652 case e1000_82576:
2653 if (!!adapter->vfs_allocated_count) {
2654 max_rss_queues = 2;
2655 break;
2656 }
2657 /* fall through */
2658 case e1000_82580:
2659 case e1000_i354:
2660 default:
2661 max_rss_queues = IGB_MAX_RX_QUEUES;
2662 break;
2663 }
2664
2665 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2666
2667 /* Determine if we need to pair queues. */
2668 switch (hw->mac.type) {
2669 case e1000_82575:
2670 case e1000_i211:
2671 /* Device supports enough interrupts without queue pairing. */
2672 break;
2673 case e1000_82576:
2674 /* If VFs are going to be allocated with RSS queues then we
2675 * should pair the queues in order to conserve interrupts due
2676 * to limited supply.
2677 */
2678 if ((adapter->rss_queues > 1) &&
2679 (adapter->vfs_allocated_count > 6))
2680 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2681 /* fall through */
2682 case e1000_82580:
2683 case e1000_i350:
2684 case e1000_i354:
2685 case e1000_i210:
2686 default:
2687 /* If rss_queues > half of max_rss_queues, pair the queues in
2688 * order to conserve interrupts due to limited supply.
2689 */
2690 if (adapter->rss_queues > (max_rss_queues / 2))
2691 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2692 break;
2693 }
2694}
2695
2696/**
2697 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2698 * @adapter: board private structure to initialize
2699 *
2700 * igb_sw_init initializes the Adapter private data structure.
2701 * Fields are initialized based on PCI device information and
2702 * OS network device settings (MTU size).
2703 **/
2704static int igb_sw_init(struct igb_adapter *adapter)
2705{
2706 struct e1000_hw *hw = &adapter->hw;
2707 struct net_device *netdev = adapter->netdev;
2708 struct pci_dev *pdev = adapter->pdev;
2709
2710 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2711
2712 /* set default ring sizes */
2713 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2714 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2715
2716 /* set default ITR values */
2717 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2718 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2719
2720 /* set default work limits */
2721 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2722
2723 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2724 VLAN_HLEN;
2725 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2726
2727 spin_lock_init(&adapter->stats64_lock);
2728#ifdef CONFIG_PCI_IOV
2729 switch (hw->mac.type) {
2730 case e1000_82576:
2731 case e1000_i350:
2732 if (max_vfs > 7) {
2733 dev_warn(&pdev->dev,
2734 "Maximum of 7 VFs per PF, using max\n");
2735 max_vfs = adapter->vfs_allocated_count = 7;
2736 } else
2737 adapter->vfs_allocated_count = max_vfs;
2738 if (adapter->vfs_allocated_count)
2739 dev_warn(&pdev->dev,
2740 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2741 break;
2742 default:
2743 break;
2744 }
2745#endif /* CONFIG_PCI_IOV */
2746
2747 igb_init_queue_configuration(adapter);
2748
2749 /* Setup and initialize a copy of the hw vlan table array */
2750 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2751 GFP_ATOMIC);
2752
2753 /* This call may decrease the number of queues */
2754 if (igb_init_interrupt_scheme(adapter, true)) {
2755 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2756 return -ENOMEM;
2757 }
2758
2759 igb_probe_vfs(adapter);
2760
2761 /* Explicitly disable IRQ since the NIC can be in any state. */
2762 igb_irq_disable(adapter);
2763
2764 if (hw->mac.type >= e1000_i350)
2765 adapter->flags &= ~IGB_FLAG_DMAC;
2766
2767 set_bit(__IGB_DOWN, &adapter->state);
2768 return 0;
2769}
2770
2771/**
2772 * igb_open - Called when a network interface is made active
2773 * @netdev: network interface device structure
2774 *
2775 * Returns 0 on success, negative value on failure
2776 *
2777 * The open entry point is called when a network interface is made
2778 * active by the system (IFF_UP). At this point all resources needed
2779 * for transmit and receive operations are allocated, the interrupt
2780 * handler is registered with the OS, the watchdog timer is started,
2781 * and the stack is notified that the interface is ready.
2782 **/
2783static int __igb_open(struct net_device *netdev, bool resuming)
2784{
2785 struct igb_adapter *adapter = netdev_priv(netdev);
2786 struct e1000_hw *hw = &adapter->hw;
2787 struct pci_dev *pdev = adapter->pdev;
2788 int err;
2789 int i;
2790
2791 /* disallow open during test */
2792 if (test_bit(__IGB_TESTING, &adapter->state)) {
2793 WARN_ON(resuming);
2794 return -EBUSY;
2795 }
2796
2797 if (!resuming)
2798 pm_runtime_get_sync(&pdev->dev);
2799
2800 netif_carrier_off(netdev);
2801
2802 /* allocate transmit descriptors */
2803 err = igb_setup_all_tx_resources(adapter);
2804 if (err)
2805 goto err_setup_tx;
2806
2807 /* allocate receive descriptors */
2808 err = igb_setup_all_rx_resources(adapter);
2809 if (err)
2810 goto err_setup_rx;
2811
2812 igb_power_up_link(adapter);
2813
2814 /* before we allocate an interrupt, we must be ready to handle it.
2815 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2816 * as soon as we call pci_request_irq, so we have to setup our
2817 * clean_rx handler before we do so.
2818 */
2819 igb_configure(adapter);
2820
2821 err = igb_request_irq(adapter);
2822 if (err)
2823 goto err_req_irq;
2824
2825 /* Notify the stack of the actual queue counts. */
2826 err = netif_set_real_num_tx_queues(adapter->netdev,
2827 adapter->num_tx_queues);
2828 if (err)
2829 goto err_set_queues;
2830
2831 err = netif_set_real_num_rx_queues(adapter->netdev,
2832 adapter->num_rx_queues);
2833 if (err)
2834 goto err_set_queues;
2835
2836 /* From here on the code is the same as igb_up() */
2837 clear_bit(__IGB_DOWN, &adapter->state);
2838
2839 for (i = 0; i < adapter->num_q_vectors; i++)
2840 napi_enable(&(adapter->q_vector[i]->napi));
2841
2842 /* Clear any pending interrupts. */
2843 rd32(E1000_ICR);
2844
2845 igb_irq_enable(adapter);
2846
2847 /* notify VFs that reset has been completed */
2848 if (adapter->vfs_allocated_count) {
2849 u32 reg_data = rd32(E1000_CTRL_EXT);
2850 reg_data |= E1000_CTRL_EXT_PFRSTD;
2851 wr32(E1000_CTRL_EXT, reg_data);
2852 }
2853
2854 netif_tx_start_all_queues(netdev);
2855
2856 if (!resuming)
2857 pm_runtime_put(&pdev->dev);
2858
2859 /* start the watchdog. */
2860 hw->mac.get_link_status = 1;
2861 schedule_work(&adapter->watchdog_task);
2862
2863 return 0;
2864
2865err_set_queues:
2866 igb_free_irq(adapter);
2867err_req_irq:
2868 igb_release_hw_control(adapter);
2869 igb_power_down_link(adapter);
2870 igb_free_all_rx_resources(adapter);
2871err_setup_rx:
2872 igb_free_all_tx_resources(adapter);
2873err_setup_tx:
2874 igb_reset(adapter);
2875 if (!resuming)
2876 pm_runtime_put(&pdev->dev);
2877
2878 return err;
2879}
2880
2881static int igb_open(struct net_device *netdev)
2882{
2883 return __igb_open(netdev, false);
2884}
2885
2886/**
2887 * igb_close - Disables a network interface
2888 * @netdev: network interface device structure
2889 *
2890 * Returns 0, this is not allowed to fail
2891 *
2892 * The close entry point is called when an interface is de-activated
2893 * by the OS. The hardware is still under the driver's control, but
2894 * needs to be disabled. A global MAC reset is issued to stop the
2895 * hardware, and all transmit and receive resources are freed.
2896 **/
2897static int __igb_close(struct net_device *netdev, bool suspending)
2898{
2899 struct igb_adapter *adapter = netdev_priv(netdev);
2900 struct pci_dev *pdev = adapter->pdev;
2901
2902 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2903
2904 if (!suspending)
2905 pm_runtime_get_sync(&pdev->dev);
2906
2907 igb_down(adapter);
2908 igb_free_irq(adapter);
2909
2910 igb_free_all_tx_resources(adapter);
2911 igb_free_all_rx_resources(adapter);
2912
2913 if (!suspending)
2914 pm_runtime_put_sync(&pdev->dev);
2915 return 0;
2916}
2917
2918static int igb_close(struct net_device *netdev)
2919{
2920 return __igb_close(netdev, false);
2921}
2922
2923/**
2924 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2925 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2926 *
2927 * Return 0 on success, negative on failure
2928 **/
2929int igb_setup_tx_resources(struct igb_ring *tx_ring)
2930{
2931 struct device *dev = tx_ring->dev;
2932 int size;
2933
2934 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
2935
2936 tx_ring->tx_buffer_info = vzalloc(size);
2937 if (!tx_ring->tx_buffer_info)
2938 goto err;
2939
2940 /* round up to nearest 4K */
2941 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
2942 tx_ring->size = ALIGN(tx_ring->size, 4096);
2943
2944 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2945 &tx_ring->dma, GFP_KERNEL);
2946 if (!tx_ring->desc)
2947 goto err;
2948
2949 tx_ring->next_to_use = 0;
2950 tx_ring->next_to_clean = 0;
2951
2952 return 0;
2953
2954err:
2955 vfree(tx_ring->tx_buffer_info);
2956 tx_ring->tx_buffer_info = NULL;
2957 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
2958 return -ENOMEM;
2959}
2960
2961/**
2962 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2963 * (Descriptors) for all queues
2964 * @adapter: board private structure
2965 *
2966 * Return 0 on success, negative on failure
2967 **/
2968static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2969{
2970 struct pci_dev *pdev = adapter->pdev;
2971 int i, err = 0;
2972
2973 for (i = 0; i < adapter->num_tx_queues; i++) {
2974 err = igb_setup_tx_resources(adapter->tx_ring[i]);
2975 if (err) {
2976 dev_err(&pdev->dev,
2977 "Allocation for Tx Queue %u failed\n", i);
2978 for (i--; i >= 0; i--)
2979 igb_free_tx_resources(adapter->tx_ring[i]);
2980 break;
2981 }
2982 }
2983
2984 return err;
2985}
2986
2987/**
2988 * igb_setup_tctl - configure the transmit control registers
2989 * @adapter: Board private structure
2990 **/
2991void igb_setup_tctl(struct igb_adapter *adapter)
2992{
2993 struct e1000_hw *hw = &adapter->hw;
2994 u32 tctl;
2995
2996 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2997 wr32(E1000_TXDCTL(0), 0);
2998
2999 /* Program the Transmit Control Register */
3000 tctl = rd32(E1000_TCTL);
3001 tctl &= ~E1000_TCTL_CT;
3002 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3003 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3004
3005 igb_config_collision_dist(hw);
3006
3007 /* Enable transmits */
3008 tctl |= E1000_TCTL_EN;
3009
3010 wr32(E1000_TCTL, tctl);
3011}
3012
3013/**
3014 * igb_configure_tx_ring - Configure transmit ring after Reset
3015 * @adapter: board private structure
3016 * @ring: tx ring to configure
3017 *
3018 * Configure a transmit ring after a reset.
3019 **/
3020void igb_configure_tx_ring(struct igb_adapter *adapter,
3021 struct igb_ring *ring)
3022{
3023 struct e1000_hw *hw = &adapter->hw;
3024 u32 txdctl = 0;
3025 u64 tdba = ring->dma;
3026 int reg_idx = ring->reg_idx;
3027
3028 /* disable the queue */
3029 wr32(E1000_TXDCTL(reg_idx), 0);
3030 wrfl();
3031 mdelay(10);
3032
3033 wr32(E1000_TDLEN(reg_idx),
3034 ring->count * sizeof(union e1000_adv_tx_desc));
3035 wr32(E1000_TDBAL(reg_idx),
3036 tdba & 0x00000000ffffffffULL);
3037 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3038
3039 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
3040 wr32(E1000_TDH(reg_idx), 0);
3041 writel(0, ring->tail);
3042
3043 txdctl |= IGB_TX_PTHRESH;
3044 txdctl |= IGB_TX_HTHRESH << 8;
3045 txdctl |= IGB_TX_WTHRESH << 16;
3046
3047 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3048 wr32(E1000_TXDCTL(reg_idx), txdctl);
3049}
3050
3051/**
3052 * igb_configure_tx - Configure transmit Unit after Reset
3053 * @adapter: board private structure
3054 *
3055 * Configure the Tx unit of the MAC after a reset.
3056 **/
3057static void igb_configure_tx(struct igb_adapter *adapter)
3058{
3059 int i;
3060
3061 for (i = 0; i < adapter->num_tx_queues; i++)
3062 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
3063}
3064
3065/**
3066 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3067 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
3068 *
3069 * Returns 0 on success, negative on failure
3070 **/
3071int igb_setup_rx_resources(struct igb_ring *rx_ring)
3072{
3073 struct device *dev = rx_ring->dev;
3074 int size;
3075
3076 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3077
3078 rx_ring->rx_buffer_info = vzalloc(size);
3079 if (!rx_ring->rx_buffer_info)
3080 goto err;
3081
3082 /* Round up to nearest 4K */
3083 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3084 rx_ring->size = ALIGN(rx_ring->size, 4096);
3085
3086 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3087 &rx_ring->dma, GFP_KERNEL);
3088 if (!rx_ring->desc)
3089 goto err;
3090
3091 rx_ring->next_to_alloc = 0;
3092 rx_ring->next_to_clean = 0;
3093 rx_ring->next_to_use = 0;
3094
3095 return 0;
3096
3097err:
3098 vfree(rx_ring->rx_buffer_info);
3099 rx_ring->rx_buffer_info = NULL;
3100 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3101 return -ENOMEM;
3102}
3103
3104/**
3105 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3106 * (Descriptors) for all queues
3107 * @adapter: board private structure
3108 *
3109 * Return 0 on success, negative on failure
3110 **/
3111static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3112{
3113 struct pci_dev *pdev = adapter->pdev;
3114 int i, err = 0;
3115
3116 for (i = 0; i < adapter->num_rx_queues; i++) {
3117 err = igb_setup_rx_resources(adapter->rx_ring[i]);
3118 if (err) {
3119 dev_err(&pdev->dev,
3120 "Allocation for Rx Queue %u failed\n", i);
3121 for (i--; i >= 0; i--)
3122 igb_free_rx_resources(adapter->rx_ring[i]);
3123 break;
3124 }
3125 }
3126
3127 return err;
3128}
3129
3130/**
3131 * igb_setup_mrqc - configure the multiple receive queue control registers
3132 * @adapter: Board private structure
3133 **/
3134static void igb_setup_mrqc(struct igb_adapter *adapter)
3135{
3136 struct e1000_hw *hw = &adapter->hw;
3137 u32 mrqc, rxcsum;
3138 u32 j, num_rx_queues;
3139 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3140 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3141 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3142 0xFA01ACBE };
3143
3144 /* Fill out hash function seeds */
3145 for (j = 0; j < 10; j++)
3146 wr32(E1000_RSSRK(j), rsskey[j]);
3147
3148 num_rx_queues = adapter->rss_queues;
3149
3150 switch (hw->mac.type) {
3151 case e1000_82576:
3152 /* 82576 supports 2 RSS queues for SR-IOV */
3153 if (adapter->vfs_allocated_count)
3154 num_rx_queues = 2;
3155 break;
3156 default:
3157 break;
3158 }
3159
3160 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3161 for (j = 0; j < IGB_RETA_SIZE; j++)
3162 adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE;
3163 adapter->rss_indir_tbl_init = num_rx_queues;
3164 }
3165 igb_write_rss_indir_tbl(adapter);
3166
3167 /* Disable raw packet checksumming so that RSS hash is placed in
3168 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3169 * offloads as they are enabled by default
3170 */
3171 rxcsum = rd32(E1000_RXCSUM);
3172 rxcsum |= E1000_RXCSUM_PCSD;
3173
3174 if (adapter->hw.mac.type >= e1000_82576)
3175 /* Enable Receive Checksum Offload for SCTP */
3176 rxcsum |= E1000_RXCSUM_CRCOFL;
3177
3178 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3179 wr32(E1000_RXCSUM, rxcsum);
3180
3181 /* Generate RSS hash based on packet types, TCP/UDP
3182 * port numbers and/or IPv4/v6 src and dst addresses
3183 */
3184 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3185 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3186 E1000_MRQC_RSS_FIELD_IPV6 |
3187 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3188 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3189
3190 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3191 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3192 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3193 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3194
3195 /* If VMDq is enabled then we set the appropriate mode for that, else
3196 * we default to RSS so that an RSS hash is calculated per packet even
3197 * if we are only using one queue
3198 */
3199 if (adapter->vfs_allocated_count) {
3200 if (hw->mac.type > e1000_82575) {
3201 /* Set the default pool for the PF's first queue */
3202 u32 vtctl = rd32(E1000_VT_CTL);
3203 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3204 E1000_VT_CTL_DISABLE_DEF_POOL);
3205 vtctl |= adapter->vfs_allocated_count <<
3206 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3207 wr32(E1000_VT_CTL, vtctl);
3208 }
3209 if (adapter->rss_queues > 1)
3210 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
3211 else
3212 mrqc |= E1000_MRQC_ENABLE_VMDQ;
3213 } else {
3214 if (hw->mac.type != e1000_i211)
3215 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
3216 }
3217 igb_vmm_control(adapter);
3218
3219 wr32(E1000_MRQC, mrqc);
3220}
3221
3222/**
3223 * igb_setup_rctl - configure the receive control registers
3224 * @adapter: Board private structure
3225 **/
3226void igb_setup_rctl(struct igb_adapter *adapter)
3227{
3228 struct e1000_hw *hw = &adapter->hw;
3229 u32 rctl;
3230
3231 rctl = rd32(E1000_RCTL);
3232
3233 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3234 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
3235
3236 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
3237 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3238
3239 /* enable stripping of CRC. It's unlikely this will break BMC
3240 * redirection as it did with e1000. Newer features require
3241 * that the HW strips the CRC.
3242 */
3243 rctl |= E1000_RCTL_SECRC;
3244
3245 /* disable store bad packets and clear size bits. */
3246 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
3247
3248 /* enable LPE to prevent packets larger than max_frame_size */
3249 rctl |= E1000_RCTL_LPE;
3250
3251 /* disable queue 0 to prevent tail write w/o re-config */
3252 wr32(E1000_RXDCTL(0), 0);
3253
3254 /* Attention!!! For SR-IOV PF driver operations you must enable
3255 * queue drop for all VF and PF queues to prevent head of line blocking
3256 * if an un-trusted VF does not provide descriptors to hardware.
3257 */
3258 if (adapter->vfs_allocated_count) {
3259 /* set all queue drop enable bits */
3260 wr32(E1000_QDE, ALL_QUEUES);
3261 }
3262
3263 /* This is useful for sniffing bad packets. */
3264 if (adapter->netdev->features & NETIF_F_RXALL) {
3265 /* UPE and MPE will be handled by normal PROMISC logic
3266 * in e1000e_set_rx_mode
3267 */
3268 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3269 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3270 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3271
3272 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3273 E1000_RCTL_DPF | /* Allow filtered pause */
3274 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3275 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3276 * and that breaks VLANs.
3277 */
3278 }
3279
3280 wr32(E1000_RCTL, rctl);
3281}
3282
3283static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3284 int vfn)
3285{
3286 struct e1000_hw *hw = &adapter->hw;
3287 u32 vmolr;
3288
3289 /* if it isn't the PF check to see if VFs are enabled and
3290 * increase the size to support vlan tags
3291 */
3292 if (vfn < adapter->vfs_allocated_count &&
3293 adapter->vf_data[vfn].vlans_enabled)
3294 size += VLAN_TAG_SIZE;
3295
3296 vmolr = rd32(E1000_VMOLR(vfn));
3297 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3298 vmolr |= size | E1000_VMOLR_LPE;
3299 wr32(E1000_VMOLR(vfn), vmolr);
3300
3301 return 0;
3302}
3303
3304/**
3305 * igb_rlpml_set - set maximum receive packet size
3306 * @adapter: board private structure
3307 *
3308 * Configure maximum receivable packet size.
3309 **/
3310static void igb_rlpml_set(struct igb_adapter *adapter)
3311{
3312 u32 max_frame_size = adapter->max_frame_size;
3313 struct e1000_hw *hw = &adapter->hw;
3314 u16 pf_id = adapter->vfs_allocated_count;
3315
3316 if (pf_id) {
3317 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3318 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
3319 * to our max jumbo frame size, in case we need to enable
3320 * jumbo frames on one of the rings later.
3321 * This will not pass over-length frames into the default
3322 * queue because it's gated by the VMOLR.RLPML.
3323 */
3324 max_frame_size = MAX_JUMBO_FRAME_SIZE;
3325 }
3326
3327 wr32(E1000_RLPML, max_frame_size);
3328}
3329
3330static inline void igb_set_vmolr(struct igb_adapter *adapter,
3331 int vfn, bool aupe)
3332{
3333 struct e1000_hw *hw = &adapter->hw;
3334 u32 vmolr;
3335
3336 /* This register exists only on 82576 and newer so if we are older then
3337 * we should exit and do nothing
3338 */
3339 if (hw->mac.type < e1000_82576)
3340 return;
3341
3342 vmolr = rd32(E1000_VMOLR(vfn));
3343 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3344 if (aupe)
3345 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3346 else
3347 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3348
3349 /* clear all bits that might not be set */
3350 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3351
3352 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3353 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3354 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
3355 * multicast packets
3356 */
3357 if (vfn <= adapter->vfs_allocated_count)
3358 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3359
3360 wr32(E1000_VMOLR(vfn), vmolr);
3361}
3362
3363/**
3364 * igb_configure_rx_ring - Configure a receive ring after Reset
3365 * @adapter: board private structure
3366 * @ring: receive ring to be configured
3367 *
3368 * Configure the Rx unit of the MAC after a reset.
3369 **/
3370void igb_configure_rx_ring(struct igb_adapter *adapter,
3371 struct igb_ring *ring)
3372{
3373 struct e1000_hw *hw = &adapter->hw;
3374 u64 rdba = ring->dma;
3375 int reg_idx = ring->reg_idx;
3376 u32 srrctl = 0, rxdctl = 0;
3377
3378 /* disable the queue */
3379 wr32(E1000_RXDCTL(reg_idx), 0);
3380
3381 /* Set DMA base address registers */
3382 wr32(E1000_RDBAL(reg_idx),
3383 rdba & 0x00000000ffffffffULL);
3384 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3385 wr32(E1000_RDLEN(reg_idx),
3386 ring->count * sizeof(union e1000_adv_rx_desc));
3387
3388 /* initialize head and tail */
3389 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3390 wr32(E1000_RDH(reg_idx), 0);
3391 writel(0, ring->tail);
3392
3393 /* set descriptor configuration */
3394 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3395 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3396 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3397 if (hw->mac.type >= e1000_82580)
3398 srrctl |= E1000_SRRCTL_TIMESTAMP;
3399 /* Only set Drop Enable if we are supporting multiple queues */
3400 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3401 srrctl |= E1000_SRRCTL_DROP_EN;
3402
3403 wr32(E1000_SRRCTL(reg_idx), srrctl);
3404
3405 /* set filtering for VMDQ pools */
3406 igb_set_vmolr(adapter, reg_idx & 0x7, true);
3407
3408 rxdctl |= IGB_RX_PTHRESH;
3409 rxdctl |= IGB_RX_HTHRESH << 8;
3410 rxdctl |= IGB_RX_WTHRESH << 16;
3411
3412 /* enable receive descriptor fetching */
3413 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3414 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3415}
3416
3417/**
3418 * igb_configure_rx - Configure receive Unit after Reset
3419 * @adapter: board private structure
3420 *
3421 * Configure the Rx unit of the MAC after a reset.
3422 **/
3423static void igb_configure_rx(struct igb_adapter *adapter)
3424{
3425 int i;
3426
3427 /* set UTA to appropriate mode */
3428 igb_set_uta(adapter);
3429
3430 /* set the correct pool for the PF default MAC address in entry 0 */
3431 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3432 adapter->vfs_allocated_count);
3433
3434 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3435 * the Base and Length of the Rx Descriptor Ring
3436 */
3437 for (i = 0; i < adapter->num_rx_queues; i++)
3438 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3439}
3440
3441/**
3442 * igb_free_tx_resources - Free Tx Resources per Queue
3443 * @tx_ring: Tx descriptor ring for a specific queue
3444 *
3445 * Free all transmit software resources
3446 **/
3447void igb_free_tx_resources(struct igb_ring *tx_ring)
3448{
3449 igb_clean_tx_ring(tx_ring);
3450
3451 vfree(tx_ring->tx_buffer_info);
3452 tx_ring->tx_buffer_info = NULL;
3453
3454 /* if not set, then don't free */
3455 if (!tx_ring->desc)
3456 return;
3457
3458 dma_free_coherent(tx_ring->dev, tx_ring->size,
3459 tx_ring->desc, tx_ring->dma);
3460
3461 tx_ring->desc = NULL;
3462}
3463
3464/**
3465 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3466 * @adapter: board private structure
3467 *
3468 * Free all transmit software resources
3469 **/
3470static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3471{
3472 int i;
3473
3474 for (i = 0; i < adapter->num_tx_queues; i++)
3475 igb_free_tx_resources(adapter->tx_ring[i]);
3476}
3477
3478void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3479 struct igb_tx_buffer *tx_buffer)
3480{
3481 if (tx_buffer->skb) {
3482 dev_kfree_skb_any(tx_buffer->skb);
3483 if (dma_unmap_len(tx_buffer, len))
3484 dma_unmap_single(ring->dev,
3485 dma_unmap_addr(tx_buffer, dma),
3486 dma_unmap_len(tx_buffer, len),
3487 DMA_TO_DEVICE);
3488 } else if (dma_unmap_len(tx_buffer, len)) {
3489 dma_unmap_page(ring->dev,
3490 dma_unmap_addr(tx_buffer, dma),
3491 dma_unmap_len(tx_buffer, len),
3492 DMA_TO_DEVICE);
3493 }
3494 tx_buffer->next_to_watch = NULL;
3495 tx_buffer->skb = NULL;
3496 dma_unmap_len_set(tx_buffer, len, 0);
3497 /* buffer_info must be completely set up in the transmit path */
3498}
3499
3500/**
3501 * igb_clean_tx_ring - Free Tx Buffers
3502 * @tx_ring: ring to be cleaned
3503 **/
3504static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3505{
3506 struct igb_tx_buffer *buffer_info;
3507 unsigned long size;
3508 u16 i;
3509
3510 if (!tx_ring->tx_buffer_info)
3511 return;
3512 /* Free all the Tx ring sk_buffs */
3513
3514 for (i = 0; i < tx_ring->count; i++) {
3515 buffer_info = &tx_ring->tx_buffer_info[i];
3516 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3517 }
3518
3519 netdev_tx_reset_queue(txring_txq(tx_ring));
3520
3521 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3522 memset(tx_ring->tx_buffer_info, 0, size);
3523
3524 /* Zero out the descriptor ring */
3525 memset(tx_ring->desc, 0, tx_ring->size);
3526
3527 tx_ring->next_to_use = 0;
3528 tx_ring->next_to_clean = 0;
3529}
3530
3531/**
3532 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3533 * @adapter: board private structure
3534 **/
3535static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3536{
3537 int i;
3538
3539 for (i = 0; i < adapter->num_tx_queues; i++)
3540 igb_clean_tx_ring(adapter->tx_ring[i]);
3541}
3542
3543/**
3544 * igb_free_rx_resources - Free Rx Resources
3545 * @rx_ring: ring to clean the resources from
3546 *
3547 * Free all receive software resources
3548 **/
3549void igb_free_rx_resources(struct igb_ring *rx_ring)
3550{
3551 igb_clean_rx_ring(rx_ring);
3552
3553 vfree(rx_ring->rx_buffer_info);
3554 rx_ring->rx_buffer_info = NULL;
3555
3556 /* if not set, then don't free */
3557 if (!rx_ring->desc)
3558 return;
3559
3560 dma_free_coherent(rx_ring->dev, rx_ring->size,
3561 rx_ring->desc, rx_ring->dma);
3562
3563 rx_ring->desc = NULL;
3564}
3565
3566/**
3567 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3568 * @adapter: board private structure
3569 *
3570 * Free all receive software resources
3571 **/
3572static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3573{
3574 int i;
3575
3576 for (i = 0; i < adapter->num_rx_queues; i++)
3577 igb_free_rx_resources(adapter->rx_ring[i]);
3578}
3579
3580/**
3581 * igb_clean_rx_ring - Free Rx Buffers per Queue
3582 * @rx_ring: ring to free buffers from
3583 **/
3584static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3585{
3586 unsigned long size;
3587 u16 i;
3588
3589 if (rx_ring->skb)
3590 dev_kfree_skb(rx_ring->skb);
3591 rx_ring->skb = NULL;
3592
3593 if (!rx_ring->rx_buffer_info)
3594 return;
3595
3596 /* Free all the Rx ring sk_buffs */
3597 for (i = 0; i < rx_ring->count; i++) {
3598 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3599
3600 if (!buffer_info->page)
3601 continue;
3602
3603 dma_unmap_page(rx_ring->dev,
3604 buffer_info->dma,
3605 PAGE_SIZE,
3606 DMA_FROM_DEVICE);
3607 __free_page(buffer_info->page);
3608
3609 buffer_info->page = NULL;
3610 }
3611
3612 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3613 memset(rx_ring->rx_buffer_info, 0, size);
3614
3615 /* Zero out the descriptor ring */
3616 memset(rx_ring->desc, 0, rx_ring->size);
3617
3618 rx_ring->next_to_alloc = 0;
3619 rx_ring->next_to_clean = 0;
3620 rx_ring->next_to_use = 0;
3621}
3622
3623/**
3624 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3625 * @adapter: board private structure
3626 **/
3627static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3628{
3629 int i;
3630
3631 for (i = 0; i < adapter->num_rx_queues; i++)
3632 igb_clean_rx_ring(adapter->rx_ring[i]);
3633}
3634
3635/**
3636 * igb_set_mac - Change the Ethernet Address of the NIC
3637 * @netdev: network interface device structure
3638 * @p: pointer to an address structure
3639 *
3640 * Returns 0 on success, negative on failure
3641 **/
3642static int igb_set_mac(struct net_device *netdev, void *p)
3643{
3644 struct igb_adapter *adapter = netdev_priv(netdev);
3645 struct e1000_hw *hw = &adapter->hw;
3646 struct sockaddr *addr = p;
3647
3648 if (!is_valid_ether_addr(addr->sa_data))
3649 return -EADDRNOTAVAIL;
3650
3651 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3652 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3653
3654 /* set the correct pool for the new PF MAC address in entry 0 */
3655 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3656 adapter->vfs_allocated_count);
3657
3658 return 0;
3659}
3660
3661/**
3662 * igb_write_mc_addr_list - write multicast addresses to MTA
3663 * @netdev: network interface device structure
3664 *
3665 * Writes multicast address list to the MTA hash table.
3666 * Returns: -ENOMEM on failure
3667 * 0 on no addresses written
3668 * X on writing X addresses to MTA
3669 **/
3670static int igb_write_mc_addr_list(struct net_device *netdev)
3671{
3672 struct igb_adapter *adapter = netdev_priv(netdev);
3673 struct e1000_hw *hw = &adapter->hw;
3674 struct netdev_hw_addr *ha;
3675 u8 *mta_list;
3676 int i;
3677
3678 if (netdev_mc_empty(netdev)) {
3679 /* nothing to program, so clear mc list */
3680 igb_update_mc_addr_list(hw, NULL, 0);
3681 igb_restore_vf_multicasts(adapter);
3682 return 0;
3683 }
3684
3685 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3686 if (!mta_list)
3687 return -ENOMEM;
3688
3689 /* The shared function expects a packed array of only addresses. */
3690 i = 0;
3691 netdev_for_each_mc_addr(ha, netdev)
3692 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3693
3694 igb_update_mc_addr_list(hw, mta_list, i);
3695 kfree(mta_list);
3696
3697 return netdev_mc_count(netdev);
3698}
3699
3700/**
3701 * igb_write_uc_addr_list - write unicast addresses to RAR table
3702 * @netdev: network interface device structure
3703 *
3704 * Writes unicast address list to the RAR table.
3705 * Returns: -ENOMEM on failure/insufficient address space
3706 * 0 on no addresses written
3707 * X on writing X addresses to the RAR table
3708 **/
3709static int igb_write_uc_addr_list(struct net_device *netdev)
3710{
3711 struct igb_adapter *adapter = netdev_priv(netdev);
3712 struct e1000_hw *hw = &adapter->hw;
3713 unsigned int vfn = adapter->vfs_allocated_count;
3714 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3715 int count = 0;
3716
3717 /* return ENOMEM indicating insufficient memory for addresses */
3718 if (netdev_uc_count(netdev) > rar_entries)
3719 return -ENOMEM;
3720
3721 if (!netdev_uc_empty(netdev) && rar_entries) {
3722 struct netdev_hw_addr *ha;
3723
3724 netdev_for_each_uc_addr(ha, netdev) {
3725 if (!rar_entries)
3726 break;
3727 igb_rar_set_qsel(adapter, ha->addr,
3728 rar_entries--,
3729 vfn);
3730 count++;
3731 }
3732 }
3733 /* write the addresses in reverse order to avoid write combining */
3734 for (; rar_entries > 0 ; rar_entries--) {
3735 wr32(E1000_RAH(rar_entries), 0);
3736 wr32(E1000_RAL(rar_entries), 0);
3737 }
3738 wrfl();
3739
3740 return count;
3741}
3742
3743/**
3744 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3745 * @netdev: network interface device structure
3746 *
3747 * The set_rx_mode entry point is called whenever the unicast or multicast
3748 * address lists or the network interface flags are updated. This routine is
3749 * responsible for configuring the hardware for proper unicast, multicast,
3750 * promiscuous mode, and all-multi behavior.
3751 **/
3752static void igb_set_rx_mode(struct net_device *netdev)
3753{
3754 struct igb_adapter *adapter = netdev_priv(netdev);
3755 struct e1000_hw *hw = &adapter->hw;
3756 unsigned int vfn = adapter->vfs_allocated_count;
3757 u32 rctl, vmolr = 0;
3758 int count;
3759
3760 /* Check for Promiscuous and All Multicast modes */
3761 rctl = rd32(E1000_RCTL);
3762
3763 /* clear the effected bits */
3764 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3765
3766 if (netdev->flags & IFF_PROMISC) {
3767 /* retain VLAN HW filtering if in VT mode */
3768 if (adapter->vfs_allocated_count)
3769 rctl |= E1000_RCTL_VFE;
3770 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3771 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3772 } else {
3773 if (netdev->flags & IFF_ALLMULTI) {
3774 rctl |= E1000_RCTL_MPE;
3775 vmolr |= E1000_VMOLR_MPME;
3776 } else {
3777 /* Write addresses to the MTA, if the attempt fails
3778 * then we should just turn on promiscuous mode so
3779 * that we can at least receive multicast traffic
3780 */
3781 count = igb_write_mc_addr_list(netdev);
3782 if (count < 0) {
3783 rctl |= E1000_RCTL_MPE;
3784 vmolr |= E1000_VMOLR_MPME;
3785 } else if (count) {
3786 vmolr |= E1000_VMOLR_ROMPE;
3787 }
3788 }
3789 /* Write addresses to available RAR registers, if there is not
3790 * sufficient space to store all the addresses then enable
3791 * unicast promiscuous mode
3792 */
3793 count = igb_write_uc_addr_list(netdev);
3794 if (count < 0) {
3795 rctl |= E1000_RCTL_UPE;
3796 vmolr |= E1000_VMOLR_ROPE;
3797 }
3798 rctl |= E1000_RCTL_VFE;
3799 }
3800 wr32(E1000_RCTL, rctl);
3801
3802 /* In order to support SR-IOV and eventually VMDq it is necessary to set
3803 * the VMOLR to enable the appropriate modes. Without this workaround
3804 * we will have issues with VLAN tag stripping not being done for frames
3805 * that are only arriving because we are the default pool
3806 */
3807 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
3808 return;
3809
3810 vmolr |= rd32(E1000_VMOLR(vfn)) &
3811 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3812 wr32(E1000_VMOLR(vfn), vmolr);
3813 igb_restore_vf_multicasts(adapter);
3814}
3815
3816static void igb_check_wvbr(struct igb_adapter *adapter)
3817{
3818 struct e1000_hw *hw = &adapter->hw;
3819 u32 wvbr = 0;
3820
3821 switch (hw->mac.type) {
3822 case e1000_82576:
3823 case e1000_i350:
3824 if (!(wvbr = rd32(E1000_WVBR)))
3825 return;
3826 break;
3827 default:
3828 break;
3829 }
3830
3831 adapter->wvbr |= wvbr;
3832}
3833
3834#define IGB_STAGGERED_QUEUE_OFFSET 8
3835
3836static void igb_spoof_check(struct igb_adapter *adapter)
3837{
3838 int j;
3839
3840 if (!adapter->wvbr)
3841 return;
3842
3843 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3844 if (adapter->wvbr & (1 << j) ||
3845 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3846 dev_warn(&adapter->pdev->dev,
3847 "Spoof event(s) detected on VF %d\n", j);
3848 adapter->wvbr &=
3849 ~((1 << j) |
3850 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3851 }
3852 }
3853}
3854
3855/* Need to wait a few seconds after link up to get diagnostic information from
3856 * the phy
3857 */
3858static void igb_update_phy_info(unsigned long data)
3859{
3860 struct igb_adapter *adapter = (struct igb_adapter *) data;
3861 igb_get_phy_info(&adapter->hw);
3862}
3863
3864/**
3865 * igb_has_link - check shared code for link and determine up/down
3866 * @adapter: pointer to driver private info
3867 **/
3868bool igb_has_link(struct igb_adapter *adapter)
3869{
3870 struct e1000_hw *hw = &adapter->hw;
3871 bool link_active = false;
3872
3873 /* get_link_status is set on LSC (link status) interrupt or
3874 * rx sequence error interrupt. get_link_status will stay
3875 * false until the e1000_check_for_link establishes link
3876 * for copper adapters ONLY
3877 */
3878 switch (hw->phy.media_type) {
3879 case e1000_media_type_copper:
3880 if (!hw->mac.get_link_status)
3881 return true;
3882 case e1000_media_type_internal_serdes:
3883 hw->mac.ops.check_for_link(hw);
3884 link_active = !hw->mac.get_link_status;
3885 break;
3886 default:
3887 case e1000_media_type_unknown:
3888 break;
3889 }
3890
3891 if (((hw->mac.type == e1000_i210) ||
3892 (hw->mac.type == e1000_i211)) &&
3893 (hw->phy.id == I210_I_PHY_ID)) {
3894 if (!netif_carrier_ok(adapter->netdev)) {
3895 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
3896 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
3897 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
3898 adapter->link_check_timeout = jiffies;
3899 }
3900 }
3901
3902 return link_active;
3903}
3904
3905static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3906{
3907 bool ret = false;
3908 u32 ctrl_ext, thstat;
3909
3910 /* check for thermal sensor event on i350 copper only */
3911 if (hw->mac.type == e1000_i350) {
3912 thstat = rd32(E1000_THSTAT);
3913 ctrl_ext = rd32(E1000_CTRL_EXT);
3914
3915 if ((hw->phy.media_type == e1000_media_type_copper) &&
3916 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
3917 ret = !!(thstat & event);
3918 }
3919
3920 return ret;
3921}
3922
3923/**
3924 * igb_watchdog - Timer Call-back
3925 * @data: pointer to adapter cast into an unsigned long
3926 **/
3927static void igb_watchdog(unsigned long data)
3928{
3929 struct igb_adapter *adapter = (struct igb_adapter *)data;
3930 /* Do the rest outside of interrupt context */
3931 schedule_work(&adapter->watchdog_task);
3932}
3933
3934static void igb_watchdog_task(struct work_struct *work)
3935{
3936 struct igb_adapter *adapter = container_of(work,
3937 struct igb_adapter,
3938 watchdog_task);
3939 struct e1000_hw *hw = &adapter->hw;
3940 struct e1000_phy_info *phy = &hw->phy;
3941 struct net_device *netdev = adapter->netdev;
3942 u32 link;
3943 int i;
3944
3945 link = igb_has_link(adapter);
3946
3947 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
3948 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
3949 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
3950 else
3951 link = false;
3952 }
3953
3954 if (link) {
3955 /* Cancel scheduled suspend requests. */
3956 pm_runtime_resume(netdev->dev.parent);
3957
3958 if (!netif_carrier_ok(netdev)) {
3959 u32 ctrl;
3960 hw->mac.ops.get_speed_and_duplex(hw,
3961 &adapter->link_speed,
3962 &adapter->link_duplex);
3963
3964 ctrl = rd32(E1000_CTRL);
3965 /* Links status message must follow this format */
3966 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3967 "Duplex, Flow Control: %s\n",
3968 netdev->name,
3969 adapter->link_speed,
3970 adapter->link_duplex == FULL_DUPLEX ?
3971 "Full" : "Half",
3972 (ctrl & E1000_CTRL_TFCE) &&
3973 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3974 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3975 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
3976
3977 /* check if SmartSpeed worked */
3978 igb_check_downshift(hw);
3979 if (phy->speed_downgraded)
3980 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
3981
3982 /* check for thermal sensor event */
3983 if (igb_thermal_sensor_event(hw,
3984 E1000_THSTAT_LINK_THROTTLE)) {
3985 netdev_info(netdev, "The network adapter link "
3986 "speed was downshifted because it "
3987 "overheated\n");
3988 }
3989
3990 /* adjust timeout factor according to speed/duplex */
3991 adapter->tx_timeout_factor = 1;
3992 switch (adapter->link_speed) {
3993 case SPEED_10:
3994 adapter->tx_timeout_factor = 14;
3995 break;
3996 case SPEED_100:
3997 /* maybe add some timeout factor ? */
3998 break;
3999 }
4000
4001 netif_carrier_on(netdev);
4002
4003 igb_ping_all_vfs(adapter);
4004 igb_check_vf_rate_limit(adapter);
4005
4006 /* link state has changed, schedule phy info update */
4007 if (!test_bit(__IGB_DOWN, &adapter->state))
4008 mod_timer(&adapter->phy_info_timer,
4009 round_jiffies(jiffies + 2 * HZ));
4010 }
4011 } else {
4012 if (netif_carrier_ok(netdev)) {
4013 adapter->link_speed = 0;
4014 adapter->link_duplex = 0;
4015
4016 /* check for thermal sensor event */
4017 if (igb_thermal_sensor_event(hw,
4018 E1000_THSTAT_PWR_DOWN)) {
4019 netdev_err(netdev, "The network adapter was "
4020 "stopped because it overheated\n");
4021 }
4022
4023 /* Links status message must follow this format */
4024 printk(KERN_INFO "igb: %s NIC Link is Down\n",
4025 netdev->name);
4026 netif_carrier_off(netdev);
4027
4028 igb_ping_all_vfs(adapter);
4029
4030 /* link state has changed, schedule phy info update */
4031 if (!test_bit(__IGB_DOWN, &adapter->state))
4032 mod_timer(&adapter->phy_info_timer,
4033 round_jiffies(jiffies + 2 * HZ));
4034
4035 pm_schedule_suspend(netdev->dev.parent,
4036 MSEC_PER_SEC * 5);
4037 }
4038 }
4039
4040 spin_lock(&adapter->stats64_lock);
4041 igb_update_stats(adapter, &adapter->stats64);
4042 spin_unlock(&adapter->stats64_lock);
4043
4044 for (i = 0; i < adapter->num_tx_queues; i++) {
4045 struct igb_ring *tx_ring = adapter->tx_ring[i];
4046 if (!netif_carrier_ok(netdev)) {
4047 /* We've lost link, so the controller stops DMA,
4048 * but we've got queued Tx work that's never going
4049 * to get done, so reset controller to flush Tx.
4050 * (Do the reset outside of interrupt context).
4051 */
4052 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4053 adapter->tx_timeout_count++;
4054 schedule_work(&adapter->reset_task);
4055 /* return immediately since reset is imminent */
4056 return;
4057 }
4058 }
4059
4060 /* Force detection of hung controller every watchdog period */
4061 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
4062 }
4063
4064 /* Cause software interrupt to ensure Rx ring is cleaned */
4065 if (adapter->msix_entries) {
4066 u32 eics = 0;
4067 for (i = 0; i < adapter->num_q_vectors; i++)
4068 eics |= adapter->q_vector[i]->eims_value;
4069 wr32(E1000_EICS, eics);
4070 } else {
4071 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4072 }
4073
4074 igb_spoof_check(adapter);
4075 igb_ptp_rx_hang(adapter);
4076
4077 /* Reset the timer */
4078 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4079 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4080 mod_timer(&adapter->watchdog_timer,
4081 round_jiffies(jiffies + HZ));
4082 else
4083 mod_timer(&adapter->watchdog_timer,
4084 round_jiffies(jiffies + 2 * HZ));
4085 }
4086}
4087
4088enum latency_range {
4089 lowest_latency = 0,
4090 low_latency = 1,
4091 bulk_latency = 2,
4092 latency_invalid = 255
4093};
4094
4095/**
4096 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4097 * @q_vector: pointer to q_vector
4098 *
4099 * Stores a new ITR value based on strictly on packet size. This
4100 * algorithm is less sophisticated than that used in igb_update_itr,
4101 * due to the difficulty of synchronizing statistics across multiple
4102 * receive rings. The divisors and thresholds used by this function
4103 * were determined based on theoretical maximum wire speed and testing
4104 * data, in order to minimize response time while increasing bulk
4105 * throughput.
4106 * This functionality is controlled by the InterruptThrottleRate module
4107 * parameter (see igb_param.c)
4108 * NOTE: This function is called only when operating in a multiqueue
4109 * receive environment.
4110 **/
4111static void igb_update_ring_itr(struct igb_q_vector *q_vector)
4112{
4113 int new_val = q_vector->itr_val;
4114 int avg_wire_size = 0;
4115 struct igb_adapter *adapter = q_vector->adapter;
4116 unsigned int packets;
4117
4118 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4119 * ints/sec - ITR timer value of 120 ticks.
4120 */
4121 if (adapter->link_speed != SPEED_1000) {
4122 new_val = IGB_4K_ITR;
4123 goto set_itr_val;
4124 }
4125
4126 packets = q_vector->rx.total_packets;
4127 if (packets)
4128 avg_wire_size = q_vector->rx.total_bytes / packets;
4129
4130 packets = q_vector->tx.total_packets;
4131 if (packets)
4132 avg_wire_size = max_t(u32, avg_wire_size,
4133 q_vector->tx.total_bytes / packets);
4134
4135 /* if avg_wire_size isn't set no work was done */
4136 if (!avg_wire_size)
4137 goto clear_counts;
4138
4139 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4140 avg_wire_size += 24;
4141
4142 /* Don't starve jumbo frames */
4143 avg_wire_size = min(avg_wire_size, 3000);
4144
4145 /* Give a little boost to mid-size frames */
4146 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4147 new_val = avg_wire_size / 3;
4148 else
4149 new_val = avg_wire_size / 2;
4150
4151 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4152 if (new_val < IGB_20K_ITR &&
4153 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4154 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4155 new_val = IGB_20K_ITR;
4156
4157set_itr_val:
4158 if (new_val != q_vector->itr_val) {
4159 q_vector->itr_val = new_val;
4160 q_vector->set_itr = 1;
4161 }
4162clear_counts:
4163 q_vector->rx.total_bytes = 0;
4164 q_vector->rx.total_packets = 0;
4165 q_vector->tx.total_bytes = 0;
4166 q_vector->tx.total_packets = 0;
4167}
4168
4169/**
4170 * igb_update_itr - update the dynamic ITR value based on statistics
4171 * @q_vector: pointer to q_vector
4172 * @ring_container: ring info to update the itr for
4173 *
4174 * Stores a new ITR value based on packets and byte
4175 * counts during the last interrupt. The advantage of per interrupt
4176 * computation is faster updates and more accurate ITR for the current
4177 * traffic pattern. Constants in this function were computed
4178 * based on theoretical maximum wire speed and thresholds were set based
4179 * on testing data as well as attempting to minimize response time
4180 * while increasing bulk throughput.
4181 * this functionality is controlled by the InterruptThrottleRate module
4182 * parameter (see igb_param.c)
4183 * NOTE: These calculations are only valid when operating in a single-
4184 * queue environment.
4185 **/
4186static void igb_update_itr(struct igb_q_vector *q_vector,
4187 struct igb_ring_container *ring_container)
4188{
4189 unsigned int packets = ring_container->total_packets;
4190 unsigned int bytes = ring_container->total_bytes;
4191 u8 itrval = ring_container->itr;
4192
4193 /* no packets, exit with status unchanged */
4194 if (packets == 0)
4195 return;
4196
4197 switch (itrval) {
4198 case lowest_latency:
4199 /* handle TSO and jumbo frames */
4200 if (bytes/packets > 8000)
4201 itrval = bulk_latency;
4202 else if ((packets < 5) && (bytes > 512))
4203 itrval = low_latency;
4204 break;
4205 case low_latency: /* 50 usec aka 20000 ints/s */
4206 if (bytes > 10000) {
4207 /* this if handles the TSO accounting */
4208 if (bytes/packets > 8000) {
4209 itrval = bulk_latency;
4210 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
4211 itrval = bulk_latency;
4212 } else if ((packets > 35)) {
4213 itrval = lowest_latency;
4214 }
4215 } else if (bytes/packets > 2000) {
4216 itrval = bulk_latency;
4217 } else if (packets <= 2 && bytes < 512) {
4218 itrval = lowest_latency;
4219 }
4220 break;
4221 case bulk_latency: /* 250 usec aka 4000 ints/s */
4222 if (bytes > 25000) {
4223 if (packets > 35)
4224 itrval = low_latency;
4225 } else if (bytes < 1500) {
4226 itrval = low_latency;
4227 }
4228 break;
4229 }
4230
4231 /* clear work counters since we have the values we need */
4232 ring_container->total_bytes = 0;
4233 ring_container->total_packets = 0;
4234
4235 /* write updated itr to ring container */
4236 ring_container->itr = itrval;
4237}
4238
4239static void igb_set_itr(struct igb_q_vector *q_vector)
4240{
4241 struct igb_adapter *adapter = q_vector->adapter;
4242 u32 new_itr = q_vector->itr_val;
4243 u8 current_itr = 0;
4244
4245 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4246 if (adapter->link_speed != SPEED_1000) {
4247 current_itr = 0;
4248 new_itr = IGB_4K_ITR;
4249 goto set_itr_now;
4250 }
4251
4252 igb_update_itr(q_vector, &q_vector->tx);
4253 igb_update_itr(q_vector, &q_vector->rx);
4254
4255 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4256
4257 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4258 if (current_itr == lowest_latency &&
4259 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4260 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4261 current_itr = low_latency;
4262
4263 switch (current_itr) {
4264 /* counts and packets in update_itr are dependent on these numbers */
4265 case lowest_latency:
4266 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
4267 break;
4268 case low_latency:
4269 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
4270 break;
4271 case bulk_latency:
4272 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
4273 break;
4274 default:
4275 break;
4276 }
4277
4278set_itr_now:
4279 if (new_itr != q_vector->itr_val) {
4280 /* this attempts to bias the interrupt rate towards Bulk
4281 * by adding intermediate steps when interrupt rate is
4282 * increasing
4283 */
4284 new_itr = new_itr > q_vector->itr_val ?
4285 max((new_itr * q_vector->itr_val) /
4286 (new_itr + (q_vector->itr_val >> 2)),
4287 new_itr) : new_itr;
4288 /* Don't write the value here; it resets the adapter's
4289 * internal timer, and causes us to delay far longer than
4290 * we should between interrupts. Instead, we write the ITR
4291 * value at the beginning of the next interrupt so the timing
4292 * ends up being correct.
4293 */
4294 q_vector->itr_val = new_itr;
4295 q_vector->set_itr = 1;
4296 }
4297}
4298
4299static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4300 u32 type_tucmd, u32 mss_l4len_idx)
4301{
4302 struct e1000_adv_tx_context_desc *context_desc;
4303 u16 i = tx_ring->next_to_use;
4304
4305 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4306
4307 i++;
4308 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4309
4310 /* set bits to identify this as an advanced context descriptor */
4311 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4312
4313 /* For 82575, context index must be unique per ring. */
4314 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4315 mss_l4len_idx |= tx_ring->reg_idx << 4;
4316
4317 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4318 context_desc->seqnum_seed = 0;
4319 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4320 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4321}
4322
4323static int igb_tso(struct igb_ring *tx_ring,
4324 struct igb_tx_buffer *first,
4325 u8 *hdr_len)
4326{
4327 struct sk_buff *skb = first->skb;
4328 u32 vlan_macip_lens, type_tucmd;
4329 u32 mss_l4len_idx, l4len;
4330
4331 if (skb->ip_summed != CHECKSUM_PARTIAL)
4332 return 0;
4333
4334 if (!skb_is_gso(skb))
4335 return 0;
4336
4337 if (skb_header_cloned(skb)) {
4338 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4339 if (err)
4340 return err;
4341 }
4342
4343 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4344 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4345
4346 if (first->protocol == __constant_htons(ETH_P_IP)) {
4347 struct iphdr *iph = ip_hdr(skb);
4348 iph->tot_len = 0;
4349 iph->check = 0;
4350 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4351 iph->daddr, 0,
4352 IPPROTO_TCP,
4353 0);
4354 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4355 first->tx_flags |= IGB_TX_FLAGS_TSO |
4356 IGB_TX_FLAGS_CSUM |
4357 IGB_TX_FLAGS_IPV4;
4358 } else if (skb_is_gso_v6(skb)) {
4359 ipv6_hdr(skb)->payload_len = 0;
4360 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4361 &ipv6_hdr(skb)->daddr,
4362 0, IPPROTO_TCP, 0);
4363 first->tx_flags |= IGB_TX_FLAGS_TSO |
4364 IGB_TX_FLAGS_CSUM;
4365 }
4366
4367 /* compute header lengths */
4368 l4len = tcp_hdrlen(skb);
4369 *hdr_len = skb_transport_offset(skb) + l4len;
4370
4371 /* update gso size and bytecount with header size */
4372 first->gso_segs = skb_shinfo(skb)->gso_segs;
4373 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4374
4375 /* MSS L4LEN IDX */
4376 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4377 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4378
4379 /* VLAN MACLEN IPLEN */
4380 vlan_macip_lens = skb_network_header_len(skb);
4381 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4382 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4383
4384 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4385
4386 return 1;
4387}
4388
4389static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4390{
4391 struct sk_buff *skb = first->skb;
4392 u32 vlan_macip_lens = 0;
4393 u32 mss_l4len_idx = 0;
4394 u32 type_tucmd = 0;
4395
4396 if (skb->ip_summed != CHECKSUM_PARTIAL) {
4397 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4398 return;
4399 } else {
4400 u8 l4_hdr = 0;
4401 switch (first->protocol) {
4402 case __constant_htons(ETH_P_IP):
4403 vlan_macip_lens |= skb_network_header_len(skb);
4404 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4405 l4_hdr = ip_hdr(skb)->protocol;
4406 break;
4407 case __constant_htons(ETH_P_IPV6):
4408 vlan_macip_lens |= skb_network_header_len(skb);
4409 l4_hdr = ipv6_hdr(skb)->nexthdr;
4410 break;
4411 default:
4412 if (unlikely(net_ratelimit())) {
4413 dev_warn(tx_ring->dev,
4414 "partial checksum but proto=%x!\n",
4415 first->protocol);
4416 }
4417 break;
4418 }
4419
4420 switch (l4_hdr) {
4421 case IPPROTO_TCP:
4422 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4423 mss_l4len_idx = tcp_hdrlen(skb) <<
4424 E1000_ADVTXD_L4LEN_SHIFT;
4425 break;
4426 case IPPROTO_SCTP:
4427 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4428 mss_l4len_idx = sizeof(struct sctphdr) <<
4429 E1000_ADVTXD_L4LEN_SHIFT;
4430 break;
4431 case IPPROTO_UDP:
4432 mss_l4len_idx = sizeof(struct udphdr) <<
4433 E1000_ADVTXD_L4LEN_SHIFT;
4434 break;
4435 default:
4436 if (unlikely(net_ratelimit())) {
4437 dev_warn(tx_ring->dev,
4438 "partial checksum but l4 proto=%x!\n",
4439 l4_hdr);
4440 }
4441 break;
4442 }
4443
4444 /* update TX checksum flag */
4445 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4446 }
4447
4448 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4449 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4450
4451 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4452}
4453
4454#define IGB_SET_FLAG(_input, _flag, _result) \
4455 ((_flag <= _result) ? \
4456 ((u32)(_input & _flag) * (_result / _flag)) : \
4457 ((u32)(_input & _flag) / (_flag / _result)))
4458
4459static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4460{
4461 /* set type for advanced descriptor with frame checksum insertion */
4462 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4463 E1000_ADVTXD_DCMD_DEXT |
4464 E1000_ADVTXD_DCMD_IFCS;
4465
4466 /* set HW vlan bit if vlan is present */
4467 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4468 (E1000_ADVTXD_DCMD_VLE));
4469
4470 /* set segmentation bits for TSO */
4471 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4472 (E1000_ADVTXD_DCMD_TSE));
4473
4474 /* set timestamp bit if present */
4475 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4476 (E1000_ADVTXD_MAC_TSTAMP));
4477
4478 /* insert frame checksum */
4479 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4480
4481 return cmd_type;
4482}
4483
4484static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4485 union e1000_adv_tx_desc *tx_desc,
4486 u32 tx_flags, unsigned int paylen)
4487{
4488 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4489
4490 /* 82575 requires a unique index per ring */
4491 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4492 olinfo_status |= tx_ring->reg_idx << 4;
4493
4494 /* insert L4 checksum */
4495 olinfo_status |= IGB_SET_FLAG(tx_flags,
4496 IGB_TX_FLAGS_CSUM,
4497 (E1000_TXD_POPTS_TXSM << 8));
4498
4499 /* insert IPv4 checksum */
4500 olinfo_status |= IGB_SET_FLAG(tx_flags,
4501 IGB_TX_FLAGS_IPV4,
4502 (E1000_TXD_POPTS_IXSM << 8));
4503
4504 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4505}
4506
4507static void igb_tx_map(struct igb_ring *tx_ring,
4508 struct igb_tx_buffer *first,
4509 const u8 hdr_len)
4510{
4511 struct sk_buff *skb = first->skb;
4512 struct igb_tx_buffer *tx_buffer;
4513 union e1000_adv_tx_desc *tx_desc;
4514 struct skb_frag_struct *frag;
4515 dma_addr_t dma;
4516 unsigned int data_len, size;
4517 u32 tx_flags = first->tx_flags;
4518 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
4519 u16 i = tx_ring->next_to_use;
4520
4521 tx_desc = IGB_TX_DESC(tx_ring, i);
4522
4523 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4524
4525 size = skb_headlen(skb);
4526 data_len = skb->data_len;
4527
4528 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4529
4530 tx_buffer = first;
4531
4532 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4533 if (dma_mapping_error(tx_ring->dev, dma))
4534 goto dma_error;
4535
4536 /* record length, and DMA address */
4537 dma_unmap_len_set(tx_buffer, len, size);
4538 dma_unmap_addr_set(tx_buffer, dma, dma);
4539
4540 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4541
4542 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4543 tx_desc->read.cmd_type_len =
4544 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
4545
4546 i++;
4547 tx_desc++;
4548 if (i == tx_ring->count) {
4549 tx_desc = IGB_TX_DESC(tx_ring, 0);
4550 i = 0;
4551 }
4552 tx_desc->read.olinfo_status = 0;
4553
4554 dma += IGB_MAX_DATA_PER_TXD;
4555 size -= IGB_MAX_DATA_PER_TXD;
4556
4557 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4558 }
4559
4560 if (likely(!data_len))
4561 break;
4562
4563 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
4564
4565 i++;
4566 tx_desc++;
4567 if (i == tx_ring->count) {
4568 tx_desc = IGB_TX_DESC(tx_ring, 0);
4569 i = 0;
4570 }
4571 tx_desc->read.olinfo_status = 0;
4572
4573 size = skb_frag_size(frag);
4574 data_len -= size;
4575
4576 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4577 size, DMA_TO_DEVICE);
4578
4579 tx_buffer = &tx_ring->tx_buffer_info[i];
4580 }
4581
4582 /* write last descriptor with RS and EOP bits */
4583 cmd_type |= size | IGB_TXD_DCMD;
4584 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
4585
4586 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4587
4588 /* set the timestamp */
4589 first->time_stamp = jiffies;
4590
4591 /* Force memory writes to complete before letting h/w know there
4592 * are new descriptors to fetch. (Only applicable for weak-ordered
4593 * memory model archs, such as IA-64).
4594 *
4595 * We also need this memory barrier to make certain all of the
4596 * status bits have been updated before next_to_watch is written.
4597 */
4598 wmb();
4599
4600 /* set next_to_watch value indicating a packet is present */
4601 first->next_to_watch = tx_desc;
4602
4603 i++;
4604 if (i == tx_ring->count)
4605 i = 0;
4606
4607 tx_ring->next_to_use = i;
4608
4609 writel(i, tx_ring->tail);
4610
4611 /* we need this if more than one processor can write to our tail
4612 * at a time, it synchronizes IO on IA64/Altix systems
4613 */
4614 mmiowb();
4615
4616 return;
4617
4618dma_error:
4619 dev_err(tx_ring->dev, "TX DMA map failed\n");
4620
4621 /* clear dma mappings for failed tx_buffer_info map */
4622 for (;;) {
4623 tx_buffer = &tx_ring->tx_buffer_info[i];
4624 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4625 if (tx_buffer == first)
4626 break;
4627 if (i == 0)
4628 i = tx_ring->count;
4629 i--;
4630 }
4631
4632 tx_ring->next_to_use = i;
4633}
4634
4635static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4636{
4637 struct net_device *netdev = tx_ring->netdev;
4638
4639 netif_stop_subqueue(netdev, tx_ring->queue_index);
4640
4641 /* Herbert's original patch had:
4642 * smp_mb__after_netif_stop_queue();
4643 * but since that doesn't exist yet, just open code it.
4644 */
4645 smp_mb();
4646
4647 /* We need to check again in a case another CPU has just
4648 * made room available.
4649 */
4650 if (igb_desc_unused(tx_ring) < size)
4651 return -EBUSY;
4652
4653 /* A reprieve! */
4654 netif_wake_subqueue(netdev, tx_ring->queue_index);
4655
4656 u64_stats_update_begin(&tx_ring->tx_syncp2);
4657 tx_ring->tx_stats.restart_queue2++;
4658 u64_stats_update_end(&tx_ring->tx_syncp2);
4659
4660 return 0;
4661}
4662
4663static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4664{
4665 if (igb_desc_unused(tx_ring) >= size)
4666 return 0;
4667 return __igb_maybe_stop_tx(tx_ring, size);
4668}
4669
4670netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4671 struct igb_ring *tx_ring)
4672{
4673 struct igb_tx_buffer *first;
4674 int tso;
4675 u32 tx_flags = 0;
4676 u16 count = TXD_USE_COUNT(skb_headlen(skb));
4677 __be16 protocol = vlan_get_protocol(skb);
4678 u8 hdr_len = 0;
4679
4680 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4681 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
4682 * + 2 desc gap to keep tail from touching head,
4683 * + 1 desc for context descriptor,
4684 * otherwise try next time
4685 */
4686 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4687 unsigned short f;
4688 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4689 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4690 } else {
4691 count += skb_shinfo(skb)->nr_frags;
4692 }
4693
4694 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
4695 /* this is a hard error */
4696 return NETDEV_TX_BUSY;
4697 }
4698
4699 /* record the location of the first descriptor for this packet */
4700 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4701 first->skb = skb;
4702 first->bytecount = skb->len;
4703 first->gso_segs = 1;
4704
4705 skb_tx_timestamp(skb);
4706
4707 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4708 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
4709
4710 if (!(adapter->ptp_tx_skb)) {
4711 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4712 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4713
4714 adapter->ptp_tx_skb = skb_get(skb);
4715 adapter->ptp_tx_start = jiffies;
4716 if (adapter->hw.mac.type == e1000_82576)
4717 schedule_work(&adapter->ptp_tx_work);
4718 }
4719 }
4720
4721 if (vlan_tx_tag_present(skb)) {
4722 tx_flags |= IGB_TX_FLAGS_VLAN;
4723 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4724 }
4725
4726 /* record initial flags and protocol */
4727 first->tx_flags = tx_flags;
4728 first->protocol = protocol;
4729
4730 tso = igb_tso(tx_ring, first, &hdr_len);
4731 if (tso < 0)
4732 goto out_drop;
4733 else if (!tso)
4734 igb_tx_csum(tx_ring, first);
4735
4736 igb_tx_map(tx_ring, first, hdr_len);
4737
4738 /* Make sure there is space in the ring for the next send. */
4739 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4740
4741 return NETDEV_TX_OK;
4742
4743out_drop:
4744 igb_unmap_and_free_tx_resource(tx_ring, first);
4745
4746 return NETDEV_TX_OK;
4747}
4748
4749static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4750 struct sk_buff *skb)
4751{
4752 unsigned int r_idx = skb->queue_mapping;
4753
4754 if (r_idx >= adapter->num_tx_queues)
4755 r_idx = r_idx % adapter->num_tx_queues;
4756
4757 return adapter->tx_ring[r_idx];
4758}
4759
4760static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4761 struct net_device *netdev)
4762{
4763 struct igb_adapter *adapter = netdev_priv(netdev);
4764
4765 if (test_bit(__IGB_DOWN, &adapter->state)) {
4766 dev_kfree_skb_any(skb);
4767 return NETDEV_TX_OK;
4768 }
4769
4770 if (skb->len <= 0) {
4771 dev_kfree_skb_any(skb);
4772 return NETDEV_TX_OK;
4773 }
4774
4775 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
4776 * in order to meet this minimum size requirement.
4777 */
4778 if (unlikely(skb->len < 17)) {
4779 if (skb_pad(skb, 17 - skb->len))
4780 return NETDEV_TX_OK;
4781 skb->len = 17;
4782 skb_set_tail_pointer(skb, 17);
4783 }
4784
4785 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
4786}
4787
4788/**
4789 * igb_tx_timeout - Respond to a Tx Hang
4790 * @netdev: network interface device structure
4791 **/
4792static void igb_tx_timeout(struct net_device *netdev)
4793{
4794 struct igb_adapter *adapter = netdev_priv(netdev);
4795 struct e1000_hw *hw = &adapter->hw;
4796
4797 /* Do the reset outside of interrupt context */
4798 adapter->tx_timeout_count++;
4799
4800 if (hw->mac.type >= e1000_82580)
4801 hw->dev_spec._82575.global_device_reset = true;
4802
4803 schedule_work(&adapter->reset_task);
4804 wr32(E1000_EICS,
4805 (adapter->eims_enable_mask & ~adapter->eims_other));
4806}
4807
4808static void igb_reset_task(struct work_struct *work)
4809{
4810 struct igb_adapter *adapter;
4811 adapter = container_of(work, struct igb_adapter, reset_task);
4812
4813 igb_dump(adapter);
4814 netdev_err(adapter->netdev, "Reset adapter\n");
4815 igb_reinit_locked(adapter);
4816}
4817
4818/**
4819 * igb_get_stats64 - Get System Network Statistics
4820 * @netdev: network interface device structure
4821 * @stats: rtnl_link_stats64 pointer
4822 **/
4823static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4824 struct rtnl_link_stats64 *stats)
4825{
4826 struct igb_adapter *adapter = netdev_priv(netdev);
4827
4828 spin_lock(&adapter->stats64_lock);
4829 igb_update_stats(adapter, &adapter->stats64);
4830 memcpy(stats, &adapter->stats64, sizeof(*stats));
4831 spin_unlock(&adapter->stats64_lock);
4832
4833 return stats;
4834}
4835
4836/**
4837 * igb_change_mtu - Change the Maximum Transfer Unit
4838 * @netdev: network interface device structure
4839 * @new_mtu: new value for maximum frame size
4840 *
4841 * Returns 0 on success, negative on failure
4842 **/
4843static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4844{
4845 struct igb_adapter *adapter = netdev_priv(netdev);
4846 struct pci_dev *pdev = adapter->pdev;
4847 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4848
4849 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
4850 dev_err(&pdev->dev, "Invalid MTU setting\n");
4851 return -EINVAL;
4852 }
4853
4854#define MAX_STD_JUMBO_FRAME_SIZE 9238
4855 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
4856 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
4857 return -EINVAL;
4858 }
4859
4860 /* adjust max frame to be at least the size of a standard frame */
4861 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4862 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
4863
4864 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4865 msleep(1);
4866
4867 /* igb_down has a dependency on max_frame_size */
4868 adapter->max_frame_size = max_frame;
4869
4870 if (netif_running(netdev))
4871 igb_down(adapter);
4872
4873 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
4874 netdev->mtu, new_mtu);
4875 netdev->mtu = new_mtu;
4876
4877 if (netif_running(netdev))
4878 igb_up(adapter);
4879 else
4880 igb_reset(adapter);
4881
4882 clear_bit(__IGB_RESETTING, &adapter->state);
4883
4884 return 0;
4885}
4886
4887/**
4888 * igb_update_stats - Update the board statistics counters
4889 * @adapter: board private structure
4890 **/
4891void igb_update_stats(struct igb_adapter *adapter,
4892 struct rtnl_link_stats64 *net_stats)
4893{
4894 struct e1000_hw *hw = &adapter->hw;
4895 struct pci_dev *pdev = adapter->pdev;
4896 u32 reg, mpc;
4897 u16 phy_tmp;
4898 int i;
4899 u64 bytes, packets;
4900 unsigned int start;
4901 u64 _bytes, _packets;
4902
4903#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4904
4905 /* Prevent stats update while adapter is being reset, or if the pci
4906 * connection is down.
4907 */
4908 if (adapter->link_speed == 0)
4909 return;
4910 if (pci_channel_offline(pdev))
4911 return;
4912
4913 bytes = 0;
4914 packets = 0;
4915
4916 rcu_read_lock();
4917 for (i = 0; i < adapter->num_rx_queues; i++) {
4918 u32 rqdpc = rd32(E1000_RQDPC(i));
4919 struct igb_ring *ring = adapter->rx_ring[i];
4920
4921 if (rqdpc) {
4922 ring->rx_stats.drops += rqdpc;
4923 net_stats->rx_fifo_errors += rqdpc;
4924 }
4925
4926 do {
4927 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4928 _bytes = ring->rx_stats.bytes;
4929 _packets = ring->rx_stats.packets;
4930 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4931 bytes += _bytes;
4932 packets += _packets;
4933 }
4934
4935 net_stats->rx_bytes = bytes;
4936 net_stats->rx_packets = packets;
4937
4938 bytes = 0;
4939 packets = 0;
4940 for (i = 0; i < adapter->num_tx_queues; i++) {
4941 struct igb_ring *ring = adapter->tx_ring[i];
4942 do {
4943 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4944 _bytes = ring->tx_stats.bytes;
4945 _packets = ring->tx_stats.packets;
4946 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4947 bytes += _bytes;
4948 packets += _packets;
4949 }
4950 net_stats->tx_bytes = bytes;
4951 net_stats->tx_packets = packets;
4952 rcu_read_unlock();
4953
4954 /* read stats registers */
4955 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4956 adapter->stats.gprc += rd32(E1000_GPRC);
4957 adapter->stats.gorc += rd32(E1000_GORCL);
4958 rd32(E1000_GORCH); /* clear GORCL */
4959 adapter->stats.bprc += rd32(E1000_BPRC);
4960 adapter->stats.mprc += rd32(E1000_MPRC);
4961 adapter->stats.roc += rd32(E1000_ROC);
4962
4963 adapter->stats.prc64 += rd32(E1000_PRC64);
4964 adapter->stats.prc127 += rd32(E1000_PRC127);
4965 adapter->stats.prc255 += rd32(E1000_PRC255);
4966 adapter->stats.prc511 += rd32(E1000_PRC511);
4967 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4968 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4969 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4970 adapter->stats.sec += rd32(E1000_SEC);
4971
4972 mpc = rd32(E1000_MPC);
4973 adapter->stats.mpc += mpc;
4974 net_stats->rx_fifo_errors += mpc;
4975 adapter->stats.scc += rd32(E1000_SCC);
4976 adapter->stats.ecol += rd32(E1000_ECOL);
4977 adapter->stats.mcc += rd32(E1000_MCC);
4978 adapter->stats.latecol += rd32(E1000_LATECOL);
4979 adapter->stats.dc += rd32(E1000_DC);
4980 adapter->stats.rlec += rd32(E1000_RLEC);
4981 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4982 adapter->stats.xontxc += rd32(E1000_XONTXC);
4983 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4984 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4985 adapter->stats.fcruc += rd32(E1000_FCRUC);
4986 adapter->stats.gptc += rd32(E1000_GPTC);
4987 adapter->stats.gotc += rd32(E1000_GOTCL);
4988 rd32(E1000_GOTCH); /* clear GOTCL */
4989 adapter->stats.rnbc += rd32(E1000_RNBC);
4990 adapter->stats.ruc += rd32(E1000_RUC);
4991 adapter->stats.rfc += rd32(E1000_RFC);
4992 adapter->stats.rjc += rd32(E1000_RJC);
4993 adapter->stats.tor += rd32(E1000_TORH);
4994 adapter->stats.tot += rd32(E1000_TOTH);
4995 adapter->stats.tpr += rd32(E1000_TPR);
4996
4997 adapter->stats.ptc64 += rd32(E1000_PTC64);
4998 adapter->stats.ptc127 += rd32(E1000_PTC127);
4999 adapter->stats.ptc255 += rd32(E1000_PTC255);
5000 adapter->stats.ptc511 += rd32(E1000_PTC511);
5001 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5002 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5003
5004 adapter->stats.mptc += rd32(E1000_MPTC);
5005 adapter->stats.bptc += rd32(E1000_BPTC);
5006
5007 adapter->stats.tpt += rd32(E1000_TPT);
5008 adapter->stats.colc += rd32(E1000_COLC);
5009
5010 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
5011 /* read internal phy specific stats */
5012 reg = rd32(E1000_CTRL_EXT);
5013 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5014 adapter->stats.rxerrc += rd32(E1000_RXERRC);
5015
5016 /* this stat has invalid values on i210/i211 */
5017 if ((hw->mac.type != e1000_i210) &&
5018 (hw->mac.type != e1000_i211))
5019 adapter->stats.tncrs += rd32(E1000_TNCRS);
5020 }
5021
5022 adapter->stats.tsctc += rd32(E1000_TSCTC);
5023 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5024
5025 adapter->stats.iac += rd32(E1000_IAC);
5026 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5027 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5028 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5029 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5030 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5031 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5032 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5033 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5034
5035 /* Fill out the OS statistics structure */
5036 net_stats->multicast = adapter->stats.mprc;
5037 net_stats->collisions = adapter->stats.colc;
5038
5039 /* Rx Errors */
5040
5041 /* RLEC on some newer hardware can be incorrect so build
5042 * our own version based on RUC and ROC
5043 */
5044 net_stats->rx_errors = adapter->stats.rxerrc +
5045 adapter->stats.crcerrs + adapter->stats.algnerrc +
5046 adapter->stats.ruc + adapter->stats.roc +
5047 adapter->stats.cexterr;
5048 net_stats->rx_length_errors = adapter->stats.ruc +
5049 adapter->stats.roc;
5050 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5051 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5052 net_stats->rx_missed_errors = adapter->stats.mpc;
5053
5054 /* Tx Errors */
5055 net_stats->tx_errors = adapter->stats.ecol +
5056 adapter->stats.latecol;
5057 net_stats->tx_aborted_errors = adapter->stats.ecol;
5058 net_stats->tx_window_errors = adapter->stats.latecol;
5059 net_stats->tx_carrier_errors = adapter->stats.tncrs;
5060
5061 /* Tx Dropped needs to be maintained elsewhere */
5062
5063 /* Phy Stats */
5064 if (hw->phy.media_type == e1000_media_type_copper) {
5065 if ((adapter->link_speed == SPEED_1000) &&
5066 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
5067 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5068 adapter->phy_stats.idle_errors += phy_tmp;
5069 }
5070 }
5071
5072 /* Management Stats */
5073 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5074 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5075 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
5076
5077 /* OS2BMC Stats */
5078 reg = rd32(E1000_MANC);
5079 if (reg & E1000_MANC_EN_BMC2OS) {
5080 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5081 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5082 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5083 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5084 }
5085}
5086
5087static irqreturn_t igb_msix_other(int irq, void *data)
5088{
5089 struct igb_adapter *adapter = data;
5090 struct e1000_hw *hw = &adapter->hw;
5091 u32 icr = rd32(E1000_ICR);
5092 /* reading ICR causes bit 31 of EICR to be cleared */
5093
5094 if (icr & E1000_ICR_DRSTA)
5095 schedule_work(&adapter->reset_task);
5096
5097 if (icr & E1000_ICR_DOUTSYNC) {
5098 /* HW is reporting DMA is out of sync */
5099 adapter->stats.doosync++;
5100 /* The DMA Out of Sync is also indication of a spoof event
5101 * in IOV mode. Check the Wrong VM Behavior register to
5102 * see if it is really a spoof event.
5103 */
5104 igb_check_wvbr(adapter);
5105 }
5106
5107 /* Check for a mailbox event */
5108 if (icr & E1000_ICR_VMMB)
5109 igb_msg_task(adapter);
5110
5111 if (icr & E1000_ICR_LSC) {
5112 hw->mac.get_link_status = 1;
5113 /* guard against interrupt when we're going down */
5114 if (!test_bit(__IGB_DOWN, &adapter->state))
5115 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5116 }
5117
5118 if (icr & E1000_ICR_TS) {
5119 u32 tsicr = rd32(E1000_TSICR);
5120
5121 if (tsicr & E1000_TSICR_TXTS) {
5122 /* acknowledge the interrupt */
5123 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5124 /* retrieve hardware timestamp */
5125 schedule_work(&adapter->ptp_tx_work);
5126 }
5127 }
5128
5129 wr32(E1000_EIMS, adapter->eims_other);
5130
5131 return IRQ_HANDLED;
5132}
5133
5134static void igb_write_itr(struct igb_q_vector *q_vector)
5135{
5136 struct igb_adapter *adapter = q_vector->adapter;
5137 u32 itr_val = q_vector->itr_val & 0x7FFC;
5138
5139 if (!q_vector->set_itr)
5140 return;
5141
5142 if (!itr_val)
5143 itr_val = 0x4;
5144
5145 if (adapter->hw.mac.type == e1000_82575)
5146 itr_val |= itr_val << 16;
5147 else
5148 itr_val |= E1000_EITR_CNT_IGNR;
5149
5150 writel(itr_val, q_vector->itr_register);
5151 q_vector->set_itr = 0;
5152}
5153
5154static irqreturn_t igb_msix_ring(int irq, void *data)
5155{
5156 struct igb_q_vector *q_vector = data;
5157
5158 /* Write the ITR value calculated from the previous interrupt. */
5159 igb_write_itr(q_vector);
5160
5161 napi_schedule(&q_vector->napi);
5162
5163 return IRQ_HANDLED;
5164}
5165
5166#ifdef CONFIG_IGB_DCA
5167static void igb_update_tx_dca(struct igb_adapter *adapter,
5168 struct igb_ring *tx_ring,
5169 int cpu)
5170{
5171 struct e1000_hw *hw = &adapter->hw;
5172 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5173
5174 if (hw->mac.type != e1000_82575)
5175 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5176
5177 /* We can enable relaxed ordering for reads, but not writes when
5178 * DCA is enabled. This is due to a known issue in some chipsets
5179 * which will cause the DCA tag to be cleared.
5180 */
5181 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5182 E1000_DCA_TXCTRL_DATA_RRO_EN |
5183 E1000_DCA_TXCTRL_DESC_DCA_EN;
5184
5185 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5186}
5187
5188static void igb_update_rx_dca(struct igb_adapter *adapter,
5189 struct igb_ring *rx_ring,
5190 int cpu)
5191{
5192 struct e1000_hw *hw = &adapter->hw;
5193 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5194
5195 if (hw->mac.type != e1000_82575)
5196 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5197
5198 /* We can enable relaxed ordering for reads, but not writes when
5199 * DCA is enabled. This is due to a known issue in some chipsets
5200 * which will cause the DCA tag to be cleared.
5201 */
5202 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5203 E1000_DCA_RXCTRL_DESC_DCA_EN;
5204
5205 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5206}
5207
5208static void igb_update_dca(struct igb_q_vector *q_vector)
5209{
5210 struct igb_adapter *adapter = q_vector->adapter;
5211 int cpu = get_cpu();
5212
5213 if (q_vector->cpu == cpu)
5214 goto out_no_update;
5215
5216 if (q_vector->tx.ring)
5217 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5218
5219 if (q_vector->rx.ring)
5220 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5221
5222 q_vector->cpu = cpu;
5223out_no_update:
5224 put_cpu();
5225}
5226
5227static void igb_setup_dca(struct igb_adapter *adapter)
5228{
5229 struct e1000_hw *hw = &adapter->hw;
5230 int i;
5231
5232 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
5233 return;
5234
5235 /* Always use CB2 mode, difference is masked in the CB driver. */
5236 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5237
5238 for (i = 0; i < adapter->num_q_vectors; i++) {
5239 adapter->q_vector[i]->cpu = -1;
5240 igb_update_dca(adapter->q_vector[i]);
5241 }
5242}
5243
5244static int __igb_notify_dca(struct device *dev, void *data)
5245{
5246 struct net_device *netdev = dev_get_drvdata(dev);
5247 struct igb_adapter *adapter = netdev_priv(netdev);
5248 struct pci_dev *pdev = adapter->pdev;
5249 struct e1000_hw *hw = &adapter->hw;
5250 unsigned long event = *(unsigned long *)data;
5251
5252 switch (event) {
5253 case DCA_PROVIDER_ADD:
5254 /* if already enabled, don't do it again */
5255 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
5256 break;
5257 if (dca_add_requester(dev) == 0) {
5258 adapter->flags |= IGB_FLAG_DCA_ENABLED;
5259 dev_info(&pdev->dev, "DCA enabled\n");
5260 igb_setup_dca(adapter);
5261 break;
5262 }
5263 /* Fall Through since DCA is disabled. */
5264 case DCA_PROVIDER_REMOVE:
5265 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
5266 /* without this a class_device is left
5267 * hanging around in the sysfs model
5268 */
5269 dca_remove_requester(dev);
5270 dev_info(&pdev->dev, "DCA disabled\n");
5271 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
5272 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
5273 }
5274 break;
5275 }
5276
5277 return 0;
5278}
5279
5280static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5281 void *p)
5282{
5283 int ret_val;
5284
5285 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5286 __igb_notify_dca);
5287
5288 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5289}
5290#endif /* CONFIG_IGB_DCA */
5291
5292#ifdef CONFIG_PCI_IOV
5293static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5294{
5295 unsigned char mac_addr[ETH_ALEN];
5296
5297 eth_zero_addr(mac_addr);
5298 igb_set_vf_mac(adapter, vf, mac_addr);
5299
5300 /* By default spoof check is enabled for all VFs */
5301 adapter->vf_data[vf].spoofchk_enabled = true;
5302
5303 return 0;
5304}
5305
5306#endif
5307static void igb_ping_all_vfs(struct igb_adapter *adapter)
5308{
5309 struct e1000_hw *hw = &adapter->hw;
5310 u32 ping;
5311 int i;
5312
5313 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5314 ping = E1000_PF_CONTROL_MSG;
5315 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5316 ping |= E1000_VT_MSGTYPE_CTS;
5317 igb_write_mbx(hw, &ping, 1, i);
5318 }
5319}
5320
5321static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5322{
5323 struct e1000_hw *hw = &adapter->hw;
5324 u32 vmolr = rd32(E1000_VMOLR(vf));
5325 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5326
5327 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5328 IGB_VF_FLAG_MULTI_PROMISC);
5329 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5330
5331 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5332 vmolr |= E1000_VMOLR_MPME;
5333 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5334 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5335 } else {
5336 /* if we have hashes and we are clearing a multicast promisc
5337 * flag we need to write the hashes to the MTA as this step
5338 * was previously skipped
5339 */
5340 if (vf_data->num_vf_mc_hashes > 30) {
5341 vmolr |= E1000_VMOLR_MPME;
5342 } else if (vf_data->num_vf_mc_hashes) {
5343 int j;
5344 vmolr |= E1000_VMOLR_ROMPE;
5345 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5346 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5347 }
5348 }
5349
5350 wr32(E1000_VMOLR(vf), vmolr);
5351
5352 /* there are flags left unprocessed, likely not supported */
5353 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5354 return -EINVAL;
5355
5356 return 0;
5357}
5358
5359static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5360 u32 *msgbuf, u32 vf)
5361{
5362 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5363 u16 *hash_list = (u16 *)&msgbuf[1];
5364 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5365 int i;
5366
5367 /* salt away the number of multicast addresses assigned
5368 * to this VF for later use to restore when the PF multi cast
5369 * list changes
5370 */
5371 vf_data->num_vf_mc_hashes = n;
5372
5373 /* only up to 30 hash values supported */
5374 if (n > 30)
5375 n = 30;
5376
5377 /* store the hashes for later use */
5378 for (i = 0; i < n; i++)
5379 vf_data->vf_mc_hashes[i] = hash_list[i];
5380
5381 /* Flush and reset the mta with the new values */
5382 igb_set_rx_mode(adapter->netdev);
5383
5384 return 0;
5385}
5386
5387static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5388{
5389 struct e1000_hw *hw = &adapter->hw;
5390 struct vf_data_storage *vf_data;
5391 int i, j;
5392
5393 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5394 u32 vmolr = rd32(E1000_VMOLR(i));
5395 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5396
5397 vf_data = &adapter->vf_data[i];
5398
5399 if ((vf_data->num_vf_mc_hashes > 30) ||
5400 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5401 vmolr |= E1000_VMOLR_MPME;
5402 } else if (vf_data->num_vf_mc_hashes) {
5403 vmolr |= E1000_VMOLR_ROMPE;
5404 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5405 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5406 }
5407 wr32(E1000_VMOLR(i), vmolr);
5408 }
5409}
5410
5411static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5412{
5413 struct e1000_hw *hw = &adapter->hw;
5414 u32 pool_mask, reg, vid;
5415 int i;
5416
5417 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5418
5419 /* Find the vlan filter for this id */
5420 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5421 reg = rd32(E1000_VLVF(i));
5422
5423 /* remove the vf from the pool */
5424 reg &= ~pool_mask;
5425
5426 /* if pool is empty then remove entry from vfta */
5427 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5428 (reg & E1000_VLVF_VLANID_ENABLE)) {
5429 reg = 0;
5430 vid = reg & E1000_VLVF_VLANID_MASK;
5431 igb_vfta_set(hw, vid, false);
5432 }
5433
5434 wr32(E1000_VLVF(i), reg);
5435 }
5436
5437 adapter->vf_data[vf].vlans_enabled = 0;
5438}
5439
5440static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5441{
5442 struct e1000_hw *hw = &adapter->hw;
5443 u32 reg, i;
5444
5445 /* The vlvf table only exists on 82576 hardware and newer */
5446 if (hw->mac.type < e1000_82576)
5447 return -1;
5448
5449 /* we only need to do this if VMDq is enabled */
5450 if (!adapter->vfs_allocated_count)
5451 return -1;
5452
5453 /* Find the vlan filter for this id */
5454 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5455 reg = rd32(E1000_VLVF(i));
5456 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5457 vid == (reg & E1000_VLVF_VLANID_MASK))
5458 break;
5459 }
5460
5461 if (add) {
5462 if (i == E1000_VLVF_ARRAY_SIZE) {
5463 /* Did not find a matching VLAN ID entry that was
5464 * enabled. Search for a free filter entry, i.e.
5465 * one without the enable bit set
5466 */
5467 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5468 reg = rd32(E1000_VLVF(i));
5469 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5470 break;
5471 }
5472 }
5473 if (i < E1000_VLVF_ARRAY_SIZE) {
5474 /* Found an enabled/available entry */
5475 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5476
5477 /* if !enabled we need to set this up in vfta */
5478 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5479 /* add VID to filter table */
5480 igb_vfta_set(hw, vid, true);
5481 reg |= E1000_VLVF_VLANID_ENABLE;
5482 }
5483 reg &= ~E1000_VLVF_VLANID_MASK;
5484 reg |= vid;
5485 wr32(E1000_VLVF(i), reg);
5486
5487 /* do not modify RLPML for PF devices */
5488 if (vf >= adapter->vfs_allocated_count)
5489 return 0;
5490
5491 if (!adapter->vf_data[vf].vlans_enabled) {
5492 u32 size;
5493 reg = rd32(E1000_VMOLR(vf));
5494 size = reg & E1000_VMOLR_RLPML_MASK;
5495 size += 4;
5496 reg &= ~E1000_VMOLR_RLPML_MASK;
5497 reg |= size;
5498 wr32(E1000_VMOLR(vf), reg);
5499 }
5500
5501 adapter->vf_data[vf].vlans_enabled++;
5502 }
5503 } else {
5504 if (i < E1000_VLVF_ARRAY_SIZE) {
5505 /* remove vf from the pool */
5506 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5507 /* if pool is empty then remove entry from vfta */
5508 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5509 reg = 0;
5510 igb_vfta_set(hw, vid, false);
5511 }
5512 wr32(E1000_VLVF(i), reg);
5513
5514 /* do not modify RLPML for PF devices */
5515 if (vf >= adapter->vfs_allocated_count)
5516 return 0;
5517
5518 adapter->vf_data[vf].vlans_enabled--;
5519 if (!adapter->vf_data[vf].vlans_enabled) {
5520 u32 size;
5521 reg = rd32(E1000_VMOLR(vf));
5522 size = reg & E1000_VMOLR_RLPML_MASK;
5523 size -= 4;
5524 reg &= ~E1000_VMOLR_RLPML_MASK;
5525 reg |= size;
5526 wr32(E1000_VMOLR(vf), reg);
5527 }
5528 }
5529 }
5530 return 0;
5531}
5532
5533static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5534{
5535 struct e1000_hw *hw = &adapter->hw;
5536
5537 if (vid)
5538 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5539 else
5540 wr32(E1000_VMVIR(vf), 0);
5541}
5542
5543static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5544 int vf, u16 vlan, u8 qos)
5545{
5546 int err = 0;
5547 struct igb_adapter *adapter = netdev_priv(netdev);
5548
5549 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5550 return -EINVAL;
5551 if (vlan || qos) {
5552 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5553 if (err)
5554 goto out;
5555 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5556 igb_set_vmolr(adapter, vf, !vlan);
5557 adapter->vf_data[vf].pf_vlan = vlan;
5558 adapter->vf_data[vf].pf_qos = qos;
5559 dev_info(&adapter->pdev->dev,
5560 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5561 if (test_bit(__IGB_DOWN, &adapter->state)) {
5562 dev_warn(&adapter->pdev->dev,
5563 "The VF VLAN has been set, but the PF device is not up.\n");
5564 dev_warn(&adapter->pdev->dev,
5565 "Bring the PF device up before attempting to use the VF device.\n");
5566 }
5567 } else {
5568 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5569 false, vf);
5570 igb_set_vmvir(adapter, vlan, vf);
5571 igb_set_vmolr(adapter, vf, true);
5572 adapter->vf_data[vf].pf_vlan = 0;
5573 adapter->vf_data[vf].pf_qos = 0;
5574 }
5575out:
5576 return err;
5577}
5578
5579static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5580{
5581 struct e1000_hw *hw = &adapter->hw;
5582 int i;
5583 u32 reg;
5584
5585 /* Find the vlan filter for this id */
5586 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5587 reg = rd32(E1000_VLVF(i));
5588 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5589 vid == (reg & E1000_VLVF_VLANID_MASK))
5590 break;
5591 }
5592
5593 if (i >= E1000_VLVF_ARRAY_SIZE)
5594 i = -1;
5595
5596 return i;
5597}
5598
5599static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5600{
5601 struct e1000_hw *hw = &adapter->hw;
5602 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5603 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5604 int err = 0;
5605
5606 /* If in promiscuous mode we need to make sure the PF also has
5607 * the VLAN filter set.
5608 */
5609 if (add && (adapter->netdev->flags & IFF_PROMISC))
5610 err = igb_vlvf_set(adapter, vid, add,
5611 adapter->vfs_allocated_count);
5612 if (err)
5613 goto out;
5614
5615 err = igb_vlvf_set(adapter, vid, add, vf);
5616
5617 if (err)
5618 goto out;
5619
5620 /* Go through all the checks to see if the VLAN filter should
5621 * be wiped completely.
5622 */
5623 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5624 u32 vlvf, bits;
5625
5626 int regndx = igb_find_vlvf_entry(adapter, vid);
5627 if (regndx < 0)
5628 goto out;
5629 /* See if any other pools are set for this VLAN filter
5630 * entry other than the PF.
5631 */
5632 vlvf = bits = rd32(E1000_VLVF(regndx));
5633 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5634 adapter->vfs_allocated_count);
5635 /* If the filter was removed then ensure PF pool bit
5636 * is cleared if the PF only added itself to the pool
5637 * because the PF is in promiscuous mode.
5638 */
5639 if ((vlvf & VLAN_VID_MASK) == vid &&
5640 !test_bit(vid, adapter->active_vlans) &&
5641 !bits)
5642 igb_vlvf_set(adapter, vid, add,
5643 adapter->vfs_allocated_count);
5644 }
5645
5646out:
5647 return err;
5648}
5649
5650static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
5651{
5652 /* clear flags - except flag that indicates PF has set the MAC */
5653 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
5654 adapter->vf_data[vf].last_nack = jiffies;
5655
5656 /* reset offloads to defaults */
5657 igb_set_vmolr(adapter, vf, true);
5658
5659 /* reset vlans for device */
5660 igb_clear_vf_vfta(adapter, vf);
5661 if (adapter->vf_data[vf].pf_vlan)
5662 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5663 adapter->vf_data[vf].pf_vlan,
5664 adapter->vf_data[vf].pf_qos);
5665 else
5666 igb_clear_vf_vfta(adapter, vf);
5667
5668 /* reset multicast table array for vf */
5669 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5670
5671 /* Flush and reset the mta with the new values */
5672 igb_set_rx_mode(adapter->netdev);
5673}
5674
5675static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5676{
5677 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5678
5679 /* clear mac address as we were hotplug removed/added */
5680 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5681 eth_zero_addr(vf_mac);
5682
5683 /* process remaining reset events */
5684 igb_vf_reset(adapter, vf);
5685}
5686
5687static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
5688{
5689 struct e1000_hw *hw = &adapter->hw;
5690 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5691 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
5692 u32 reg, msgbuf[3];
5693 u8 *addr = (u8 *)(&msgbuf[1]);
5694
5695 /* process all the same items cleared in a function level reset */
5696 igb_vf_reset(adapter, vf);
5697
5698 /* set vf mac address */
5699 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
5700
5701 /* enable transmit and receive for vf */
5702 reg = rd32(E1000_VFTE);
5703 wr32(E1000_VFTE, reg | (1 << vf));
5704 reg = rd32(E1000_VFRE);
5705 wr32(E1000_VFRE, reg | (1 << vf));
5706
5707 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
5708
5709 /* reply to reset with ack and vf mac address */
5710 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5711 memcpy(addr, vf_mac, 6);
5712 igb_write_mbx(hw, msgbuf, 3, vf);
5713}
5714
5715static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5716{
5717 /* The VF MAC Address is stored in a packed array of bytes
5718 * starting at the second 32 bit word of the msg array
5719 */
5720 unsigned char *addr = (char *)&msg[1];
5721 int err = -1;
5722
5723 if (is_valid_ether_addr(addr))
5724 err = igb_set_vf_mac(adapter, vf, addr);
5725
5726 return err;
5727}
5728
5729static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5730{
5731 struct e1000_hw *hw = &adapter->hw;
5732 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5733 u32 msg = E1000_VT_MSGTYPE_NACK;
5734
5735 /* if device isn't clear to send it shouldn't be reading either */
5736 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5737 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
5738 igb_write_mbx(hw, &msg, 1, vf);
5739 vf_data->last_nack = jiffies;
5740 }
5741}
5742
5743static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
5744{
5745 struct pci_dev *pdev = adapter->pdev;
5746 u32 msgbuf[E1000_VFMAILBOX_SIZE];
5747 struct e1000_hw *hw = &adapter->hw;
5748 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5749 s32 retval;
5750
5751 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
5752
5753 if (retval) {
5754 /* if receive failed revoke VF CTS stats and restart init */
5755 dev_err(&pdev->dev, "Error receiving message from VF\n");
5756 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5757 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5758 return;
5759 goto out;
5760 }
5761
5762 /* this is a message we already processed, do nothing */
5763 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
5764 return;
5765
5766 /* until the vf completes a reset it should not be
5767 * allowed to start any configuration.
5768 */
5769 if (msgbuf[0] == E1000_VF_RESET) {
5770 igb_vf_reset_msg(adapter, vf);
5771 return;
5772 }
5773
5774 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
5775 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5776 return;
5777 retval = -1;
5778 goto out;
5779 }
5780
5781 switch ((msgbuf[0] & 0xFFFF)) {
5782 case E1000_VF_SET_MAC_ADDR:
5783 retval = -EINVAL;
5784 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5785 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5786 else
5787 dev_warn(&pdev->dev,
5788 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
5789 vf);
5790 break;
5791 case E1000_VF_SET_PROMISC:
5792 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5793 break;
5794 case E1000_VF_SET_MULTICAST:
5795 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5796 break;
5797 case E1000_VF_SET_LPE:
5798 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5799 break;
5800 case E1000_VF_SET_VLAN:
5801 retval = -1;
5802 if (vf_data->pf_vlan)
5803 dev_warn(&pdev->dev,
5804 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
5805 vf);
5806 else
5807 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
5808 break;
5809 default:
5810 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
5811 retval = -1;
5812 break;
5813 }
5814
5815 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5816out:
5817 /* notify the VF of the results of what it sent us */
5818 if (retval)
5819 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5820 else
5821 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5822
5823 igb_write_mbx(hw, msgbuf, 1, vf);
5824}
5825
5826static void igb_msg_task(struct igb_adapter *adapter)
5827{
5828 struct e1000_hw *hw = &adapter->hw;
5829 u32 vf;
5830
5831 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5832 /* process any reset requests */
5833 if (!igb_check_for_rst(hw, vf))
5834 igb_vf_reset_event(adapter, vf);
5835
5836 /* process any messages pending */
5837 if (!igb_check_for_msg(hw, vf))
5838 igb_rcv_msg_from_vf(adapter, vf);
5839
5840 /* process any acks */
5841 if (!igb_check_for_ack(hw, vf))
5842 igb_rcv_ack_from_vf(adapter, vf);
5843 }
5844}
5845
5846/**
5847 * igb_set_uta - Set unicast filter table address
5848 * @adapter: board private structure
5849 *
5850 * The unicast table address is a register array of 32-bit registers.
5851 * The table is meant to be used in a way similar to how the MTA is used
5852 * however due to certain limitations in the hardware it is necessary to
5853 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5854 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
5855 **/
5856static void igb_set_uta(struct igb_adapter *adapter)
5857{
5858 struct e1000_hw *hw = &adapter->hw;
5859 int i;
5860
5861 /* The UTA table only exists on 82576 hardware and newer */
5862 if (hw->mac.type < e1000_82576)
5863 return;
5864
5865 /* we only need to do this if VMDq is enabled */
5866 if (!adapter->vfs_allocated_count)
5867 return;
5868
5869 for (i = 0; i < hw->mac.uta_reg_count; i++)
5870 array_wr32(E1000_UTA, i, ~0);
5871}
5872
5873/**
5874 * igb_intr_msi - Interrupt Handler
5875 * @irq: interrupt number
5876 * @data: pointer to a network interface device structure
5877 **/
5878static irqreturn_t igb_intr_msi(int irq, void *data)
5879{
5880 struct igb_adapter *adapter = data;
5881 struct igb_q_vector *q_vector = adapter->q_vector[0];
5882 struct e1000_hw *hw = &adapter->hw;
5883 /* read ICR disables interrupts using IAM */
5884 u32 icr = rd32(E1000_ICR);
5885
5886 igb_write_itr(q_vector);
5887
5888 if (icr & E1000_ICR_DRSTA)
5889 schedule_work(&adapter->reset_task);
5890
5891 if (icr & E1000_ICR_DOUTSYNC) {
5892 /* HW is reporting DMA is out of sync */
5893 adapter->stats.doosync++;
5894 }
5895
5896 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5897 hw->mac.get_link_status = 1;
5898 if (!test_bit(__IGB_DOWN, &adapter->state))
5899 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5900 }
5901
5902 if (icr & E1000_ICR_TS) {
5903 u32 tsicr = rd32(E1000_TSICR);
5904
5905 if (tsicr & E1000_TSICR_TXTS) {
5906 /* acknowledge the interrupt */
5907 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5908 /* retrieve hardware timestamp */
5909 schedule_work(&adapter->ptp_tx_work);
5910 }
5911 }
5912
5913 napi_schedule(&q_vector->napi);
5914
5915 return IRQ_HANDLED;
5916}
5917
5918/**
5919 * igb_intr - Legacy Interrupt Handler
5920 * @irq: interrupt number
5921 * @data: pointer to a network interface device structure
5922 **/
5923static irqreturn_t igb_intr(int irq, void *data)
5924{
5925 struct igb_adapter *adapter = data;
5926 struct igb_q_vector *q_vector = adapter->q_vector[0];
5927 struct e1000_hw *hw = &adapter->hw;
5928 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5929 * need for the IMC write
5930 */
5931 u32 icr = rd32(E1000_ICR);
5932
5933 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5934 * not set, then the adapter didn't send an interrupt
5935 */
5936 if (!(icr & E1000_ICR_INT_ASSERTED))
5937 return IRQ_NONE;
5938
5939 igb_write_itr(q_vector);
5940
5941 if (icr & E1000_ICR_DRSTA)
5942 schedule_work(&adapter->reset_task);
5943
5944 if (icr & E1000_ICR_DOUTSYNC) {
5945 /* HW is reporting DMA is out of sync */
5946 adapter->stats.doosync++;
5947 }
5948
5949 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5950 hw->mac.get_link_status = 1;
5951 /* guard against interrupt when we're going down */
5952 if (!test_bit(__IGB_DOWN, &adapter->state))
5953 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5954 }
5955
5956 if (icr & E1000_ICR_TS) {
5957 u32 tsicr = rd32(E1000_TSICR);
5958
5959 if (tsicr & E1000_TSICR_TXTS) {
5960 /* acknowledge the interrupt */
5961 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5962 /* retrieve hardware timestamp */
5963 schedule_work(&adapter->ptp_tx_work);
5964 }
5965 }
5966
5967 napi_schedule(&q_vector->napi);
5968
5969 return IRQ_HANDLED;
5970}
5971
5972static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
5973{
5974 struct igb_adapter *adapter = q_vector->adapter;
5975 struct e1000_hw *hw = &adapter->hw;
5976
5977 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5978 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5979 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5980 igb_set_itr(q_vector);
5981 else
5982 igb_update_ring_itr(q_vector);
5983 }
5984
5985 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5986 if (adapter->msix_entries)
5987 wr32(E1000_EIMS, q_vector->eims_value);
5988 else
5989 igb_irq_enable(adapter);
5990 }
5991}
5992
5993/**
5994 * igb_poll - NAPI Rx polling callback
5995 * @napi: napi polling structure
5996 * @budget: count of how many packets we should handle
5997 **/
5998static int igb_poll(struct napi_struct *napi, int budget)
5999{
6000 struct igb_q_vector *q_vector = container_of(napi,
6001 struct igb_q_vector,
6002 napi);
6003 bool clean_complete = true;
6004
6005#ifdef CONFIG_IGB_DCA
6006 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6007 igb_update_dca(q_vector);
6008#endif
6009 if (q_vector->tx.ring)
6010 clean_complete = igb_clean_tx_irq(q_vector);
6011
6012 if (q_vector->rx.ring)
6013 clean_complete &= igb_clean_rx_irq(q_vector, budget);
6014
6015 /* If all work not completed, return budget and keep polling */
6016 if (!clean_complete)
6017 return budget;
6018
6019 /* If not enough Rx work done, exit the polling mode */
6020 napi_complete(napi);
6021 igb_ring_irq_enable(q_vector);
6022
6023 return 0;
6024}
6025
6026/**
6027 * igb_clean_tx_irq - Reclaim resources after transmit completes
6028 * @q_vector: pointer to q_vector containing needed info
6029 *
6030 * returns true if ring is completely cleaned
6031 **/
6032static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
6033{
6034 struct igb_adapter *adapter = q_vector->adapter;
6035 struct igb_ring *tx_ring = q_vector->tx.ring;
6036 struct igb_tx_buffer *tx_buffer;
6037 union e1000_adv_tx_desc *tx_desc;
6038 unsigned int total_bytes = 0, total_packets = 0;
6039 unsigned int budget = q_vector->tx.work_limit;
6040 unsigned int i = tx_ring->next_to_clean;
6041
6042 if (test_bit(__IGB_DOWN, &adapter->state))
6043 return true;
6044
6045 tx_buffer = &tx_ring->tx_buffer_info[i];
6046 tx_desc = IGB_TX_DESC(tx_ring, i);
6047 i -= tx_ring->count;
6048
6049 do {
6050 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
6051
6052 /* if next_to_watch is not set then there is no work pending */
6053 if (!eop_desc)
6054 break;
6055
6056 /* prevent any other reads prior to eop_desc */
6057 read_barrier_depends();
6058
6059 /* if DD is not set pending work has not been completed */
6060 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6061 break;
6062
6063 /* clear next_to_watch to prevent false hangs */
6064 tx_buffer->next_to_watch = NULL;
6065
6066 /* update the statistics for this packet */
6067 total_bytes += tx_buffer->bytecount;
6068 total_packets += tx_buffer->gso_segs;
6069
6070 /* free the skb */
6071 dev_kfree_skb_any(tx_buffer->skb);
6072
6073 /* unmap skb header data */
6074 dma_unmap_single(tx_ring->dev,
6075 dma_unmap_addr(tx_buffer, dma),
6076 dma_unmap_len(tx_buffer, len),
6077 DMA_TO_DEVICE);
6078
6079 /* clear tx_buffer data */
6080 tx_buffer->skb = NULL;
6081 dma_unmap_len_set(tx_buffer, len, 0);
6082
6083 /* clear last DMA location and unmap remaining buffers */
6084 while (tx_desc != eop_desc) {
6085 tx_buffer++;
6086 tx_desc++;
6087 i++;
6088 if (unlikely(!i)) {
6089 i -= tx_ring->count;
6090 tx_buffer = tx_ring->tx_buffer_info;
6091 tx_desc = IGB_TX_DESC(tx_ring, 0);
6092 }
6093
6094 /* unmap any remaining paged data */
6095 if (dma_unmap_len(tx_buffer, len)) {
6096 dma_unmap_page(tx_ring->dev,
6097 dma_unmap_addr(tx_buffer, dma),
6098 dma_unmap_len(tx_buffer, len),
6099 DMA_TO_DEVICE);
6100 dma_unmap_len_set(tx_buffer, len, 0);
6101 }
6102 }
6103
6104 /* move us one more past the eop_desc for start of next pkt */
6105 tx_buffer++;
6106 tx_desc++;
6107 i++;
6108 if (unlikely(!i)) {
6109 i -= tx_ring->count;
6110 tx_buffer = tx_ring->tx_buffer_info;
6111 tx_desc = IGB_TX_DESC(tx_ring, 0);
6112 }
6113
6114 /* issue prefetch for next Tx descriptor */
6115 prefetch(tx_desc);
6116
6117 /* update budget accounting */
6118 budget--;
6119 } while (likely(budget));
6120
6121 netdev_tx_completed_queue(txring_txq(tx_ring),
6122 total_packets, total_bytes);
6123 i += tx_ring->count;
6124 tx_ring->next_to_clean = i;
6125 u64_stats_update_begin(&tx_ring->tx_syncp);
6126 tx_ring->tx_stats.bytes += total_bytes;
6127 tx_ring->tx_stats.packets += total_packets;
6128 u64_stats_update_end(&tx_ring->tx_syncp);
6129 q_vector->tx.total_bytes += total_bytes;
6130 q_vector->tx.total_packets += total_packets;
6131
6132 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
6133 struct e1000_hw *hw = &adapter->hw;
6134
6135 /* Detect a transmit hang in hardware, this serializes the
6136 * check with the clearing of time_stamp and movement of i
6137 */
6138 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
6139 if (tx_buffer->next_to_watch &&
6140 time_after(jiffies, tx_buffer->time_stamp +
6141 (adapter->tx_timeout_factor * HZ)) &&
6142 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
6143
6144 /* detected Tx unit hang */
6145 dev_err(tx_ring->dev,
6146 "Detected Tx Unit Hang\n"
6147 " Tx Queue <%d>\n"
6148 " TDH <%x>\n"
6149 " TDT <%x>\n"
6150 " next_to_use <%x>\n"
6151 " next_to_clean <%x>\n"
6152 "buffer_info[next_to_clean]\n"
6153 " time_stamp <%lx>\n"
6154 " next_to_watch <%p>\n"
6155 " jiffies <%lx>\n"
6156 " desc.status <%x>\n",
6157 tx_ring->queue_index,
6158 rd32(E1000_TDH(tx_ring->reg_idx)),
6159 readl(tx_ring->tail),
6160 tx_ring->next_to_use,
6161 tx_ring->next_to_clean,
6162 tx_buffer->time_stamp,
6163 tx_buffer->next_to_watch,
6164 jiffies,
6165 tx_buffer->next_to_watch->wb.status);
6166 netif_stop_subqueue(tx_ring->netdev,
6167 tx_ring->queue_index);
6168
6169 /* we are about to reset, no point in enabling stuff */
6170 return true;
6171 }
6172 }
6173
6174#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6175 if (unlikely(total_packets &&
6176 netif_carrier_ok(tx_ring->netdev) &&
6177 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
6178 /* Make sure that anybody stopping the queue after this
6179 * sees the new next_to_clean.
6180 */
6181 smp_mb();
6182 if (__netif_subqueue_stopped(tx_ring->netdev,
6183 tx_ring->queue_index) &&
6184 !(test_bit(__IGB_DOWN, &adapter->state))) {
6185 netif_wake_subqueue(tx_ring->netdev,
6186 tx_ring->queue_index);
6187
6188 u64_stats_update_begin(&tx_ring->tx_syncp);
6189 tx_ring->tx_stats.restart_queue++;
6190 u64_stats_update_end(&tx_ring->tx_syncp);
6191 }
6192 }
6193
6194 return !!budget;
6195}
6196
6197/**
6198 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6199 * @rx_ring: rx descriptor ring to store buffers on
6200 * @old_buff: donor buffer to have page reused
6201 *
6202 * Synchronizes page for reuse by the adapter
6203 **/
6204static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6205 struct igb_rx_buffer *old_buff)
6206{
6207 struct igb_rx_buffer *new_buff;
6208 u16 nta = rx_ring->next_to_alloc;
6209
6210 new_buff = &rx_ring->rx_buffer_info[nta];
6211
6212 /* update, and store next to alloc */
6213 nta++;
6214 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6215
6216 /* transfer page from old buffer to new buffer */
6217 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6218
6219 /* sync the buffer for use by the device */
6220 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6221 old_buff->page_offset,
6222 IGB_RX_BUFSZ,
6223 DMA_FROM_DEVICE);
6224}
6225
6226static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6227 struct page *page,
6228 unsigned int truesize)
6229{
6230 /* avoid re-using remote pages */
6231 if (unlikely(page_to_nid(page) != numa_node_id()))
6232 return false;
6233
6234#if (PAGE_SIZE < 8192)
6235 /* if we are only owner of page we can reuse it */
6236 if (unlikely(page_count(page) != 1))
6237 return false;
6238
6239 /* flip page offset to other buffer */
6240 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6241
6242 /* since we are the only owner of the page and we need to
6243 * increment it, just set the value to 2 in order to avoid
6244 * an unnecessary locked operation
6245 */
6246 atomic_set(&page->_count, 2);
6247#else
6248 /* move offset up to the next cache line */
6249 rx_buffer->page_offset += truesize;
6250
6251 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6252 return false;
6253
6254 /* bump ref count on page before it is given to the stack */
6255 get_page(page);
6256#endif
6257
6258 return true;
6259}
6260
6261/**
6262 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6263 * @rx_ring: rx descriptor ring to transact packets on
6264 * @rx_buffer: buffer containing page to add
6265 * @rx_desc: descriptor containing length of buffer written by hardware
6266 * @skb: sk_buff to place the data into
6267 *
6268 * This function will add the data contained in rx_buffer->page to the skb.
6269 * This is done either through a direct copy if the data in the buffer is
6270 * less than the skb header size, otherwise it will just attach the page as
6271 * a frag to the skb.
6272 *
6273 * The function will then update the page offset if necessary and return
6274 * true if the buffer can be reused by the adapter.
6275 **/
6276static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6277 struct igb_rx_buffer *rx_buffer,
6278 union e1000_adv_rx_desc *rx_desc,
6279 struct sk_buff *skb)
6280{
6281 struct page *page = rx_buffer->page;
6282 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6283#if (PAGE_SIZE < 8192)
6284 unsigned int truesize = IGB_RX_BUFSZ;
6285#else
6286 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6287#endif
6288
6289 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6290 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6291
6292 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6293 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6294 va += IGB_TS_HDR_LEN;
6295 size -= IGB_TS_HDR_LEN;
6296 }
6297
6298 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6299
6300 /* we can reuse buffer as-is, just make sure it is local */
6301 if (likely(page_to_nid(page) == numa_node_id()))
6302 return true;
6303
6304 /* this page cannot be reused so discard it */
6305 put_page(page);
6306 return false;
6307 }
6308
6309 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6310 rx_buffer->page_offset, size, truesize);
6311
6312 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6313}
6314
6315static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6316 union e1000_adv_rx_desc *rx_desc,
6317 struct sk_buff *skb)
6318{
6319 struct igb_rx_buffer *rx_buffer;
6320 struct page *page;
6321
6322 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6323
6324 page = rx_buffer->page;
6325 prefetchw(page);
6326
6327 if (likely(!skb)) {
6328 void *page_addr = page_address(page) +
6329 rx_buffer->page_offset;
6330
6331 /* prefetch first cache line of first page */
6332 prefetch(page_addr);
6333#if L1_CACHE_BYTES < 128
6334 prefetch(page_addr + L1_CACHE_BYTES);
6335#endif
6336
6337 /* allocate a skb to store the frags */
6338 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6339 IGB_RX_HDR_LEN);
6340 if (unlikely(!skb)) {
6341 rx_ring->rx_stats.alloc_failed++;
6342 return NULL;
6343 }
6344
6345 /* we will be copying header into skb->data in
6346 * pskb_may_pull so it is in our interest to prefetch
6347 * it now to avoid a possible cache miss
6348 */
6349 prefetchw(skb->data);
6350 }
6351
6352 /* we are reusing so sync this buffer for CPU use */
6353 dma_sync_single_range_for_cpu(rx_ring->dev,
6354 rx_buffer->dma,
6355 rx_buffer->page_offset,
6356 IGB_RX_BUFSZ,
6357 DMA_FROM_DEVICE);
6358
6359 /* pull page into skb */
6360 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6361 /* hand second half of page back to the ring */
6362 igb_reuse_rx_page(rx_ring, rx_buffer);
6363 } else {
6364 /* we are not reusing the buffer so unmap it */
6365 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6366 PAGE_SIZE, DMA_FROM_DEVICE);
6367 }
6368
6369 /* clear contents of rx_buffer */
6370 rx_buffer->page = NULL;
6371
6372 return skb;
6373}
6374
6375static inline void igb_rx_checksum(struct igb_ring *ring,
6376 union e1000_adv_rx_desc *rx_desc,
6377 struct sk_buff *skb)
6378{
6379 skb_checksum_none_assert(skb);
6380
6381 /* Ignore Checksum bit is set */
6382 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6383 return;
6384
6385 /* Rx checksum disabled via ethtool */
6386 if (!(ring->netdev->features & NETIF_F_RXCSUM))
6387 return;
6388
6389 /* TCP/UDP checksum error bit is set */
6390 if (igb_test_staterr(rx_desc,
6391 E1000_RXDEXT_STATERR_TCPE |
6392 E1000_RXDEXT_STATERR_IPE)) {
6393 /* work around errata with sctp packets where the TCPE aka
6394 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6395 * packets, (aka let the stack check the crc32c)
6396 */
6397 if (!((skb->len == 60) &&
6398 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6399 u64_stats_update_begin(&ring->rx_syncp);
6400 ring->rx_stats.csum_err++;
6401 u64_stats_update_end(&ring->rx_syncp);
6402 }
6403 /* let the stack verify checksum errors */
6404 return;
6405 }
6406 /* It must be a TCP or UDP packet with a valid checksum */
6407 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6408 E1000_RXD_STAT_UDPCS))
6409 skb->ip_summed = CHECKSUM_UNNECESSARY;
6410
6411 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6412 le32_to_cpu(rx_desc->wb.upper.status_error));
6413}
6414
6415static inline void igb_rx_hash(struct igb_ring *ring,
6416 union e1000_adv_rx_desc *rx_desc,
6417 struct sk_buff *skb)
6418{
6419 if (ring->netdev->features & NETIF_F_RXHASH)
6420 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6421}
6422
6423/**
6424 * igb_is_non_eop - process handling of non-EOP buffers
6425 * @rx_ring: Rx ring being processed
6426 * @rx_desc: Rx descriptor for current buffer
6427 * @skb: current socket buffer containing buffer in progress
6428 *
6429 * This function updates next to clean. If the buffer is an EOP buffer
6430 * this function exits returning false, otherwise it will place the
6431 * sk_buff in the next buffer to be chained and return true indicating
6432 * that this is in fact a non-EOP buffer.
6433 **/
6434static bool igb_is_non_eop(struct igb_ring *rx_ring,
6435 union e1000_adv_rx_desc *rx_desc)
6436{
6437 u32 ntc = rx_ring->next_to_clean + 1;
6438
6439 /* fetch, update, and store next to clean */
6440 ntc = (ntc < rx_ring->count) ? ntc : 0;
6441 rx_ring->next_to_clean = ntc;
6442
6443 prefetch(IGB_RX_DESC(rx_ring, ntc));
6444
6445 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6446 return false;
6447
6448 return true;
6449}
6450
6451/**
6452 * igb_get_headlen - determine size of header for LRO/GRO
6453 * @data: pointer to the start of the headers
6454 * @max_len: total length of section to find headers in
6455 *
6456 * This function is meant to determine the length of headers that will
6457 * be recognized by hardware for LRO, and GRO offloads. The main
6458 * motivation of doing this is to only perform one pull for IPv4 TCP
6459 * packets so that we can do basic things like calculating the gso_size
6460 * based on the average data per packet.
6461 **/
6462static unsigned int igb_get_headlen(unsigned char *data,
6463 unsigned int max_len)
6464{
6465 union {
6466 unsigned char *network;
6467 /* l2 headers */
6468 struct ethhdr *eth;
6469 struct vlan_hdr *vlan;
6470 /* l3 headers */
6471 struct iphdr *ipv4;
6472 struct ipv6hdr *ipv6;
6473 } hdr;
6474 __be16 protocol;
6475 u8 nexthdr = 0; /* default to not TCP */
6476 u8 hlen;
6477
6478 /* this should never happen, but better safe than sorry */
6479 if (max_len < ETH_HLEN)
6480 return max_len;
6481
6482 /* initialize network frame pointer */
6483 hdr.network = data;
6484
6485 /* set first protocol and move network header forward */
6486 protocol = hdr.eth->h_proto;
6487 hdr.network += ETH_HLEN;
6488
6489 /* handle any vlan tag if present */
6490 if (protocol == __constant_htons(ETH_P_8021Q)) {
6491 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6492 return max_len;
6493
6494 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6495 hdr.network += VLAN_HLEN;
6496 }
6497
6498 /* handle L3 protocols */
6499 if (protocol == __constant_htons(ETH_P_IP)) {
6500 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6501 return max_len;
6502
6503 /* access ihl as a u8 to avoid unaligned access on ia64 */
6504 hlen = (hdr.network[0] & 0x0F) << 2;
6505
6506 /* verify hlen meets minimum size requirements */
6507 if (hlen < sizeof(struct iphdr))
6508 return hdr.network - data;
6509
6510 /* record next protocol if header is present */
6511 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
6512 nexthdr = hdr.ipv4->protocol;
6513 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6514 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6515 return max_len;
6516
6517 /* record next protocol */
6518 nexthdr = hdr.ipv6->nexthdr;
6519 hlen = sizeof(struct ipv6hdr);
6520 } else {
6521 return hdr.network - data;
6522 }
6523
6524 /* relocate pointer to start of L4 header */
6525 hdr.network += hlen;
6526
6527 /* finally sort out TCP */
6528 if (nexthdr == IPPROTO_TCP) {
6529 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6530 return max_len;
6531
6532 /* access doff as a u8 to avoid unaligned access on ia64 */
6533 hlen = (hdr.network[12] & 0xF0) >> 2;
6534
6535 /* verify hlen meets minimum size requirements */
6536 if (hlen < sizeof(struct tcphdr))
6537 return hdr.network - data;
6538
6539 hdr.network += hlen;
6540 } else if (nexthdr == IPPROTO_UDP) {
6541 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6542 return max_len;
6543
6544 hdr.network += sizeof(struct udphdr);
6545 }
6546
6547 /* If everything has gone correctly hdr.network should be the
6548 * data section of the packet and will be the end of the header.
6549 * If not then it probably represents the end of the last recognized
6550 * header.
6551 */
6552 if ((hdr.network - data) < max_len)
6553 return hdr.network - data;
6554 else
6555 return max_len;
6556}
6557
6558/**
6559 * igb_pull_tail - igb specific version of skb_pull_tail
6560 * @rx_ring: rx descriptor ring packet is being transacted on
6561 * @rx_desc: pointer to the EOP Rx descriptor
6562 * @skb: pointer to current skb being adjusted
6563 *
6564 * This function is an igb specific version of __pskb_pull_tail. The
6565 * main difference between this version and the original function is that
6566 * this function can make several assumptions about the state of things
6567 * that allow for significant optimizations versus the standard function.
6568 * As a result we can do things like drop a frag and maintain an accurate
6569 * truesize for the skb.
6570 */
6571static void igb_pull_tail(struct igb_ring *rx_ring,
6572 union e1000_adv_rx_desc *rx_desc,
6573 struct sk_buff *skb)
6574{
6575 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6576 unsigned char *va;
6577 unsigned int pull_len;
6578
6579 /* it is valid to use page_address instead of kmap since we are
6580 * working with pages allocated out of the lomem pool per
6581 * alloc_page(GFP_ATOMIC)
6582 */
6583 va = skb_frag_address(frag);
6584
6585 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6586 /* retrieve timestamp from buffer */
6587 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6588
6589 /* update pointers to remove timestamp header */
6590 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6591 frag->page_offset += IGB_TS_HDR_LEN;
6592 skb->data_len -= IGB_TS_HDR_LEN;
6593 skb->len -= IGB_TS_HDR_LEN;
6594
6595 /* move va to start of packet data */
6596 va += IGB_TS_HDR_LEN;
6597 }
6598
6599 /* we need the header to contain the greater of either ETH_HLEN or
6600 * 60 bytes if the skb->len is less than 60 for skb_pad.
6601 */
6602 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6603
6604 /* align pull length to size of long to optimize memcpy performance */
6605 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6606
6607 /* update all of the pointers */
6608 skb_frag_size_sub(frag, pull_len);
6609 frag->page_offset += pull_len;
6610 skb->data_len -= pull_len;
6611 skb->tail += pull_len;
6612}
6613
6614/**
6615 * igb_cleanup_headers - Correct corrupted or empty headers
6616 * @rx_ring: rx descriptor ring packet is being transacted on
6617 * @rx_desc: pointer to the EOP Rx descriptor
6618 * @skb: pointer to current skb being fixed
6619 *
6620 * Address the case where we are pulling data in on pages only
6621 * and as such no data is present in the skb header.
6622 *
6623 * In addition if skb is not at least 60 bytes we need to pad it so that
6624 * it is large enough to qualify as a valid Ethernet frame.
6625 *
6626 * Returns true if an error was encountered and skb was freed.
6627 **/
6628static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6629 union e1000_adv_rx_desc *rx_desc,
6630 struct sk_buff *skb)
6631{
6632 if (unlikely((igb_test_staterr(rx_desc,
6633 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6634 struct net_device *netdev = rx_ring->netdev;
6635 if (!(netdev->features & NETIF_F_RXALL)) {
6636 dev_kfree_skb_any(skb);
6637 return true;
6638 }
6639 }
6640
6641 /* place header in linear portion of buffer */
6642 if (skb_is_nonlinear(skb))
6643 igb_pull_tail(rx_ring, rx_desc, skb);
6644
6645 /* if skb_pad returns an error the skb was freed */
6646 if (unlikely(skb->len < 60)) {
6647 int pad_len = 60 - skb->len;
6648
6649 if (skb_pad(skb, pad_len))
6650 return true;
6651 __skb_put(skb, pad_len);
6652 }
6653
6654 return false;
6655}
6656
6657/**
6658 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6659 * @rx_ring: rx descriptor ring packet is being transacted on
6660 * @rx_desc: pointer to the EOP Rx descriptor
6661 * @skb: pointer to current skb being populated
6662 *
6663 * This function checks the ring, descriptor, and packet information in
6664 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6665 * other fields within the skb.
6666 **/
6667static void igb_process_skb_fields(struct igb_ring *rx_ring,
6668 union e1000_adv_rx_desc *rx_desc,
6669 struct sk_buff *skb)
6670{
6671 struct net_device *dev = rx_ring->netdev;
6672
6673 igb_rx_hash(rx_ring, rx_desc, skb);
6674
6675 igb_rx_checksum(rx_ring, rx_desc, skb);
6676
6677 igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
6678
6679 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
6680 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6681 u16 vid;
6682 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6683 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6684 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6685 else
6686 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6687
6688 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
6689 }
6690
6691 skb_record_rx_queue(skb, rx_ring->queue_index);
6692
6693 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6694}
6695
6696static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6697{
6698 struct igb_ring *rx_ring = q_vector->rx.ring;
6699 struct sk_buff *skb = rx_ring->skb;
6700 unsigned int total_bytes = 0, total_packets = 0;
6701 u16 cleaned_count = igb_desc_unused(rx_ring);
6702
6703 do {
6704 union e1000_adv_rx_desc *rx_desc;
6705
6706 /* return some buffers to hardware, one at a time is too slow */
6707 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6708 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6709 cleaned_count = 0;
6710 }
6711
6712 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6713
6714 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6715 break;
6716
6717 /* This memory barrier is needed to keep us from reading
6718 * any other fields out of the rx_desc until we know the
6719 * RXD_STAT_DD bit is set
6720 */
6721 rmb();
6722
6723 /* retrieve a buffer from the ring */
6724 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6725
6726 /* exit if we failed to retrieve a buffer */
6727 if (!skb)
6728 break;
6729
6730 cleaned_count++;
6731
6732 /* fetch next buffer in frame if non-eop */
6733 if (igb_is_non_eop(rx_ring, rx_desc))
6734 continue;
6735
6736 /* verify the packet layout is correct */
6737 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6738 skb = NULL;
6739 continue;
6740 }
6741
6742 /* probably a little skewed due to removing CRC */
6743 total_bytes += skb->len;
6744
6745 /* populate checksum, timestamp, VLAN, and protocol */
6746 igb_process_skb_fields(rx_ring, rx_desc, skb);
6747
6748 napi_gro_receive(&q_vector->napi, skb);
6749
6750 /* reset skb pointer */
6751 skb = NULL;
6752
6753 /* update budget accounting */
6754 total_packets++;
6755 } while (likely(total_packets < budget));
6756
6757 /* place incomplete frames back on ring for completion */
6758 rx_ring->skb = skb;
6759
6760 u64_stats_update_begin(&rx_ring->rx_syncp);
6761 rx_ring->rx_stats.packets += total_packets;
6762 rx_ring->rx_stats.bytes += total_bytes;
6763 u64_stats_update_end(&rx_ring->rx_syncp);
6764 q_vector->rx.total_packets += total_packets;
6765 q_vector->rx.total_bytes += total_bytes;
6766
6767 if (cleaned_count)
6768 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6769
6770 return (total_packets < budget);
6771}
6772
6773static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
6774 struct igb_rx_buffer *bi)
6775{
6776 struct page *page = bi->page;
6777 dma_addr_t dma;
6778
6779 /* since we are recycling buffers we should seldom need to alloc */
6780 if (likely(page))
6781 return true;
6782
6783 /* alloc new page for storage */
6784 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6785 if (unlikely(!page)) {
6786 rx_ring->rx_stats.alloc_failed++;
6787 return false;
6788 }
6789
6790 /* map page for use */
6791 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
6792
6793 /* if mapping failed free memory back to system since
6794 * there isn't much point in holding memory we can't use
6795 */
6796 if (dma_mapping_error(rx_ring->dev, dma)) {
6797 __free_page(page);
6798
6799 rx_ring->rx_stats.alloc_failed++;
6800 return false;
6801 }
6802
6803 bi->dma = dma;
6804 bi->page = page;
6805 bi->page_offset = 0;
6806
6807 return true;
6808}
6809
6810/**
6811 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
6812 * @adapter: address of board private structure
6813 **/
6814void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
6815{
6816 union e1000_adv_rx_desc *rx_desc;
6817 struct igb_rx_buffer *bi;
6818 u16 i = rx_ring->next_to_use;
6819
6820 /* nothing to do */
6821 if (!cleaned_count)
6822 return;
6823
6824 rx_desc = IGB_RX_DESC(rx_ring, i);
6825 bi = &rx_ring->rx_buffer_info[i];
6826 i -= rx_ring->count;
6827
6828 do {
6829 if (!igb_alloc_mapped_page(rx_ring, bi))
6830 break;
6831
6832 /* Refresh the desc even if buffer_addrs didn't change
6833 * because each write-back erases this info.
6834 */
6835 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
6836
6837 rx_desc++;
6838 bi++;
6839 i++;
6840 if (unlikely(!i)) {
6841 rx_desc = IGB_RX_DESC(rx_ring, 0);
6842 bi = rx_ring->rx_buffer_info;
6843 i -= rx_ring->count;
6844 }
6845
6846 /* clear the hdr_addr for the next_to_use descriptor */
6847 rx_desc->read.hdr_addr = 0;
6848
6849 cleaned_count--;
6850 } while (cleaned_count);
6851
6852 i += rx_ring->count;
6853
6854 if (rx_ring->next_to_use != i) {
6855 /* record the next descriptor to use */
6856 rx_ring->next_to_use = i;
6857
6858 /* update next to alloc since we have filled the ring */
6859 rx_ring->next_to_alloc = i;
6860
6861 /* Force memory writes to complete before letting h/w
6862 * know there are new descriptors to fetch. (Only
6863 * applicable for weak-ordered memory model archs,
6864 * such as IA-64).
6865 */
6866 wmb();
6867 writel(i, rx_ring->tail);
6868 }
6869}
6870
6871/**
6872 * igb_mii_ioctl -
6873 * @netdev:
6874 * @ifreq:
6875 * @cmd:
6876 **/
6877static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6878{
6879 struct igb_adapter *adapter = netdev_priv(netdev);
6880 struct mii_ioctl_data *data = if_mii(ifr);
6881
6882 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6883 return -EOPNOTSUPP;
6884
6885 switch (cmd) {
6886 case SIOCGMIIPHY:
6887 data->phy_id = adapter->hw.phy.addr;
6888 break;
6889 case SIOCGMIIREG:
6890 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6891 &data->val_out))
6892 return -EIO;
6893 break;
6894 case SIOCSMIIREG:
6895 default:
6896 return -EOPNOTSUPP;
6897 }
6898 return 0;
6899}
6900
6901/**
6902 * igb_ioctl -
6903 * @netdev:
6904 * @ifreq:
6905 * @cmd:
6906 **/
6907static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6908{
6909 switch (cmd) {
6910 case SIOCGMIIPHY:
6911 case SIOCGMIIREG:
6912 case SIOCSMIIREG:
6913 return igb_mii_ioctl(netdev, ifr, cmd);
6914 case SIOCSHWTSTAMP:
6915 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
6916 default:
6917 return -EOPNOTSUPP;
6918 }
6919}
6920
6921s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6922{
6923 struct igb_adapter *adapter = hw->back;
6924
6925 if (pcie_capability_read_word(adapter->pdev, reg, value))
6926 return -E1000_ERR_CONFIG;
6927
6928 return 0;
6929}
6930
6931s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6932{
6933 struct igb_adapter *adapter = hw->back;
6934
6935 if (pcie_capability_write_word(adapter->pdev, reg, *value))
6936 return -E1000_ERR_CONFIG;
6937
6938 return 0;
6939}
6940
6941static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
6942{
6943 struct igb_adapter *adapter = netdev_priv(netdev);
6944 struct e1000_hw *hw = &adapter->hw;
6945 u32 ctrl, rctl;
6946 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
6947
6948 if (enable) {
6949 /* enable VLAN tag insert/strip */
6950 ctrl = rd32(E1000_CTRL);
6951 ctrl |= E1000_CTRL_VME;
6952 wr32(E1000_CTRL, ctrl);
6953
6954 /* Disable CFI check */
6955 rctl = rd32(E1000_RCTL);
6956 rctl &= ~E1000_RCTL_CFIEN;
6957 wr32(E1000_RCTL, rctl);
6958 } else {
6959 /* disable VLAN tag insert/strip */
6960 ctrl = rd32(E1000_CTRL);
6961 ctrl &= ~E1000_CTRL_VME;
6962 wr32(E1000_CTRL, ctrl);
6963 }
6964
6965 igb_rlpml_set(adapter);
6966}
6967
6968static int igb_vlan_rx_add_vid(struct net_device *netdev,
6969 __be16 proto, u16 vid)
6970{
6971 struct igb_adapter *adapter = netdev_priv(netdev);
6972 struct e1000_hw *hw = &adapter->hw;
6973 int pf_id = adapter->vfs_allocated_count;
6974
6975 /* attempt to add filter to vlvf array */
6976 igb_vlvf_set(adapter, vid, true, pf_id);
6977
6978 /* add the filter since PF can receive vlans w/o entry in vlvf */
6979 igb_vfta_set(hw, vid, true);
6980
6981 set_bit(vid, adapter->active_vlans);
6982
6983 return 0;
6984}
6985
6986static int igb_vlan_rx_kill_vid(struct net_device *netdev,
6987 __be16 proto, u16 vid)
6988{
6989 struct igb_adapter *adapter = netdev_priv(netdev);
6990 struct e1000_hw *hw = &adapter->hw;
6991 int pf_id = adapter->vfs_allocated_count;
6992 s32 err;
6993
6994 /* remove vlan from VLVF table array */
6995 err = igb_vlvf_set(adapter, vid, false, pf_id);
6996
6997 /* if vid was not present in VLVF just remove it from table */
6998 if (err)
6999 igb_vfta_set(hw, vid, false);
7000
7001 clear_bit(vid, adapter->active_vlans);
7002
7003 return 0;
7004}
7005
7006static void igb_restore_vlan(struct igb_adapter *adapter)
7007{
7008 u16 vid;
7009
7010 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7011
7012 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
7013 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
7014}
7015
7016int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
7017{
7018 struct pci_dev *pdev = adapter->pdev;
7019 struct e1000_mac_info *mac = &adapter->hw.mac;
7020
7021 mac->autoneg = 0;
7022
7023 /* Make sure dplx is at most 1 bit and lsb of speed is not set
7024 * for the switch() below to work
7025 */
7026 if ((spd & 1) || (dplx & ~1))
7027 goto err_inval;
7028
7029 /* Fiber NIC's only allow 1000 gbps Full duplex
7030 * and 100Mbps Full duplex for 100baseFx sfp
7031 */
7032 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7033 switch (spd + dplx) {
7034 case SPEED_10 + DUPLEX_HALF:
7035 case SPEED_10 + DUPLEX_FULL:
7036 case SPEED_100 + DUPLEX_HALF:
7037 goto err_inval;
7038 default:
7039 break;
7040 }
7041 }
7042
7043 switch (spd + dplx) {
7044 case SPEED_10 + DUPLEX_HALF:
7045 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7046 break;
7047 case SPEED_10 + DUPLEX_FULL:
7048 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7049 break;
7050 case SPEED_100 + DUPLEX_HALF:
7051 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7052 break;
7053 case SPEED_100 + DUPLEX_FULL:
7054 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7055 break;
7056 case SPEED_1000 + DUPLEX_FULL:
7057 mac->autoneg = 1;
7058 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7059 break;
7060 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7061 default:
7062 goto err_inval;
7063 }
7064
7065 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7066 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7067
7068 return 0;
7069
7070err_inval:
7071 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7072 return -EINVAL;
7073}
7074
7075static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7076 bool runtime)
7077{
7078 struct net_device *netdev = pci_get_drvdata(pdev);
7079 struct igb_adapter *adapter = netdev_priv(netdev);
7080 struct e1000_hw *hw = &adapter->hw;
7081 u32 ctrl, rctl, status;
7082 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
7083#ifdef CONFIG_PM
7084 int retval = 0;
7085#endif
7086
7087 netif_device_detach(netdev);
7088
7089 if (netif_running(netdev))
7090 __igb_close(netdev, true);
7091
7092 igb_clear_interrupt_scheme(adapter);
7093
7094#ifdef CONFIG_PM
7095 retval = pci_save_state(pdev);
7096 if (retval)
7097 return retval;
7098#endif
7099
7100 status = rd32(E1000_STATUS);
7101 if (status & E1000_STATUS_LU)
7102 wufc &= ~E1000_WUFC_LNKC;
7103
7104 if (wufc) {
7105 igb_setup_rctl(adapter);
7106 igb_set_rx_mode(netdev);
7107
7108 /* turn on all-multi mode if wake on multicast is enabled */
7109 if (wufc & E1000_WUFC_MC) {
7110 rctl = rd32(E1000_RCTL);
7111 rctl |= E1000_RCTL_MPE;
7112 wr32(E1000_RCTL, rctl);
7113 }
7114
7115 ctrl = rd32(E1000_CTRL);
7116 /* advertise wake from D3Cold */
7117 #define E1000_CTRL_ADVD3WUC 0x00100000
7118 /* phy power management enable */
7119 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7120 ctrl |= E1000_CTRL_ADVD3WUC;
7121 wr32(E1000_CTRL, ctrl);
7122
7123 /* Allow time for pending master requests to run */
7124 igb_disable_pcie_master(hw);
7125
7126 wr32(E1000_WUC, E1000_WUC_PME_EN);
7127 wr32(E1000_WUFC, wufc);
7128 } else {
7129 wr32(E1000_WUC, 0);
7130 wr32(E1000_WUFC, 0);
7131 }
7132
7133 *enable_wake = wufc || adapter->en_mng_pt;
7134 if (!*enable_wake)
7135 igb_power_down_link(adapter);
7136 else
7137 igb_power_up_link(adapter);
7138
7139 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7140 * would have already happened in close and is redundant.
7141 */
7142 igb_release_hw_control(adapter);
7143
7144 pci_disable_device(pdev);
7145
7146 return 0;
7147}
7148
7149#ifdef CONFIG_PM
7150#ifdef CONFIG_PM_SLEEP
7151static int igb_suspend(struct device *dev)
7152{
7153 int retval;
7154 bool wake;
7155 struct pci_dev *pdev = to_pci_dev(dev);
7156
7157 retval = __igb_shutdown(pdev, &wake, 0);
7158 if (retval)
7159 return retval;
7160
7161 if (wake) {
7162 pci_prepare_to_sleep(pdev);
7163 } else {
7164 pci_wake_from_d3(pdev, false);
7165 pci_set_power_state(pdev, PCI_D3hot);
7166 }
7167
7168 return 0;
7169}
7170#endif /* CONFIG_PM_SLEEP */
7171
7172static int igb_resume(struct device *dev)
7173{
7174 struct pci_dev *pdev = to_pci_dev(dev);
7175 struct net_device *netdev = pci_get_drvdata(pdev);
7176 struct igb_adapter *adapter = netdev_priv(netdev);
7177 struct e1000_hw *hw = &adapter->hw;
7178 u32 err;
7179
7180 pci_set_power_state(pdev, PCI_D0);
7181 pci_restore_state(pdev);
7182 pci_save_state(pdev);
7183
7184 err = pci_enable_device_mem(pdev);
7185 if (err) {
7186 dev_err(&pdev->dev,
7187 "igb: Cannot enable PCI device from suspend\n");
7188 return err;
7189 }
7190 pci_set_master(pdev);
7191
7192 pci_enable_wake(pdev, PCI_D3hot, 0);
7193 pci_enable_wake(pdev, PCI_D3cold, 0);
7194
7195 if (igb_init_interrupt_scheme(adapter, true)) {
7196 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7197 return -ENOMEM;
7198 }
7199
7200 igb_reset(adapter);
7201
7202 /* let the f/w know that the h/w is now under the control of the
7203 * driver.
7204 */
7205 igb_get_hw_control(adapter);
7206
7207 wr32(E1000_WUS, ~0);
7208
7209 if (netdev->flags & IFF_UP) {
7210 rtnl_lock();
7211 err = __igb_open(netdev, true);
7212 rtnl_unlock();
7213 if (err)
7214 return err;
7215 }
7216
7217 netif_device_attach(netdev);
7218 return 0;
7219}
7220
7221#ifdef CONFIG_PM_RUNTIME
7222static int igb_runtime_idle(struct device *dev)
7223{
7224 struct pci_dev *pdev = to_pci_dev(dev);
7225 struct net_device *netdev = pci_get_drvdata(pdev);
7226 struct igb_adapter *adapter = netdev_priv(netdev);
7227
7228 if (!igb_has_link(adapter))
7229 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7230
7231 return -EBUSY;
7232}
7233
7234static int igb_runtime_suspend(struct device *dev)
7235{
7236 struct pci_dev *pdev = to_pci_dev(dev);
7237 int retval;
7238 bool wake;
7239
7240 retval = __igb_shutdown(pdev, &wake, 1);
7241 if (retval)
7242 return retval;
7243
7244 if (wake) {
7245 pci_prepare_to_sleep(pdev);
7246 } else {
7247 pci_wake_from_d3(pdev, false);
7248 pci_set_power_state(pdev, PCI_D3hot);
7249 }
7250
7251 return 0;
7252}
7253
7254static int igb_runtime_resume(struct device *dev)
7255{
7256 return igb_resume(dev);
7257}
7258#endif /* CONFIG_PM_RUNTIME */
7259#endif
7260
7261static void igb_shutdown(struct pci_dev *pdev)
7262{
7263 bool wake;
7264
7265 __igb_shutdown(pdev, &wake, 0);
7266
7267 if (system_state == SYSTEM_POWER_OFF) {
7268 pci_wake_from_d3(pdev, wake);
7269 pci_set_power_state(pdev, PCI_D3hot);
7270 }
7271}
7272
7273#ifdef CONFIG_PCI_IOV
7274static int igb_sriov_reinit(struct pci_dev *dev)
7275{
7276 struct net_device *netdev = pci_get_drvdata(dev);
7277 struct igb_adapter *adapter = netdev_priv(netdev);
7278 struct pci_dev *pdev = adapter->pdev;
7279
7280 rtnl_lock();
7281
7282 if (netif_running(netdev))
7283 igb_close(netdev);
7284
7285 igb_clear_interrupt_scheme(adapter);
7286
7287 igb_init_queue_configuration(adapter);
7288
7289 if (igb_init_interrupt_scheme(adapter, true)) {
7290 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7291 return -ENOMEM;
7292 }
7293
7294 if (netif_running(netdev))
7295 igb_open(netdev);
7296
7297 rtnl_unlock();
7298
7299 return 0;
7300}
7301
7302static int igb_pci_disable_sriov(struct pci_dev *dev)
7303{
7304 int err = igb_disable_sriov(dev);
7305
7306 if (!err)
7307 err = igb_sriov_reinit(dev);
7308
7309 return err;
7310}
7311
7312static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7313{
7314 int err = igb_enable_sriov(dev, num_vfs);
7315
7316 if (err)
7317 goto out;
7318
7319 err = igb_sriov_reinit(dev);
7320 if (!err)
7321 return num_vfs;
7322
7323out:
7324 return err;
7325}
7326
7327#endif
7328static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7329{
7330#ifdef CONFIG_PCI_IOV
7331 if (num_vfs == 0)
7332 return igb_pci_disable_sriov(dev);
7333 else
7334 return igb_pci_enable_sriov(dev, num_vfs);
7335#endif
7336 return 0;
7337}
7338
7339#ifdef CONFIG_NET_POLL_CONTROLLER
7340/* Polling 'interrupt' - used by things like netconsole to send skbs
7341 * without having to re-enable interrupts. It's not called while
7342 * the interrupt routine is executing.
7343 */
7344static void igb_netpoll(struct net_device *netdev)
7345{
7346 struct igb_adapter *adapter = netdev_priv(netdev);
7347 struct e1000_hw *hw = &adapter->hw;
7348 struct igb_q_vector *q_vector;
7349 int i;
7350
7351 for (i = 0; i < adapter->num_q_vectors; i++) {
7352 q_vector = adapter->q_vector[i];
7353 if (adapter->msix_entries)
7354 wr32(E1000_EIMC, q_vector->eims_value);
7355 else
7356 igb_irq_disable(adapter);
7357 napi_schedule(&q_vector->napi);
7358 }
7359}
7360#endif /* CONFIG_NET_POLL_CONTROLLER */
7361
7362/**
7363 * igb_io_error_detected - called when PCI error is detected
7364 * @pdev: Pointer to PCI device
7365 * @state: The current pci connection state
7366 *
7367 * This function is called after a PCI bus error affecting
7368 * this device has been detected.
7369 **/
7370static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7371 pci_channel_state_t state)
7372{
7373 struct net_device *netdev = pci_get_drvdata(pdev);
7374 struct igb_adapter *adapter = netdev_priv(netdev);
7375
7376 netif_device_detach(netdev);
7377
7378 if (state == pci_channel_io_perm_failure)
7379 return PCI_ERS_RESULT_DISCONNECT;
7380
7381 if (netif_running(netdev))
7382 igb_down(adapter);
7383 pci_disable_device(pdev);
7384
7385 /* Request a slot slot reset. */
7386 return PCI_ERS_RESULT_NEED_RESET;
7387}
7388
7389/**
7390 * igb_io_slot_reset - called after the pci bus has been reset.
7391 * @pdev: Pointer to PCI device
7392 *
7393 * Restart the card from scratch, as if from a cold-boot. Implementation
7394 * resembles the first-half of the igb_resume routine.
7395 **/
7396static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7397{
7398 struct net_device *netdev = pci_get_drvdata(pdev);
7399 struct igb_adapter *adapter = netdev_priv(netdev);
7400 struct e1000_hw *hw = &adapter->hw;
7401 pci_ers_result_t result;
7402 int err;
7403
7404 if (pci_enable_device_mem(pdev)) {
7405 dev_err(&pdev->dev,
7406 "Cannot re-enable PCI device after reset.\n");
7407 result = PCI_ERS_RESULT_DISCONNECT;
7408 } else {
7409 pci_set_master(pdev);
7410 pci_restore_state(pdev);
7411 pci_save_state(pdev);
7412
7413 pci_enable_wake(pdev, PCI_D3hot, 0);
7414 pci_enable_wake(pdev, PCI_D3cold, 0);
7415
7416 igb_reset(adapter);
7417 wr32(E1000_WUS, ~0);
7418 result = PCI_ERS_RESULT_RECOVERED;
7419 }
7420
7421 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7422 if (err) {
7423 dev_err(&pdev->dev,
7424 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7425 err);
7426 /* non-fatal, continue */
7427 }
7428
7429 return result;
7430}
7431
7432/**
7433 * igb_io_resume - called when traffic can start flowing again.
7434 * @pdev: Pointer to PCI device
7435 *
7436 * This callback is called when the error recovery driver tells us that
7437 * its OK to resume normal operation. Implementation resembles the
7438 * second-half of the igb_resume routine.
7439 */
7440static void igb_io_resume(struct pci_dev *pdev)
7441{
7442 struct net_device *netdev = pci_get_drvdata(pdev);
7443 struct igb_adapter *adapter = netdev_priv(netdev);
7444
7445 if (netif_running(netdev)) {
7446 if (igb_up(adapter)) {
7447 dev_err(&pdev->dev, "igb_up failed after reset\n");
7448 return;
7449 }
7450 }
7451
7452 netif_device_attach(netdev);
7453
7454 /* let the f/w know that the h/w is now under the control of the
7455 * driver.
7456 */
7457 igb_get_hw_control(adapter);
7458}
7459
7460static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7461 u8 qsel)
7462{
7463 u32 rar_low, rar_high;
7464 struct e1000_hw *hw = &adapter->hw;
7465
7466 /* HW expects these in little endian so we reverse the byte order
7467 * from network order (big endian) to little endian
7468 */
7469 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7470 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7471 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7472
7473 /* Indicate to hardware the Address is Valid. */
7474 rar_high |= E1000_RAH_AV;
7475
7476 if (hw->mac.type == e1000_82575)
7477 rar_high |= E1000_RAH_POOL_1 * qsel;
7478 else
7479 rar_high |= E1000_RAH_POOL_1 << qsel;
7480
7481 wr32(E1000_RAL(index), rar_low);
7482 wrfl();
7483 wr32(E1000_RAH(index), rar_high);
7484 wrfl();
7485}
7486
7487static int igb_set_vf_mac(struct igb_adapter *adapter,
7488 int vf, unsigned char *mac_addr)
7489{
7490 struct e1000_hw *hw = &adapter->hw;
7491 /* VF MAC addresses start at end of receive addresses and moves
7492 * towards the first, as a result a collision should not be possible
7493 */
7494 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7495
7496 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7497
7498 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7499
7500 return 0;
7501}
7502
7503static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7504{
7505 struct igb_adapter *adapter = netdev_priv(netdev);
7506 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7507 return -EINVAL;
7508 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7509 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7510 dev_info(&adapter->pdev->dev,
7511 "Reload the VF driver to make this change effective.");
7512 if (test_bit(__IGB_DOWN, &adapter->state)) {
7513 dev_warn(&adapter->pdev->dev,
7514 "The VF MAC address has been set, but the PF device is not up.\n");
7515 dev_warn(&adapter->pdev->dev,
7516 "Bring the PF device up before attempting to use the VF device.\n");
7517 }
7518 return igb_set_vf_mac(adapter, vf, mac);
7519}
7520
7521static int igb_link_mbps(int internal_link_speed)
7522{
7523 switch (internal_link_speed) {
7524 case SPEED_100:
7525 return 100;
7526 case SPEED_1000:
7527 return 1000;
7528 default:
7529 return 0;
7530 }
7531}
7532
7533static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7534 int link_speed)
7535{
7536 int rf_dec, rf_int;
7537 u32 bcnrc_val;
7538
7539 if (tx_rate != 0) {
7540 /* Calculate the rate factor values to set */
7541 rf_int = link_speed / tx_rate;
7542 rf_dec = (link_speed - (rf_int * tx_rate));
7543 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7544 tx_rate;
7545
7546 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7547 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7548 E1000_RTTBCNRC_RF_INT_MASK);
7549 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7550 } else {
7551 bcnrc_val = 0;
7552 }
7553
7554 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7555 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7556 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7557 */
7558 wr32(E1000_RTTBCNRM, 0x14);
7559 wr32(E1000_RTTBCNRC, bcnrc_val);
7560}
7561
7562static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7563{
7564 int actual_link_speed, i;
7565 bool reset_rate = false;
7566
7567 /* VF TX rate limit was not set or not supported */
7568 if ((adapter->vf_rate_link_speed == 0) ||
7569 (adapter->hw.mac.type != e1000_82576))
7570 return;
7571
7572 actual_link_speed = igb_link_mbps(adapter->link_speed);
7573 if (actual_link_speed != adapter->vf_rate_link_speed) {
7574 reset_rate = true;
7575 adapter->vf_rate_link_speed = 0;
7576 dev_info(&adapter->pdev->dev,
7577 "Link speed has been changed. VF Transmit rate is disabled\n");
7578 }
7579
7580 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7581 if (reset_rate)
7582 adapter->vf_data[i].tx_rate = 0;
7583
7584 igb_set_vf_rate_limit(&adapter->hw, i,
7585 adapter->vf_data[i].tx_rate,
7586 actual_link_speed);
7587 }
7588}
7589
7590static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7591{
7592 struct igb_adapter *adapter = netdev_priv(netdev);
7593 struct e1000_hw *hw = &adapter->hw;
7594 int actual_link_speed;
7595
7596 if (hw->mac.type != e1000_82576)
7597 return -EOPNOTSUPP;
7598
7599 actual_link_speed = igb_link_mbps(adapter->link_speed);
7600 if ((vf >= adapter->vfs_allocated_count) ||
7601 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7602 (tx_rate < 0) || (tx_rate > actual_link_speed))
7603 return -EINVAL;
7604
7605 adapter->vf_rate_link_speed = actual_link_speed;
7606 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7607 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7608
7609 return 0;
7610}
7611
7612static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7613 bool setting)
7614{
7615 struct igb_adapter *adapter = netdev_priv(netdev);
7616 struct e1000_hw *hw = &adapter->hw;
7617 u32 reg_val, reg_offset;
7618
7619 if (!adapter->vfs_allocated_count)
7620 return -EOPNOTSUPP;
7621
7622 if (vf >= adapter->vfs_allocated_count)
7623 return -EINVAL;
7624
7625 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7626 reg_val = rd32(reg_offset);
7627 if (setting)
7628 reg_val |= ((1 << vf) |
7629 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7630 else
7631 reg_val &= ~((1 << vf) |
7632 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7633 wr32(reg_offset, reg_val);
7634
7635 adapter->vf_data[vf].spoofchk_enabled = setting;
7636 return E1000_SUCCESS;
7637}
7638
7639static int igb_ndo_get_vf_config(struct net_device *netdev,
7640 int vf, struct ifla_vf_info *ivi)
7641{
7642 struct igb_adapter *adapter = netdev_priv(netdev);
7643 if (vf >= adapter->vfs_allocated_count)
7644 return -EINVAL;
7645 ivi->vf = vf;
7646 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7647 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
7648 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7649 ivi->qos = adapter->vf_data[vf].pf_qos;
7650 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
7651 return 0;
7652}
7653
7654static void igb_vmm_control(struct igb_adapter *adapter)
7655{
7656 struct e1000_hw *hw = &adapter->hw;
7657 u32 reg;
7658
7659 switch (hw->mac.type) {
7660 case e1000_82575:
7661 case e1000_i210:
7662 case e1000_i211:
7663 case e1000_i354:
7664 default:
7665 /* replication is not supported for 82575 */
7666 return;
7667 case e1000_82576:
7668 /* notify HW that the MAC is adding vlan tags */
7669 reg = rd32(E1000_DTXCTL);
7670 reg |= E1000_DTXCTL_VLAN_ADDED;
7671 wr32(E1000_DTXCTL, reg);
7672 case e1000_82580:
7673 /* enable replication vlan tag stripping */
7674 reg = rd32(E1000_RPLOLR);
7675 reg |= E1000_RPLOLR_STRVLAN;
7676 wr32(E1000_RPLOLR, reg);
7677 case e1000_i350:
7678 /* none of the above registers are supported by i350 */
7679 break;
7680 }
7681
7682 if (adapter->vfs_allocated_count) {
7683 igb_vmdq_set_loopback_pf(hw, true);
7684 igb_vmdq_set_replication_pf(hw, true);
7685 igb_vmdq_set_anti_spoofing_pf(hw, true,
7686 adapter->vfs_allocated_count);
7687 } else {
7688 igb_vmdq_set_loopback_pf(hw, false);
7689 igb_vmdq_set_replication_pf(hw, false);
7690 }
7691}
7692
7693static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7694{
7695 struct e1000_hw *hw = &adapter->hw;
7696 u32 dmac_thr;
7697 u16 hwm;
7698
7699 if (hw->mac.type > e1000_82580) {
7700 if (adapter->flags & IGB_FLAG_DMAC) {
7701 u32 reg;
7702
7703 /* force threshold to 0. */
7704 wr32(E1000_DMCTXTH, 0);
7705
7706 /* DMA Coalescing high water mark needs to be greater
7707 * than the Rx threshold. Set hwm to PBA - max frame
7708 * size in 16B units, capping it at PBA - 6KB.
7709 */
7710 hwm = 64 * pba - adapter->max_frame_size / 16;
7711 if (hwm < 64 * (pba - 6))
7712 hwm = 64 * (pba - 6);
7713 reg = rd32(E1000_FCRTC);
7714 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7715 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7716 & E1000_FCRTC_RTH_COAL_MASK);
7717 wr32(E1000_FCRTC, reg);
7718
7719 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
7720 * frame size, capping it at PBA - 10KB.
7721 */
7722 dmac_thr = pba - adapter->max_frame_size / 512;
7723 if (dmac_thr < pba - 10)
7724 dmac_thr = pba - 10;
7725 reg = rd32(E1000_DMACR);
7726 reg &= ~E1000_DMACR_DMACTHR_MASK;
7727 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7728 & E1000_DMACR_DMACTHR_MASK);
7729
7730 /* transition to L0x or L1 if available..*/
7731 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7732
7733 /* watchdog timer= +-1000 usec in 32usec intervals */
7734 reg |= (1000 >> 5);
7735
7736 /* Disable BMC-to-OS Watchdog Enable */
7737 if (hw->mac.type != e1000_i354)
7738 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7739
7740 wr32(E1000_DMACR, reg);
7741
7742 /* no lower threshold to disable
7743 * coalescing(smart fifb)-UTRESH=0
7744 */
7745 wr32(E1000_DMCRTRH, 0);
7746
7747 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7748
7749 wr32(E1000_DMCTLX, reg);
7750
7751 /* free space in tx packet buffer to wake from
7752 * DMA coal
7753 */
7754 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7755 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7756
7757 /* make low power state decision controlled
7758 * by DMA coal
7759 */
7760 reg = rd32(E1000_PCIEMISC);
7761 reg &= ~E1000_PCIEMISC_LX_DECISION;
7762 wr32(E1000_PCIEMISC, reg);
7763 } /* endif adapter->dmac is not disabled */
7764 } else if (hw->mac.type == e1000_82580) {
7765 u32 reg = rd32(E1000_PCIEMISC);
7766 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7767 wr32(E1000_DMACR, 0);
7768 }
7769}
7770
7771/**
7772 * igb_read_i2c_byte - Reads 8 bit word over I2C
7773 * @hw: pointer to hardware structure
7774 * @byte_offset: byte offset to read
7775 * @dev_addr: device address
7776 * @data: value read
7777 *
7778 * Performs byte read operation over I2C interface at
7779 * a specified device address.
7780 **/
7781s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7782 u8 dev_addr, u8 *data)
7783{
7784 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7785 struct i2c_client *this_client = adapter->i2c_client;
7786 s32 status;
7787 u16 swfw_mask = 0;
7788
7789 if (!this_client)
7790 return E1000_ERR_I2C;
7791
7792 swfw_mask = E1000_SWFW_PHY0_SM;
7793
7794 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
7795 != E1000_SUCCESS)
7796 return E1000_ERR_SWFW_SYNC;
7797
7798 status = i2c_smbus_read_byte_data(this_client, byte_offset);
7799 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7800
7801 if (status < 0)
7802 return E1000_ERR_I2C;
7803 else {
7804 *data = status;
7805 return E1000_SUCCESS;
7806 }
7807}
7808
7809/**
7810 * igb_write_i2c_byte - Writes 8 bit word over I2C
7811 * @hw: pointer to hardware structure
7812 * @byte_offset: byte offset to write
7813 * @dev_addr: device address
7814 * @data: value to write
7815 *
7816 * Performs byte write operation over I2C interface at
7817 * a specified device address.
7818 **/
7819s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7820 u8 dev_addr, u8 data)
7821{
7822 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7823 struct i2c_client *this_client = adapter->i2c_client;
7824 s32 status;
7825 u16 swfw_mask = E1000_SWFW_PHY0_SM;
7826
7827 if (!this_client)
7828 return E1000_ERR_I2C;
7829
7830 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
7831 return E1000_ERR_SWFW_SYNC;
7832 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7833 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7834
7835 if (status)
7836 return E1000_ERR_I2C;
7837 else
7838 return E1000_SUCCESS;
7839
7840}
7841/* igb_main.c */
Linux kernel - Deliverables
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