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igb: Merge VLVF configuration into igb_vfta_set
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
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CommitLineData
1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
23
24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/init.h>
29#include <linux/bitops.h>
30#include <linux/vmalloc.h>
31#include <linux/pagemap.h>
32#include <linux/netdevice.h>
33#include <linux/ipv6.h>
34#include <linux/slab.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/net_tstamp.h>
38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if.h>
41#include <linux/if_vlan.h>
42#include <linux/pci.h>
43#include <linux/pci-aspm.h>
44#include <linux/delay.h>
45#include <linux/interrupt.h>
46#include <linux/ip.h>
47#include <linux/tcp.h>
48#include <linux/sctp.h>
49#include <linux/if_ether.h>
50#include <linux/aer.h>
51#include <linux/prefetch.h>
52#include <linux/pm_runtime.h>
53#ifdef CONFIG_IGB_DCA
54#include <linux/dca.h>
55#endif
56#include <linux/i2c.h>
57#include "igb.h"
58
59#define MAJ 5
60#define MIN 3
61#define BUILD 0
62#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
63__stringify(BUILD) "-k"
64char igb_driver_name[] = "igb";
65char igb_driver_version[] = DRV_VERSION;
66static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
68static const char igb_copyright[] =
69 "Copyright (c) 2007-2014 Intel Corporation.";
70
71static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73};
74
75static const struct pci_device_id igb_pci_tbl[] = {
76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113};
114
115MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
117static int igb_setup_all_tx_resources(struct igb_adapter *);
118static int igb_setup_all_rx_resources(struct igb_adapter *);
119static void igb_free_all_tx_resources(struct igb_adapter *);
120static void igb_free_all_rx_resources(struct igb_adapter *);
121static void igb_setup_mrqc(struct igb_adapter *);
122static int igb_probe(struct pci_dev *, const struct pci_device_id *);
123static void igb_remove(struct pci_dev *pdev);
124static int igb_sw_init(struct igb_adapter *);
125static int igb_open(struct net_device *);
126static int igb_close(struct net_device *);
127static void igb_configure(struct igb_adapter *);
128static void igb_configure_tx(struct igb_adapter *);
129static void igb_configure_rx(struct igb_adapter *);
130static void igb_clean_all_tx_rings(struct igb_adapter *);
131static void igb_clean_all_rx_rings(struct igb_adapter *);
132static void igb_clean_tx_ring(struct igb_ring *);
133static void igb_clean_rx_ring(struct igb_ring *);
134static void igb_set_rx_mode(struct net_device *);
135static void igb_update_phy_info(unsigned long);
136static void igb_watchdog(unsigned long);
137static void igb_watchdog_task(struct work_struct *);
138static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
139static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
140 struct rtnl_link_stats64 *stats);
141static int igb_change_mtu(struct net_device *, int);
142static int igb_set_mac(struct net_device *, void *);
143static void igb_set_uta(struct igb_adapter *adapter);
144static irqreturn_t igb_intr(int irq, void *);
145static irqreturn_t igb_intr_msi(int irq, void *);
146static irqreturn_t igb_msix_other(int irq, void *);
147static irqreturn_t igb_msix_ring(int irq, void *);
148#ifdef CONFIG_IGB_DCA
149static void igb_update_dca(struct igb_q_vector *);
150static void igb_setup_dca(struct igb_adapter *);
151#endif /* CONFIG_IGB_DCA */
152static int igb_poll(struct napi_struct *, int);
153static bool igb_clean_tx_irq(struct igb_q_vector *);
154static int igb_clean_rx_irq(struct igb_q_vector *, int);
155static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156static void igb_tx_timeout(struct net_device *);
157static void igb_reset_task(struct work_struct *);
158static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
160static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
162static void igb_restore_vlan(struct igb_adapter *);
163static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
164static void igb_ping_all_vfs(struct igb_adapter *);
165static void igb_msg_task(struct igb_adapter *);
166static void igb_vmm_control(struct igb_adapter *);
167static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
168static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
169static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
172static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
173static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 bool setting);
175static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
177static void igb_check_vf_rate_limit(struct igb_adapter *);
178
179#ifdef CONFIG_PCI_IOV
180static int igb_vf_configure(struct igb_adapter *adapter, int vf);
181static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
182static int igb_disable_sriov(struct pci_dev *dev);
183static int igb_pci_disable_sriov(struct pci_dev *dev);
184#endif
185
186#ifdef CONFIG_PM
187#ifdef CONFIG_PM_SLEEP
188static int igb_suspend(struct device *);
189#endif
190static int igb_resume(struct device *);
191static int igb_runtime_suspend(struct device *dev);
192static int igb_runtime_resume(struct device *dev);
193static int igb_runtime_idle(struct device *dev);
194static const struct dev_pm_ops igb_pm_ops = {
195 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
196 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
197 igb_runtime_idle)
198};
199#endif
200static void igb_shutdown(struct pci_dev *);
201static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
202#ifdef CONFIG_IGB_DCA
203static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
204static struct notifier_block dca_notifier = {
205 .notifier_call = igb_notify_dca,
206 .next = NULL,
207 .priority = 0
208};
209#endif
210#ifdef CONFIG_NET_POLL_CONTROLLER
211/* for netdump / net console */
212static void igb_netpoll(struct net_device *);
213#endif
214#ifdef CONFIG_PCI_IOV
215static unsigned int max_vfs;
216module_param(max_vfs, uint, 0);
217MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
218#endif /* CONFIG_PCI_IOV */
219
220static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
221 pci_channel_state_t);
222static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
223static void igb_io_resume(struct pci_dev *);
224
225static const struct pci_error_handlers igb_err_handler = {
226 .error_detected = igb_io_error_detected,
227 .slot_reset = igb_io_slot_reset,
228 .resume = igb_io_resume,
229};
230
231static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
232
233static struct pci_driver igb_driver = {
234 .name = igb_driver_name,
235 .id_table = igb_pci_tbl,
236 .probe = igb_probe,
237 .remove = igb_remove,
238#ifdef CONFIG_PM
239 .driver.pm = &igb_pm_ops,
240#endif
241 .shutdown = igb_shutdown,
242 .sriov_configure = igb_pci_sriov_configure,
243 .err_handler = &igb_err_handler
244};
245
246MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
247MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
248MODULE_LICENSE("GPL");
249MODULE_VERSION(DRV_VERSION);
250
251#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
252static int debug = -1;
253module_param(debug, int, 0);
254MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
255
256struct igb_reg_info {
257 u32 ofs;
258 char *name;
259};
260
261static const struct igb_reg_info igb_reg_info_tbl[] = {
262
263 /* General Registers */
264 {E1000_CTRL, "CTRL"},
265 {E1000_STATUS, "STATUS"},
266 {E1000_CTRL_EXT, "CTRL_EXT"},
267
268 /* Interrupt Registers */
269 {E1000_ICR, "ICR"},
270
271 /* RX Registers */
272 {E1000_RCTL, "RCTL"},
273 {E1000_RDLEN(0), "RDLEN"},
274 {E1000_RDH(0), "RDH"},
275 {E1000_RDT(0), "RDT"},
276 {E1000_RXDCTL(0), "RXDCTL"},
277 {E1000_RDBAL(0), "RDBAL"},
278 {E1000_RDBAH(0), "RDBAH"},
279
280 /* TX Registers */
281 {E1000_TCTL, "TCTL"},
282 {E1000_TDBAL(0), "TDBAL"},
283 {E1000_TDBAH(0), "TDBAH"},
284 {E1000_TDLEN(0), "TDLEN"},
285 {E1000_TDH(0), "TDH"},
286 {E1000_TDT(0), "TDT"},
287 {E1000_TXDCTL(0), "TXDCTL"},
288 {E1000_TDFH, "TDFH"},
289 {E1000_TDFT, "TDFT"},
290 {E1000_TDFHS, "TDFHS"},
291 {E1000_TDFPC, "TDFPC"},
292
293 /* List Terminator */
294 {}
295};
296
297/* igb_regdump - register printout routine */
298static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
299{
300 int n = 0;
301 char rname[16];
302 u32 regs[8];
303
304 switch (reginfo->ofs) {
305 case E1000_RDLEN(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDLEN(n));
308 break;
309 case E1000_RDH(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDH(n));
312 break;
313 case E1000_RDT(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDT(n));
316 break;
317 case E1000_RXDCTL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RXDCTL(n));
320 break;
321 case E1000_RDBAL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAL(n));
324 break;
325 case E1000_RDBAH(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAH(n));
328 break;
329 case E1000_TDBAL(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAL(n));
332 break;
333 case E1000_TDBAH(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDBAH(n));
336 break;
337 case E1000_TDLEN(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDLEN(n));
340 break;
341 case E1000_TDH(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDH(n));
344 break;
345 case E1000_TDT(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDT(n));
348 break;
349 case E1000_TXDCTL(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TXDCTL(n));
352 break;
353 default:
354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
355 return;
356 }
357
358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
360 regs[2], regs[3]);
361}
362
363/* igb_dump - Print registers, Tx-rings and Rx-rings */
364static void igb_dump(struct igb_adapter *adapter)
365{
366 struct net_device *netdev = adapter->netdev;
367 struct e1000_hw *hw = &adapter->hw;
368 struct igb_reg_info *reginfo;
369 struct igb_ring *tx_ring;
370 union e1000_adv_tx_desc *tx_desc;
371 struct my_u0 { u64 a; u64 b; } *u0;
372 struct igb_ring *rx_ring;
373 union e1000_adv_rx_desc *rx_desc;
374 u32 staterr;
375 u16 i, n;
376
377 if (!netif_msg_hw(adapter))
378 return;
379
380 /* Print netdevice Info */
381 if (netdev) {
382 dev_info(&adapter->pdev->dev, "Net device Info\n");
383 pr_info("Device Name state trans_start last_rx\n");
384 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
385 netdev->state, netdev->trans_start, netdev->last_rx);
386 }
387
388 /* Print Registers */
389 dev_info(&adapter->pdev->dev, "Register Dump\n");
390 pr_info(" Register Name Value\n");
391 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
392 reginfo->name; reginfo++) {
393 igb_regdump(hw, reginfo);
394 }
395
396 /* Print TX Ring Summary */
397 if (!netdev || !netif_running(netdev))
398 goto exit;
399
400 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
401 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
402 for (n = 0; n < adapter->num_tx_queues; n++) {
403 struct igb_tx_buffer *buffer_info;
404 tx_ring = adapter->tx_ring[n];
405 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
406 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
407 n, tx_ring->next_to_use, tx_ring->next_to_clean,
408 (u64)dma_unmap_addr(buffer_info, dma),
409 dma_unmap_len(buffer_info, len),
410 buffer_info->next_to_watch,
411 (u64)buffer_info->time_stamp);
412 }
413
414 /* Print TX Rings */
415 if (!netif_msg_tx_done(adapter))
416 goto rx_ring_summary;
417
418 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
419
420 /* Transmit Descriptor Formats
421 *
422 * Advanced Transmit Descriptor
423 * +--------------------------------------------------------------+
424 * 0 | Buffer Address [63:0] |
425 * +--------------------------------------------------------------+
426 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
427 * +--------------------------------------------------------------+
428 * 63 46 45 40 39 38 36 35 32 31 24 15 0
429 */
430
431 for (n = 0; n < adapter->num_tx_queues; n++) {
432 tx_ring = adapter->tx_ring[n];
433 pr_info("------------------------------------\n");
434 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
435 pr_info("------------------------------------\n");
436 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
437
438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
439 const char *next_desc;
440 struct igb_tx_buffer *buffer_info;
441 tx_desc = IGB_TX_DESC(tx_ring, i);
442 buffer_info = &tx_ring->tx_buffer_info[i];
443 u0 = (struct my_u0 *)tx_desc;
444 if (i == tx_ring->next_to_use &&
445 i == tx_ring->next_to_clean)
446 next_desc = " NTC/U";
447 else if (i == tx_ring->next_to_use)
448 next_desc = " NTU";
449 else if (i == tx_ring->next_to_clean)
450 next_desc = " NTC";
451 else
452 next_desc = "";
453
454 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
455 i, le64_to_cpu(u0->a),
456 le64_to_cpu(u0->b),
457 (u64)dma_unmap_addr(buffer_info, dma),
458 dma_unmap_len(buffer_info, len),
459 buffer_info->next_to_watch,
460 (u64)buffer_info->time_stamp,
461 buffer_info->skb, next_desc);
462
463 if (netif_msg_pktdata(adapter) && buffer_info->skb)
464 print_hex_dump(KERN_INFO, "",
465 DUMP_PREFIX_ADDRESS,
466 16, 1, buffer_info->skb->data,
467 dma_unmap_len(buffer_info, len),
468 true);
469 }
470 }
471
472 /* Print RX Rings Summary */
473rx_ring_summary:
474 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
475 pr_info("Queue [NTU] [NTC]\n");
476 for (n = 0; n < adapter->num_rx_queues; n++) {
477 rx_ring = adapter->rx_ring[n];
478 pr_info(" %5d %5X %5X\n",
479 n, rx_ring->next_to_use, rx_ring->next_to_clean);
480 }
481
482 /* Print RX Rings */
483 if (!netif_msg_rx_status(adapter))
484 goto exit;
485
486 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
487
488 /* Advanced Receive Descriptor (Read) Format
489 * 63 1 0
490 * +-----------------------------------------------------+
491 * 0 | Packet Buffer Address [63:1] |A0/NSE|
492 * +----------------------------------------------+------+
493 * 8 | Header Buffer Address [63:1] | DD |
494 * +-----------------------------------------------------+
495 *
496 *
497 * Advanced Receive Descriptor (Write-Back) Format
498 *
499 * 63 48 47 32 31 30 21 20 17 16 4 3 0
500 * +------------------------------------------------------+
501 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
502 * | Checksum Ident | | | | Type | Type |
503 * +------------------------------------------------------+
504 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
505 * +------------------------------------------------------+
506 * 63 48 47 32 31 20 19 0
507 */
508
509 for (n = 0; n < adapter->num_rx_queues; n++) {
510 rx_ring = adapter->rx_ring[n];
511 pr_info("------------------------------------\n");
512 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
513 pr_info("------------------------------------\n");
514 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
515 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
516
517 for (i = 0; i < rx_ring->count; i++) {
518 const char *next_desc;
519 struct igb_rx_buffer *buffer_info;
520 buffer_info = &rx_ring->rx_buffer_info[i];
521 rx_desc = IGB_RX_DESC(rx_ring, i);
522 u0 = (struct my_u0 *)rx_desc;
523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
524
525 if (i == rx_ring->next_to_use)
526 next_desc = " NTU";
527 else if (i == rx_ring->next_to_clean)
528 next_desc = " NTC";
529 else
530 next_desc = "";
531
532 if (staterr & E1000_RXD_STAT_DD) {
533 /* Descriptor Done */
534 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
535 "RWB", i,
536 le64_to_cpu(u0->a),
537 le64_to_cpu(u0->b),
538 next_desc);
539 } else {
540 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
541 "R ", i,
542 le64_to_cpu(u0->a),
543 le64_to_cpu(u0->b),
544 (u64)buffer_info->dma,
545 next_desc);
546
547 if (netif_msg_pktdata(adapter) &&
548 buffer_info->dma && buffer_info->page) {
549 print_hex_dump(KERN_INFO, "",
550 DUMP_PREFIX_ADDRESS,
551 16, 1,
552 page_address(buffer_info->page) +
553 buffer_info->page_offset,
554 IGB_RX_BUFSZ, true);
555 }
556 }
557 }
558 }
559
560exit:
561 return;
562}
563
564/**
565 * igb_get_i2c_data - Reads the I2C SDA data bit
566 * @hw: pointer to hardware structure
567 * @i2cctl: Current value of I2CCTL register
568 *
569 * Returns the I2C data bit value
570 **/
571static int igb_get_i2c_data(void *data)
572{
573 struct igb_adapter *adapter = (struct igb_adapter *)data;
574 struct e1000_hw *hw = &adapter->hw;
575 s32 i2cctl = rd32(E1000_I2CPARAMS);
576
577 return !!(i2cctl & E1000_I2C_DATA_IN);
578}
579
580/**
581 * igb_set_i2c_data - Sets the I2C data bit
582 * @data: pointer to hardware structure
583 * @state: I2C data value (0 or 1) to set
584 *
585 * Sets the I2C data bit
586 **/
587static void igb_set_i2c_data(void *data, int state)
588{
589 struct igb_adapter *adapter = (struct igb_adapter *)data;
590 struct e1000_hw *hw = &adapter->hw;
591 s32 i2cctl = rd32(E1000_I2CPARAMS);
592
593 if (state)
594 i2cctl |= E1000_I2C_DATA_OUT;
595 else
596 i2cctl &= ~E1000_I2C_DATA_OUT;
597
598 i2cctl &= ~E1000_I2C_DATA_OE_N;
599 i2cctl |= E1000_I2C_CLK_OE_N;
600 wr32(E1000_I2CPARAMS, i2cctl);
601 wrfl();
602
603}
604
605/**
606 * igb_set_i2c_clk - Sets the I2C SCL clock
607 * @data: pointer to hardware structure
608 * @state: state to set clock
609 *
610 * Sets the I2C clock line to state
611 **/
612static void igb_set_i2c_clk(void *data, int state)
613{
614 struct igb_adapter *adapter = (struct igb_adapter *)data;
615 struct e1000_hw *hw = &adapter->hw;
616 s32 i2cctl = rd32(E1000_I2CPARAMS);
617
618 if (state) {
619 i2cctl |= E1000_I2C_CLK_OUT;
620 i2cctl &= ~E1000_I2C_CLK_OE_N;
621 } else {
622 i2cctl &= ~E1000_I2C_CLK_OUT;
623 i2cctl &= ~E1000_I2C_CLK_OE_N;
624 }
625 wr32(E1000_I2CPARAMS, i2cctl);
626 wrfl();
627}
628
629/**
630 * igb_get_i2c_clk - Gets the I2C SCL clock state
631 * @data: pointer to hardware structure
632 *
633 * Gets the I2C clock state
634 **/
635static int igb_get_i2c_clk(void *data)
636{
637 struct igb_adapter *adapter = (struct igb_adapter *)data;
638 struct e1000_hw *hw = &adapter->hw;
639 s32 i2cctl = rd32(E1000_I2CPARAMS);
640
641 return !!(i2cctl & E1000_I2C_CLK_IN);
642}
643
644static const struct i2c_algo_bit_data igb_i2c_algo = {
645 .setsda = igb_set_i2c_data,
646 .setscl = igb_set_i2c_clk,
647 .getsda = igb_get_i2c_data,
648 .getscl = igb_get_i2c_clk,
649 .udelay = 5,
650 .timeout = 20,
651};
652
653/**
654 * igb_get_hw_dev - return device
655 * @hw: pointer to hardware structure
656 *
657 * used by hardware layer to print debugging information
658 **/
659struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
660{
661 struct igb_adapter *adapter = hw->back;
662 return adapter->netdev;
663}
664
665/**
666 * igb_init_module - Driver Registration Routine
667 *
668 * igb_init_module is the first routine called when the driver is
669 * loaded. All it does is register with the PCI subsystem.
670 **/
671static int __init igb_init_module(void)
672{
673 int ret;
674
675 pr_info("%s - version %s\n",
676 igb_driver_string, igb_driver_version);
677 pr_info("%s\n", igb_copyright);
678
679#ifdef CONFIG_IGB_DCA
680 dca_register_notify(&dca_notifier);
681#endif
682 ret = pci_register_driver(&igb_driver);
683 return ret;
684}
685
686module_init(igb_init_module);
687
688/**
689 * igb_exit_module - Driver Exit Cleanup Routine
690 *
691 * igb_exit_module is called just before the driver is removed
692 * from memory.
693 **/
694static void __exit igb_exit_module(void)
695{
696#ifdef CONFIG_IGB_DCA
697 dca_unregister_notify(&dca_notifier);
698#endif
699 pci_unregister_driver(&igb_driver);
700}
701
702module_exit(igb_exit_module);
703
704#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
705/**
706 * igb_cache_ring_register - Descriptor ring to register mapping
707 * @adapter: board private structure to initialize
708 *
709 * Once we know the feature-set enabled for the device, we'll cache
710 * the register offset the descriptor ring is assigned to.
711 **/
712static void igb_cache_ring_register(struct igb_adapter *adapter)
713{
714 int i = 0, j = 0;
715 u32 rbase_offset = adapter->vfs_allocated_count;
716
717 switch (adapter->hw.mac.type) {
718 case e1000_82576:
719 /* The queues are allocated for virtualization such that VF 0
720 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
721 * In order to avoid collision we start at the first free queue
722 * and continue consuming queues in the same sequence
723 */
724 if (adapter->vfs_allocated_count) {
725 for (; i < adapter->rss_queues; i++)
726 adapter->rx_ring[i]->reg_idx = rbase_offset +
727 Q_IDX_82576(i);
728 }
729 /* Fall through */
730 case e1000_82575:
731 case e1000_82580:
732 case e1000_i350:
733 case e1000_i354:
734 case e1000_i210:
735 case e1000_i211:
736 /* Fall through */
737 default:
738 for (; i < adapter->num_rx_queues; i++)
739 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
740 for (; j < adapter->num_tx_queues; j++)
741 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
742 break;
743 }
744}
745
746u32 igb_rd32(struct e1000_hw *hw, u32 reg)
747{
748 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
749 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
750 u32 value = 0;
751
752 if (E1000_REMOVED(hw_addr))
753 return ~value;
754
755 value = readl(&hw_addr[reg]);
756
757 /* reads should not return all F's */
758 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
759 struct net_device *netdev = igb->netdev;
760 hw->hw_addr = NULL;
761 netif_device_detach(netdev);
762 netdev_err(netdev, "PCIe link lost, device now detached\n");
763 }
764
765 return value;
766}
767
768/**
769 * igb_write_ivar - configure ivar for given MSI-X vector
770 * @hw: pointer to the HW structure
771 * @msix_vector: vector number we are allocating to a given ring
772 * @index: row index of IVAR register to write within IVAR table
773 * @offset: column offset of in IVAR, should be multiple of 8
774 *
775 * This function is intended to handle the writing of the IVAR register
776 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
777 * each containing an cause allocation for an Rx and Tx ring, and a
778 * variable number of rows depending on the number of queues supported.
779 **/
780static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
781 int index, int offset)
782{
783 u32 ivar = array_rd32(E1000_IVAR0, index);
784
785 /* clear any bits that are currently set */
786 ivar &= ~((u32)0xFF << offset);
787
788 /* write vector and valid bit */
789 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
790
791 array_wr32(E1000_IVAR0, index, ivar);
792}
793
794#define IGB_N0_QUEUE -1
795static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
796{
797 struct igb_adapter *adapter = q_vector->adapter;
798 struct e1000_hw *hw = &adapter->hw;
799 int rx_queue = IGB_N0_QUEUE;
800 int tx_queue = IGB_N0_QUEUE;
801 u32 msixbm = 0;
802
803 if (q_vector->rx.ring)
804 rx_queue = q_vector->rx.ring->reg_idx;
805 if (q_vector->tx.ring)
806 tx_queue = q_vector->tx.ring->reg_idx;
807
808 switch (hw->mac.type) {
809 case e1000_82575:
810 /* The 82575 assigns vectors using a bitmask, which matches the
811 * bitmask for the EICR/EIMS/EIMC registers. To assign one
812 * or more queues to a vector, we write the appropriate bits
813 * into the MSIXBM register for that vector.
814 */
815 if (rx_queue > IGB_N0_QUEUE)
816 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
817 if (tx_queue > IGB_N0_QUEUE)
818 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
819 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
820 msixbm |= E1000_EIMS_OTHER;
821 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
822 q_vector->eims_value = msixbm;
823 break;
824 case e1000_82576:
825 /* 82576 uses a table that essentially consists of 2 columns
826 * with 8 rows. The ordering is column-major so we use the
827 * lower 3 bits as the row index, and the 4th bit as the
828 * column offset.
829 */
830 if (rx_queue > IGB_N0_QUEUE)
831 igb_write_ivar(hw, msix_vector,
832 rx_queue & 0x7,
833 (rx_queue & 0x8) << 1);
834 if (tx_queue > IGB_N0_QUEUE)
835 igb_write_ivar(hw, msix_vector,
836 tx_queue & 0x7,
837 ((tx_queue & 0x8) << 1) + 8);
838 q_vector->eims_value = 1 << msix_vector;
839 break;
840 case e1000_82580:
841 case e1000_i350:
842 case e1000_i354:
843 case e1000_i210:
844 case e1000_i211:
845 /* On 82580 and newer adapters the scheme is similar to 82576
846 * however instead of ordering column-major we have things
847 * ordered row-major. So we traverse the table by using
848 * bit 0 as the column offset, and the remaining bits as the
849 * row index.
850 */
851 if (rx_queue > IGB_N0_QUEUE)
852 igb_write_ivar(hw, msix_vector,
853 rx_queue >> 1,
854 (rx_queue & 0x1) << 4);
855 if (tx_queue > IGB_N0_QUEUE)
856 igb_write_ivar(hw, msix_vector,
857 tx_queue >> 1,
858 ((tx_queue & 0x1) << 4) + 8);
859 q_vector->eims_value = 1 << msix_vector;
860 break;
861 default:
862 BUG();
863 break;
864 }
865
866 /* add q_vector eims value to global eims_enable_mask */
867 adapter->eims_enable_mask |= q_vector->eims_value;
868
869 /* configure q_vector to set itr on first interrupt */
870 q_vector->set_itr = 1;
871}
872
873/**
874 * igb_configure_msix - Configure MSI-X hardware
875 * @adapter: board private structure to initialize
876 *
877 * igb_configure_msix sets up the hardware to properly
878 * generate MSI-X interrupts.
879 **/
880static void igb_configure_msix(struct igb_adapter *adapter)
881{
882 u32 tmp;
883 int i, vector = 0;
884 struct e1000_hw *hw = &adapter->hw;
885
886 adapter->eims_enable_mask = 0;
887
888 /* set vector for other causes, i.e. link changes */
889 switch (hw->mac.type) {
890 case e1000_82575:
891 tmp = rd32(E1000_CTRL_EXT);
892 /* enable MSI-X PBA support*/
893 tmp |= E1000_CTRL_EXT_PBA_CLR;
894
895 /* Auto-Mask interrupts upon ICR read. */
896 tmp |= E1000_CTRL_EXT_EIAME;
897 tmp |= E1000_CTRL_EXT_IRCA;
898
899 wr32(E1000_CTRL_EXT, tmp);
900
901 /* enable msix_other interrupt */
902 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
903 adapter->eims_other = E1000_EIMS_OTHER;
904
905 break;
906
907 case e1000_82576:
908 case e1000_82580:
909 case e1000_i350:
910 case e1000_i354:
911 case e1000_i210:
912 case e1000_i211:
913 /* Turn on MSI-X capability first, or our settings
914 * won't stick. And it will take days to debug.
915 */
916 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
917 E1000_GPIE_PBA | E1000_GPIE_EIAME |
918 E1000_GPIE_NSICR);
919
920 /* enable msix_other interrupt */
921 adapter->eims_other = 1 << vector;
922 tmp = (vector++ | E1000_IVAR_VALID) << 8;
923
924 wr32(E1000_IVAR_MISC, tmp);
925 break;
926 default:
927 /* do nothing, since nothing else supports MSI-X */
928 break;
929 } /* switch (hw->mac.type) */
930
931 adapter->eims_enable_mask |= adapter->eims_other;
932
933 for (i = 0; i < adapter->num_q_vectors; i++)
934 igb_assign_vector(adapter->q_vector[i], vector++);
935
936 wrfl();
937}
938
939/**
940 * igb_request_msix - Initialize MSI-X interrupts
941 * @adapter: board private structure to initialize
942 *
943 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
944 * kernel.
945 **/
946static int igb_request_msix(struct igb_adapter *adapter)
947{
948 struct net_device *netdev = adapter->netdev;
949 int i, err = 0, vector = 0, free_vector = 0;
950
951 err = request_irq(adapter->msix_entries[vector].vector,
952 igb_msix_other, 0, netdev->name, adapter);
953 if (err)
954 goto err_out;
955
956 for (i = 0; i < adapter->num_q_vectors; i++) {
957 struct igb_q_vector *q_vector = adapter->q_vector[i];
958
959 vector++;
960
961 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
962
963 if (q_vector->rx.ring && q_vector->tx.ring)
964 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
965 q_vector->rx.ring->queue_index);
966 else if (q_vector->tx.ring)
967 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
968 q_vector->tx.ring->queue_index);
969 else if (q_vector->rx.ring)
970 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
971 q_vector->rx.ring->queue_index);
972 else
973 sprintf(q_vector->name, "%s-unused", netdev->name);
974
975 err = request_irq(adapter->msix_entries[vector].vector,
976 igb_msix_ring, 0, q_vector->name,
977 q_vector);
978 if (err)
979 goto err_free;
980 }
981
982 igb_configure_msix(adapter);
983 return 0;
984
985err_free:
986 /* free already assigned IRQs */
987 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
988
989 vector--;
990 for (i = 0; i < vector; i++) {
991 free_irq(adapter->msix_entries[free_vector++].vector,
992 adapter->q_vector[i]);
993 }
994err_out:
995 return err;
996}
997
998/**
999 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1000 * @adapter: board private structure to initialize
1001 * @v_idx: Index of vector to be freed
1002 *
1003 * This function frees the memory allocated to the q_vector.
1004 **/
1005static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1006{
1007 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1008
1009 adapter->q_vector[v_idx] = NULL;
1010
1011 /* igb_get_stats64() might access the rings on this vector,
1012 * we must wait a grace period before freeing it.
1013 */
1014 if (q_vector)
1015 kfree_rcu(q_vector, rcu);
1016}
1017
1018/**
1019 * igb_reset_q_vector - Reset config for interrupt vector
1020 * @adapter: board private structure to initialize
1021 * @v_idx: Index of vector to be reset
1022 *
1023 * If NAPI is enabled it will delete any references to the
1024 * NAPI struct. This is preparation for igb_free_q_vector.
1025 **/
1026static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1027{
1028 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1029
1030 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1031 * allocated. So, q_vector is NULL so we should stop here.
1032 */
1033 if (!q_vector)
1034 return;
1035
1036 if (q_vector->tx.ring)
1037 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1038
1039 if (q_vector->rx.ring)
1040 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
1041
1042 netif_napi_del(&q_vector->napi);
1043
1044}
1045
1046static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1047{
1048 int v_idx = adapter->num_q_vectors;
1049
1050 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1051 pci_disable_msix(adapter->pdev);
1052 else if (adapter->flags & IGB_FLAG_HAS_MSI)
1053 pci_disable_msi(adapter->pdev);
1054
1055 while (v_idx--)
1056 igb_reset_q_vector(adapter, v_idx);
1057}
1058
1059/**
1060 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1061 * @adapter: board private structure to initialize
1062 *
1063 * This function frees the memory allocated to the q_vectors. In addition if
1064 * NAPI is enabled it will delete any references to the NAPI struct prior
1065 * to freeing the q_vector.
1066 **/
1067static void igb_free_q_vectors(struct igb_adapter *adapter)
1068{
1069 int v_idx = adapter->num_q_vectors;
1070
1071 adapter->num_tx_queues = 0;
1072 adapter->num_rx_queues = 0;
1073 adapter->num_q_vectors = 0;
1074
1075 while (v_idx--) {
1076 igb_reset_q_vector(adapter, v_idx);
1077 igb_free_q_vector(adapter, v_idx);
1078 }
1079}
1080
1081/**
1082 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1083 * @adapter: board private structure to initialize
1084 *
1085 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1086 * MSI-X interrupts allocated.
1087 */
1088static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1089{
1090 igb_free_q_vectors(adapter);
1091 igb_reset_interrupt_capability(adapter);
1092}
1093
1094/**
1095 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1096 * @adapter: board private structure to initialize
1097 * @msix: boolean value of MSIX capability
1098 *
1099 * Attempt to configure interrupts using the best available
1100 * capabilities of the hardware and kernel.
1101 **/
1102static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1103{
1104 int err;
1105 int numvecs, i;
1106
1107 if (!msix)
1108 goto msi_only;
1109 adapter->flags |= IGB_FLAG_HAS_MSIX;
1110
1111 /* Number of supported queues. */
1112 adapter->num_rx_queues = adapter->rss_queues;
1113 if (adapter->vfs_allocated_count)
1114 adapter->num_tx_queues = 1;
1115 else
1116 adapter->num_tx_queues = adapter->rss_queues;
1117
1118 /* start with one vector for every Rx queue */
1119 numvecs = adapter->num_rx_queues;
1120
1121 /* if Tx handler is separate add 1 for every Tx queue */
1122 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1123 numvecs += adapter->num_tx_queues;
1124
1125 /* store the number of vectors reserved for queues */
1126 adapter->num_q_vectors = numvecs;
1127
1128 /* add 1 vector for link status interrupts */
1129 numvecs++;
1130 for (i = 0; i < numvecs; i++)
1131 adapter->msix_entries[i].entry = i;
1132
1133 err = pci_enable_msix_range(adapter->pdev,
1134 adapter->msix_entries,
1135 numvecs,
1136 numvecs);
1137 if (err > 0)
1138 return;
1139
1140 igb_reset_interrupt_capability(adapter);
1141
1142 /* If we can't do MSI-X, try MSI */
1143msi_only:
1144 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1145#ifdef CONFIG_PCI_IOV
1146 /* disable SR-IOV for non MSI-X configurations */
1147 if (adapter->vf_data) {
1148 struct e1000_hw *hw = &adapter->hw;
1149 /* disable iov and allow time for transactions to clear */
1150 pci_disable_sriov(adapter->pdev);
1151 msleep(500);
1152
1153 kfree(adapter->vf_data);
1154 adapter->vf_data = NULL;
1155 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1156 wrfl();
1157 msleep(100);
1158 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1159 }
1160#endif
1161 adapter->vfs_allocated_count = 0;
1162 adapter->rss_queues = 1;
1163 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1164 adapter->num_rx_queues = 1;
1165 adapter->num_tx_queues = 1;
1166 adapter->num_q_vectors = 1;
1167 if (!pci_enable_msi(adapter->pdev))
1168 adapter->flags |= IGB_FLAG_HAS_MSI;
1169}
1170
1171static void igb_add_ring(struct igb_ring *ring,
1172 struct igb_ring_container *head)
1173{
1174 head->ring = ring;
1175 head->count++;
1176}
1177
1178/**
1179 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1180 * @adapter: board private structure to initialize
1181 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1182 * @v_idx: index of vector in adapter struct
1183 * @txr_count: total number of Tx rings to allocate
1184 * @txr_idx: index of first Tx ring to allocate
1185 * @rxr_count: total number of Rx rings to allocate
1186 * @rxr_idx: index of first Rx ring to allocate
1187 *
1188 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1189 **/
1190static int igb_alloc_q_vector(struct igb_adapter *adapter,
1191 int v_count, int v_idx,
1192 int txr_count, int txr_idx,
1193 int rxr_count, int rxr_idx)
1194{
1195 struct igb_q_vector *q_vector;
1196 struct igb_ring *ring;
1197 int ring_count, size;
1198
1199 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1200 if (txr_count > 1 || rxr_count > 1)
1201 return -ENOMEM;
1202
1203 ring_count = txr_count + rxr_count;
1204 size = sizeof(struct igb_q_vector) +
1205 (sizeof(struct igb_ring) * ring_count);
1206
1207 /* allocate q_vector and rings */
1208 q_vector = adapter->q_vector[v_idx];
1209 if (!q_vector) {
1210 q_vector = kzalloc(size, GFP_KERNEL);
1211 } else if (size > ksize(q_vector)) {
1212 kfree_rcu(q_vector, rcu);
1213 q_vector = kzalloc(size, GFP_KERNEL);
1214 } else {
1215 memset(q_vector, 0, size);
1216 }
1217 if (!q_vector)
1218 return -ENOMEM;
1219
1220 /* initialize NAPI */
1221 netif_napi_add(adapter->netdev, &q_vector->napi,
1222 igb_poll, 64);
1223
1224 /* tie q_vector and adapter together */
1225 adapter->q_vector[v_idx] = q_vector;
1226 q_vector->adapter = adapter;
1227
1228 /* initialize work limits */
1229 q_vector->tx.work_limit = adapter->tx_work_limit;
1230
1231 /* initialize ITR configuration */
1232 q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
1233 q_vector->itr_val = IGB_START_ITR;
1234
1235 /* initialize pointer to rings */
1236 ring = q_vector->ring;
1237
1238 /* intialize ITR */
1239 if (rxr_count) {
1240 /* rx or rx/tx vector */
1241 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1242 q_vector->itr_val = adapter->rx_itr_setting;
1243 } else {
1244 /* tx only vector */
1245 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1246 q_vector->itr_val = adapter->tx_itr_setting;
1247 }
1248
1249 if (txr_count) {
1250 /* assign generic ring traits */
1251 ring->dev = &adapter->pdev->dev;
1252 ring->netdev = adapter->netdev;
1253
1254 /* configure backlink on ring */
1255 ring->q_vector = q_vector;
1256
1257 /* update q_vector Tx values */
1258 igb_add_ring(ring, &q_vector->tx);
1259
1260 /* For 82575, context index must be unique per ring. */
1261 if (adapter->hw.mac.type == e1000_82575)
1262 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1263
1264 /* apply Tx specific ring traits */
1265 ring->count = adapter->tx_ring_count;
1266 ring->queue_index = txr_idx;
1267
1268 u64_stats_init(&ring->tx_syncp);
1269 u64_stats_init(&ring->tx_syncp2);
1270
1271 /* assign ring to adapter */
1272 adapter->tx_ring[txr_idx] = ring;
1273
1274 /* push pointer to next ring */
1275 ring++;
1276 }
1277
1278 if (rxr_count) {
1279 /* assign generic ring traits */
1280 ring->dev = &adapter->pdev->dev;
1281 ring->netdev = adapter->netdev;
1282
1283 /* configure backlink on ring */
1284 ring->q_vector = q_vector;
1285
1286 /* update q_vector Rx values */
1287 igb_add_ring(ring, &q_vector->rx);
1288
1289 /* set flag indicating ring supports SCTP checksum offload */
1290 if (adapter->hw.mac.type >= e1000_82576)
1291 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1292
1293 /* On i350, i354, i210, and i211, loopback VLAN packets
1294 * have the tag byte-swapped.
1295 */
1296 if (adapter->hw.mac.type >= e1000_i350)
1297 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1298
1299 /* apply Rx specific ring traits */
1300 ring->count = adapter->rx_ring_count;
1301 ring->queue_index = rxr_idx;
1302
1303 u64_stats_init(&ring->rx_syncp);
1304
1305 /* assign ring to adapter */
1306 adapter->rx_ring[rxr_idx] = ring;
1307 }
1308
1309 return 0;
1310}
1311
1312
1313/**
1314 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1315 * @adapter: board private structure to initialize
1316 *
1317 * We allocate one q_vector per queue interrupt. If allocation fails we
1318 * return -ENOMEM.
1319 **/
1320static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1321{
1322 int q_vectors = adapter->num_q_vectors;
1323 int rxr_remaining = adapter->num_rx_queues;
1324 int txr_remaining = adapter->num_tx_queues;
1325 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1326 int err;
1327
1328 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1329 for (; rxr_remaining; v_idx++) {
1330 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1331 0, 0, 1, rxr_idx);
1332
1333 if (err)
1334 goto err_out;
1335
1336 /* update counts and index */
1337 rxr_remaining--;
1338 rxr_idx++;
1339 }
1340 }
1341
1342 for (; v_idx < q_vectors; v_idx++) {
1343 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1344 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1345
1346 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1347 tqpv, txr_idx, rqpv, rxr_idx);
1348
1349 if (err)
1350 goto err_out;
1351
1352 /* update counts and index */
1353 rxr_remaining -= rqpv;
1354 txr_remaining -= tqpv;
1355 rxr_idx++;
1356 txr_idx++;
1357 }
1358
1359 return 0;
1360
1361err_out:
1362 adapter->num_tx_queues = 0;
1363 adapter->num_rx_queues = 0;
1364 adapter->num_q_vectors = 0;
1365
1366 while (v_idx--)
1367 igb_free_q_vector(adapter, v_idx);
1368
1369 return -ENOMEM;
1370}
1371
1372/**
1373 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1374 * @adapter: board private structure to initialize
1375 * @msix: boolean value of MSIX capability
1376 *
1377 * This function initializes the interrupts and allocates all of the queues.
1378 **/
1379static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1380{
1381 struct pci_dev *pdev = adapter->pdev;
1382 int err;
1383
1384 igb_set_interrupt_capability(adapter, msix);
1385
1386 err = igb_alloc_q_vectors(adapter);
1387 if (err) {
1388 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1389 goto err_alloc_q_vectors;
1390 }
1391
1392 igb_cache_ring_register(adapter);
1393
1394 return 0;
1395
1396err_alloc_q_vectors:
1397 igb_reset_interrupt_capability(adapter);
1398 return err;
1399}
1400
1401/**
1402 * igb_request_irq - initialize interrupts
1403 * @adapter: board private structure to initialize
1404 *
1405 * Attempts to configure interrupts using the best available
1406 * capabilities of the hardware and kernel.
1407 **/
1408static int igb_request_irq(struct igb_adapter *adapter)
1409{
1410 struct net_device *netdev = adapter->netdev;
1411 struct pci_dev *pdev = adapter->pdev;
1412 int err = 0;
1413
1414 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1415 err = igb_request_msix(adapter);
1416 if (!err)
1417 goto request_done;
1418 /* fall back to MSI */
1419 igb_free_all_tx_resources(adapter);
1420 igb_free_all_rx_resources(adapter);
1421
1422 igb_clear_interrupt_scheme(adapter);
1423 err = igb_init_interrupt_scheme(adapter, false);
1424 if (err)
1425 goto request_done;
1426
1427 igb_setup_all_tx_resources(adapter);
1428 igb_setup_all_rx_resources(adapter);
1429 igb_configure(adapter);
1430 }
1431
1432 igb_assign_vector(adapter->q_vector[0], 0);
1433
1434 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1435 err = request_irq(pdev->irq, igb_intr_msi, 0,
1436 netdev->name, adapter);
1437 if (!err)
1438 goto request_done;
1439
1440 /* fall back to legacy interrupts */
1441 igb_reset_interrupt_capability(adapter);
1442 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1443 }
1444
1445 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1446 netdev->name, adapter);
1447
1448 if (err)
1449 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1450 err);
1451
1452request_done:
1453 return err;
1454}
1455
1456static void igb_free_irq(struct igb_adapter *adapter)
1457{
1458 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1459 int vector = 0, i;
1460
1461 free_irq(adapter->msix_entries[vector++].vector, adapter);
1462
1463 for (i = 0; i < adapter->num_q_vectors; i++)
1464 free_irq(adapter->msix_entries[vector++].vector,
1465 adapter->q_vector[i]);
1466 } else {
1467 free_irq(adapter->pdev->irq, adapter);
1468 }
1469}
1470
1471/**
1472 * igb_irq_disable - Mask off interrupt generation on the NIC
1473 * @adapter: board private structure
1474 **/
1475static void igb_irq_disable(struct igb_adapter *adapter)
1476{
1477 struct e1000_hw *hw = &adapter->hw;
1478
1479 /* we need to be careful when disabling interrupts. The VFs are also
1480 * mapped into these registers and so clearing the bits can cause
1481 * issues on the VF drivers so we only need to clear what we set
1482 */
1483 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1484 u32 regval = rd32(E1000_EIAM);
1485
1486 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1487 wr32(E1000_EIMC, adapter->eims_enable_mask);
1488 regval = rd32(E1000_EIAC);
1489 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1490 }
1491
1492 wr32(E1000_IAM, 0);
1493 wr32(E1000_IMC, ~0);
1494 wrfl();
1495 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1496 int i;
1497
1498 for (i = 0; i < adapter->num_q_vectors; i++)
1499 synchronize_irq(adapter->msix_entries[i].vector);
1500 } else {
1501 synchronize_irq(adapter->pdev->irq);
1502 }
1503}
1504
1505/**
1506 * igb_irq_enable - Enable default interrupt generation settings
1507 * @adapter: board private structure
1508 **/
1509static void igb_irq_enable(struct igb_adapter *adapter)
1510{
1511 struct e1000_hw *hw = &adapter->hw;
1512
1513 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1514 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1515 u32 regval = rd32(E1000_EIAC);
1516
1517 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1518 regval = rd32(E1000_EIAM);
1519 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1520 wr32(E1000_EIMS, adapter->eims_enable_mask);
1521 if (adapter->vfs_allocated_count) {
1522 wr32(E1000_MBVFIMR, 0xFF);
1523 ims |= E1000_IMS_VMMB;
1524 }
1525 wr32(E1000_IMS, ims);
1526 } else {
1527 wr32(E1000_IMS, IMS_ENABLE_MASK |
1528 E1000_IMS_DRSTA);
1529 wr32(E1000_IAM, IMS_ENABLE_MASK |
1530 E1000_IMS_DRSTA);
1531 }
1532}
1533
1534static void igb_update_mng_vlan(struct igb_adapter *adapter)
1535{
1536 struct e1000_hw *hw = &adapter->hw;
1537 u16 pf_id = adapter->vfs_allocated_count;
1538 u16 vid = adapter->hw.mng_cookie.vlan_id;
1539 u16 old_vid = adapter->mng_vlan_id;
1540
1541 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1542 /* add VID to filter table */
1543 igb_vfta_set(hw, vid, pf_id, true, true);
1544 adapter->mng_vlan_id = vid;
1545 } else {
1546 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1547 }
1548
1549 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1550 (vid != old_vid) &&
1551 !test_bit(old_vid, adapter->active_vlans)) {
1552 /* remove VID from filter table */
1553 igb_vfta_set(hw, vid, pf_id, false, true);
1554 }
1555}
1556
1557/**
1558 * igb_release_hw_control - release control of the h/w to f/w
1559 * @adapter: address of board private structure
1560 *
1561 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1562 * For ASF and Pass Through versions of f/w this means that the
1563 * driver is no longer loaded.
1564 **/
1565static void igb_release_hw_control(struct igb_adapter *adapter)
1566{
1567 struct e1000_hw *hw = &adapter->hw;
1568 u32 ctrl_ext;
1569
1570 /* Let firmware take over control of h/w */
1571 ctrl_ext = rd32(E1000_CTRL_EXT);
1572 wr32(E1000_CTRL_EXT,
1573 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1574}
1575
1576/**
1577 * igb_get_hw_control - get control of the h/w from f/w
1578 * @adapter: address of board private structure
1579 *
1580 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1581 * For ASF and Pass Through versions of f/w this means that
1582 * the driver is loaded.
1583 **/
1584static void igb_get_hw_control(struct igb_adapter *adapter)
1585{
1586 struct e1000_hw *hw = &adapter->hw;
1587 u32 ctrl_ext;
1588
1589 /* Let firmware know the driver has taken over */
1590 ctrl_ext = rd32(E1000_CTRL_EXT);
1591 wr32(E1000_CTRL_EXT,
1592 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1593}
1594
1595/**
1596 * igb_configure - configure the hardware for RX and TX
1597 * @adapter: private board structure
1598 **/
1599static void igb_configure(struct igb_adapter *adapter)
1600{
1601 struct net_device *netdev = adapter->netdev;
1602 int i;
1603
1604 igb_get_hw_control(adapter);
1605 igb_set_rx_mode(netdev);
1606
1607 igb_restore_vlan(adapter);
1608
1609 igb_setup_tctl(adapter);
1610 igb_setup_mrqc(adapter);
1611 igb_setup_rctl(adapter);
1612
1613 igb_configure_tx(adapter);
1614 igb_configure_rx(adapter);
1615
1616 igb_rx_fifo_flush_82575(&adapter->hw);
1617
1618 /* call igb_desc_unused which always leaves
1619 * at least 1 descriptor unused to make sure
1620 * next_to_use != next_to_clean
1621 */
1622 for (i = 0; i < adapter->num_rx_queues; i++) {
1623 struct igb_ring *ring = adapter->rx_ring[i];
1624 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1625 }
1626}
1627
1628/**
1629 * igb_power_up_link - Power up the phy/serdes link
1630 * @adapter: address of board private structure
1631 **/
1632void igb_power_up_link(struct igb_adapter *adapter)
1633{
1634 igb_reset_phy(&adapter->hw);
1635
1636 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1637 igb_power_up_phy_copper(&adapter->hw);
1638 else
1639 igb_power_up_serdes_link_82575(&adapter->hw);
1640
1641 igb_setup_link(&adapter->hw);
1642}
1643
1644/**
1645 * igb_power_down_link - Power down the phy/serdes link
1646 * @adapter: address of board private structure
1647 */
1648static void igb_power_down_link(struct igb_adapter *adapter)
1649{
1650 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1651 igb_power_down_phy_copper_82575(&adapter->hw);
1652 else
1653 igb_shutdown_serdes_link_82575(&adapter->hw);
1654}
1655
1656/**
1657 * Detect and switch function for Media Auto Sense
1658 * @adapter: address of the board private structure
1659 **/
1660static void igb_check_swap_media(struct igb_adapter *adapter)
1661{
1662 struct e1000_hw *hw = &adapter->hw;
1663 u32 ctrl_ext, connsw;
1664 bool swap_now = false;
1665
1666 ctrl_ext = rd32(E1000_CTRL_EXT);
1667 connsw = rd32(E1000_CONNSW);
1668
1669 /* need to live swap if current media is copper and we have fiber/serdes
1670 * to go to.
1671 */
1672
1673 if ((hw->phy.media_type == e1000_media_type_copper) &&
1674 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1675 swap_now = true;
1676 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1677 /* copper signal takes time to appear */
1678 if (adapter->copper_tries < 4) {
1679 adapter->copper_tries++;
1680 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1681 wr32(E1000_CONNSW, connsw);
1682 return;
1683 } else {
1684 adapter->copper_tries = 0;
1685 if ((connsw & E1000_CONNSW_PHYSD) &&
1686 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1687 swap_now = true;
1688 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1689 wr32(E1000_CONNSW, connsw);
1690 }
1691 }
1692 }
1693
1694 if (!swap_now)
1695 return;
1696
1697 switch (hw->phy.media_type) {
1698 case e1000_media_type_copper:
1699 netdev_info(adapter->netdev,
1700 "MAS: changing media to fiber/serdes\n");
1701 ctrl_ext |=
1702 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1703 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1704 adapter->copper_tries = 0;
1705 break;
1706 case e1000_media_type_internal_serdes:
1707 case e1000_media_type_fiber:
1708 netdev_info(adapter->netdev,
1709 "MAS: changing media to copper\n");
1710 ctrl_ext &=
1711 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1712 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1713 break;
1714 default:
1715 /* shouldn't get here during regular operation */
1716 netdev_err(adapter->netdev,
1717 "AMS: Invalid media type found, returning\n");
1718 break;
1719 }
1720 wr32(E1000_CTRL_EXT, ctrl_ext);
1721}
1722
1723/**
1724 * igb_up - Open the interface and prepare it to handle traffic
1725 * @adapter: board private structure
1726 **/
1727int igb_up(struct igb_adapter *adapter)
1728{
1729 struct e1000_hw *hw = &adapter->hw;
1730 int i;
1731
1732 /* hardware has been reset, we need to reload some things */
1733 igb_configure(adapter);
1734
1735 clear_bit(__IGB_DOWN, &adapter->state);
1736
1737 for (i = 0; i < adapter->num_q_vectors; i++)
1738 napi_enable(&(adapter->q_vector[i]->napi));
1739
1740 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1741 igb_configure_msix(adapter);
1742 else
1743 igb_assign_vector(adapter->q_vector[0], 0);
1744
1745 /* Clear any pending interrupts. */
1746 rd32(E1000_ICR);
1747 igb_irq_enable(adapter);
1748
1749 /* notify VFs that reset has been completed */
1750 if (adapter->vfs_allocated_count) {
1751 u32 reg_data = rd32(E1000_CTRL_EXT);
1752
1753 reg_data |= E1000_CTRL_EXT_PFRSTD;
1754 wr32(E1000_CTRL_EXT, reg_data);
1755 }
1756
1757 netif_tx_start_all_queues(adapter->netdev);
1758
1759 /* start the watchdog. */
1760 hw->mac.get_link_status = 1;
1761 schedule_work(&adapter->watchdog_task);
1762
1763 if ((adapter->flags & IGB_FLAG_EEE) &&
1764 (!hw->dev_spec._82575.eee_disable))
1765 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1766
1767 return 0;
1768}
1769
1770void igb_down(struct igb_adapter *adapter)
1771{
1772 struct net_device *netdev = adapter->netdev;
1773 struct e1000_hw *hw = &adapter->hw;
1774 u32 tctl, rctl;
1775 int i;
1776
1777 /* signal that we're down so the interrupt handler does not
1778 * reschedule our watchdog timer
1779 */
1780 set_bit(__IGB_DOWN, &adapter->state);
1781
1782 /* disable receives in the hardware */
1783 rctl = rd32(E1000_RCTL);
1784 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1785 /* flush and sleep below */
1786
1787 netif_carrier_off(netdev);
1788 netif_tx_stop_all_queues(netdev);
1789
1790 /* disable transmits in the hardware */
1791 tctl = rd32(E1000_TCTL);
1792 tctl &= ~E1000_TCTL_EN;
1793 wr32(E1000_TCTL, tctl);
1794 /* flush both disables and wait for them to finish */
1795 wrfl();
1796 usleep_range(10000, 11000);
1797
1798 igb_irq_disable(adapter);
1799
1800 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1801
1802 for (i = 0; i < adapter->num_q_vectors; i++) {
1803 if (adapter->q_vector[i]) {
1804 napi_synchronize(&adapter->q_vector[i]->napi);
1805 napi_disable(&adapter->q_vector[i]->napi);
1806 }
1807 }
1808
1809 del_timer_sync(&adapter->watchdog_timer);
1810 del_timer_sync(&adapter->phy_info_timer);
1811
1812 /* record the stats before reset*/
1813 spin_lock(&adapter->stats64_lock);
1814 igb_update_stats(adapter, &adapter->stats64);
1815 spin_unlock(&adapter->stats64_lock);
1816
1817 adapter->link_speed = 0;
1818 adapter->link_duplex = 0;
1819
1820 if (!pci_channel_offline(adapter->pdev))
1821 igb_reset(adapter);
1822 igb_clean_all_tx_rings(adapter);
1823 igb_clean_all_rx_rings(adapter);
1824#ifdef CONFIG_IGB_DCA
1825
1826 /* since we reset the hardware DCA settings were cleared */
1827 igb_setup_dca(adapter);
1828#endif
1829}
1830
1831void igb_reinit_locked(struct igb_adapter *adapter)
1832{
1833 WARN_ON(in_interrupt());
1834 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1835 usleep_range(1000, 2000);
1836 igb_down(adapter);
1837 igb_up(adapter);
1838 clear_bit(__IGB_RESETTING, &adapter->state);
1839}
1840
1841/** igb_enable_mas - Media Autosense re-enable after swap
1842 *
1843 * @adapter: adapter struct
1844 **/
1845static void igb_enable_mas(struct igb_adapter *adapter)
1846{
1847 struct e1000_hw *hw = &adapter->hw;
1848 u32 connsw = rd32(E1000_CONNSW);
1849
1850 /* configure for SerDes media detect */
1851 if ((hw->phy.media_type == e1000_media_type_copper) &&
1852 (!(connsw & E1000_CONNSW_SERDESD))) {
1853 connsw |= E1000_CONNSW_ENRGSRC;
1854 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1855 wr32(E1000_CONNSW, connsw);
1856 wrfl();
1857 }
1858}
1859
1860void igb_reset(struct igb_adapter *adapter)
1861{
1862 struct pci_dev *pdev = adapter->pdev;
1863 struct e1000_hw *hw = &adapter->hw;
1864 struct e1000_mac_info *mac = &hw->mac;
1865 struct e1000_fc_info *fc = &hw->fc;
1866 u32 pba, hwm;
1867
1868 /* Repartition Pba for greater than 9k mtu
1869 * To take effect CTRL.RST is required.
1870 */
1871 switch (mac->type) {
1872 case e1000_i350:
1873 case e1000_i354:
1874 case e1000_82580:
1875 pba = rd32(E1000_RXPBS);
1876 pba = igb_rxpbs_adjust_82580(pba);
1877 break;
1878 case e1000_82576:
1879 pba = rd32(E1000_RXPBS);
1880 pba &= E1000_RXPBS_SIZE_MASK_82576;
1881 break;
1882 case e1000_82575:
1883 case e1000_i210:
1884 case e1000_i211:
1885 default:
1886 pba = E1000_PBA_34K;
1887 break;
1888 }
1889
1890 if (mac->type == e1000_82575) {
1891 u32 min_rx_space, min_tx_space, needed_tx_space;
1892
1893 /* write Rx PBA so that hardware can report correct Tx PBA */
1894 wr32(E1000_PBA, pba);
1895
1896 /* To maintain wire speed transmits, the Tx FIFO should be
1897 * large enough to accommodate two full transmit packets,
1898 * rounded up to the next 1KB and expressed in KB. Likewise,
1899 * the Rx FIFO should be large enough to accommodate at least
1900 * one full receive packet and is similarly rounded up and
1901 * expressed in KB.
1902 */
1903 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
1904
1905 /* The Tx FIFO also stores 16 bytes of information about the Tx
1906 * but don't include Ethernet FCS because hardware appends it.
1907 * We only need to round down to the nearest 512 byte block
1908 * count since the value we care about is 2 frames, not 1.
1909 */
1910 min_tx_space = adapter->max_frame_size;
1911 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
1912 min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
1913
1914 /* upper 16 bits has Tx packet buffer allocation size in KB */
1915 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
1916
1917 /* If current Tx allocation is less than the min Tx FIFO size,
1918 * and the min Tx FIFO size is less than the current Rx FIFO
1919 * allocation, take space away from current Rx allocation.
1920 */
1921 if (needed_tx_space < pba) {
1922 pba -= needed_tx_space;
1923
1924 /* if short on Rx space, Rx wins and must trump Tx
1925 * adjustment
1926 */
1927 if (pba < min_rx_space)
1928 pba = min_rx_space;
1929 }
1930
1931 /* adjust PBA for jumbo frames */
1932 wr32(E1000_PBA, pba);
1933 }
1934
1935 /* flow control settings
1936 * The high water mark must be low enough to fit one full frame
1937 * after transmitting the pause frame. As such we must have enough
1938 * space to allow for us to complete our current transmit and then
1939 * receive the frame that is in progress from the link partner.
1940 * Set it to:
1941 * - the full Rx FIFO size minus one full Tx plus one full Rx frame
1942 */
1943 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
1944
1945 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
1946 fc->low_water = fc->high_water - 16;
1947 fc->pause_time = 0xFFFF;
1948 fc->send_xon = 1;
1949 fc->current_mode = fc->requested_mode;
1950
1951 /* disable receive for all VFs and wait one second */
1952 if (adapter->vfs_allocated_count) {
1953 int i;
1954
1955 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1956 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1957
1958 /* ping all the active vfs to let them know we are going down */
1959 igb_ping_all_vfs(adapter);
1960
1961 /* disable transmits and receives */
1962 wr32(E1000_VFRE, 0);
1963 wr32(E1000_VFTE, 0);
1964 }
1965
1966 /* Allow time for pending master requests to run */
1967 hw->mac.ops.reset_hw(hw);
1968 wr32(E1000_WUC, 0);
1969
1970 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1971 /* need to resetup here after media swap */
1972 adapter->ei.get_invariants(hw);
1973 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1974 }
1975 if ((mac->type == e1000_82575) &&
1976 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
1977 igb_enable_mas(adapter);
1978 }
1979 if (hw->mac.ops.init_hw(hw))
1980 dev_err(&pdev->dev, "Hardware Error\n");
1981
1982 /* Flow control settings reset on hardware reset, so guarantee flow
1983 * control is off when forcing speed.
1984 */
1985 if (!hw->mac.autoneg)
1986 igb_force_mac_fc(hw);
1987
1988 igb_init_dmac(adapter, pba);
1989#ifdef CONFIG_IGB_HWMON
1990 /* Re-initialize the thermal sensor on i350 devices. */
1991 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1992 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1993 /* If present, re-initialize the external thermal sensor
1994 * interface.
1995 */
1996 if (adapter->ets)
1997 mac->ops.init_thermal_sensor_thresh(hw);
1998 }
1999 }
2000#endif
2001 /* Re-establish EEE setting */
2002 if (hw->phy.media_type == e1000_media_type_copper) {
2003 switch (mac->type) {
2004 case e1000_i350:
2005 case e1000_i210:
2006 case e1000_i211:
2007 igb_set_eee_i350(hw, true, true);
2008 break;
2009 case e1000_i354:
2010 igb_set_eee_i354(hw, true, true);
2011 break;
2012 default:
2013 break;
2014 }
2015 }
2016 if (!netif_running(adapter->netdev))
2017 igb_power_down_link(adapter);
2018
2019 igb_update_mng_vlan(adapter);
2020
2021 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2022 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2023
2024 /* Re-enable PTP, where applicable. */
2025 igb_ptp_reset(adapter);
2026
2027 igb_get_phy_info(hw);
2028}
2029
2030static netdev_features_t igb_fix_features(struct net_device *netdev,
2031 netdev_features_t features)
2032{
2033 /* Since there is no support for separate Rx/Tx vlan accel
2034 * enable/disable make sure Tx flag is always in same state as Rx.
2035 */
2036 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2037 features |= NETIF_F_HW_VLAN_CTAG_TX;
2038 else
2039 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2040
2041 return features;
2042}
2043
2044static int igb_set_features(struct net_device *netdev,
2045 netdev_features_t features)
2046{
2047 netdev_features_t changed = netdev->features ^ features;
2048 struct igb_adapter *adapter = netdev_priv(netdev);
2049
2050 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2051 igb_vlan_mode(netdev, features);
2052
2053 if (!(changed & NETIF_F_RXALL))
2054 return 0;
2055
2056 netdev->features = features;
2057
2058 if (netif_running(netdev))
2059 igb_reinit_locked(adapter);
2060 else
2061 igb_reset(adapter);
2062
2063 return 0;
2064}
2065
2066static const struct net_device_ops igb_netdev_ops = {
2067 .ndo_open = igb_open,
2068 .ndo_stop = igb_close,
2069 .ndo_start_xmit = igb_xmit_frame,
2070 .ndo_get_stats64 = igb_get_stats64,
2071 .ndo_set_rx_mode = igb_set_rx_mode,
2072 .ndo_set_mac_address = igb_set_mac,
2073 .ndo_change_mtu = igb_change_mtu,
2074 .ndo_do_ioctl = igb_ioctl,
2075 .ndo_tx_timeout = igb_tx_timeout,
2076 .ndo_validate_addr = eth_validate_addr,
2077 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2078 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
2079 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2080 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
2081 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
2082 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
2083 .ndo_get_vf_config = igb_ndo_get_vf_config,
2084#ifdef CONFIG_NET_POLL_CONTROLLER
2085 .ndo_poll_controller = igb_netpoll,
2086#endif
2087 .ndo_fix_features = igb_fix_features,
2088 .ndo_set_features = igb_set_features,
2089 .ndo_features_check = passthru_features_check,
2090};
2091
2092/**
2093 * igb_set_fw_version - Configure version string for ethtool
2094 * @adapter: adapter struct
2095 **/
2096void igb_set_fw_version(struct igb_adapter *adapter)
2097{
2098 struct e1000_hw *hw = &adapter->hw;
2099 struct e1000_fw_version fw;
2100
2101 igb_get_fw_version(hw, &fw);
2102
2103 switch (hw->mac.type) {
2104 case e1000_i210:
2105 case e1000_i211:
2106 if (!(igb_get_flash_presence_i210(hw))) {
2107 snprintf(adapter->fw_version,
2108 sizeof(adapter->fw_version),
2109 "%2d.%2d-%d",
2110 fw.invm_major, fw.invm_minor,
2111 fw.invm_img_type);
2112 break;
2113 }
2114 /* fall through */
2115 default:
2116 /* if option is rom valid, display its version too */
2117 if (fw.or_valid) {
2118 snprintf(adapter->fw_version,
2119 sizeof(adapter->fw_version),
2120 "%d.%d, 0x%08x, %d.%d.%d",
2121 fw.eep_major, fw.eep_minor, fw.etrack_id,
2122 fw.or_major, fw.or_build, fw.or_patch);
2123 /* no option rom */
2124 } else if (fw.etrack_id != 0X0000) {
2125 snprintf(adapter->fw_version,
2126 sizeof(adapter->fw_version),
2127 "%d.%d, 0x%08x",
2128 fw.eep_major, fw.eep_minor, fw.etrack_id);
2129 } else {
2130 snprintf(adapter->fw_version,
2131 sizeof(adapter->fw_version),
2132 "%d.%d.%d",
2133 fw.eep_major, fw.eep_minor, fw.eep_build);
2134 }
2135 break;
2136 }
2137}
2138
2139/**
2140 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2141 *
2142 * @adapter: adapter struct
2143 **/
2144static void igb_init_mas(struct igb_adapter *adapter)
2145{
2146 struct e1000_hw *hw = &adapter->hw;
2147 u16 eeprom_data;
2148
2149 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2150 switch (hw->bus.func) {
2151 case E1000_FUNC_0:
2152 if (eeprom_data & IGB_MAS_ENABLE_0) {
2153 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2154 netdev_info(adapter->netdev,
2155 "MAS: Enabling Media Autosense for port %d\n",
2156 hw->bus.func);
2157 }
2158 break;
2159 case E1000_FUNC_1:
2160 if (eeprom_data & IGB_MAS_ENABLE_1) {
2161 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2162 netdev_info(adapter->netdev,
2163 "MAS: Enabling Media Autosense for port %d\n",
2164 hw->bus.func);
2165 }
2166 break;
2167 case E1000_FUNC_2:
2168 if (eeprom_data & IGB_MAS_ENABLE_2) {
2169 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2170 netdev_info(adapter->netdev,
2171 "MAS: Enabling Media Autosense for port %d\n",
2172 hw->bus.func);
2173 }
2174 break;
2175 case E1000_FUNC_3:
2176 if (eeprom_data & IGB_MAS_ENABLE_3) {
2177 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2178 netdev_info(adapter->netdev,
2179 "MAS: Enabling Media Autosense for port %d\n",
2180 hw->bus.func);
2181 }
2182 break;
2183 default:
2184 /* Shouldn't get here */
2185 netdev_err(adapter->netdev,
2186 "MAS: Invalid port configuration, returning\n");
2187 break;
2188 }
2189}
2190
2191/**
2192 * igb_init_i2c - Init I2C interface
2193 * @adapter: pointer to adapter structure
2194 **/
2195static s32 igb_init_i2c(struct igb_adapter *adapter)
2196{
2197 s32 status = 0;
2198
2199 /* I2C interface supported on i350 devices */
2200 if (adapter->hw.mac.type != e1000_i350)
2201 return 0;
2202
2203 /* Initialize the i2c bus which is controlled by the registers.
2204 * This bus will use the i2c_algo_bit structue that implements
2205 * the protocol through toggling of the 4 bits in the register.
2206 */
2207 adapter->i2c_adap.owner = THIS_MODULE;
2208 adapter->i2c_algo = igb_i2c_algo;
2209 adapter->i2c_algo.data = adapter;
2210 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2211 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2212 strlcpy(adapter->i2c_adap.name, "igb BB",
2213 sizeof(adapter->i2c_adap.name));
2214 status = i2c_bit_add_bus(&adapter->i2c_adap);
2215 return status;
2216}
2217
2218/**
2219 * igb_probe - Device Initialization Routine
2220 * @pdev: PCI device information struct
2221 * @ent: entry in igb_pci_tbl
2222 *
2223 * Returns 0 on success, negative on failure
2224 *
2225 * igb_probe initializes an adapter identified by a pci_dev structure.
2226 * The OS initialization, configuring of the adapter private structure,
2227 * and a hardware reset occur.
2228 **/
2229static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2230{
2231 struct net_device *netdev;
2232 struct igb_adapter *adapter;
2233 struct e1000_hw *hw;
2234 u16 eeprom_data = 0;
2235 s32 ret_val;
2236 static int global_quad_port_a; /* global quad port a indication */
2237 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2238 int err, pci_using_dac;
2239 u8 part_str[E1000_PBANUM_LENGTH];
2240
2241 /* Catch broken hardware that put the wrong VF device ID in
2242 * the PCIe SR-IOV capability.
2243 */
2244 if (pdev->is_virtfn) {
2245 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
2246 pci_name(pdev), pdev->vendor, pdev->device);
2247 return -EINVAL;
2248 }
2249
2250 err = pci_enable_device_mem(pdev);
2251 if (err)
2252 return err;
2253
2254 pci_using_dac = 0;
2255 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2256 if (!err) {
2257 pci_using_dac = 1;
2258 } else {
2259 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2260 if (err) {
2261 dev_err(&pdev->dev,
2262 "No usable DMA configuration, aborting\n");
2263 goto err_dma;
2264 }
2265 }
2266
2267 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2268 IORESOURCE_MEM),
2269 igb_driver_name);
2270 if (err)
2271 goto err_pci_reg;
2272
2273 pci_enable_pcie_error_reporting(pdev);
2274
2275 pci_set_master(pdev);
2276 pci_save_state(pdev);
2277
2278 err = -ENOMEM;
2279 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2280 IGB_MAX_TX_QUEUES);
2281 if (!netdev)
2282 goto err_alloc_etherdev;
2283
2284 SET_NETDEV_DEV(netdev, &pdev->dev);
2285
2286 pci_set_drvdata(pdev, netdev);
2287 adapter = netdev_priv(netdev);
2288 adapter->netdev = netdev;
2289 adapter->pdev = pdev;
2290 hw = &adapter->hw;
2291 hw->back = adapter;
2292 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2293
2294 err = -EIO;
2295 adapter->io_addr = pci_iomap(pdev, 0, 0);
2296 if (!adapter->io_addr)
2297 goto err_ioremap;
2298 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
2299 hw->hw_addr = adapter->io_addr;
2300
2301 netdev->netdev_ops = &igb_netdev_ops;
2302 igb_set_ethtool_ops(netdev);
2303 netdev->watchdog_timeo = 5 * HZ;
2304
2305 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2306
2307 netdev->mem_start = pci_resource_start(pdev, 0);
2308 netdev->mem_end = pci_resource_end(pdev, 0);
2309
2310 /* PCI config space info */
2311 hw->vendor_id = pdev->vendor;
2312 hw->device_id = pdev->device;
2313 hw->revision_id = pdev->revision;
2314 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2315 hw->subsystem_device_id = pdev->subsystem_device;
2316
2317 /* Copy the default MAC, PHY and NVM function pointers */
2318 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2319 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2320 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2321 /* Initialize skew-specific constants */
2322 err = ei->get_invariants(hw);
2323 if (err)
2324 goto err_sw_init;
2325
2326 /* setup the private structure */
2327 err = igb_sw_init(adapter);
2328 if (err)
2329 goto err_sw_init;
2330
2331 igb_get_bus_info_pcie(hw);
2332
2333 hw->phy.autoneg_wait_to_complete = false;
2334
2335 /* Copper options */
2336 if (hw->phy.media_type == e1000_media_type_copper) {
2337 hw->phy.mdix = AUTO_ALL_MODES;
2338 hw->phy.disable_polarity_correction = false;
2339 hw->phy.ms_type = e1000_ms_hw_default;
2340 }
2341
2342 if (igb_check_reset_block(hw))
2343 dev_info(&pdev->dev,
2344 "PHY reset is blocked due to SOL/IDER session.\n");
2345
2346 /* features is initialized to 0 in allocation, it might have bits
2347 * set by igb_sw_init so we should use an or instead of an
2348 * assignment.
2349 */
2350 netdev->features |= NETIF_F_SG |
2351 NETIF_F_IP_CSUM |
2352 NETIF_F_IPV6_CSUM |
2353 NETIF_F_TSO |
2354 NETIF_F_TSO6 |
2355 NETIF_F_RXHASH |
2356 NETIF_F_RXCSUM |
2357 NETIF_F_HW_VLAN_CTAG_RX |
2358 NETIF_F_HW_VLAN_CTAG_TX;
2359
2360 /* copy netdev features into list of user selectable features */
2361 netdev->hw_features |= netdev->features;
2362 netdev->hw_features |= NETIF_F_RXALL;
2363
2364 /* set this bit last since it cannot be part of hw_features */
2365 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2366
2367 netdev->vlan_features |= NETIF_F_TSO |
2368 NETIF_F_TSO6 |
2369 NETIF_F_IP_CSUM |
2370 NETIF_F_IPV6_CSUM |
2371 NETIF_F_SG;
2372
2373 netdev->priv_flags |= IFF_SUPP_NOFCS;
2374
2375 if (pci_using_dac) {
2376 netdev->features |= NETIF_F_HIGHDMA;
2377 netdev->vlan_features |= NETIF_F_HIGHDMA;
2378 }
2379
2380 if (hw->mac.type >= e1000_82576) {
2381 netdev->hw_features |= NETIF_F_SCTP_CRC;
2382 netdev->features |= NETIF_F_SCTP_CRC;
2383 }
2384
2385 netdev->priv_flags |= IFF_UNICAST_FLT;
2386
2387 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2388
2389 /* before reading the NVM, reset the controller to put the device in a
2390 * known good starting state
2391 */
2392 hw->mac.ops.reset_hw(hw);
2393
2394 /* make sure the NVM is good , i211/i210 parts can have special NVM
2395 * that doesn't contain a checksum
2396 */
2397 switch (hw->mac.type) {
2398 case e1000_i210:
2399 case e1000_i211:
2400 if (igb_get_flash_presence_i210(hw)) {
2401 if (hw->nvm.ops.validate(hw) < 0) {
2402 dev_err(&pdev->dev,
2403 "The NVM Checksum Is Not Valid\n");
2404 err = -EIO;
2405 goto err_eeprom;
2406 }
2407 }
2408 break;
2409 default:
2410 if (hw->nvm.ops.validate(hw) < 0) {
2411 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2412 err = -EIO;
2413 goto err_eeprom;
2414 }
2415 break;
2416 }
2417
2418 /* copy the MAC address out of the NVM */
2419 if (hw->mac.ops.read_mac_addr(hw))
2420 dev_err(&pdev->dev, "NVM Read Error\n");
2421
2422 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2423
2424 if (!is_valid_ether_addr(netdev->dev_addr)) {
2425 dev_err(&pdev->dev, "Invalid MAC Address\n");
2426 err = -EIO;
2427 goto err_eeprom;
2428 }
2429
2430 /* get firmware version for ethtool -i */
2431 igb_set_fw_version(adapter);
2432
2433 /* configure RXPBSIZE and TXPBSIZE */
2434 if (hw->mac.type == e1000_i210) {
2435 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2436 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2437 }
2438
2439 setup_timer(&adapter->watchdog_timer, igb_watchdog,
2440 (unsigned long) adapter);
2441 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2442 (unsigned long) adapter);
2443
2444 INIT_WORK(&adapter->reset_task, igb_reset_task);
2445 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2446
2447 /* Initialize link properties that are user-changeable */
2448 adapter->fc_autoneg = true;
2449 hw->mac.autoneg = true;
2450 hw->phy.autoneg_advertised = 0x2f;
2451
2452 hw->fc.requested_mode = e1000_fc_default;
2453 hw->fc.current_mode = e1000_fc_default;
2454
2455 igb_validate_mdi_setting(hw);
2456
2457 /* By default, support wake on port A */
2458 if (hw->bus.func == 0)
2459 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2460
2461 /* Check the NVM for wake support on non-port A ports */
2462 if (hw->mac.type >= e1000_82580)
2463 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2464 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2465 &eeprom_data);
2466 else if (hw->bus.func == 1)
2467 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2468
2469 if (eeprom_data & IGB_EEPROM_APME)
2470 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2471
2472 /* now that we have the eeprom settings, apply the special cases where
2473 * the eeprom may be wrong or the board simply won't support wake on
2474 * lan on a particular port
2475 */
2476 switch (pdev->device) {
2477 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2478 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2479 break;
2480 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2481 case E1000_DEV_ID_82576_FIBER:
2482 case E1000_DEV_ID_82576_SERDES:
2483 /* Wake events only supported on port A for dual fiber
2484 * regardless of eeprom setting
2485 */
2486 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2487 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2488 break;
2489 case E1000_DEV_ID_82576_QUAD_COPPER:
2490 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2491 /* if quad port adapter, disable WoL on all but port A */
2492 if (global_quad_port_a != 0)
2493 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2494 else
2495 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2496 /* Reset for multiple quad port adapters */
2497 if (++global_quad_port_a == 4)
2498 global_quad_port_a = 0;
2499 break;
2500 default:
2501 /* If the device can't wake, don't set software support */
2502 if (!device_can_wakeup(&adapter->pdev->dev))
2503 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2504 }
2505
2506 /* initialize the wol settings based on the eeprom settings */
2507 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2508 adapter->wol |= E1000_WUFC_MAG;
2509
2510 /* Some vendors want WoL disabled by default, but still supported */
2511 if ((hw->mac.type == e1000_i350) &&
2512 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2513 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2514 adapter->wol = 0;
2515 }
2516
2517 device_set_wakeup_enable(&adapter->pdev->dev,
2518 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2519
2520 /* reset the hardware with the new settings */
2521 igb_reset(adapter);
2522
2523 /* Init the I2C interface */
2524 err = igb_init_i2c(adapter);
2525 if (err) {
2526 dev_err(&pdev->dev, "failed to init i2c interface\n");
2527 goto err_eeprom;
2528 }
2529
2530 /* let the f/w know that the h/w is now under the control of the
2531 * driver.
2532 */
2533 igb_get_hw_control(adapter);
2534
2535 strcpy(netdev->name, "eth%d");
2536 err = register_netdev(netdev);
2537 if (err)
2538 goto err_register;
2539
2540 /* carrier off reporting is important to ethtool even BEFORE open */
2541 netif_carrier_off(netdev);
2542
2543#ifdef CONFIG_IGB_DCA
2544 if (dca_add_requester(&pdev->dev) == 0) {
2545 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2546 dev_info(&pdev->dev, "DCA enabled\n");
2547 igb_setup_dca(adapter);
2548 }
2549
2550#endif
2551#ifdef CONFIG_IGB_HWMON
2552 /* Initialize the thermal sensor on i350 devices. */
2553 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2554 u16 ets_word;
2555
2556 /* Read the NVM to determine if this i350 device supports an
2557 * external thermal sensor.
2558 */
2559 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2560 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2561 adapter->ets = true;
2562 else
2563 adapter->ets = false;
2564 if (igb_sysfs_init(adapter))
2565 dev_err(&pdev->dev,
2566 "failed to allocate sysfs resources\n");
2567 } else {
2568 adapter->ets = false;
2569 }
2570#endif
2571 /* Check if Media Autosense is enabled */
2572 adapter->ei = *ei;
2573 if (hw->dev_spec._82575.mas_capable)
2574 igb_init_mas(adapter);
2575
2576 /* do hw tstamp init after resetting */
2577 igb_ptp_init(adapter);
2578
2579 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2580 /* print bus type/speed/width info, not applicable to i354 */
2581 if (hw->mac.type != e1000_i354) {
2582 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2583 netdev->name,
2584 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2585 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2586 "unknown"),
2587 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2588 "Width x4" :
2589 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2590 "Width x2" :
2591 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2592 "Width x1" : "unknown"), netdev->dev_addr);
2593 }
2594
2595 if ((hw->mac.type >= e1000_i210 ||
2596 igb_get_flash_presence_i210(hw))) {
2597 ret_val = igb_read_part_string(hw, part_str,
2598 E1000_PBANUM_LENGTH);
2599 } else {
2600 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2601 }
2602
2603 if (ret_val)
2604 strcpy(part_str, "Unknown");
2605 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2606 dev_info(&pdev->dev,
2607 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2608 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
2609 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2610 adapter->num_rx_queues, adapter->num_tx_queues);
2611 if (hw->phy.media_type == e1000_media_type_copper) {
2612 switch (hw->mac.type) {
2613 case e1000_i350:
2614 case e1000_i210:
2615 case e1000_i211:
2616 /* Enable EEE for internal copper PHY devices */
2617 err = igb_set_eee_i350(hw, true, true);
2618 if ((!err) &&
2619 (!hw->dev_spec._82575.eee_disable)) {
2620 adapter->eee_advert =
2621 MDIO_EEE_100TX | MDIO_EEE_1000T;
2622 adapter->flags |= IGB_FLAG_EEE;
2623 }
2624 break;
2625 case e1000_i354:
2626 if ((rd32(E1000_CTRL_EXT) &
2627 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2628 err = igb_set_eee_i354(hw, true, true);
2629 if ((!err) &&
2630 (!hw->dev_spec._82575.eee_disable)) {
2631 adapter->eee_advert =
2632 MDIO_EEE_100TX | MDIO_EEE_1000T;
2633 adapter->flags |= IGB_FLAG_EEE;
2634 }
2635 }
2636 break;
2637 default:
2638 break;
2639 }
2640 }
2641 pm_runtime_put_noidle(&pdev->dev);
2642 return 0;
2643
2644err_register:
2645 igb_release_hw_control(adapter);
2646 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
2647err_eeprom:
2648 if (!igb_check_reset_block(hw))
2649 igb_reset_phy(hw);
2650
2651 if (hw->flash_address)
2652 iounmap(hw->flash_address);
2653err_sw_init:
2654 kfree(adapter->shadow_vfta);
2655 igb_clear_interrupt_scheme(adapter);
2656#ifdef CONFIG_PCI_IOV
2657 igb_disable_sriov(pdev);
2658#endif
2659 pci_iounmap(pdev, adapter->io_addr);
2660err_ioremap:
2661 free_netdev(netdev);
2662err_alloc_etherdev:
2663 pci_release_selected_regions(pdev,
2664 pci_select_bars(pdev, IORESOURCE_MEM));
2665err_pci_reg:
2666err_dma:
2667 pci_disable_device(pdev);
2668 return err;
2669}
2670
2671#ifdef CONFIG_PCI_IOV
2672static int igb_disable_sriov(struct pci_dev *pdev)
2673{
2674 struct net_device *netdev = pci_get_drvdata(pdev);
2675 struct igb_adapter *adapter = netdev_priv(netdev);
2676 struct e1000_hw *hw = &adapter->hw;
2677
2678 /* reclaim resources allocated to VFs */
2679 if (adapter->vf_data) {
2680 /* disable iov and allow time for transactions to clear */
2681 if (pci_vfs_assigned(pdev)) {
2682 dev_warn(&pdev->dev,
2683 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2684 return -EPERM;
2685 } else {
2686 pci_disable_sriov(pdev);
2687 msleep(500);
2688 }
2689
2690 kfree(adapter->vf_data);
2691 adapter->vf_data = NULL;
2692 adapter->vfs_allocated_count = 0;
2693 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2694 wrfl();
2695 msleep(100);
2696 dev_info(&pdev->dev, "IOV Disabled\n");
2697
2698 /* Re-enable DMA Coalescing flag since IOV is turned off */
2699 adapter->flags |= IGB_FLAG_DMAC;
2700 }
2701
2702 return 0;
2703}
2704
2705static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2706{
2707 struct net_device *netdev = pci_get_drvdata(pdev);
2708 struct igb_adapter *adapter = netdev_priv(netdev);
2709 int old_vfs = pci_num_vf(pdev);
2710 int err = 0;
2711 int i;
2712
2713 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
2714 err = -EPERM;
2715 goto out;
2716 }
2717 if (!num_vfs)
2718 goto out;
2719
2720 if (old_vfs) {
2721 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2722 old_vfs, max_vfs);
2723 adapter->vfs_allocated_count = old_vfs;
2724 } else
2725 adapter->vfs_allocated_count = num_vfs;
2726
2727 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2728 sizeof(struct vf_data_storage), GFP_KERNEL);
2729
2730 /* if allocation failed then we do not support SR-IOV */
2731 if (!adapter->vf_data) {
2732 adapter->vfs_allocated_count = 0;
2733 dev_err(&pdev->dev,
2734 "Unable to allocate memory for VF Data Storage\n");
2735 err = -ENOMEM;
2736 goto out;
2737 }
2738
2739 /* only call pci_enable_sriov() if no VFs are allocated already */
2740 if (!old_vfs) {
2741 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2742 if (err)
2743 goto err_out;
2744 }
2745 dev_info(&pdev->dev, "%d VFs allocated\n",
2746 adapter->vfs_allocated_count);
2747 for (i = 0; i < adapter->vfs_allocated_count; i++)
2748 igb_vf_configure(adapter, i);
2749
2750 /* DMA Coalescing is not supported in IOV mode. */
2751 adapter->flags &= ~IGB_FLAG_DMAC;
2752 goto out;
2753
2754err_out:
2755 kfree(adapter->vf_data);
2756 adapter->vf_data = NULL;
2757 adapter->vfs_allocated_count = 0;
2758out:
2759 return err;
2760}
2761
2762#endif
2763/**
2764 * igb_remove_i2c - Cleanup I2C interface
2765 * @adapter: pointer to adapter structure
2766 **/
2767static void igb_remove_i2c(struct igb_adapter *adapter)
2768{
2769 /* free the adapter bus structure */
2770 i2c_del_adapter(&adapter->i2c_adap);
2771}
2772
2773/**
2774 * igb_remove - Device Removal Routine
2775 * @pdev: PCI device information struct
2776 *
2777 * igb_remove is called by the PCI subsystem to alert the driver
2778 * that it should release a PCI device. The could be caused by a
2779 * Hot-Plug event, or because the driver is going to be removed from
2780 * memory.
2781 **/
2782static void igb_remove(struct pci_dev *pdev)
2783{
2784 struct net_device *netdev = pci_get_drvdata(pdev);
2785 struct igb_adapter *adapter = netdev_priv(netdev);
2786 struct e1000_hw *hw = &adapter->hw;
2787
2788 pm_runtime_get_noresume(&pdev->dev);
2789#ifdef CONFIG_IGB_HWMON
2790 igb_sysfs_exit(adapter);
2791#endif
2792 igb_remove_i2c(adapter);
2793 igb_ptp_stop(adapter);
2794 /* The watchdog timer may be rescheduled, so explicitly
2795 * disable watchdog from being rescheduled.
2796 */
2797 set_bit(__IGB_DOWN, &adapter->state);
2798 del_timer_sync(&adapter->watchdog_timer);
2799 del_timer_sync(&adapter->phy_info_timer);
2800
2801 cancel_work_sync(&adapter->reset_task);
2802 cancel_work_sync(&adapter->watchdog_task);
2803
2804#ifdef CONFIG_IGB_DCA
2805 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2806 dev_info(&pdev->dev, "DCA disabled\n");
2807 dca_remove_requester(&pdev->dev);
2808 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2809 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2810 }
2811#endif
2812
2813 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2814 * would have already happened in close and is redundant.
2815 */
2816 igb_release_hw_control(adapter);
2817
2818#ifdef CONFIG_PCI_IOV
2819 igb_disable_sriov(pdev);
2820#endif
2821
2822 unregister_netdev(netdev);
2823
2824 igb_clear_interrupt_scheme(adapter);
2825
2826 pci_iounmap(pdev, adapter->io_addr);
2827 if (hw->flash_address)
2828 iounmap(hw->flash_address);
2829 pci_release_selected_regions(pdev,
2830 pci_select_bars(pdev, IORESOURCE_MEM));
2831
2832 kfree(adapter->shadow_vfta);
2833 free_netdev(netdev);
2834
2835 pci_disable_pcie_error_reporting(pdev);
2836
2837 pci_disable_device(pdev);
2838}
2839
2840/**
2841 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2842 * @adapter: board private structure to initialize
2843 *
2844 * This function initializes the vf specific data storage and then attempts to
2845 * allocate the VFs. The reason for ordering it this way is because it is much
2846 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2847 * the memory for the VFs.
2848 **/
2849static void igb_probe_vfs(struct igb_adapter *adapter)
2850{
2851#ifdef CONFIG_PCI_IOV
2852 struct pci_dev *pdev = adapter->pdev;
2853 struct e1000_hw *hw = &adapter->hw;
2854
2855 /* Virtualization features not supported on i210 family. */
2856 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2857 return;
2858
2859 /* Of the below we really only want the effect of getting
2860 * IGB_FLAG_HAS_MSIX set (if available), without which
2861 * igb_enable_sriov() has no effect.
2862 */
2863 igb_set_interrupt_capability(adapter, true);
2864 igb_reset_interrupt_capability(adapter);
2865
2866 pci_sriov_set_totalvfs(pdev, 7);
2867 igb_enable_sriov(pdev, max_vfs);
2868
2869#endif /* CONFIG_PCI_IOV */
2870}
2871
2872static void igb_init_queue_configuration(struct igb_adapter *adapter)
2873{
2874 struct e1000_hw *hw = &adapter->hw;
2875 u32 max_rss_queues;
2876
2877 /* Determine the maximum number of RSS queues supported. */
2878 switch (hw->mac.type) {
2879 case e1000_i211:
2880 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2881 break;
2882 case e1000_82575:
2883 case e1000_i210:
2884 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2885 break;
2886 case e1000_i350:
2887 /* I350 cannot do RSS and SR-IOV at the same time */
2888 if (!!adapter->vfs_allocated_count) {
2889 max_rss_queues = 1;
2890 break;
2891 }
2892 /* fall through */
2893 case e1000_82576:
2894 if (!!adapter->vfs_allocated_count) {
2895 max_rss_queues = 2;
2896 break;
2897 }
2898 /* fall through */
2899 case e1000_82580:
2900 case e1000_i354:
2901 default:
2902 max_rss_queues = IGB_MAX_RX_QUEUES;
2903 break;
2904 }
2905
2906 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2907
2908 igb_set_flag_queue_pairs(adapter, max_rss_queues);
2909}
2910
2911void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
2912 const u32 max_rss_queues)
2913{
2914 struct e1000_hw *hw = &adapter->hw;
2915
2916 /* Determine if we need to pair queues. */
2917 switch (hw->mac.type) {
2918 case e1000_82575:
2919 case e1000_i211:
2920 /* Device supports enough interrupts without queue pairing. */
2921 break;
2922 case e1000_82576:
2923 case e1000_82580:
2924 case e1000_i350:
2925 case e1000_i354:
2926 case e1000_i210:
2927 default:
2928 /* If rss_queues > half of max_rss_queues, pair the queues in
2929 * order to conserve interrupts due to limited supply.
2930 */
2931 if (adapter->rss_queues > (max_rss_queues / 2))
2932 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2933 else
2934 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
2935 break;
2936 }
2937}
2938
2939/**
2940 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2941 * @adapter: board private structure to initialize
2942 *
2943 * igb_sw_init initializes the Adapter private data structure.
2944 * Fields are initialized based on PCI device information and
2945 * OS network device settings (MTU size).
2946 **/
2947static int igb_sw_init(struct igb_adapter *adapter)
2948{
2949 struct e1000_hw *hw = &adapter->hw;
2950 struct net_device *netdev = adapter->netdev;
2951 struct pci_dev *pdev = adapter->pdev;
2952
2953 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2954
2955 /* set default ring sizes */
2956 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2957 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2958
2959 /* set default ITR values */
2960 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2961 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2962
2963 /* set default work limits */
2964 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2965
2966 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2967 VLAN_HLEN;
2968 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2969
2970 spin_lock_init(&adapter->stats64_lock);
2971#ifdef CONFIG_PCI_IOV
2972 switch (hw->mac.type) {
2973 case e1000_82576:
2974 case e1000_i350:
2975 if (max_vfs > 7) {
2976 dev_warn(&pdev->dev,
2977 "Maximum of 7 VFs per PF, using max\n");
2978 max_vfs = adapter->vfs_allocated_count = 7;
2979 } else
2980 adapter->vfs_allocated_count = max_vfs;
2981 if (adapter->vfs_allocated_count)
2982 dev_warn(&pdev->dev,
2983 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2984 break;
2985 default:
2986 break;
2987 }
2988#endif /* CONFIG_PCI_IOV */
2989
2990 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
2991 adapter->flags |= IGB_FLAG_HAS_MSIX;
2992
2993 igb_probe_vfs(adapter);
2994
2995 igb_init_queue_configuration(adapter);
2996
2997 /* Setup and initialize a copy of the hw vlan table array */
2998 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2999 GFP_ATOMIC);
3000
3001 /* This call may decrease the number of queues */
3002 if (igb_init_interrupt_scheme(adapter, true)) {
3003 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3004 return -ENOMEM;
3005 }
3006
3007 /* Explicitly disable IRQ since the NIC can be in any state. */
3008 igb_irq_disable(adapter);
3009
3010 if (hw->mac.type >= e1000_i350)
3011 adapter->flags &= ~IGB_FLAG_DMAC;
3012
3013 set_bit(__IGB_DOWN, &adapter->state);
3014 return 0;
3015}
3016
3017/**
3018 * igb_open - Called when a network interface is made active
3019 * @netdev: network interface device structure
3020 *
3021 * Returns 0 on success, negative value on failure
3022 *
3023 * The open entry point is called when a network interface is made
3024 * active by the system (IFF_UP). At this point all resources needed
3025 * for transmit and receive operations are allocated, the interrupt
3026 * handler is registered with the OS, the watchdog timer is started,
3027 * and the stack is notified that the interface is ready.
3028 **/
3029static int __igb_open(struct net_device *netdev, bool resuming)
3030{
3031 struct igb_adapter *adapter = netdev_priv(netdev);
3032 struct e1000_hw *hw = &adapter->hw;
3033 struct pci_dev *pdev = adapter->pdev;
3034 int err;
3035 int i;
3036
3037 /* disallow open during test */
3038 if (test_bit(__IGB_TESTING, &adapter->state)) {
3039 WARN_ON(resuming);
3040 return -EBUSY;
3041 }
3042
3043 if (!resuming)
3044 pm_runtime_get_sync(&pdev->dev);
3045
3046 netif_carrier_off(netdev);
3047
3048 /* allocate transmit descriptors */
3049 err = igb_setup_all_tx_resources(adapter);
3050 if (err)
3051 goto err_setup_tx;
3052
3053 /* allocate receive descriptors */
3054 err = igb_setup_all_rx_resources(adapter);
3055 if (err)
3056 goto err_setup_rx;
3057
3058 igb_power_up_link(adapter);
3059
3060 /* before we allocate an interrupt, we must be ready to handle it.
3061 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3062 * as soon as we call pci_request_irq, so we have to setup our
3063 * clean_rx handler before we do so.
3064 */
3065 igb_configure(adapter);
3066
3067 err = igb_request_irq(adapter);
3068 if (err)
3069 goto err_req_irq;
3070
3071 /* Notify the stack of the actual queue counts. */
3072 err = netif_set_real_num_tx_queues(adapter->netdev,
3073 adapter->num_tx_queues);
3074 if (err)
3075 goto err_set_queues;
3076
3077 err = netif_set_real_num_rx_queues(adapter->netdev,
3078 adapter->num_rx_queues);
3079 if (err)
3080 goto err_set_queues;
3081
3082 /* From here on the code is the same as igb_up() */
3083 clear_bit(__IGB_DOWN, &adapter->state);
3084
3085 for (i = 0; i < adapter->num_q_vectors; i++)
3086 napi_enable(&(adapter->q_vector[i]->napi));
3087
3088 /* Clear any pending interrupts. */
3089 rd32(E1000_ICR);
3090
3091 igb_irq_enable(adapter);
3092
3093 /* notify VFs that reset has been completed */
3094 if (adapter->vfs_allocated_count) {
3095 u32 reg_data = rd32(E1000_CTRL_EXT);
3096
3097 reg_data |= E1000_CTRL_EXT_PFRSTD;
3098 wr32(E1000_CTRL_EXT, reg_data);
3099 }
3100
3101 netif_tx_start_all_queues(netdev);
3102
3103 if (!resuming)
3104 pm_runtime_put(&pdev->dev);
3105
3106 /* start the watchdog. */
3107 hw->mac.get_link_status = 1;
3108 schedule_work(&adapter->watchdog_task);
3109
3110 return 0;
3111
3112err_set_queues:
3113 igb_free_irq(adapter);
3114err_req_irq:
3115 igb_release_hw_control(adapter);
3116 igb_power_down_link(adapter);
3117 igb_free_all_rx_resources(adapter);
3118err_setup_rx:
3119 igb_free_all_tx_resources(adapter);
3120err_setup_tx:
3121 igb_reset(adapter);
3122 if (!resuming)
3123 pm_runtime_put(&pdev->dev);
3124
3125 return err;
3126}
3127
3128static int igb_open(struct net_device *netdev)
3129{
3130 return __igb_open(netdev, false);
3131}
3132
3133/**
3134 * igb_close - Disables a network interface
3135 * @netdev: network interface device structure
3136 *
3137 * Returns 0, this is not allowed to fail
3138 *
3139 * The close entry point is called when an interface is de-activated
3140 * by the OS. The hardware is still under the driver's control, but
3141 * needs to be disabled. A global MAC reset is issued to stop the
3142 * hardware, and all transmit and receive resources are freed.
3143 **/
3144static int __igb_close(struct net_device *netdev, bool suspending)
3145{
3146 struct igb_adapter *adapter = netdev_priv(netdev);
3147 struct pci_dev *pdev = adapter->pdev;
3148
3149 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3150
3151 if (!suspending)
3152 pm_runtime_get_sync(&pdev->dev);
3153
3154 igb_down(adapter);
3155 igb_free_irq(adapter);
3156
3157 igb_free_all_tx_resources(adapter);
3158 igb_free_all_rx_resources(adapter);
3159
3160 if (!suspending)
3161 pm_runtime_put_sync(&pdev->dev);
3162 return 0;
3163}
3164
3165static int igb_close(struct net_device *netdev)
3166{
3167 return __igb_close(netdev, false);
3168}
3169
3170/**
3171 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3172 * @tx_ring: tx descriptor ring (for a specific queue) to setup
3173 *
3174 * Return 0 on success, negative on failure
3175 **/
3176int igb_setup_tx_resources(struct igb_ring *tx_ring)
3177{
3178 struct device *dev = tx_ring->dev;
3179 int size;
3180
3181 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3182
3183 tx_ring->tx_buffer_info = vzalloc(size);
3184 if (!tx_ring->tx_buffer_info)
3185 goto err;
3186
3187 /* round up to nearest 4K */
3188 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
3189 tx_ring->size = ALIGN(tx_ring->size, 4096);
3190
3191 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3192 &tx_ring->dma, GFP_KERNEL);
3193 if (!tx_ring->desc)
3194 goto err;
3195
3196 tx_ring->next_to_use = 0;
3197 tx_ring->next_to_clean = 0;
3198
3199 return 0;
3200
3201err:
3202 vfree(tx_ring->tx_buffer_info);
3203 tx_ring->tx_buffer_info = NULL;
3204 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
3205 return -ENOMEM;
3206}
3207
3208/**
3209 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3210 * (Descriptors) for all queues
3211 * @adapter: board private structure
3212 *
3213 * Return 0 on success, negative on failure
3214 **/
3215static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3216{
3217 struct pci_dev *pdev = adapter->pdev;
3218 int i, err = 0;
3219
3220 for (i = 0; i < adapter->num_tx_queues; i++) {
3221 err = igb_setup_tx_resources(adapter->tx_ring[i]);
3222 if (err) {
3223 dev_err(&pdev->dev,
3224 "Allocation for Tx Queue %u failed\n", i);
3225 for (i--; i >= 0; i--)
3226 igb_free_tx_resources(adapter->tx_ring[i]);
3227 break;
3228 }
3229 }
3230
3231 return err;
3232}
3233
3234/**
3235 * igb_setup_tctl - configure the transmit control registers
3236 * @adapter: Board private structure
3237 **/
3238void igb_setup_tctl(struct igb_adapter *adapter)
3239{
3240 struct e1000_hw *hw = &adapter->hw;
3241 u32 tctl;
3242
3243 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3244 wr32(E1000_TXDCTL(0), 0);
3245
3246 /* Program the Transmit Control Register */
3247 tctl = rd32(E1000_TCTL);
3248 tctl &= ~E1000_TCTL_CT;
3249 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3250 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3251
3252 igb_config_collision_dist(hw);
3253
3254 /* Enable transmits */
3255 tctl |= E1000_TCTL_EN;
3256
3257 wr32(E1000_TCTL, tctl);
3258}
3259
3260/**
3261 * igb_configure_tx_ring - Configure transmit ring after Reset
3262 * @adapter: board private structure
3263 * @ring: tx ring to configure
3264 *
3265 * Configure a transmit ring after a reset.
3266 **/
3267void igb_configure_tx_ring(struct igb_adapter *adapter,
3268 struct igb_ring *ring)
3269{
3270 struct e1000_hw *hw = &adapter->hw;
3271 u32 txdctl = 0;
3272 u64 tdba = ring->dma;
3273 int reg_idx = ring->reg_idx;
3274
3275 /* disable the queue */
3276 wr32(E1000_TXDCTL(reg_idx), 0);
3277 wrfl();
3278 mdelay(10);
3279
3280 wr32(E1000_TDLEN(reg_idx),
3281 ring->count * sizeof(union e1000_adv_tx_desc));
3282 wr32(E1000_TDBAL(reg_idx),
3283 tdba & 0x00000000ffffffffULL);
3284 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3285
3286 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
3287 wr32(E1000_TDH(reg_idx), 0);
3288 writel(0, ring->tail);
3289
3290 txdctl |= IGB_TX_PTHRESH;
3291 txdctl |= IGB_TX_HTHRESH << 8;
3292 txdctl |= IGB_TX_WTHRESH << 16;
3293
3294 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3295 wr32(E1000_TXDCTL(reg_idx), txdctl);
3296}
3297
3298/**
3299 * igb_configure_tx - Configure transmit Unit after Reset
3300 * @adapter: board private structure
3301 *
3302 * Configure the Tx unit of the MAC after a reset.
3303 **/
3304static void igb_configure_tx(struct igb_adapter *adapter)
3305{
3306 int i;
3307
3308 for (i = 0; i < adapter->num_tx_queues; i++)
3309 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
3310}
3311
3312/**
3313 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3314 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
3315 *
3316 * Returns 0 on success, negative on failure
3317 **/
3318int igb_setup_rx_resources(struct igb_ring *rx_ring)
3319{
3320 struct device *dev = rx_ring->dev;
3321 int size;
3322
3323 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3324
3325 rx_ring->rx_buffer_info = vzalloc(size);
3326 if (!rx_ring->rx_buffer_info)
3327 goto err;
3328
3329 /* Round up to nearest 4K */
3330 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3331 rx_ring->size = ALIGN(rx_ring->size, 4096);
3332
3333 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3334 &rx_ring->dma, GFP_KERNEL);
3335 if (!rx_ring->desc)
3336 goto err;
3337
3338 rx_ring->next_to_alloc = 0;
3339 rx_ring->next_to_clean = 0;
3340 rx_ring->next_to_use = 0;
3341
3342 return 0;
3343
3344err:
3345 vfree(rx_ring->rx_buffer_info);
3346 rx_ring->rx_buffer_info = NULL;
3347 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3348 return -ENOMEM;
3349}
3350
3351/**
3352 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3353 * (Descriptors) for all queues
3354 * @adapter: board private structure
3355 *
3356 * Return 0 on success, negative on failure
3357 **/
3358static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3359{
3360 struct pci_dev *pdev = adapter->pdev;
3361 int i, err = 0;
3362
3363 for (i = 0; i < adapter->num_rx_queues; i++) {
3364 err = igb_setup_rx_resources(adapter->rx_ring[i]);
3365 if (err) {
3366 dev_err(&pdev->dev,
3367 "Allocation for Rx Queue %u failed\n", i);
3368 for (i--; i >= 0; i--)
3369 igb_free_rx_resources(adapter->rx_ring[i]);
3370 break;
3371 }
3372 }
3373
3374 return err;
3375}
3376
3377/**
3378 * igb_setup_mrqc - configure the multiple receive queue control registers
3379 * @adapter: Board private structure
3380 **/
3381static void igb_setup_mrqc(struct igb_adapter *adapter)
3382{
3383 struct e1000_hw *hw = &adapter->hw;
3384 u32 mrqc, rxcsum;
3385 u32 j, num_rx_queues;
3386 u32 rss_key[10];
3387
3388 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3389 for (j = 0; j < 10; j++)
3390 wr32(E1000_RSSRK(j), rss_key[j]);
3391
3392 num_rx_queues = adapter->rss_queues;
3393
3394 switch (hw->mac.type) {
3395 case e1000_82576:
3396 /* 82576 supports 2 RSS queues for SR-IOV */
3397 if (adapter->vfs_allocated_count)
3398 num_rx_queues = 2;
3399 break;
3400 default:
3401 break;
3402 }
3403
3404 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3405 for (j = 0; j < IGB_RETA_SIZE; j++)
3406 adapter->rss_indir_tbl[j] =
3407 (j * num_rx_queues) / IGB_RETA_SIZE;
3408 adapter->rss_indir_tbl_init = num_rx_queues;
3409 }
3410 igb_write_rss_indir_tbl(adapter);
3411
3412 /* Disable raw packet checksumming so that RSS hash is placed in
3413 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3414 * offloads as they are enabled by default
3415 */
3416 rxcsum = rd32(E1000_RXCSUM);
3417 rxcsum |= E1000_RXCSUM_PCSD;
3418
3419 if (adapter->hw.mac.type >= e1000_82576)
3420 /* Enable Receive Checksum Offload for SCTP */
3421 rxcsum |= E1000_RXCSUM_CRCOFL;
3422
3423 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3424 wr32(E1000_RXCSUM, rxcsum);
3425
3426 /* Generate RSS hash based on packet types, TCP/UDP
3427 * port numbers and/or IPv4/v6 src and dst addresses
3428 */
3429 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3430 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3431 E1000_MRQC_RSS_FIELD_IPV6 |
3432 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3433 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3434
3435 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3436 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3437 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3438 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3439
3440 /* If VMDq is enabled then we set the appropriate mode for that, else
3441 * we default to RSS so that an RSS hash is calculated per packet even
3442 * if we are only using one queue
3443 */
3444 if (adapter->vfs_allocated_count) {
3445 if (hw->mac.type > e1000_82575) {
3446 /* Set the default pool for the PF's first queue */
3447 u32 vtctl = rd32(E1000_VT_CTL);
3448
3449 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3450 E1000_VT_CTL_DISABLE_DEF_POOL);
3451 vtctl |= adapter->vfs_allocated_count <<
3452 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3453 wr32(E1000_VT_CTL, vtctl);
3454 }
3455 if (adapter->rss_queues > 1)
3456 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
3457 else
3458 mrqc |= E1000_MRQC_ENABLE_VMDQ;
3459 } else {
3460 if (hw->mac.type != e1000_i211)
3461 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
3462 }
3463 igb_vmm_control(adapter);
3464
3465 wr32(E1000_MRQC, mrqc);
3466}
3467
3468/**
3469 * igb_setup_rctl - configure the receive control registers
3470 * @adapter: Board private structure
3471 **/
3472void igb_setup_rctl(struct igb_adapter *adapter)
3473{
3474 struct e1000_hw *hw = &adapter->hw;
3475 u32 rctl;
3476
3477 rctl = rd32(E1000_RCTL);
3478
3479 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3480 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
3481
3482 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
3483 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3484
3485 /* enable stripping of CRC. It's unlikely this will break BMC
3486 * redirection as it did with e1000. Newer features require
3487 * that the HW strips the CRC.
3488 */
3489 rctl |= E1000_RCTL_SECRC;
3490
3491 /* disable store bad packets and clear size bits. */
3492 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
3493
3494 /* enable LPE to allow for reception of jumbo frames */
3495 rctl |= E1000_RCTL_LPE;
3496
3497 /* disable queue 0 to prevent tail write w/o re-config */
3498 wr32(E1000_RXDCTL(0), 0);
3499
3500 /* Attention!!! For SR-IOV PF driver operations you must enable
3501 * queue drop for all VF and PF queues to prevent head of line blocking
3502 * if an un-trusted VF does not provide descriptors to hardware.
3503 */
3504 if (adapter->vfs_allocated_count) {
3505 /* set all queue drop enable bits */
3506 wr32(E1000_QDE, ALL_QUEUES);
3507 }
3508
3509 /* This is useful for sniffing bad packets. */
3510 if (adapter->netdev->features & NETIF_F_RXALL) {
3511 /* UPE and MPE will be handled by normal PROMISC logic
3512 * in e1000e_set_rx_mode
3513 */
3514 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3515 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3516 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3517
3518 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3519 E1000_RCTL_DPF | /* Allow filtered pause */
3520 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3521 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3522 * and that breaks VLANs.
3523 */
3524 }
3525
3526 wr32(E1000_RCTL, rctl);
3527}
3528
3529static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3530 int vfn)
3531{
3532 struct e1000_hw *hw = &adapter->hw;
3533 u32 vmolr;
3534
3535 if (size > MAX_JUMBO_FRAME_SIZE)
3536 size = MAX_JUMBO_FRAME_SIZE;
3537
3538 vmolr = rd32(E1000_VMOLR(vfn));
3539 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3540 vmolr |= size | E1000_VMOLR_LPE;
3541 wr32(E1000_VMOLR(vfn), vmolr);
3542
3543 return 0;
3544}
3545
3546static inline void igb_set_vmolr(struct igb_adapter *adapter,
3547 int vfn, bool aupe)
3548{
3549 struct e1000_hw *hw = &adapter->hw;
3550 u32 vmolr;
3551
3552 /* This register exists only on 82576 and newer so if we are older then
3553 * we should exit and do nothing
3554 */
3555 if (hw->mac.type < e1000_82576)
3556 return;
3557
3558 vmolr = rd32(E1000_VMOLR(vfn));
3559 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3560 if (hw->mac.type == e1000_i350) {
3561 u32 dvmolr;
3562
3563 dvmolr = rd32(E1000_DVMOLR(vfn));
3564 dvmolr |= E1000_DVMOLR_STRVLAN;
3565 wr32(E1000_DVMOLR(vfn), dvmolr);
3566 }
3567 if (aupe)
3568 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3569 else
3570 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3571
3572 /* clear all bits that might not be set */
3573 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3574
3575 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3576 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3577 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
3578 * multicast packets
3579 */
3580 if (vfn <= adapter->vfs_allocated_count)
3581 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3582
3583 wr32(E1000_VMOLR(vfn), vmolr);
3584}
3585
3586/**
3587 * igb_configure_rx_ring - Configure a receive ring after Reset
3588 * @adapter: board private structure
3589 * @ring: receive ring to be configured
3590 *
3591 * Configure the Rx unit of the MAC after a reset.
3592 **/
3593void igb_configure_rx_ring(struct igb_adapter *adapter,
3594 struct igb_ring *ring)
3595{
3596 struct e1000_hw *hw = &adapter->hw;
3597 u64 rdba = ring->dma;
3598 int reg_idx = ring->reg_idx;
3599 u32 srrctl = 0, rxdctl = 0;
3600
3601 /* disable the queue */
3602 wr32(E1000_RXDCTL(reg_idx), 0);
3603
3604 /* Set DMA base address registers */
3605 wr32(E1000_RDBAL(reg_idx),
3606 rdba & 0x00000000ffffffffULL);
3607 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3608 wr32(E1000_RDLEN(reg_idx),
3609 ring->count * sizeof(union e1000_adv_rx_desc));
3610
3611 /* initialize head and tail */
3612 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3613 wr32(E1000_RDH(reg_idx), 0);
3614 writel(0, ring->tail);
3615
3616 /* set descriptor configuration */
3617 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3618 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3619 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3620 if (hw->mac.type >= e1000_82580)
3621 srrctl |= E1000_SRRCTL_TIMESTAMP;
3622 /* Only set Drop Enable if we are supporting multiple queues */
3623 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3624 srrctl |= E1000_SRRCTL_DROP_EN;
3625
3626 wr32(E1000_SRRCTL(reg_idx), srrctl);
3627
3628 /* set filtering for VMDQ pools */
3629 igb_set_vmolr(adapter, reg_idx & 0x7, true);
3630
3631 rxdctl |= IGB_RX_PTHRESH;
3632 rxdctl |= IGB_RX_HTHRESH << 8;
3633 rxdctl |= IGB_RX_WTHRESH << 16;
3634
3635 /* enable receive descriptor fetching */
3636 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3637 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3638}
3639
3640/**
3641 * igb_configure_rx - Configure receive Unit after Reset
3642 * @adapter: board private structure
3643 *
3644 * Configure the Rx unit of the MAC after a reset.
3645 **/
3646static void igb_configure_rx(struct igb_adapter *adapter)
3647{
3648 int i;
3649
3650 /* set UTA to appropriate mode */
3651 igb_set_uta(adapter);
3652
3653 /* set the correct pool for the PF default MAC address in entry 0 */
3654 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3655 adapter->vfs_allocated_count);
3656
3657 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3658 * the Base and Length of the Rx Descriptor Ring
3659 */
3660 for (i = 0; i < adapter->num_rx_queues; i++)
3661 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3662}
3663
3664/**
3665 * igb_free_tx_resources - Free Tx Resources per Queue
3666 * @tx_ring: Tx descriptor ring for a specific queue
3667 *
3668 * Free all transmit software resources
3669 **/
3670void igb_free_tx_resources(struct igb_ring *tx_ring)
3671{
3672 igb_clean_tx_ring(tx_ring);
3673
3674 vfree(tx_ring->tx_buffer_info);
3675 tx_ring->tx_buffer_info = NULL;
3676
3677 /* if not set, then don't free */
3678 if (!tx_ring->desc)
3679 return;
3680
3681 dma_free_coherent(tx_ring->dev, tx_ring->size,
3682 tx_ring->desc, tx_ring->dma);
3683
3684 tx_ring->desc = NULL;
3685}
3686
3687/**
3688 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3689 * @adapter: board private structure
3690 *
3691 * Free all transmit software resources
3692 **/
3693static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3694{
3695 int i;
3696
3697 for (i = 0; i < adapter->num_tx_queues; i++)
3698 if (adapter->tx_ring[i])
3699 igb_free_tx_resources(adapter->tx_ring[i]);
3700}
3701
3702void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3703 struct igb_tx_buffer *tx_buffer)
3704{
3705 if (tx_buffer->skb) {
3706 dev_kfree_skb_any(tx_buffer->skb);
3707 if (dma_unmap_len(tx_buffer, len))
3708 dma_unmap_single(ring->dev,
3709 dma_unmap_addr(tx_buffer, dma),
3710 dma_unmap_len(tx_buffer, len),
3711 DMA_TO_DEVICE);
3712 } else if (dma_unmap_len(tx_buffer, len)) {
3713 dma_unmap_page(ring->dev,
3714 dma_unmap_addr(tx_buffer, dma),
3715 dma_unmap_len(tx_buffer, len),
3716 DMA_TO_DEVICE);
3717 }
3718 tx_buffer->next_to_watch = NULL;
3719 tx_buffer->skb = NULL;
3720 dma_unmap_len_set(tx_buffer, len, 0);
3721 /* buffer_info must be completely set up in the transmit path */
3722}
3723
3724/**
3725 * igb_clean_tx_ring - Free Tx Buffers
3726 * @tx_ring: ring to be cleaned
3727 **/
3728static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3729{
3730 struct igb_tx_buffer *buffer_info;
3731 unsigned long size;
3732 u16 i;
3733
3734 if (!tx_ring->tx_buffer_info)
3735 return;
3736 /* Free all the Tx ring sk_buffs */
3737
3738 for (i = 0; i < tx_ring->count; i++) {
3739 buffer_info = &tx_ring->tx_buffer_info[i];
3740 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3741 }
3742
3743 netdev_tx_reset_queue(txring_txq(tx_ring));
3744
3745 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3746 memset(tx_ring->tx_buffer_info, 0, size);
3747
3748 /* Zero out the descriptor ring */
3749 memset(tx_ring->desc, 0, tx_ring->size);
3750
3751 tx_ring->next_to_use = 0;
3752 tx_ring->next_to_clean = 0;
3753}
3754
3755/**
3756 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3757 * @adapter: board private structure
3758 **/
3759static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3760{
3761 int i;
3762
3763 for (i = 0; i < adapter->num_tx_queues; i++)
3764 if (adapter->tx_ring[i])
3765 igb_clean_tx_ring(adapter->tx_ring[i]);
3766}
3767
3768/**
3769 * igb_free_rx_resources - Free Rx Resources
3770 * @rx_ring: ring to clean the resources from
3771 *
3772 * Free all receive software resources
3773 **/
3774void igb_free_rx_resources(struct igb_ring *rx_ring)
3775{
3776 igb_clean_rx_ring(rx_ring);
3777
3778 vfree(rx_ring->rx_buffer_info);
3779 rx_ring->rx_buffer_info = NULL;
3780
3781 /* if not set, then don't free */
3782 if (!rx_ring->desc)
3783 return;
3784
3785 dma_free_coherent(rx_ring->dev, rx_ring->size,
3786 rx_ring->desc, rx_ring->dma);
3787
3788 rx_ring->desc = NULL;
3789}
3790
3791/**
3792 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3793 * @adapter: board private structure
3794 *
3795 * Free all receive software resources
3796 **/
3797static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3798{
3799 int i;
3800
3801 for (i = 0; i < adapter->num_rx_queues; i++)
3802 if (adapter->rx_ring[i])
3803 igb_free_rx_resources(adapter->rx_ring[i]);
3804}
3805
3806/**
3807 * igb_clean_rx_ring - Free Rx Buffers per Queue
3808 * @rx_ring: ring to free buffers from
3809 **/
3810static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3811{
3812 unsigned long size;
3813 u16 i;
3814
3815 if (rx_ring->skb)
3816 dev_kfree_skb(rx_ring->skb);
3817 rx_ring->skb = NULL;
3818
3819 if (!rx_ring->rx_buffer_info)
3820 return;
3821
3822 /* Free all the Rx ring sk_buffs */
3823 for (i = 0; i < rx_ring->count; i++) {
3824 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3825
3826 if (!buffer_info->page)
3827 continue;
3828
3829 dma_unmap_page(rx_ring->dev,
3830 buffer_info->dma,
3831 PAGE_SIZE,
3832 DMA_FROM_DEVICE);
3833 __free_page(buffer_info->page);
3834
3835 buffer_info->page = NULL;
3836 }
3837
3838 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3839 memset(rx_ring->rx_buffer_info, 0, size);
3840
3841 /* Zero out the descriptor ring */
3842 memset(rx_ring->desc, 0, rx_ring->size);
3843
3844 rx_ring->next_to_alloc = 0;
3845 rx_ring->next_to_clean = 0;
3846 rx_ring->next_to_use = 0;
3847}
3848
3849/**
3850 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3851 * @adapter: board private structure
3852 **/
3853static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3854{
3855 int i;
3856
3857 for (i = 0; i < adapter->num_rx_queues; i++)
3858 if (adapter->rx_ring[i])
3859 igb_clean_rx_ring(adapter->rx_ring[i]);
3860}
3861
3862/**
3863 * igb_set_mac - Change the Ethernet Address of the NIC
3864 * @netdev: network interface device structure
3865 * @p: pointer to an address structure
3866 *
3867 * Returns 0 on success, negative on failure
3868 **/
3869static int igb_set_mac(struct net_device *netdev, void *p)
3870{
3871 struct igb_adapter *adapter = netdev_priv(netdev);
3872 struct e1000_hw *hw = &adapter->hw;
3873 struct sockaddr *addr = p;
3874
3875 if (!is_valid_ether_addr(addr->sa_data))
3876 return -EADDRNOTAVAIL;
3877
3878 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3879 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3880
3881 /* set the correct pool for the new PF MAC address in entry 0 */
3882 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3883 adapter->vfs_allocated_count);
3884
3885 return 0;
3886}
3887
3888/**
3889 * igb_write_mc_addr_list - write multicast addresses to MTA
3890 * @netdev: network interface device structure
3891 *
3892 * Writes multicast address list to the MTA hash table.
3893 * Returns: -ENOMEM on failure
3894 * 0 on no addresses written
3895 * X on writing X addresses to MTA
3896 **/
3897static int igb_write_mc_addr_list(struct net_device *netdev)
3898{
3899 struct igb_adapter *adapter = netdev_priv(netdev);
3900 struct e1000_hw *hw = &adapter->hw;
3901 struct netdev_hw_addr *ha;
3902 u8 *mta_list;
3903 int i;
3904
3905 if (netdev_mc_empty(netdev)) {
3906 /* nothing to program, so clear mc list */
3907 igb_update_mc_addr_list(hw, NULL, 0);
3908 igb_restore_vf_multicasts(adapter);
3909 return 0;
3910 }
3911
3912 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3913 if (!mta_list)
3914 return -ENOMEM;
3915
3916 /* The shared function expects a packed array of only addresses. */
3917 i = 0;
3918 netdev_for_each_mc_addr(ha, netdev)
3919 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3920
3921 igb_update_mc_addr_list(hw, mta_list, i);
3922 kfree(mta_list);
3923
3924 return netdev_mc_count(netdev);
3925}
3926
3927/**
3928 * igb_write_uc_addr_list - write unicast addresses to RAR table
3929 * @netdev: network interface device structure
3930 *
3931 * Writes unicast address list to the RAR table.
3932 * Returns: -ENOMEM on failure/insufficient address space
3933 * 0 on no addresses written
3934 * X on writing X addresses to the RAR table
3935 **/
3936static int igb_write_uc_addr_list(struct net_device *netdev)
3937{
3938 struct igb_adapter *adapter = netdev_priv(netdev);
3939 struct e1000_hw *hw = &adapter->hw;
3940 unsigned int vfn = adapter->vfs_allocated_count;
3941 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3942 int count = 0;
3943
3944 /* return ENOMEM indicating insufficient memory for addresses */
3945 if (netdev_uc_count(netdev) > rar_entries)
3946 return -ENOMEM;
3947
3948 if (!netdev_uc_empty(netdev) && rar_entries) {
3949 struct netdev_hw_addr *ha;
3950
3951 netdev_for_each_uc_addr(ha, netdev) {
3952 if (!rar_entries)
3953 break;
3954 igb_rar_set_qsel(adapter, ha->addr,
3955 rar_entries--,
3956 vfn);
3957 count++;
3958 }
3959 }
3960 /* write the addresses in reverse order to avoid write combining */
3961 for (; rar_entries > 0 ; rar_entries--) {
3962 wr32(E1000_RAH(rar_entries), 0);
3963 wr32(E1000_RAL(rar_entries), 0);
3964 }
3965 wrfl();
3966
3967 return count;
3968}
3969
3970/**
3971 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3972 * @netdev: network interface device structure
3973 *
3974 * The set_rx_mode entry point is called whenever the unicast or multicast
3975 * address lists or the network interface flags are updated. This routine is
3976 * responsible for configuring the hardware for proper unicast, multicast,
3977 * promiscuous mode, and all-multi behavior.
3978 **/
3979static void igb_set_rx_mode(struct net_device *netdev)
3980{
3981 struct igb_adapter *adapter = netdev_priv(netdev);
3982 struct e1000_hw *hw = &adapter->hw;
3983 unsigned int vfn = adapter->vfs_allocated_count;
3984 u32 rctl, vmolr = 0;
3985 int count;
3986
3987 /* Check for Promiscuous and All Multicast modes */
3988 rctl = rd32(E1000_RCTL);
3989
3990 /* clear the effected bits */
3991 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3992
3993 if (netdev->flags & IFF_PROMISC) {
3994 /* retain VLAN HW filtering if in VT mode */
3995 if (adapter->vfs_allocated_count)
3996 rctl |= E1000_RCTL_VFE;
3997 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3998 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3999 } else {
4000 if (netdev->flags & IFF_ALLMULTI) {
4001 rctl |= E1000_RCTL_MPE;
4002 vmolr |= E1000_VMOLR_MPME;
4003 } else {
4004 /* Write addresses to the MTA, if the attempt fails
4005 * then we should just turn on promiscuous mode so
4006 * that we can at least receive multicast traffic
4007 */
4008 count = igb_write_mc_addr_list(netdev);
4009 if (count < 0) {
4010 rctl |= E1000_RCTL_MPE;
4011 vmolr |= E1000_VMOLR_MPME;
4012 } else if (count) {
4013 vmolr |= E1000_VMOLR_ROMPE;
4014 }
4015 }
4016 /* Write addresses to available RAR registers, if there is not
4017 * sufficient space to store all the addresses then enable
4018 * unicast promiscuous mode
4019 */
4020 count = igb_write_uc_addr_list(netdev);
4021 if (count < 0) {
4022 rctl |= E1000_RCTL_UPE;
4023 vmolr |= E1000_VMOLR_ROPE;
4024 }
4025 rctl |= E1000_RCTL_VFE;
4026 }
4027 wr32(E1000_RCTL, rctl);
4028
4029 /* In order to support SR-IOV and eventually VMDq it is necessary to set
4030 * the VMOLR to enable the appropriate modes. Without this workaround
4031 * we will have issues with VLAN tag stripping not being done for frames
4032 * that are only arriving because we are the default pool
4033 */
4034 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
4035 return;
4036
4037 vmolr |= rd32(E1000_VMOLR(vfn)) &
4038 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
4039
4040 /* enable Rx jumbo frames, no need for restriction */
4041 vmolr &= ~E1000_VMOLR_RLPML_MASK;
4042 vmolr |= MAX_JUMBO_FRAME_SIZE | E1000_VMOLR_LPE;
4043
4044 wr32(E1000_VMOLR(vfn), vmolr);
4045 wr32(E1000_RLPML, MAX_JUMBO_FRAME_SIZE);
4046
4047 igb_restore_vf_multicasts(adapter);
4048}
4049
4050static void igb_check_wvbr(struct igb_adapter *adapter)
4051{
4052 struct e1000_hw *hw = &adapter->hw;
4053 u32 wvbr = 0;
4054
4055 switch (hw->mac.type) {
4056 case e1000_82576:
4057 case e1000_i350:
4058 wvbr = rd32(E1000_WVBR);
4059 if (!wvbr)
4060 return;
4061 break;
4062 default:
4063 break;
4064 }
4065
4066 adapter->wvbr |= wvbr;
4067}
4068
4069#define IGB_STAGGERED_QUEUE_OFFSET 8
4070
4071static void igb_spoof_check(struct igb_adapter *adapter)
4072{
4073 int j;
4074
4075 if (!adapter->wvbr)
4076 return;
4077
4078 for (j = 0; j < adapter->vfs_allocated_count; j++) {
4079 if (adapter->wvbr & (1 << j) ||
4080 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4081 dev_warn(&adapter->pdev->dev,
4082 "Spoof event(s) detected on VF %d\n", j);
4083 adapter->wvbr &=
4084 ~((1 << j) |
4085 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4086 }
4087 }
4088}
4089
4090/* Need to wait a few seconds after link up to get diagnostic information from
4091 * the phy
4092 */
4093static void igb_update_phy_info(unsigned long data)
4094{
4095 struct igb_adapter *adapter = (struct igb_adapter *) data;
4096 igb_get_phy_info(&adapter->hw);
4097}
4098
4099/**
4100 * igb_has_link - check shared code for link and determine up/down
4101 * @adapter: pointer to driver private info
4102 **/
4103bool igb_has_link(struct igb_adapter *adapter)
4104{
4105 struct e1000_hw *hw = &adapter->hw;
4106 bool link_active = false;
4107
4108 /* get_link_status is set on LSC (link status) interrupt or
4109 * rx sequence error interrupt. get_link_status will stay
4110 * false until the e1000_check_for_link establishes link
4111 * for copper adapters ONLY
4112 */
4113 switch (hw->phy.media_type) {
4114 case e1000_media_type_copper:
4115 if (!hw->mac.get_link_status)
4116 return true;
4117 case e1000_media_type_internal_serdes:
4118 hw->mac.ops.check_for_link(hw);
4119 link_active = !hw->mac.get_link_status;
4120 break;
4121 default:
4122 case e1000_media_type_unknown:
4123 break;
4124 }
4125
4126 if (((hw->mac.type == e1000_i210) ||
4127 (hw->mac.type == e1000_i211)) &&
4128 (hw->phy.id == I210_I_PHY_ID)) {
4129 if (!netif_carrier_ok(adapter->netdev)) {
4130 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4131 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4132 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4133 adapter->link_check_timeout = jiffies;
4134 }
4135 }
4136
4137 return link_active;
4138}
4139
4140static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4141{
4142 bool ret = false;
4143 u32 ctrl_ext, thstat;
4144
4145 /* check for thermal sensor event on i350 copper only */
4146 if (hw->mac.type == e1000_i350) {
4147 thstat = rd32(E1000_THSTAT);
4148 ctrl_ext = rd32(E1000_CTRL_EXT);
4149
4150 if ((hw->phy.media_type == e1000_media_type_copper) &&
4151 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
4152 ret = !!(thstat & event);
4153 }
4154
4155 return ret;
4156}
4157
4158/**
4159 * igb_check_lvmmc - check for malformed packets received
4160 * and indicated in LVMMC register
4161 * @adapter: pointer to adapter
4162 **/
4163static void igb_check_lvmmc(struct igb_adapter *adapter)
4164{
4165 struct e1000_hw *hw = &adapter->hw;
4166 u32 lvmmc;
4167
4168 lvmmc = rd32(E1000_LVMMC);
4169 if (lvmmc) {
4170 if (unlikely(net_ratelimit())) {
4171 netdev_warn(adapter->netdev,
4172 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4173 lvmmc);
4174 }
4175 }
4176}
4177
4178/**
4179 * igb_watchdog - Timer Call-back
4180 * @data: pointer to adapter cast into an unsigned long
4181 **/
4182static void igb_watchdog(unsigned long data)
4183{
4184 struct igb_adapter *adapter = (struct igb_adapter *)data;
4185 /* Do the rest outside of interrupt context */
4186 schedule_work(&adapter->watchdog_task);
4187}
4188
4189static void igb_watchdog_task(struct work_struct *work)
4190{
4191 struct igb_adapter *adapter = container_of(work,
4192 struct igb_adapter,
4193 watchdog_task);
4194 struct e1000_hw *hw = &adapter->hw;
4195 struct e1000_phy_info *phy = &hw->phy;
4196 struct net_device *netdev = adapter->netdev;
4197 u32 link;
4198 int i;
4199 u32 connsw;
4200
4201 link = igb_has_link(adapter);
4202
4203 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4204 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4205 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4206 else
4207 link = false;
4208 }
4209
4210 /* Force link down if we have fiber to swap to */
4211 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4212 if (hw->phy.media_type == e1000_media_type_copper) {
4213 connsw = rd32(E1000_CONNSW);
4214 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4215 link = 0;
4216 }
4217 }
4218 if (link) {
4219 /* Perform a reset if the media type changed. */
4220 if (hw->dev_spec._82575.media_changed) {
4221 hw->dev_spec._82575.media_changed = false;
4222 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4223 igb_reset(adapter);
4224 }
4225 /* Cancel scheduled suspend requests. */
4226 pm_runtime_resume(netdev->dev.parent);
4227
4228 if (!netif_carrier_ok(netdev)) {
4229 u32 ctrl;
4230
4231 hw->mac.ops.get_speed_and_duplex(hw,
4232 &adapter->link_speed,
4233 &adapter->link_duplex);
4234
4235 ctrl = rd32(E1000_CTRL);
4236 /* Links status message must follow this format */
4237 netdev_info(netdev,
4238 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4239 netdev->name,
4240 adapter->link_speed,
4241 adapter->link_duplex == FULL_DUPLEX ?
4242 "Full" : "Half",
4243 (ctrl & E1000_CTRL_TFCE) &&
4244 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4245 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4246 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
4247
4248 /* disable EEE if enabled */
4249 if ((adapter->flags & IGB_FLAG_EEE) &&
4250 (adapter->link_duplex == HALF_DUPLEX)) {
4251 dev_info(&adapter->pdev->dev,
4252 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4253 adapter->hw.dev_spec._82575.eee_disable = true;
4254 adapter->flags &= ~IGB_FLAG_EEE;
4255 }
4256
4257 /* check if SmartSpeed worked */
4258 igb_check_downshift(hw);
4259 if (phy->speed_downgraded)
4260 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4261
4262 /* check for thermal sensor event */
4263 if (igb_thermal_sensor_event(hw,
4264 E1000_THSTAT_LINK_THROTTLE))
4265 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
4266
4267 /* adjust timeout factor according to speed/duplex */
4268 adapter->tx_timeout_factor = 1;
4269 switch (adapter->link_speed) {
4270 case SPEED_10:
4271 adapter->tx_timeout_factor = 14;
4272 break;
4273 case SPEED_100:
4274 /* maybe add some timeout factor ? */
4275 break;
4276 }
4277
4278 netif_carrier_on(netdev);
4279
4280 igb_ping_all_vfs(adapter);
4281 igb_check_vf_rate_limit(adapter);
4282
4283 /* link state has changed, schedule phy info update */
4284 if (!test_bit(__IGB_DOWN, &adapter->state))
4285 mod_timer(&adapter->phy_info_timer,
4286 round_jiffies(jiffies + 2 * HZ));
4287 }
4288 } else {
4289 if (netif_carrier_ok(netdev)) {
4290 adapter->link_speed = 0;
4291 adapter->link_duplex = 0;
4292
4293 /* check for thermal sensor event */
4294 if (igb_thermal_sensor_event(hw,
4295 E1000_THSTAT_PWR_DOWN)) {
4296 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
4297 }
4298
4299 /* Links status message must follow this format */
4300 netdev_info(netdev, "igb: %s NIC Link is Down\n",
4301 netdev->name);
4302 netif_carrier_off(netdev);
4303
4304 igb_ping_all_vfs(adapter);
4305
4306 /* link state has changed, schedule phy info update */
4307 if (!test_bit(__IGB_DOWN, &adapter->state))
4308 mod_timer(&adapter->phy_info_timer,
4309 round_jiffies(jiffies + 2 * HZ));
4310
4311 /* link is down, time to check for alternate media */
4312 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4313 igb_check_swap_media(adapter);
4314 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4315 schedule_work(&adapter->reset_task);
4316 /* return immediately */
4317 return;
4318 }
4319 }
4320 pm_schedule_suspend(netdev->dev.parent,
4321 MSEC_PER_SEC * 5);
4322
4323 /* also check for alternate media here */
4324 } else if (!netif_carrier_ok(netdev) &&
4325 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4326 igb_check_swap_media(adapter);
4327 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4328 schedule_work(&adapter->reset_task);
4329 /* return immediately */
4330 return;
4331 }
4332 }
4333 }
4334
4335 spin_lock(&adapter->stats64_lock);
4336 igb_update_stats(adapter, &adapter->stats64);
4337 spin_unlock(&adapter->stats64_lock);
4338
4339 for (i = 0; i < adapter->num_tx_queues; i++) {
4340 struct igb_ring *tx_ring = adapter->tx_ring[i];
4341 if (!netif_carrier_ok(netdev)) {
4342 /* We've lost link, so the controller stops DMA,
4343 * but we've got queued Tx work that's never going
4344 * to get done, so reset controller to flush Tx.
4345 * (Do the reset outside of interrupt context).
4346 */
4347 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4348 adapter->tx_timeout_count++;
4349 schedule_work(&adapter->reset_task);
4350 /* return immediately since reset is imminent */
4351 return;
4352 }
4353 }
4354
4355 /* Force detection of hung controller every watchdog period */
4356 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
4357 }
4358
4359 /* Cause software interrupt to ensure Rx ring is cleaned */
4360 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
4361 u32 eics = 0;
4362
4363 for (i = 0; i < adapter->num_q_vectors; i++)
4364 eics |= adapter->q_vector[i]->eims_value;
4365 wr32(E1000_EICS, eics);
4366 } else {
4367 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4368 }
4369
4370 igb_spoof_check(adapter);
4371 igb_ptp_rx_hang(adapter);
4372
4373 /* Check LVMMC register on i350/i354 only */
4374 if ((adapter->hw.mac.type == e1000_i350) ||
4375 (adapter->hw.mac.type == e1000_i354))
4376 igb_check_lvmmc(adapter);
4377
4378 /* Reset the timer */
4379 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4380 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4381 mod_timer(&adapter->watchdog_timer,
4382 round_jiffies(jiffies + HZ));
4383 else
4384 mod_timer(&adapter->watchdog_timer,
4385 round_jiffies(jiffies + 2 * HZ));
4386 }
4387}
4388
4389enum latency_range {
4390 lowest_latency = 0,
4391 low_latency = 1,
4392 bulk_latency = 2,
4393 latency_invalid = 255
4394};
4395
4396/**
4397 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4398 * @q_vector: pointer to q_vector
4399 *
4400 * Stores a new ITR value based on strictly on packet size. This
4401 * algorithm is less sophisticated than that used in igb_update_itr,
4402 * due to the difficulty of synchronizing statistics across multiple
4403 * receive rings. The divisors and thresholds used by this function
4404 * were determined based on theoretical maximum wire speed and testing
4405 * data, in order to minimize response time while increasing bulk
4406 * throughput.
4407 * This functionality is controlled by ethtool's coalescing settings.
4408 * NOTE: This function is called only when operating in a multiqueue
4409 * receive environment.
4410 **/
4411static void igb_update_ring_itr(struct igb_q_vector *q_vector)
4412{
4413 int new_val = q_vector->itr_val;
4414 int avg_wire_size = 0;
4415 struct igb_adapter *adapter = q_vector->adapter;
4416 unsigned int packets;
4417
4418 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4419 * ints/sec - ITR timer value of 120 ticks.
4420 */
4421 if (adapter->link_speed != SPEED_1000) {
4422 new_val = IGB_4K_ITR;
4423 goto set_itr_val;
4424 }
4425
4426 packets = q_vector->rx.total_packets;
4427 if (packets)
4428 avg_wire_size = q_vector->rx.total_bytes / packets;
4429
4430 packets = q_vector->tx.total_packets;
4431 if (packets)
4432 avg_wire_size = max_t(u32, avg_wire_size,
4433 q_vector->tx.total_bytes / packets);
4434
4435 /* if avg_wire_size isn't set no work was done */
4436 if (!avg_wire_size)
4437 goto clear_counts;
4438
4439 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4440 avg_wire_size += 24;
4441
4442 /* Don't starve jumbo frames */
4443 avg_wire_size = min(avg_wire_size, 3000);
4444
4445 /* Give a little boost to mid-size frames */
4446 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4447 new_val = avg_wire_size / 3;
4448 else
4449 new_val = avg_wire_size / 2;
4450
4451 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4452 if (new_val < IGB_20K_ITR &&
4453 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4454 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4455 new_val = IGB_20K_ITR;
4456
4457set_itr_val:
4458 if (new_val != q_vector->itr_val) {
4459 q_vector->itr_val = new_val;
4460 q_vector->set_itr = 1;
4461 }
4462clear_counts:
4463 q_vector->rx.total_bytes = 0;
4464 q_vector->rx.total_packets = 0;
4465 q_vector->tx.total_bytes = 0;
4466 q_vector->tx.total_packets = 0;
4467}
4468
4469/**
4470 * igb_update_itr - update the dynamic ITR value based on statistics
4471 * @q_vector: pointer to q_vector
4472 * @ring_container: ring info to update the itr for
4473 *
4474 * Stores a new ITR value based on packets and byte
4475 * counts during the last interrupt. The advantage of per interrupt
4476 * computation is faster updates and more accurate ITR for the current
4477 * traffic pattern. Constants in this function were computed
4478 * based on theoretical maximum wire speed and thresholds were set based
4479 * on testing data as well as attempting to minimize response time
4480 * while increasing bulk throughput.
4481 * This functionality is controlled by ethtool's coalescing settings.
4482 * NOTE: These calculations are only valid when operating in a single-
4483 * queue environment.
4484 **/
4485static void igb_update_itr(struct igb_q_vector *q_vector,
4486 struct igb_ring_container *ring_container)
4487{
4488 unsigned int packets = ring_container->total_packets;
4489 unsigned int bytes = ring_container->total_bytes;
4490 u8 itrval = ring_container->itr;
4491
4492 /* no packets, exit with status unchanged */
4493 if (packets == 0)
4494 return;
4495
4496 switch (itrval) {
4497 case lowest_latency:
4498 /* handle TSO and jumbo frames */
4499 if (bytes/packets > 8000)
4500 itrval = bulk_latency;
4501 else if ((packets < 5) && (bytes > 512))
4502 itrval = low_latency;
4503 break;
4504 case low_latency: /* 50 usec aka 20000 ints/s */
4505 if (bytes > 10000) {
4506 /* this if handles the TSO accounting */
4507 if (bytes/packets > 8000)
4508 itrval = bulk_latency;
4509 else if ((packets < 10) || ((bytes/packets) > 1200))
4510 itrval = bulk_latency;
4511 else if ((packets > 35))
4512 itrval = lowest_latency;
4513 } else if (bytes/packets > 2000) {
4514 itrval = bulk_latency;
4515 } else if (packets <= 2 && bytes < 512) {
4516 itrval = lowest_latency;
4517 }
4518 break;
4519 case bulk_latency: /* 250 usec aka 4000 ints/s */
4520 if (bytes > 25000) {
4521 if (packets > 35)
4522 itrval = low_latency;
4523 } else if (bytes < 1500) {
4524 itrval = low_latency;
4525 }
4526 break;
4527 }
4528
4529 /* clear work counters since we have the values we need */
4530 ring_container->total_bytes = 0;
4531 ring_container->total_packets = 0;
4532
4533 /* write updated itr to ring container */
4534 ring_container->itr = itrval;
4535}
4536
4537static void igb_set_itr(struct igb_q_vector *q_vector)
4538{
4539 struct igb_adapter *adapter = q_vector->adapter;
4540 u32 new_itr = q_vector->itr_val;
4541 u8 current_itr = 0;
4542
4543 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4544 if (adapter->link_speed != SPEED_1000) {
4545 current_itr = 0;
4546 new_itr = IGB_4K_ITR;
4547 goto set_itr_now;
4548 }
4549
4550 igb_update_itr(q_vector, &q_vector->tx);
4551 igb_update_itr(q_vector, &q_vector->rx);
4552
4553 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4554
4555 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4556 if (current_itr == lowest_latency &&
4557 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4558 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4559 current_itr = low_latency;
4560
4561 switch (current_itr) {
4562 /* counts and packets in update_itr are dependent on these numbers */
4563 case lowest_latency:
4564 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
4565 break;
4566 case low_latency:
4567 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
4568 break;
4569 case bulk_latency:
4570 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
4571 break;
4572 default:
4573 break;
4574 }
4575
4576set_itr_now:
4577 if (new_itr != q_vector->itr_val) {
4578 /* this attempts to bias the interrupt rate towards Bulk
4579 * by adding intermediate steps when interrupt rate is
4580 * increasing
4581 */
4582 new_itr = new_itr > q_vector->itr_val ?
4583 max((new_itr * q_vector->itr_val) /
4584 (new_itr + (q_vector->itr_val >> 2)),
4585 new_itr) : new_itr;
4586 /* Don't write the value here; it resets the adapter's
4587 * internal timer, and causes us to delay far longer than
4588 * we should between interrupts. Instead, we write the ITR
4589 * value at the beginning of the next interrupt so the timing
4590 * ends up being correct.
4591 */
4592 q_vector->itr_val = new_itr;
4593 q_vector->set_itr = 1;
4594 }
4595}
4596
4597static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4598 u32 type_tucmd, u32 mss_l4len_idx)
4599{
4600 struct e1000_adv_tx_context_desc *context_desc;
4601 u16 i = tx_ring->next_to_use;
4602
4603 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4604
4605 i++;
4606 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4607
4608 /* set bits to identify this as an advanced context descriptor */
4609 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4610
4611 /* For 82575, context index must be unique per ring. */
4612 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4613 mss_l4len_idx |= tx_ring->reg_idx << 4;
4614
4615 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4616 context_desc->seqnum_seed = 0;
4617 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4618 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4619}
4620
4621static int igb_tso(struct igb_ring *tx_ring,
4622 struct igb_tx_buffer *first,
4623 u8 *hdr_len)
4624{
4625 struct sk_buff *skb = first->skb;
4626 u32 vlan_macip_lens, type_tucmd;
4627 u32 mss_l4len_idx, l4len;
4628 int err;
4629
4630 if (skb->ip_summed != CHECKSUM_PARTIAL)
4631 return 0;
4632
4633 if (!skb_is_gso(skb))
4634 return 0;
4635
4636 err = skb_cow_head(skb, 0);
4637 if (err < 0)
4638 return err;
4639
4640 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4641 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4642
4643 if (first->protocol == htons(ETH_P_IP)) {
4644 struct iphdr *iph = ip_hdr(skb);
4645 iph->tot_len = 0;
4646 iph->check = 0;
4647 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4648 iph->daddr, 0,
4649 IPPROTO_TCP,
4650 0);
4651 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4652 first->tx_flags |= IGB_TX_FLAGS_TSO |
4653 IGB_TX_FLAGS_CSUM |
4654 IGB_TX_FLAGS_IPV4;
4655 } else if (skb_is_gso_v6(skb)) {
4656 ipv6_hdr(skb)->payload_len = 0;
4657 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4658 &ipv6_hdr(skb)->daddr,
4659 0, IPPROTO_TCP, 0);
4660 first->tx_flags |= IGB_TX_FLAGS_TSO |
4661 IGB_TX_FLAGS_CSUM;
4662 }
4663
4664 /* compute header lengths */
4665 l4len = tcp_hdrlen(skb);
4666 *hdr_len = skb_transport_offset(skb) + l4len;
4667
4668 /* update gso size and bytecount with header size */
4669 first->gso_segs = skb_shinfo(skb)->gso_segs;
4670 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4671
4672 /* MSS L4LEN IDX */
4673 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4674 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4675
4676 /* VLAN MACLEN IPLEN */
4677 vlan_macip_lens = skb_network_header_len(skb);
4678 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4679 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4680
4681 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4682
4683 return 1;
4684}
4685
4686static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4687{
4688 struct sk_buff *skb = first->skb;
4689 u32 vlan_macip_lens = 0;
4690 u32 mss_l4len_idx = 0;
4691 u32 type_tucmd = 0;
4692
4693 if (skb->ip_summed != CHECKSUM_PARTIAL) {
4694 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4695 return;
4696 } else {
4697 u8 l4_hdr = 0;
4698
4699 switch (first->protocol) {
4700 case htons(ETH_P_IP):
4701 vlan_macip_lens |= skb_network_header_len(skb);
4702 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4703 l4_hdr = ip_hdr(skb)->protocol;
4704 break;
4705 case htons(ETH_P_IPV6):
4706 vlan_macip_lens |= skb_network_header_len(skb);
4707 l4_hdr = ipv6_hdr(skb)->nexthdr;
4708 break;
4709 default:
4710 if (unlikely(net_ratelimit())) {
4711 dev_warn(tx_ring->dev,
4712 "partial checksum but proto=%x!\n",
4713 first->protocol);
4714 }
4715 break;
4716 }
4717
4718 switch (l4_hdr) {
4719 case IPPROTO_TCP:
4720 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4721 mss_l4len_idx = tcp_hdrlen(skb) <<
4722 E1000_ADVTXD_L4LEN_SHIFT;
4723 break;
4724 case IPPROTO_SCTP:
4725 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4726 mss_l4len_idx = sizeof(struct sctphdr) <<
4727 E1000_ADVTXD_L4LEN_SHIFT;
4728 break;
4729 case IPPROTO_UDP:
4730 mss_l4len_idx = sizeof(struct udphdr) <<
4731 E1000_ADVTXD_L4LEN_SHIFT;
4732 break;
4733 default:
4734 if (unlikely(net_ratelimit())) {
4735 dev_warn(tx_ring->dev,
4736 "partial checksum but l4 proto=%x!\n",
4737 l4_hdr);
4738 }
4739 break;
4740 }
4741
4742 /* update TX checksum flag */
4743 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4744 }
4745
4746 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4747 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4748
4749 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4750}
4751
4752#define IGB_SET_FLAG(_input, _flag, _result) \
4753 ((_flag <= _result) ? \
4754 ((u32)(_input & _flag) * (_result / _flag)) : \
4755 ((u32)(_input & _flag) / (_flag / _result)))
4756
4757static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4758{
4759 /* set type for advanced descriptor with frame checksum insertion */
4760 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4761 E1000_ADVTXD_DCMD_DEXT |
4762 E1000_ADVTXD_DCMD_IFCS;
4763
4764 /* set HW vlan bit if vlan is present */
4765 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4766 (E1000_ADVTXD_DCMD_VLE));
4767
4768 /* set segmentation bits for TSO */
4769 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4770 (E1000_ADVTXD_DCMD_TSE));
4771
4772 /* set timestamp bit if present */
4773 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4774 (E1000_ADVTXD_MAC_TSTAMP));
4775
4776 /* insert frame checksum */
4777 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4778
4779 return cmd_type;
4780}
4781
4782static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4783 union e1000_adv_tx_desc *tx_desc,
4784 u32 tx_flags, unsigned int paylen)
4785{
4786 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4787
4788 /* 82575 requires a unique index per ring */
4789 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4790 olinfo_status |= tx_ring->reg_idx << 4;
4791
4792 /* insert L4 checksum */
4793 olinfo_status |= IGB_SET_FLAG(tx_flags,
4794 IGB_TX_FLAGS_CSUM,
4795 (E1000_TXD_POPTS_TXSM << 8));
4796
4797 /* insert IPv4 checksum */
4798 olinfo_status |= IGB_SET_FLAG(tx_flags,
4799 IGB_TX_FLAGS_IPV4,
4800 (E1000_TXD_POPTS_IXSM << 8));
4801
4802 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4803}
4804
4805static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4806{
4807 struct net_device *netdev = tx_ring->netdev;
4808
4809 netif_stop_subqueue(netdev, tx_ring->queue_index);
4810
4811 /* Herbert's original patch had:
4812 * smp_mb__after_netif_stop_queue();
4813 * but since that doesn't exist yet, just open code it.
4814 */
4815 smp_mb();
4816
4817 /* We need to check again in a case another CPU has just
4818 * made room available.
4819 */
4820 if (igb_desc_unused(tx_ring) < size)
4821 return -EBUSY;
4822
4823 /* A reprieve! */
4824 netif_wake_subqueue(netdev, tx_ring->queue_index);
4825
4826 u64_stats_update_begin(&tx_ring->tx_syncp2);
4827 tx_ring->tx_stats.restart_queue2++;
4828 u64_stats_update_end(&tx_ring->tx_syncp2);
4829
4830 return 0;
4831}
4832
4833static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4834{
4835 if (igb_desc_unused(tx_ring) >= size)
4836 return 0;
4837 return __igb_maybe_stop_tx(tx_ring, size);
4838}
4839
4840static void igb_tx_map(struct igb_ring *tx_ring,
4841 struct igb_tx_buffer *first,
4842 const u8 hdr_len)
4843{
4844 struct sk_buff *skb = first->skb;
4845 struct igb_tx_buffer *tx_buffer;
4846 union e1000_adv_tx_desc *tx_desc;
4847 struct skb_frag_struct *frag;
4848 dma_addr_t dma;
4849 unsigned int data_len, size;
4850 u32 tx_flags = first->tx_flags;
4851 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
4852 u16 i = tx_ring->next_to_use;
4853
4854 tx_desc = IGB_TX_DESC(tx_ring, i);
4855
4856 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4857
4858 size = skb_headlen(skb);
4859 data_len = skb->data_len;
4860
4861 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4862
4863 tx_buffer = first;
4864
4865 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4866 if (dma_mapping_error(tx_ring->dev, dma))
4867 goto dma_error;
4868
4869 /* record length, and DMA address */
4870 dma_unmap_len_set(tx_buffer, len, size);
4871 dma_unmap_addr_set(tx_buffer, dma, dma);
4872
4873 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4874
4875 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4876 tx_desc->read.cmd_type_len =
4877 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
4878
4879 i++;
4880 tx_desc++;
4881 if (i == tx_ring->count) {
4882 tx_desc = IGB_TX_DESC(tx_ring, 0);
4883 i = 0;
4884 }
4885 tx_desc->read.olinfo_status = 0;
4886
4887 dma += IGB_MAX_DATA_PER_TXD;
4888 size -= IGB_MAX_DATA_PER_TXD;
4889
4890 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4891 }
4892
4893 if (likely(!data_len))
4894 break;
4895
4896 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
4897
4898 i++;
4899 tx_desc++;
4900 if (i == tx_ring->count) {
4901 tx_desc = IGB_TX_DESC(tx_ring, 0);
4902 i = 0;
4903 }
4904 tx_desc->read.olinfo_status = 0;
4905
4906 size = skb_frag_size(frag);
4907 data_len -= size;
4908
4909 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4910 size, DMA_TO_DEVICE);
4911
4912 tx_buffer = &tx_ring->tx_buffer_info[i];
4913 }
4914
4915 /* write last descriptor with RS and EOP bits */
4916 cmd_type |= size | IGB_TXD_DCMD;
4917 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
4918
4919 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4920
4921 /* set the timestamp */
4922 first->time_stamp = jiffies;
4923
4924 /* Force memory writes to complete before letting h/w know there
4925 * are new descriptors to fetch. (Only applicable for weak-ordered
4926 * memory model archs, such as IA-64).
4927 *
4928 * We also need this memory barrier to make certain all of the
4929 * status bits have been updated before next_to_watch is written.
4930 */
4931 wmb();
4932
4933 /* set next_to_watch value indicating a packet is present */
4934 first->next_to_watch = tx_desc;
4935
4936 i++;
4937 if (i == tx_ring->count)
4938 i = 0;
4939
4940 tx_ring->next_to_use = i;
4941
4942 /* Make sure there is space in the ring for the next send. */
4943 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4944
4945 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
4946 writel(i, tx_ring->tail);
4947
4948 /* we need this if more than one processor can write to our tail
4949 * at a time, it synchronizes IO on IA64/Altix systems
4950 */
4951 mmiowb();
4952 }
4953 return;
4954
4955dma_error:
4956 dev_err(tx_ring->dev, "TX DMA map failed\n");
4957
4958 /* clear dma mappings for failed tx_buffer_info map */
4959 for (;;) {
4960 tx_buffer = &tx_ring->tx_buffer_info[i];
4961 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4962 if (tx_buffer == first)
4963 break;
4964 if (i == 0)
4965 i = tx_ring->count;
4966 i--;
4967 }
4968
4969 tx_ring->next_to_use = i;
4970}
4971
4972netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4973 struct igb_ring *tx_ring)
4974{
4975 struct igb_tx_buffer *first;
4976 int tso;
4977 u32 tx_flags = 0;
4978 unsigned short f;
4979 u16 count = TXD_USE_COUNT(skb_headlen(skb));
4980 __be16 protocol = vlan_get_protocol(skb);
4981 u8 hdr_len = 0;
4982
4983 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4984 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
4985 * + 2 desc gap to keep tail from touching head,
4986 * + 1 desc for context descriptor,
4987 * otherwise try next time
4988 */
4989 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4990 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4991
4992 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
4993 /* this is a hard error */
4994 return NETDEV_TX_BUSY;
4995 }
4996
4997 /* record the location of the first descriptor for this packet */
4998 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4999 first->skb = skb;
5000 first->bytecount = skb->len;
5001 first->gso_segs = 1;
5002
5003 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5004 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
5005
5006 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5007 &adapter->state)) {
5008 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5009 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5010
5011 adapter->ptp_tx_skb = skb_get(skb);
5012 adapter->ptp_tx_start = jiffies;
5013 if (adapter->hw.mac.type == e1000_82576)
5014 schedule_work(&adapter->ptp_tx_work);
5015 }
5016 }
5017
5018 skb_tx_timestamp(skb);
5019
5020 if (skb_vlan_tag_present(skb)) {
5021 tx_flags |= IGB_TX_FLAGS_VLAN;
5022 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
5023 }
5024
5025 /* record initial flags and protocol */
5026 first->tx_flags = tx_flags;
5027 first->protocol = protocol;
5028
5029 tso = igb_tso(tx_ring, first, &hdr_len);
5030 if (tso < 0)
5031 goto out_drop;
5032 else if (!tso)
5033 igb_tx_csum(tx_ring, first);
5034
5035 igb_tx_map(tx_ring, first, hdr_len);
5036
5037 return NETDEV_TX_OK;
5038
5039out_drop:
5040 igb_unmap_and_free_tx_resource(tx_ring, first);
5041
5042 return NETDEV_TX_OK;
5043}
5044
5045static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5046 struct sk_buff *skb)
5047{
5048 unsigned int r_idx = skb->queue_mapping;
5049
5050 if (r_idx >= adapter->num_tx_queues)
5051 r_idx = r_idx % adapter->num_tx_queues;
5052
5053 return adapter->tx_ring[r_idx];
5054}
5055
5056static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5057 struct net_device *netdev)
5058{
5059 struct igb_adapter *adapter = netdev_priv(netdev);
5060
5061 if (test_bit(__IGB_DOWN, &adapter->state)) {
5062 dev_kfree_skb_any(skb);
5063 return NETDEV_TX_OK;
5064 }
5065
5066 if (skb->len <= 0) {
5067 dev_kfree_skb_any(skb);
5068 return NETDEV_TX_OK;
5069 }
5070
5071 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
5072 * in order to meet this minimum size requirement.
5073 */
5074 if (skb_put_padto(skb, 17))
5075 return NETDEV_TX_OK;
5076
5077 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
5078}
5079
5080/**
5081 * igb_tx_timeout - Respond to a Tx Hang
5082 * @netdev: network interface device structure
5083 **/
5084static void igb_tx_timeout(struct net_device *netdev)
5085{
5086 struct igb_adapter *adapter = netdev_priv(netdev);
5087 struct e1000_hw *hw = &adapter->hw;
5088
5089 /* Do the reset outside of interrupt context */
5090 adapter->tx_timeout_count++;
5091
5092 if (hw->mac.type >= e1000_82580)
5093 hw->dev_spec._82575.global_device_reset = true;
5094
5095 schedule_work(&adapter->reset_task);
5096 wr32(E1000_EICS,
5097 (adapter->eims_enable_mask & ~adapter->eims_other));
5098}
5099
5100static void igb_reset_task(struct work_struct *work)
5101{
5102 struct igb_adapter *adapter;
5103 adapter = container_of(work, struct igb_adapter, reset_task);
5104
5105 igb_dump(adapter);
5106 netdev_err(adapter->netdev, "Reset adapter\n");
5107 igb_reinit_locked(adapter);
5108}
5109
5110/**
5111 * igb_get_stats64 - Get System Network Statistics
5112 * @netdev: network interface device structure
5113 * @stats: rtnl_link_stats64 pointer
5114 **/
5115static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
5116 struct rtnl_link_stats64 *stats)
5117{
5118 struct igb_adapter *adapter = netdev_priv(netdev);
5119
5120 spin_lock(&adapter->stats64_lock);
5121 igb_update_stats(adapter, &adapter->stats64);
5122 memcpy(stats, &adapter->stats64, sizeof(*stats));
5123 spin_unlock(&adapter->stats64_lock);
5124
5125 return stats;
5126}
5127
5128/**
5129 * igb_change_mtu - Change the Maximum Transfer Unit
5130 * @netdev: network interface device structure
5131 * @new_mtu: new value for maximum frame size
5132 *
5133 * Returns 0 on success, negative on failure
5134 **/
5135static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5136{
5137 struct igb_adapter *adapter = netdev_priv(netdev);
5138 struct pci_dev *pdev = adapter->pdev;
5139 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
5140
5141 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
5142 dev_err(&pdev->dev, "Invalid MTU setting\n");
5143 return -EINVAL;
5144 }
5145
5146#define MAX_STD_JUMBO_FRAME_SIZE 9238
5147 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
5148 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
5149 return -EINVAL;
5150 }
5151
5152 /* adjust max frame to be at least the size of a standard frame */
5153 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5154 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5155
5156 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
5157 usleep_range(1000, 2000);
5158
5159 /* igb_down has a dependency on max_frame_size */
5160 adapter->max_frame_size = max_frame;
5161
5162 if (netif_running(netdev))
5163 igb_down(adapter);
5164
5165 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
5166 netdev->mtu, new_mtu);
5167 netdev->mtu = new_mtu;
5168
5169 if (netif_running(netdev))
5170 igb_up(adapter);
5171 else
5172 igb_reset(adapter);
5173
5174 clear_bit(__IGB_RESETTING, &adapter->state);
5175
5176 return 0;
5177}
5178
5179/**
5180 * igb_update_stats - Update the board statistics counters
5181 * @adapter: board private structure
5182 **/
5183void igb_update_stats(struct igb_adapter *adapter,
5184 struct rtnl_link_stats64 *net_stats)
5185{
5186 struct e1000_hw *hw = &adapter->hw;
5187 struct pci_dev *pdev = adapter->pdev;
5188 u32 reg, mpc;
5189 int i;
5190 u64 bytes, packets;
5191 unsigned int start;
5192 u64 _bytes, _packets;
5193
5194 /* Prevent stats update while adapter is being reset, or if the pci
5195 * connection is down.
5196 */
5197 if (adapter->link_speed == 0)
5198 return;
5199 if (pci_channel_offline(pdev))
5200 return;
5201
5202 bytes = 0;
5203 packets = 0;
5204
5205 rcu_read_lock();
5206 for (i = 0; i < adapter->num_rx_queues; i++) {
5207 struct igb_ring *ring = adapter->rx_ring[i];
5208 u32 rqdpc = rd32(E1000_RQDPC(i));
5209 if (hw->mac.type >= e1000_i210)
5210 wr32(E1000_RQDPC(i), 0);
5211
5212 if (rqdpc) {
5213 ring->rx_stats.drops += rqdpc;
5214 net_stats->rx_fifo_errors += rqdpc;
5215 }
5216
5217 do {
5218 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
5219 _bytes = ring->rx_stats.bytes;
5220 _packets = ring->rx_stats.packets;
5221 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
5222 bytes += _bytes;
5223 packets += _packets;
5224 }
5225
5226 net_stats->rx_bytes = bytes;
5227 net_stats->rx_packets = packets;
5228
5229 bytes = 0;
5230 packets = 0;
5231 for (i = 0; i < adapter->num_tx_queues; i++) {
5232 struct igb_ring *ring = adapter->tx_ring[i];
5233 do {
5234 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
5235 _bytes = ring->tx_stats.bytes;
5236 _packets = ring->tx_stats.packets;
5237 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
5238 bytes += _bytes;
5239 packets += _packets;
5240 }
5241 net_stats->tx_bytes = bytes;
5242 net_stats->tx_packets = packets;
5243 rcu_read_unlock();
5244
5245 /* read stats registers */
5246 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5247 adapter->stats.gprc += rd32(E1000_GPRC);
5248 adapter->stats.gorc += rd32(E1000_GORCL);
5249 rd32(E1000_GORCH); /* clear GORCL */
5250 adapter->stats.bprc += rd32(E1000_BPRC);
5251 adapter->stats.mprc += rd32(E1000_MPRC);
5252 adapter->stats.roc += rd32(E1000_ROC);
5253
5254 adapter->stats.prc64 += rd32(E1000_PRC64);
5255 adapter->stats.prc127 += rd32(E1000_PRC127);
5256 adapter->stats.prc255 += rd32(E1000_PRC255);
5257 adapter->stats.prc511 += rd32(E1000_PRC511);
5258 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5259 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5260 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5261 adapter->stats.sec += rd32(E1000_SEC);
5262
5263 mpc = rd32(E1000_MPC);
5264 adapter->stats.mpc += mpc;
5265 net_stats->rx_fifo_errors += mpc;
5266 adapter->stats.scc += rd32(E1000_SCC);
5267 adapter->stats.ecol += rd32(E1000_ECOL);
5268 adapter->stats.mcc += rd32(E1000_MCC);
5269 adapter->stats.latecol += rd32(E1000_LATECOL);
5270 adapter->stats.dc += rd32(E1000_DC);
5271 adapter->stats.rlec += rd32(E1000_RLEC);
5272 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5273 adapter->stats.xontxc += rd32(E1000_XONTXC);
5274 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5275 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5276 adapter->stats.fcruc += rd32(E1000_FCRUC);
5277 adapter->stats.gptc += rd32(E1000_GPTC);
5278 adapter->stats.gotc += rd32(E1000_GOTCL);
5279 rd32(E1000_GOTCH); /* clear GOTCL */
5280 adapter->stats.rnbc += rd32(E1000_RNBC);
5281 adapter->stats.ruc += rd32(E1000_RUC);
5282 adapter->stats.rfc += rd32(E1000_RFC);
5283 adapter->stats.rjc += rd32(E1000_RJC);
5284 adapter->stats.tor += rd32(E1000_TORH);
5285 adapter->stats.tot += rd32(E1000_TOTH);
5286 adapter->stats.tpr += rd32(E1000_TPR);
5287
5288 adapter->stats.ptc64 += rd32(E1000_PTC64);
5289 adapter->stats.ptc127 += rd32(E1000_PTC127);
5290 adapter->stats.ptc255 += rd32(E1000_PTC255);
5291 adapter->stats.ptc511 += rd32(E1000_PTC511);
5292 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5293 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5294
5295 adapter->stats.mptc += rd32(E1000_MPTC);
5296 adapter->stats.bptc += rd32(E1000_BPTC);
5297
5298 adapter->stats.tpt += rd32(E1000_TPT);
5299 adapter->stats.colc += rd32(E1000_COLC);
5300
5301 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
5302 /* read internal phy specific stats */
5303 reg = rd32(E1000_CTRL_EXT);
5304 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5305 adapter->stats.rxerrc += rd32(E1000_RXERRC);
5306
5307 /* this stat has invalid values on i210/i211 */
5308 if ((hw->mac.type != e1000_i210) &&
5309 (hw->mac.type != e1000_i211))
5310 adapter->stats.tncrs += rd32(E1000_TNCRS);
5311 }
5312
5313 adapter->stats.tsctc += rd32(E1000_TSCTC);
5314 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5315
5316 adapter->stats.iac += rd32(E1000_IAC);
5317 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5318 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5319 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5320 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5321 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5322 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5323 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5324 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5325
5326 /* Fill out the OS statistics structure */
5327 net_stats->multicast = adapter->stats.mprc;
5328 net_stats->collisions = adapter->stats.colc;
5329
5330 /* Rx Errors */
5331
5332 /* RLEC on some newer hardware can be incorrect so build
5333 * our own version based on RUC and ROC
5334 */
5335 net_stats->rx_errors = adapter->stats.rxerrc +
5336 adapter->stats.crcerrs + adapter->stats.algnerrc +
5337 adapter->stats.ruc + adapter->stats.roc +
5338 adapter->stats.cexterr;
5339 net_stats->rx_length_errors = adapter->stats.ruc +
5340 adapter->stats.roc;
5341 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5342 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5343 net_stats->rx_missed_errors = adapter->stats.mpc;
5344
5345 /* Tx Errors */
5346 net_stats->tx_errors = adapter->stats.ecol +
5347 adapter->stats.latecol;
5348 net_stats->tx_aborted_errors = adapter->stats.ecol;
5349 net_stats->tx_window_errors = adapter->stats.latecol;
5350 net_stats->tx_carrier_errors = adapter->stats.tncrs;
5351
5352 /* Tx Dropped needs to be maintained elsewhere */
5353
5354 /* Management Stats */
5355 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5356 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5357 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
5358
5359 /* OS2BMC Stats */
5360 reg = rd32(E1000_MANC);
5361 if (reg & E1000_MANC_EN_BMC2OS) {
5362 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5363 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5364 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5365 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5366 }
5367}
5368
5369static void igb_tsync_interrupt(struct igb_adapter *adapter)
5370{
5371 struct e1000_hw *hw = &adapter->hw;
5372 struct ptp_clock_event event;
5373 struct timespec64 ts;
5374 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
5375
5376 if (tsicr & TSINTR_SYS_WRAP) {
5377 event.type = PTP_CLOCK_PPS;
5378 if (adapter->ptp_caps.pps)
5379 ptp_clock_event(adapter->ptp_clock, &event);
5380 else
5381 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5382 ack |= TSINTR_SYS_WRAP;
5383 }
5384
5385 if (tsicr & E1000_TSICR_TXTS) {
5386 /* retrieve hardware timestamp */
5387 schedule_work(&adapter->ptp_tx_work);
5388 ack |= E1000_TSICR_TXTS;
5389 }
5390
5391 if (tsicr & TSINTR_TT0) {
5392 spin_lock(&adapter->tmreg_lock);
5393 ts = timespec64_add(adapter->perout[0].start,
5394 adapter->perout[0].period);
5395 /* u32 conversion of tv_sec is safe until y2106 */
5396 wr32(E1000_TRGTTIML0, ts.tv_nsec);
5397 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec);
5398 tsauxc = rd32(E1000_TSAUXC);
5399 tsauxc |= TSAUXC_EN_TT0;
5400 wr32(E1000_TSAUXC, tsauxc);
5401 adapter->perout[0].start = ts;
5402 spin_unlock(&adapter->tmreg_lock);
5403 ack |= TSINTR_TT0;
5404 }
5405
5406 if (tsicr & TSINTR_TT1) {
5407 spin_lock(&adapter->tmreg_lock);
5408 ts = timespec64_add(adapter->perout[1].start,
5409 adapter->perout[1].period);
5410 wr32(E1000_TRGTTIML1, ts.tv_nsec);
5411 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec);
5412 tsauxc = rd32(E1000_TSAUXC);
5413 tsauxc |= TSAUXC_EN_TT1;
5414 wr32(E1000_TSAUXC, tsauxc);
5415 adapter->perout[1].start = ts;
5416 spin_unlock(&adapter->tmreg_lock);
5417 ack |= TSINTR_TT1;
5418 }
5419
5420 if (tsicr & TSINTR_AUTT0) {
5421 nsec = rd32(E1000_AUXSTMPL0);
5422 sec = rd32(E1000_AUXSTMPH0);
5423 event.type = PTP_CLOCK_EXTTS;
5424 event.index = 0;
5425 event.timestamp = sec * 1000000000ULL + nsec;
5426 ptp_clock_event(adapter->ptp_clock, &event);
5427 ack |= TSINTR_AUTT0;
5428 }
5429
5430 if (tsicr & TSINTR_AUTT1) {
5431 nsec = rd32(E1000_AUXSTMPL1);
5432 sec = rd32(E1000_AUXSTMPH1);
5433 event.type = PTP_CLOCK_EXTTS;
5434 event.index = 1;
5435 event.timestamp = sec * 1000000000ULL + nsec;
5436 ptp_clock_event(adapter->ptp_clock, &event);
5437 ack |= TSINTR_AUTT1;
5438 }
5439
5440 /* acknowledge the interrupts */
5441 wr32(E1000_TSICR, ack);
5442}
5443
5444static irqreturn_t igb_msix_other(int irq, void *data)
5445{
5446 struct igb_adapter *adapter = data;
5447 struct e1000_hw *hw = &adapter->hw;
5448 u32 icr = rd32(E1000_ICR);
5449 /* reading ICR causes bit 31 of EICR to be cleared */
5450
5451 if (icr & E1000_ICR_DRSTA)
5452 schedule_work(&adapter->reset_task);
5453
5454 if (icr & E1000_ICR_DOUTSYNC) {
5455 /* HW is reporting DMA is out of sync */
5456 adapter->stats.doosync++;
5457 /* The DMA Out of Sync is also indication of a spoof event
5458 * in IOV mode. Check the Wrong VM Behavior register to
5459 * see if it is really a spoof event.
5460 */
5461 igb_check_wvbr(adapter);
5462 }
5463
5464 /* Check for a mailbox event */
5465 if (icr & E1000_ICR_VMMB)
5466 igb_msg_task(adapter);
5467
5468 if (icr & E1000_ICR_LSC) {
5469 hw->mac.get_link_status = 1;
5470 /* guard against interrupt when we're going down */
5471 if (!test_bit(__IGB_DOWN, &adapter->state))
5472 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5473 }
5474
5475 if (icr & E1000_ICR_TS)
5476 igb_tsync_interrupt(adapter);
5477
5478 wr32(E1000_EIMS, adapter->eims_other);
5479
5480 return IRQ_HANDLED;
5481}
5482
5483static void igb_write_itr(struct igb_q_vector *q_vector)
5484{
5485 struct igb_adapter *adapter = q_vector->adapter;
5486 u32 itr_val = q_vector->itr_val & 0x7FFC;
5487
5488 if (!q_vector->set_itr)
5489 return;
5490
5491 if (!itr_val)
5492 itr_val = 0x4;
5493
5494 if (adapter->hw.mac.type == e1000_82575)
5495 itr_val |= itr_val << 16;
5496 else
5497 itr_val |= E1000_EITR_CNT_IGNR;
5498
5499 writel(itr_val, q_vector->itr_register);
5500 q_vector->set_itr = 0;
5501}
5502
5503static irqreturn_t igb_msix_ring(int irq, void *data)
5504{
5505 struct igb_q_vector *q_vector = data;
5506
5507 /* Write the ITR value calculated from the previous interrupt. */
5508 igb_write_itr(q_vector);
5509
5510 napi_schedule(&q_vector->napi);
5511
5512 return IRQ_HANDLED;
5513}
5514
5515#ifdef CONFIG_IGB_DCA
5516static void igb_update_tx_dca(struct igb_adapter *adapter,
5517 struct igb_ring *tx_ring,
5518 int cpu)
5519{
5520 struct e1000_hw *hw = &adapter->hw;
5521 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5522
5523 if (hw->mac.type != e1000_82575)
5524 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5525
5526 /* We can enable relaxed ordering for reads, but not writes when
5527 * DCA is enabled. This is due to a known issue in some chipsets
5528 * which will cause the DCA tag to be cleared.
5529 */
5530 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5531 E1000_DCA_TXCTRL_DATA_RRO_EN |
5532 E1000_DCA_TXCTRL_DESC_DCA_EN;
5533
5534 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5535}
5536
5537static void igb_update_rx_dca(struct igb_adapter *adapter,
5538 struct igb_ring *rx_ring,
5539 int cpu)
5540{
5541 struct e1000_hw *hw = &adapter->hw;
5542 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5543
5544 if (hw->mac.type != e1000_82575)
5545 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5546
5547 /* We can enable relaxed ordering for reads, but not writes when
5548 * DCA is enabled. This is due to a known issue in some chipsets
5549 * which will cause the DCA tag to be cleared.
5550 */
5551 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5552 E1000_DCA_RXCTRL_DESC_DCA_EN;
5553
5554 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5555}
5556
5557static void igb_update_dca(struct igb_q_vector *q_vector)
5558{
5559 struct igb_adapter *adapter = q_vector->adapter;
5560 int cpu = get_cpu();
5561
5562 if (q_vector->cpu == cpu)
5563 goto out_no_update;
5564
5565 if (q_vector->tx.ring)
5566 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5567
5568 if (q_vector->rx.ring)
5569 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5570
5571 q_vector->cpu = cpu;
5572out_no_update:
5573 put_cpu();
5574}
5575
5576static void igb_setup_dca(struct igb_adapter *adapter)
5577{
5578 struct e1000_hw *hw = &adapter->hw;
5579 int i;
5580
5581 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
5582 return;
5583
5584 /* Always use CB2 mode, difference is masked in the CB driver. */
5585 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5586
5587 for (i = 0; i < adapter->num_q_vectors; i++) {
5588 adapter->q_vector[i]->cpu = -1;
5589 igb_update_dca(adapter->q_vector[i]);
5590 }
5591}
5592
5593static int __igb_notify_dca(struct device *dev, void *data)
5594{
5595 struct net_device *netdev = dev_get_drvdata(dev);
5596 struct igb_adapter *adapter = netdev_priv(netdev);
5597 struct pci_dev *pdev = adapter->pdev;
5598 struct e1000_hw *hw = &adapter->hw;
5599 unsigned long event = *(unsigned long *)data;
5600
5601 switch (event) {
5602 case DCA_PROVIDER_ADD:
5603 /* if already enabled, don't do it again */
5604 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
5605 break;
5606 if (dca_add_requester(dev) == 0) {
5607 adapter->flags |= IGB_FLAG_DCA_ENABLED;
5608 dev_info(&pdev->dev, "DCA enabled\n");
5609 igb_setup_dca(adapter);
5610 break;
5611 }
5612 /* Fall Through since DCA is disabled. */
5613 case DCA_PROVIDER_REMOVE:
5614 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
5615 /* without this a class_device is left
5616 * hanging around in the sysfs model
5617 */
5618 dca_remove_requester(dev);
5619 dev_info(&pdev->dev, "DCA disabled\n");
5620 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
5621 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
5622 }
5623 break;
5624 }
5625
5626 return 0;
5627}
5628
5629static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5630 void *p)
5631{
5632 int ret_val;
5633
5634 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5635 __igb_notify_dca);
5636
5637 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5638}
5639#endif /* CONFIG_IGB_DCA */
5640
5641#ifdef CONFIG_PCI_IOV
5642static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5643{
5644 unsigned char mac_addr[ETH_ALEN];
5645
5646 eth_zero_addr(mac_addr);
5647 igb_set_vf_mac(adapter, vf, mac_addr);
5648
5649 /* By default spoof check is enabled for all VFs */
5650 adapter->vf_data[vf].spoofchk_enabled = true;
5651
5652 return 0;
5653}
5654
5655#endif
5656static void igb_ping_all_vfs(struct igb_adapter *adapter)
5657{
5658 struct e1000_hw *hw = &adapter->hw;
5659 u32 ping;
5660 int i;
5661
5662 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5663 ping = E1000_PF_CONTROL_MSG;
5664 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5665 ping |= E1000_VT_MSGTYPE_CTS;
5666 igb_write_mbx(hw, &ping, 1, i);
5667 }
5668}
5669
5670static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5671{
5672 struct e1000_hw *hw = &adapter->hw;
5673 u32 vmolr = rd32(E1000_VMOLR(vf));
5674 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5675
5676 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5677 IGB_VF_FLAG_MULTI_PROMISC);
5678 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5679
5680 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5681 vmolr |= E1000_VMOLR_MPME;
5682 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5683 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5684 } else {
5685 /* if we have hashes and we are clearing a multicast promisc
5686 * flag we need to write the hashes to the MTA as this step
5687 * was previously skipped
5688 */
5689 if (vf_data->num_vf_mc_hashes > 30) {
5690 vmolr |= E1000_VMOLR_MPME;
5691 } else if (vf_data->num_vf_mc_hashes) {
5692 int j;
5693
5694 vmolr |= E1000_VMOLR_ROMPE;
5695 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5696 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5697 }
5698 }
5699
5700 wr32(E1000_VMOLR(vf), vmolr);
5701
5702 /* there are flags left unprocessed, likely not supported */
5703 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5704 return -EINVAL;
5705
5706 return 0;
5707}
5708
5709static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5710 u32 *msgbuf, u32 vf)
5711{
5712 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5713 u16 *hash_list = (u16 *)&msgbuf[1];
5714 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5715 int i;
5716
5717 /* salt away the number of multicast addresses assigned
5718 * to this VF for later use to restore when the PF multi cast
5719 * list changes
5720 */
5721 vf_data->num_vf_mc_hashes = n;
5722
5723 /* only up to 30 hash values supported */
5724 if (n > 30)
5725 n = 30;
5726
5727 /* store the hashes for later use */
5728 for (i = 0; i < n; i++)
5729 vf_data->vf_mc_hashes[i] = hash_list[i];
5730
5731 /* Flush and reset the mta with the new values */
5732 igb_set_rx_mode(adapter->netdev);
5733
5734 return 0;
5735}
5736
5737static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5738{
5739 struct e1000_hw *hw = &adapter->hw;
5740 struct vf_data_storage *vf_data;
5741 int i, j;
5742
5743 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5744 u32 vmolr = rd32(E1000_VMOLR(i));
5745
5746 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5747
5748 vf_data = &adapter->vf_data[i];
5749
5750 if ((vf_data->num_vf_mc_hashes > 30) ||
5751 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5752 vmolr |= E1000_VMOLR_MPME;
5753 } else if (vf_data->num_vf_mc_hashes) {
5754 vmolr |= E1000_VMOLR_ROMPE;
5755 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5756 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5757 }
5758 wr32(E1000_VMOLR(i), vmolr);
5759 }
5760}
5761
5762static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5763{
5764 struct e1000_hw *hw = &adapter->hw;
5765 u32 pool_mask, reg, vid;
5766 int i;
5767
5768 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5769
5770 /* Find the vlan filter for this id */
5771 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5772 reg = rd32(E1000_VLVF(i));
5773
5774 /* remove the vf from the pool */
5775 reg &= ~pool_mask;
5776
5777 /* if pool is empty then remove entry from vfta */
5778 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5779 (reg & E1000_VLVF_VLANID_ENABLE)) {
5780 reg = 0;
5781 vid = reg & E1000_VLVF_VLANID_MASK;
5782 igb_vfta_set(hw, vid, vf, false, true);
5783 }
5784
5785 wr32(E1000_VLVF(i), reg);
5786 }
5787}
5788
5789static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5790{
5791 struct e1000_hw *hw = &adapter->hw;
5792
5793 if (vid)
5794 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5795 else
5796 wr32(E1000_VMVIR(vf), 0);
5797}
5798
5799static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5800 int vf, u16 vlan, u8 qos)
5801{
5802 struct igb_adapter *adapter = netdev_priv(netdev);
5803 struct e1000_hw *hw = &adapter->hw;
5804 int err = 0;
5805
5806 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5807 return -EINVAL;
5808 if (vlan || qos) {
5809 err = igb_vfta_set(hw, vlan, vf, !!vlan, false);
5810 if (err)
5811 goto out;
5812 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5813 igb_set_vmolr(adapter, vf, !vlan);
5814 adapter->vf_data[vf].pf_vlan = vlan;
5815 adapter->vf_data[vf].pf_qos = qos;
5816 dev_info(&adapter->pdev->dev,
5817 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5818 if (test_bit(__IGB_DOWN, &adapter->state)) {
5819 dev_warn(&adapter->pdev->dev,
5820 "The VF VLAN has been set, but the PF device is not up.\n");
5821 dev_warn(&adapter->pdev->dev,
5822 "Bring the PF device up before attempting to use the VF device.\n");
5823 }
5824 } else {
5825 igb_vfta_set(hw, adapter->vf_data[vf].pf_vlan, vf,
5826 false, false);
5827 igb_set_vmvir(adapter, vlan, vf);
5828 igb_set_vmolr(adapter, vf, true);
5829 adapter->vf_data[vf].pf_vlan = 0;
5830 adapter->vf_data[vf].pf_qos = 0;
5831 }
5832out:
5833 return err;
5834}
5835
5836static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5837{
5838 struct e1000_hw *hw = &adapter->hw;
5839 int i;
5840 u32 reg;
5841
5842 /* Find the vlan filter for this id */
5843 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5844 reg = rd32(E1000_VLVF(i));
5845 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5846 vid == (reg & E1000_VLVF_VLANID_MASK))
5847 break;
5848 }
5849
5850 if (i >= E1000_VLVF_ARRAY_SIZE)
5851 i = -1;
5852
5853 return i;
5854}
5855
5856static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5857{
5858 struct e1000_hw *hw = &adapter->hw;
5859 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5860 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5861 int err = 0;
5862
5863 /* If in promiscuous mode we need to make sure the PF also has
5864 * the VLAN filter set.
5865 */
5866 if (add && (adapter->netdev->flags & IFF_PROMISC))
5867 err = igb_vfta_set(hw, vid, adapter->vfs_allocated_count,
5868 true, false);
5869 if (err)
5870 goto out;
5871
5872 err = igb_vfta_set(hw, vid, vf, !!add, false);
5873
5874 if (err)
5875 goto out;
5876
5877 /* Go through all the checks to see if the VLAN filter should
5878 * be wiped completely.
5879 */
5880 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5881 u32 vlvf, bits;
5882 int regndx = igb_find_vlvf_entry(adapter, vid);
5883
5884 if (regndx < 0)
5885 goto out;
5886 /* See if any other pools are set for this VLAN filter
5887 * entry other than the PF.
5888 */
5889 vlvf = bits = rd32(E1000_VLVF(regndx));
5890 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5891 adapter->vfs_allocated_count);
5892 /* If the filter was removed then ensure PF pool bit
5893 * is cleared if the PF only added itself to the pool
5894 * because the PF is in promiscuous mode.
5895 */
5896 if ((vlvf & VLAN_VID_MASK) == vid &&
5897 !test_bit(vid, adapter->active_vlans) &&
5898 !bits)
5899 igb_vfta_set(hw, vid, adapter->vfs_allocated_count,
5900 false, false);
5901 }
5902
5903out:
5904 return err;
5905}
5906
5907static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
5908{
5909 /* clear flags - except flag that indicates PF has set the MAC */
5910 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
5911 adapter->vf_data[vf].last_nack = jiffies;
5912
5913 /* reset offloads to defaults */
5914 igb_set_vmolr(adapter, vf, true);
5915
5916 /* reset vlans for device */
5917 igb_clear_vf_vfta(adapter, vf);
5918 if (adapter->vf_data[vf].pf_vlan)
5919 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5920 adapter->vf_data[vf].pf_vlan,
5921 adapter->vf_data[vf].pf_qos);
5922 else
5923 igb_clear_vf_vfta(adapter, vf);
5924
5925 /* reset multicast table array for vf */
5926 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5927
5928 /* Flush and reset the mta with the new values */
5929 igb_set_rx_mode(adapter->netdev);
5930}
5931
5932static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5933{
5934 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5935
5936 /* clear mac address as we were hotplug removed/added */
5937 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5938 eth_zero_addr(vf_mac);
5939
5940 /* process remaining reset events */
5941 igb_vf_reset(adapter, vf);
5942}
5943
5944static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
5945{
5946 struct e1000_hw *hw = &adapter->hw;
5947 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5948 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
5949 u32 reg, msgbuf[3];
5950 u8 *addr = (u8 *)(&msgbuf[1]);
5951
5952 /* process all the same items cleared in a function level reset */
5953 igb_vf_reset(adapter, vf);
5954
5955 /* set vf mac address */
5956 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
5957
5958 /* enable transmit and receive for vf */
5959 reg = rd32(E1000_VFTE);
5960 wr32(E1000_VFTE, reg | (1 << vf));
5961 reg = rd32(E1000_VFRE);
5962 wr32(E1000_VFRE, reg | (1 << vf));
5963
5964 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
5965
5966 /* reply to reset with ack and vf mac address */
5967 if (!is_zero_ether_addr(vf_mac)) {
5968 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5969 memcpy(addr, vf_mac, ETH_ALEN);
5970 } else {
5971 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
5972 }
5973 igb_write_mbx(hw, msgbuf, 3, vf);
5974}
5975
5976static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5977{
5978 /* The VF MAC Address is stored in a packed array of bytes
5979 * starting at the second 32 bit word of the msg array
5980 */
5981 unsigned char *addr = (char *)&msg[1];
5982 int err = -1;
5983
5984 if (is_valid_ether_addr(addr))
5985 err = igb_set_vf_mac(adapter, vf, addr);
5986
5987 return err;
5988}
5989
5990static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5991{
5992 struct e1000_hw *hw = &adapter->hw;
5993 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5994 u32 msg = E1000_VT_MSGTYPE_NACK;
5995
5996 /* if device isn't clear to send it shouldn't be reading either */
5997 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5998 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
5999 igb_write_mbx(hw, &msg, 1, vf);
6000 vf_data->last_nack = jiffies;
6001 }
6002}
6003
6004static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
6005{
6006 struct pci_dev *pdev = adapter->pdev;
6007 u32 msgbuf[E1000_VFMAILBOX_SIZE];
6008 struct e1000_hw *hw = &adapter->hw;
6009 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6010 s32 retval;
6011
6012 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
6013
6014 if (retval) {
6015 /* if receive failed revoke VF CTS stats and restart init */
6016 dev_err(&pdev->dev, "Error receiving message from VF\n");
6017 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6018 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6019 return;
6020 goto out;
6021 }
6022
6023 /* this is a message we already processed, do nothing */
6024 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
6025 return;
6026
6027 /* until the vf completes a reset it should not be
6028 * allowed to start any configuration.
6029 */
6030 if (msgbuf[0] == E1000_VF_RESET) {
6031 igb_vf_reset_msg(adapter, vf);
6032 return;
6033 }
6034
6035 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
6036 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6037 return;
6038 retval = -1;
6039 goto out;
6040 }
6041
6042 switch ((msgbuf[0] & 0xFFFF)) {
6043 case E1000_VF_SET_MAC_ADDR:
6044 retval = -EINVAL;
6045 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6046 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6047 else
6048 dev_warn(&pdev->dev,
6049 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6050 vf);
6051 break;
6052 case E1000_VF_SET_PROMISC:
6053 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6054 break;
6055 case E1000_VF_SET_MULTICAST:
6056 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6057 break;
6058 case E1000_VF_SET_LPE:
6059 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6060 break;
6061 case E1000_VF_SET_VLAN:
6062 retval = -1;
6063 if (vf_data->pf_vlan)
6064 dev_warn(&pdev->dev,
6065 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6066 vf);
6067 else
6068 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
6069 break;
6070 default:
6071 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
6072 retval = -1;
6073 break;
6074 }
6075
6076 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6077out:
6078 /* notify the VF of the results of what it sent us */
6079 if (retval)
6080 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6081 else
6082 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6083
6084 igb_write_mbx(hw, msgbuf, 1, vf);
6085}
6086
6087static void igb_msg_task(struct igb_adapter *adapter)
6088{
6089 struct e1000_hw *hw = &adapter->hw;
6090 u32 vf;
6091
6092 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6093 /* process any reset requests */
6094 if (!igb_check_for_rst(hw, vf))
6095 igb_vf_reset_event(adapter, vf);
6096
6097 /* process any messages pending */
6098 if (!igb_check_for_msg(hw, vf))
6099 igb_rcv_msg_from_vf(adapter, vf);
6100
6101 /* process any acks */
6102 if (!igb_check_for_ack(hw, vf))
6103 igb_rcv_ack_from_vf(adapter, vf);
6104 }
6105}
6106
6107/**
6108 * igb_set_uta - Set unicast filter table address
6109 * @adapter: board private structure
6110 *
6111 * The unicast table address is a register array of 32-bit registers.
6112 * The table is meant to be used in a way similar to how the MTA is used
6113 * however due to certain limitations in the hardware it is necessary to
6114 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6115 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
6116 **/
6117static void igb_set_uta(struct igb_adapter *adapter)
6118{
6119 struct e1000_hw *hw = &adapter->hw;
6120 int i;
6121
6122 /* The UTA table only exists on 82576 hardware and newer */
6123 if (hw->mac.type < e1000_82576)
6124 return;
6125
6126 /* we only need to do this if VMDq is enabled */
6127 if (!adapter->vfs_allocated_count)
6128 return;
6129
6130 for (i = 0; i < hw->mac.uta_reg_count; i++)
6131 array_wr32(E1000_UTA, i, ~0);
6132}
6133
6134/**
6135 * igb_intr_msi - Interrupt Handler
6136 * @irq: interrupt number
6137 * @data: pointer to a network interface device structure
6138 **/
6139static irqreturn_t igb_intr_msi(int irq, void *data)
6140{
6141 struct igb_adapter *adapter = data;
6142 struct igb_q_vector *q_vector = adapter->q_vector[0];
6143 struct e1000_hw *hw = &adapter->hw;
6144 /* read ICR disables interrupts using IAM */
6145 u32 icr = rd32(E1000_ICR);
6146
6147 igb_write_itr(q_vector);
6148
6149 if (icr & E1000_ICR_DRSTA)
6150 schedule_work(&adapter->reset_task);
6151
6152 if (icr & E1000_ICR_DOUTSYNC) {
6153 /* HW is reporting DMA is out of sync */
6154 adapter->stats.doosync++;
6155 }
6156
6157 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6158 hw->mac.get_link_status = 1;
6159 if (!test_bit(__IGB_DOWN, &adapter->state))
6160 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6161 }
6162
6163 if (icr & E1000_ICR_TS)
6164 igb_tsync_interrupt(adapter);
6165
6166 napi_schedule(&q_vector->napi);
6167
6168 return IRQ_HANDLED;
6169}
6170
6171/**
6172 * igb_intr - Legacy Interrupt Handler
6173 * @irq: interrupt number
6174 * @data: pointer to a network interface device structure
6175 **/
6176static irqreturn_t igb_intr(int irq, void *data)
6177{
6178 struct igb_adapter *adapter = data;
6179 struct igb_q_vector *q_vector = adapter->q_vector[0];
6180 struct e1000_hw *hw = &adapter->hw;
6181 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
6182 * need for the IMC write
6183 */
6184 u32 icr = rd32(E1000_ICR);
6185
6186 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
6187 * not set, then the adapter didn't send an interrupt
6188 */
6189 if (!(icr & E1000_ICR_INT_ASSERTED))
6190 return IRQ_NONE;
6191
6192 igb_write_itr(q_vector);
6193
6194 if (icr & E1000_ICR_DRSTA)
6195 schedule_work(&adapter->reset_task);
6196
6197 if (icr & E1000_ICR_DOUTSYNC) {
6198 /* HW is reporting DMA is out of sync */
6199 adapter->stats.doosync++;
6200 }
6201
6202 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6203 hw->mac.get_link_status = 1;
6204 /* guard against interrupt when we're going down */
6205 if (!test_bit(__IGB_DOWN, &adapter->state))
6206 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6207 }
6208
6209 if (icr & E1000_ICR_TS)
6210 igb_tsync_interrupt(adapter);
6211
6212 napi_schedule(&q_vector->napi);
6213
6214 return IRQ_HANDLED;
6215}
6216
6217static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
6218{
6219 struct igb_adapter *adapter = q_vector->adapter;
6220 struct e1000_hw *hw = &adapter->hw;
6221
6222 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6223 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6224 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6225 igb_set_itr(q_vector);
6226 else
6227 igb_update_ring_itr(q_vector);
6228 }
6229
6230 if (!test_bit(__IGB_DOWN, &adapter->state)) {
6231 if (adapter->flags & IGB_FLAG_HAS_MSIX)
6232 wr32(E1000_EIMS, q_vector->eims_value);
6233 else
6234 igb_irq_enable(adapter);
6235 }
6236}
6237
6238/**
6239 * igb_poll - NAPI Rx polling callback
6240 * @napi: napi polling structure
6241 * @budget: count of how many packets we should handle
6242 **/
6243static int igb_poll(struct napi_struct *napi, int budget)
6244{
6245 struct igb_q_vector *q_vector = container_of(napi,
6246 struct igb_q_vector,
6247 napi);
6248 bool clean_complete = true;
6249 int work_done = 0;
6250
6251#ifdef CONFIG_IGB_DCA
6252 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6253 igb_update_dca(q_vector);
6254#endif
6255 if (q_vector->tx.ring)
6256 clean_complete = igb_clean_tx_irq(q_vector);
6257
6258 if (q_vector->rx.ring) {
6259 int cleaned = igb_clean_rx_irq(q_vector, budget);
6260
6261 work_done += cleaned;
6262 clean_complete &= (cleaned < budget);
6263 }
6264
6265 /* If all work not completed, return budget and keep polling */
6266 if (!clean_complete)
6267 return budget;
6268
6269 /* If not enough Rx work done, exit the polling mode */
6270 napi_complete_done(napi, work_done);
6271 igb_ring_irq_enable(q_vector);
6272
6273 return 0;
6274}
6275
6276/**
6277 * igb_clean_tx_irq - Reclaim resources after transmit completes
6278 * @q_vector: pointer to q_vector containing needed info
6279 *
6280 * returns true if ring is completely cleaned
6281 **/
6282static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
6283{
6284 struct igb_adapter *adapter = q_vector->adapter;
6285 struct igb_ring *tx_ring = q_vector->tx.ring;
6286 struct igb_tx_buffer *tx_buffer;
6287 union e1000_adv_tx_desc *tx_desc;
6288 unsigned int total_bytes = 0, total_packets = 0;
6289 unsigned int budget = q_vector->tx.work_limit;
6290 unsigned int i = tx_ring->next_to_clean;
6291
6292 if (test_bit(__IGB_DOWN, &adapter->state))
6293 return true;
6294
6295 tx_buffer = &tx_ring->tx_buffer_info[i];
6296 tx_desc = IGB_TX_DESC(tx_ring, i);
6297 i -= tx_ring->count;
6298
6299 do {
6300 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
6301
6302 /* if next_to_watch is not set then there is no work pending */
6303 if (!eop_desc)
6304 break;
6305
6306 /* prevent any other reads prior to eop_desc */
6307 read_barrier_depends();
6308
6309 /* if DD is not set pending work has not been completed */
6310 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6311 break;
6312
6313 /* clear next_to_watch to prevent false hangs */
6314 tx_buffer->next_to_watch = NULL;
6315
6316 /* update the statistics for this packet */
6317 total_bytes += tx_buffer->bytecount;
6318 total_packets += tx_buffer->gso_segs;
6319
6320 /* free the skb */
6321 dev_consume_skb_any(tx_buffer->skb);
6322
6323 /* unmap skb header data */
6324 dma_unmap_single(tx_ring->dev,
6325 dma_unmap_addr(tx_buffer, dma),
6326 dma_unmap_len(tx_buffer, len),
6327 DMA_TO_DEVICE);
6328
6329 /* clear tx_buffer data */
6330 tx_buffer->skb = NULL;
6331 dma_unmap_len_set(tx_buffer, len, 0);
6332
6333 /* clear last DMA location and unmap remaining buffers */
6334 while (tx_desc != eop_desc) {
6335 tx_buffer++;
6336 tx_desc++;
6337 i++;
6338 if (unlikely(!i)) {
6339 i -= tx_ring->count;
6340 tx_buffer = tx_ring->tx_buffer_info;
6341 tx_desc = IGB_TX_DESC(tx_ring, 0);
6342 }
6343
6344 /* unmap any remaining paged data */
6345 if (dma_unmap_len(tx_buffer, len)) {
6346 dma_unmap_page(tx_ring->dev,
6347 dma_unmap_addr(tx_buffer, dma),
6348 dma_unmap_len(tx_buffer, len),
6349 DMA_TO_DEVICE);
6350 dma_unmap_len_set(tx_buffer, len, 0);
6351 }
6352 }
6353
6354 /* move us one more past the eop_desc for start of next pkt */
6355 tx_buffer++;
6356 tx_desc++;
6357 i++;
6358 if (unlikely(!i)) {
6359 i -= tx_ring->count;
6360 tx_buffer = tx_ring->tx_buffer_info;
6361 tx_desc = IGB_TX_DESC(tx_ring, 0);
6362 }
6363
6364 /* issue prefetch for next Tx descriptor */
6365 prefetch(tx_desc);
6366
6367 /* update budget accounting */
6368 budget--;
6369 } while (likely(budget));
6370
6371 netdev_tx_completed_queue(txring_txq(tx_ring),
6372 total_packets, total_bytes);
6373 i += tx_ring->count;
6374 tx_ring->next_to_clean = i;
6375 u64_stats_update_begin(&tx_ring->tx_syncp);
6376 tx_ring->tx_stats.bytes += total_bytes;
6377 tx_ring->tx_stats.packets += total_packets;
6378 u64_stats_update_end(&tx_ring->tx_syncp);
6379 q_vector->tx.total_bytes += total_bytes;
6380 q_vector->tx.total_packets += total_packets;
6381
6382 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
6383 struct e1000_hw *hw = &adapter->hw;
6384
6385 /* Detect a transmit hang in hardware, this serializes the
6386 * check with the clearing of time_stamp and movement of i
6387 */
6388 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
6389 if (tx_buffer->next_to_watch &&
6390 time_after(jiffies, tx_buffer->time_stamp +
6391 (adapter->tx_timeout_factor * HZ)) &&
6392 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
6393
6394 /* detected Tx unit hang */
6395 dev_err(tx_ring->dev,
6396 "Detected Tx Unit Hang\n"
6397 " Tx Queue <%d>\n"
6398 " TDH <%x>\n"
6399 " TDT <%x>\n"
6400 " next_to_use <%x>\n"
6401 " next_to_clean <%x>\n"
6402 "buffer_info[next_to_clean]\n"
6403 " time_stamp <%lx>\n"
6404 " next_to_watch <%p>\n"
6405 " jiffies <%lx>\n"
6406 " desc.status <%x>\n",
6407 tx_ring->queue_index,
6408 rd32(E1000_TDH(tx_ring->reg_idx)),
6409 readl(tx_ring->tail),
6410 tx_ring->next_to_use,
6411 tx_ring->next_to_clean,
6412 tx_buffer->time_stamp,
6413 tx_buffer->next_to_watch,
6414 jiffies,
6415 tx_buffer->next_to_watch->wb.status);
6416 netif_stop_subqueue(tx_ring->netdev,
6417 tx_ring->queue_index);
6418
6419 /* we are about to reset, no point in enabling stuff */
6420 return true;
6421 }
6422 }
6423
6424#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6425 if (unlikely(total_packets &&
6426 netif_carrier_ok(tx_ring->netdev) &&
6427 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
6428 /* Make sure that anybody stopping the queue after this
6429 * sees the new next_to_clean.
6430 */
6431 smp_mb();
6432 if (__netif_subqueue_stopped(tx_ring->netdev,
6433 tx_ring->queue_index) &&
6434 !(test_bit(__IGB_DOWN, &adapter->state))) {
6435 netif_wake_subqueue(tx_ring->netdev,
6436 tx_ring->queue_index);
6437
6438 u64_stats_update_begin(&tx_ring->tx_syncp);
6439 tx_ring->tx_stats.restart_queue++;
6440 u64_stats_update_end(&tx_ring->tx_syncp);
6441 }
6442 }
6443
6444 return !!budget;
6445}
6446
6447/**
6448 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6449 * @rx_ring: rx descriptor ring to store buffers on
6450 * @old_buff: donor buffer to have page reused
6451 *
6452 * Synchronizes page for reuse by the adapter
6453 **/
6454static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6455 struct igb_rx_buffer *old_buff)
6456{
6457 struct igb_rx_buffer *new_buff;
6458 u16 nta = rx_ring->next_to_alloc;
6459
6460 new_buff = &rx_ring->rx_buffer_info[nta];
6461
6462 /* update, and store next to alloc */
6463 nta++;
6464 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6465
6466 /* transfer page from old buffer to new buffer */
6467 *new_buff = *old_buff;
6468
6469 /* sync the buffer for use by the device */
6470 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6471 old_buff->page_offset,
6472 IGB_RX_BUFSZ,
6473 DMA_FROM_DEVICE);
6474}
6475
6476static inline bool igb_page_is_reserved(struct page *page)
6477{
6478 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
6479}
6480
6481static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6482 struct page *page,
6483 unsigned int truesize)
6484{
6485 /* avoid re-using remote pages */
6486 if (unlikely(igb_page_is_reserved(page)))
6487 return false;
6488
6489#if (PAGE_SIZE < 8192)
6490 /* if we are only owner of page we can reuse it */
6491 if (unlikely(page_count(page) != 1))
6492 return false;
6493
6494 /* flip page offset to other buffer */
6495 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6496#else
6497 /* move offset up to the next cache line */
6498 rx_buffer->page_offset += truesize;
6499
6500 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6501 return false;
6502#endif
6503
6504 /* Even if we own the page, we are not allowed to use atomic_set()
6505 * This would break get_page_unless_zero() users.
6506 */
6507 atomic_inc(&page->_count);
6508
6509 return true;
6510}
6511
6512/**
6513 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6514 * @rx_ring: rx descriptor ring to transact packets on
6515 * @rx_buffer: buffer containing page to add
6516 * @rx_desc: descriptor containing length of buffer written by hardware
6517 * @skb: sk_buff to place the data into
6518 *
6519 * This function will add the data contained in rx_buffer->page to the skb.
6520 * This is done either through a direct copy if the data in the buffer is
6521 * less than the skb header size, otherwise it will just attach the page as
6522 * a frag to the skb.
6523 *
6524 * The function will then update the page offset if necessary and return
6525 * true if the buffer can be reused by the adapter.
6526 **/
6527static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6528 struct igb_rx_buffer *rx_buffer,
6529 union e1000_adv_rx_desc *rx_desc,
6530 struct sk_buff *skb)
6531{
6532 struct page *page = rx_buffer->page;
6533 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6534 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6535#if (PAGE_SIZE < 8192)
6536 unsigned int truesize = IGB_RX_BUFSZ;
6537#else
6538 unsigned int truesize = SKB_DATA_ALIGN(size);
6539#endif
6540 unsigned int pull_len;
6541
6542 if (unlikely(skb_is_nonlinear(skb)))
6543 goto add_tail_frag;
6544
6545 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
6546 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6547 va += IGB_TS_HDR_LEN;
6548 size -= IGB_TS_HDR_LEN;
6549 }
6550
6551 if (likely(size <= IGB_RX_HDR_LEN)) {
6552 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6553
6554 /* page is not reserved, we can reuse buffer as-is */
6555 if (likely(!igb_page_is_reserved(page)))
6556 return true;
6557
6558 /* this page cannot be reused so discard it */
6559 __free_page(page);
6560 return false;
6561 }
6562
6563 /* we need the header to contain the greater of either ETH_HLEN or
6564 * 60 bytes if the skb->len is less than 60 for skb_pad.
6565 */
6566 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6567
6568 /* align pull length to size of long to optimize memcpy performance */
6569 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long)));
6570
6571 /* update all of the pointers */
6572 va += pull_len;
6573 size -= pull_len;
6574
6575add_tail_frag:
6576 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6577 (unsigned long)va & ~PAGE_MASK, size, truesize);
6578
6579 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6580}
6581
6582static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6583 union e1000_adv_rx_desc *rx_desc,
6584 struct sk_buff *skb)
6585{
6586 struct igb_rx_buffer *rx_buffer;
6587 struct page *page;
6588
6589 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6590 page = rx_buffer->page;
6591 prefetchw(page);
6592
6593 if (likely(!skb)) {
6594 void *page_addr = page_address(page) +
6595 rx_buffer->page_offset;
6596
6597 /* prefetch first cache line of first page */
6598 prefetch(page_addr);
6599#if L1_CACHE_BYTES < 128
6600 prefetch(page_addr + L1_CACHE_BYTES);
6601#endif
6602
6603 /* allocate a skb to store the frags */
6604 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
6605 if (unlikely(!skb)) {
6606 rx_ring->rx_stats.alloc_failed++;
6607 return NULL;
6608 }
6609
6610 /* we will be copying header into skb->data in
6611 * pskb_may_pull so it is in our interest to prefetch
6612 * it now to avoid a possible cache miss
6613 */
6614 prefetchw(skb->data);
6615 }
6616
6617 /* we are reusing so sync this buffer for CPU use */
6618 dma_sync_single_range_for_cpu(rx_ring->dev,
6619 rx_buffer->dma,
6620 rx_buffer->page_offset,
6621 IGB_RX_BUFSZ,
6622 DMA_FROM_DEVICE);
6623
6624 /* pull page into skb */
6625 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6626 /* hand second half of page back to the ring */
6627 igb_reuse_rx_page(rx_ring, rx_buffer);
6628 } else {
6629 /* we are not reusing the buffer so unmap it */
6630 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6631 PAGE_SIZE, DMA_FROM_DEVICE);
6632 }
6633
6634 /* clear contents of rx_buffer */
6635 rx_buffer->page = NULL;
6636
6637 return skb;
6638}
6639
6640static inline void igb_rx_checksum(struct igb_ring *ring,
6641 union e1000_adv_rx_desc *rx_desc,
6642 struct sk_buff *skb)
6643{
6644 skb_checksum_none_assert(skb);
6645
6646 /* Ignore Checksum bit is set */
6647 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6648 return;
6649
6650 /* Rx checksum disabled via ethtool */
6651 if (!(ring->netdev->features & NETIF_F_RXCSUM))
6652 return;
6653
6654 /* TCP/UDP checksum error bit is set */
6655 if (igb_test_staterr(rx_desc,
6656 E1000_RXDEXT_STATERR_TCPE |
6657 E1000_RXDEXT_STATERR_IPE)) {
6658 /* work around errata with sctp packets where the TCPE aka
6659 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6660 * packets, (aka let the stack check the crc32c)
6661 */
6662 if (!((skb->len == 60) &&
6663 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6664 u64_stats_update_begin(&ring->rx_syncp);
6665 ring->rx_stats.csum_err++;
6666 u64_stats_update_end(&ring->rx_syncp);
6667 }
6668 /* let the stack verify checksum errors */
6669 return;
6670 }
6671 /* It must be a TCP or UDP packet with a valid checksum */
6672 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6673 E1000_RXD_STAT_UDPCS))
6674 skb->ip_summed = CHECKSUM_UNNECESSARY;
6675
6676 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6677 le32_to_cpu(rx_desc->wb.upper.status_error));
6678}
6679
6680static inline void igb_rx_hash(struct igb_ring *ring,
6681 union e1000_adv_rx_desc *rx_desc,
6682 struct sk_buff *skb)
6683{
6684 if (ring->netdev->features & NETIF_F_RXHASH)
6685 skb_set_hash(skb,
6686 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6687 PKT_HASH_TYPE_L3);
6688}
6689
6690/**
6691 * igb_is_non_eop - process handling of non-EOP buffers
6692 * @rx_ring: Rx ring being processed
6693 * @rx_desc: Rx descriptor for current buffer
6694 * @skb: current socket buffer containing buffer in progress
6695 *
6696 * This function updates next to clean. If the buffer is an EOP buffer
6697 * this function exits returning false, otherwise it will place the
6698 * sk_buff in the next buffer to be chained and return true indicating
6699 * that this is in fact a non-EOP buffer.
6700 **/
6701static bool igb_is_non_eop(struct igb_ring *rx_ring,
6702 union e1000_adv_rx_desc *rx_desc)
6703{
6704 u32 ntc = rx_ring->next_to_clean + 1;
6705
6706 /* fetch, update, and store next to clean */
6707 ntc = (ntc < rx_ring->count) ? ntc : 0;
6708 rx_ring->next_to_clean = ntc;
6709
6710 prefetch(IGB_RX_DESC(rx_ring, ntc));
6711
6712 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6713 return false;
6714
6715 return true;
6716}
6717
6718/**
6719 * igb_cleanup_headers - Correct corrupted or empty headers
6720 * @rx_ring: rx descriptor ring packet is being transacted on
6721 * @rx_desc: pointer to the EOP Rx descriptor
6722 * @skb: pointer to current skb being fixed
6723 *
6724 * Address the case where we are pulling data in on pages only
6725 * and as such no data is present in the skb header.
6726 *
6727 * In addition if skb is not at least 60 bytes we need to pad it so that
6728 * it is large enough to qualify as a valid Ethernet frame.
6729 *
6730 * Returns true if an error was encountered and skb was freed.
6731 **/
6732static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6733 union e1000_adv_rx_desc *rx_desc,
6734 struct sk_buff *skb)
6735{
6736 if (unlikely((igb_test_staterr(rx_desc,
6737 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6738 struct net_device *netdev = rx_ring->netdev;
6739 if (!(netdev->features & NETIF_F_RXALL)) {
6740 dev_kfree_skb_any(skb);
6741 return true;
6742 }
6743 }
6744
6745 /* if eth_skb_pad returns an error the skb was freed */
6746 if (eth_skb_pad(skb))
6747 return true;
6748
6749 return false;
6750}
6751
6752/**
6753 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6754 * @rx_ring: rx descriptor ring packet is being transacted on
6755 * @rx_desc: pointer to the EOP Rx descriptor
6756 * @skb: pointer to current skb being populated
6757 *
6758 * This function checks the ring, descriptor, and packet information in
6759 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6760 * other fields within the skb.
6761 **/
6762static void igb_process_skb_fields(struct igb_ring *rx_ring,
6763 union e1000_adv_rx_desc *rx_desc,
6764 struct sk_buff *skb)
6765{
6766 struct net_device *dev = rx_ring->netdev;
6767
6768 igb_rx_hash(rx_ring, rx_desc, skb);
6769
6770 igb_rx_checksum(rx_ring, rx_desc, skb);
6771
6772 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6773 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6774 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
6775
6776 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
6777 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6778 u16 vid;
6779
6780 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6781 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6782 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6783 else
6784 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6785
6786 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
6787 }
6788
6789 skb_record_rx_queue(skb, rx_ring->queue_index);
6790
6791 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6792}
6793
6794static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6795{
6796 struct igb_ring *rx_ring = q_vector->rx.ring;
6797 struct sk_buff *skb = rx_ring->skb;
6798 unsigned int total_bytes = 0, total_packets = 0;
6799 u16 cleaned_count = igb_desc_unused(rx_ring);
6800
6801 while (likely(total_packets < budget)) {
6802 union e1000_adv_rx_desc *rx_desc;
6803
6804 /* return some buffers to hardware, one at a time is too slow */
6805 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6806 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6807 cleaned_count = 0;
6808 }
6809
6810 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6811
6812 if (!rx_desc->wb.upper.status_error)
6813 break;
6814
6815 /* This memory barrier is needed to keep us from reading
6816 * any other fields out of the rx_desc until we know the
6817 * descriptor has been written back
6818 */
6819 dma_rmb();
6820
6821 /* retrieve a buffer from the ring */
6822 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6823
6824 /* exit if we failed to retrieve a buffer */
6825 if (!skb)
6826 break;
6827
6828 cleaned_count++;
6829
6830 /* fetch next buffer in frame if non-eop */
6831 if (igb_is_non_eop(rx_ring, rx_desc))
6832 continue;
6833
6834 /* verify the packet layout is correct */
6835 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6836 skb = NULL;
6837 continue;
6838 }
6839
6840 /* probably a little skewed due to removing CRC */
6841 total_bytes += skb->len;
6842
6843 /* populate checksum, timestamp, VLAN, and protocol */
6844 igb_process_skb_fields(rx_ring, rx_desc, skb);
6845
6846 napi_gro_receive(&q_vector->napi, skb);
6847
6848 /* reset skb pointer */
6849 skb = NULL;
6850
6851 /* update budget accounting */
6852 total_packets++;
6853 }
6854
6855 /* place incomplete frames back on ring for completion */
6856 rx_ring->skb = skb;
6857
6858 u64_stats_update_begin(&rx_ring->rx_syncp);
6859 rx_ring->rx_stats.packets += total_packets;
6860 rx_ring->rx_stats.bytes += total_bytes;
6861 u64_stats_update_end(&rx_ring->rx_syncp);
6862 q_vector->rx.total_packets += total_packets;
6863 q_vector->rx.total_bytes += total_bytes;
6864
6865 if (cleaned_count)
6866 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6867
6868 return total_packets;
6869}
6870
6871static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
6872 struct igb_rx_buffer *bi)
6873{
6874 struct page *page = bi->page;
6875 dma_addr_t dma;
6876
6877 /* since we are recycling buffers we should seldom need to alloc */
6878 if (likely(page))
6879 return true;
6880
6881 /* alloc new page for storage */
6882 page = dev_alloc_page();
6883 if (unlikely(!page)) {
6884 rx_ring->rx_stats.alloc_failed++;
6885 return false;
6886 }
6887
6888 /* map page for use */
6889 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
6890
6891 /* if mapping failed free memory back to system since
6892 * there isn't much point in holding memory we can't use
6893 */
6894 if (dma_mapping_error(rx_ring->dev, dma)) {
6895 __free_page(page);
6896
6897 rx_ring->rx_stats.alloc_failed++;
6898 return false;
6899 }
6900
6901 bi->dma = dma;
6902 bi->page = page;
6903 bi->page_offset = 0;
6904
6905 return true;
6906}
6907
6908/**
6909 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
6910 * @adapter: address of board private structure
6911 **/
6912void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
6913{
6914 union e1000_adv_rx_desc *rx_desc;
6915 struct igb_rx_buffer *bi;
6916 u16 i = rx_ring->next_to_use;
6917
6918 /* nothing to do */
6919 if (!cleaned_count)
6920 return;
6921
6922 rx_desc = IGB_RX_DESC(rx_ring, i);
6923 bi = &rx_ring->rx_buffer_info[i];
6924 i -= rx_ring->count;
6925
6926 do {
6927 if (!igb_alloc_mapped_page(rx_ring, bi))
6928 break;
6929
6930 /* Refresh the desc even if buffer_addrs didn't change
6931 * because each write-back erases this info.
6932 */
6933 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
6934
6935 rx_desc++;
6936 bi++;
6937 i++;
6938 if (unlikely(!i)) {
6939 rx_desc = IGB_RX_DESC(rx_ring, 0);
6940 bi = rx_ring->rx_buffer_info;
6941 i -= rx_ring->count;
6942 }
6943
6944 /* clear the status bits for the next_to_use descriptor */
6945 rx_desc->wb.upper.status_error = 0;
6946
6947 cleaned_count--;
6948 } while (cleaned_count);
6949
6950 i += rx_ring->count;
6951
6952 if (rx_ring->next_to_use != i) {
6953 /* record the next descriptor to use */
6954 rx_ring->next_to_use = i;
6955
6956 /* update next to alloc since we have filled the ring */
6957 rx_ring->next_to_alloc = i;
6958
6959 /* Force memory writes to complete before letting h/w
6960 * know there are new descriptors to fetch. (Only
6961 * applicable for weak-ordered memory model archs,
6962 * such as IA-64).
6963 */
6964 wmb();
6965 writel(i, rx_ring->tail);
6966 }
6967}
6968
6969/**
6970 * igb_mii_ioctl -
6971 * @netdev:
6972 * @ifreq:
6973 * @cmd:
6974 **/
6975static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6976{
6977 struct igb_adapter *adapter = netdev_priv(netdev);
6978 struct mii_ioctl_data *data = if_mii(ifr);
6979
6980 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6981 return -EOPNOTSUPP;
6982
6983 switch (cmd) {
6984 case SIOCGMIIPHY:
6985 data->phy_id = adapter->hw.phy.addr;
6986 break;
6987 case SIOCGMIIREG:
6988 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6989 &data->val_out))
6990 return -EIO;
6991 break;
6992 case SIOCSMIIREG:
6993 default:
6994 return -EOPNOTSUPP;
6995 }
6996 return 0;
6997}
6998
6999/**
7000 * igb_ioctl -
7001 * @netdev:
7002 * @ifreq:
7003 * @cmd:
7004 **/
7005static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7006{
7007 switch (cmd) {
7008 case SIOCGMIIPHY:
7009 case SIOCGMIIREG:
7010 case SIOCSMIIREG:
7011 return igb_mii_ioctl(netdev, ifr, cmd);
7012 case SIOCGHWTSTAMP:
7013 return igb_ptp_get_ts_config(netdev, ifr);
7014 case SIOCSHWTSTAMP:
7015 return igb_ptp_set_ts_config(netdev, ifr);
7016 default:
7017 return -EOPNOTSUPP;
7018 }
7019}
7020
7021void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7022{
7023 struct igb_adapter *adapter = hw->back;
7024
7025 pci_read_config_word(adapter->pdev, reg, value);
7026}
7027
7028void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7029{
7030 struct igb_adapter *adapter = hw->back;
7031
7032 pci_write_config_word(adapter->pdev, reg, *value);
7033}
7034
7035s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7036{
7037 struct igb_adapter *adapter = hw->back;
7038
7039 if (pcie_capability_read_word(adapter->pdev, reg, value))
7040 return -E1000_ERR_CONFIG;
7041
7042 return 0;
7043}
7044
7045s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7046{
7047 struct igb_adapter *adapter = hw->back;
7048
7049 if (pcie_capability_write_word(adapter->pdev, reg, *value))
7050 return -E1000_ERR_CONFIG;
7051
7052 return 0;
7053}
7054
7055static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
7056{
7057 struct igb_adapter *adapter = netdev_priv(netdev);
7058 struct e1000_hw *hw = &adapter->hw;
7059 u32 ctrl, rctl;
7060 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
7061
7062 if (enable) {
7063 /* enable VLAN tag insert/strip */
7064 ctrl = rd32(E1000_CTRL);
7065 ctrl |= E1000_CTRL_VME;
7066 wr32(E1000_CTRL, ctrl);
7067
7068 /* Disable CFI check */
7069 rctl = rd32(E1000_RCTL);
7070 rctl &= ~E1000_RCTL_CFIEN;
7071 wr32(E1000_RCTL, rctl);
7072 } else {
7073 /* disable VLAN tag insert/strip */
7074 ctrl = rd32(E1000_CTRL);
7075 ctrl &= ~E1000_CTRL_VME;
7076 wr32(E1000_CTRL, ctrl);
7077 }
7078}
7079
7080static int igb_vlan_rx_add_vid(struct net_device *netdev,
7081 __be16 proto, u16 vid)
7082{
7083 struct igb_adapter *adapter = netdev_priv(netdev);
7084 struct e1000_hw *hw = &adapter->hw;
7085 int pf_id = adapter->vfs_allocated_count;
7086
7087 /* add the filter since PF can receive vlans w/o entry in vlvf */
7088 igb_vfta_set(hw, vid, pf_id, true, true);
7089 set_bit(vid, adapter->active_vlans);
7090
7091 return 0;
7092}
7093
7094static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7095 __be16 proto, u16 vid)
7096{
7097 struct igb_adapter *adapter = netdev_priv(netdev);
7098 int pf_id = adapter->vfs_allocated_count;
7099 struct e1000_hw *hw = &adapter->hw;
7100
7101 /* remove VID from filter table */
7102 igb_vfta_set(hw, vid, pf_id, false, true);
7103
7104 clear_bit(vid, adapter->active_vlans);
7105
7106 return 0;
7107}
7108
7109static void igb_restore_vlan(struct igb_adapter *adapter)
7110{
7111 u16 vid = 1;
7112
7113 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7114 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
7115
7116 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
7117 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
7118}
7119
7120int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
7121{
7122 struct pci_dev *pdev = adapter->pdev;
7123 struct e1000_mac_info *mac = &adapter->hw.mac;
7124
7125 mac->autoneg = 0;
7126
7127 /* Make sure dplx is at most 1 bit and lsb of speed is not set
7128 * for the switch() below to work
7129 */
7130 if ((spd & 1) || (dplx & ~1))
7131 goto err_inval;
7132
7133 /* Fiber NIC's only allow 1000 gbps Full duplex
7134 * and 100Mbps Full duplex for 100baseFx sfp
7135 */
7136 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7137 switch (spd + dplx) {
7138 case SPEED_10 + DUPLEX_HALF:
7139 case SPEED_10 + DUPLEX_FULL:
7140 case SPEED_100 + DUPLEX_HALF:
7141 goto err_inval;
7142 default:
7143 break;
7144 }
7145 }
7146
7147 switch (spd + dplx) {
7148 case SPEED_10 + DUPLEX_HALF:
7149 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7150 break;
7151 case SPEED_10 + DUPLEX_FULL:
7152 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7153 break;
7154 case SPEED_100 + DUPLEX_HALF:
7155 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7156 break;
7157 case SPEED_100 + DUPLEX_FULL:
7158 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7159 break;
7160 case SPEED_1000 + DUPLEX_FULL:
7161 mac->autoneg = 1;
7162 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7163 break;
7164 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7165 default:
7166 goto err_inval;
7167 }
7168
7169 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7170 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7171
7172 return 0;
7173
7174err_inval:
7175 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7176 return -EINVAL;
7177}
7178
7179static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7180 bool runtime)
7181{
7182 struct net_device *netdev = pci_get_drvdata(pdev);
7183 struct igb_adapter *adapter = netdev_priv(netdev);
7184 struct e1000_hw *hw = &adapter->hw;
7185 u32 ctrl, rctl, status;
7186 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
7187#ifdef CONFIG_PM
7188 int retval = 0;
7189#endif
7190
7191 netif_device_detach(netdev);
7192
7193 if (netif_running(netdev))
7194 __igb_close(netdev, true);
7195
7196 igb_clear_interrupt_scheme(adapter);
7197
7198#ifdef CONFIG_PM
7199 retval = pci_save_state(pdev);
7200 if (retval)
7201 return retval;
7202#endif
7203
7204 status = rd32(E1000_STATUS);
7205 if (status & E1000_STATUS_LU)
7206 wufc &= ~E1000_WUFC_LNKC;
7207
7208 if (wufc) {
7209 igb_setup_rctl(adapter);
7210 igb_set_rx_mode(netdev);
7211
7212 /* turn on all-multi mode if wake on multicast is enabled */
7213 if (wufc & E1000_WUFC_MC) {
7214 rctl = rd32(E1000_RCTL);
7215 rctl |= E1000_RCTL_MPE;
7216 wr32(E1000_RCTL, rctl);
7217 }
7218
7219 ctrl = rd32(E1000_CTRL);
7220 /* advertise wake from D3Cold */
7221 #define E1000_CTRL_ADVD3WUC 0x00100000
7222 /* phy power management enable */
7223 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7224 ctrl |= E1000_CTRL_ADVD3WUC;
7225 wr32(E1000_CTRL, ctrl);
7226
7227 /* Allow time for pending master requests to run */
7228 igb_disable_pcie_master(hw);
7229
7230 wr32(E1000_WUC, E1000_WUC_PME_EN);
7231 wr32(E1000_WUFC, wufc);
7232 } else {
7233 wr32(E1000_WUC, 0);
7234 wr32(E1000_WUFC, 0);
7235 }
7236
7237 *enable_wake = wufc || adapter->en_mng_pt;
7238 if (!*enable_wake)
7239 igb_power_down_link(adapter);
7240 else
7241 igb_power_up_link(adapter);
7242
7243 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7244 * would have already happened in close and is redundant.
7245 */
7246 igb_release_hw_control(adapter);
7247
7248 pci_disable_device(pdev);
7249
7250 return 0;
7251}
7252
7253#ifdef CONFIG_PM
7254#ifdef CONFIG_PM_SLEEP
7255static int igb_suspend(struct device *dev)
7256{
7257 int retval;
7258 bool wake;
7259 struct pci_dev *pdev = to_pci_dev(dev);
7260
7261 retval = __igb_shutdown(pdev, &wake, 0);
7262 if (retval)
7263 return retval;
7264
7265 if (wake) {
7266 pci_prepare_to_sleep(pdev);
7267 } else {
7268 pci_wake_from_d3(pdev, false);
7269 pci_set_power_state(pdev, PCI_D3hot);
7270 }
7271
7272 return 0;
7273}
7274#endif /* CONFIG_PM_SLEEP */
7275
7276static int igb_resume(struct device *dev)
7277{
7278 struct pci_dev *pdev = to_pci_dev(dev);
7279 struct net_device *netdev = pci_get_drvdata(pdev);
7280 struct igb_adapter *adapter = netdev_priv(netdev);
7281 struct e1000_hw *hw = &adapter->hw;
7282 u32 err;
7283
7284 pci_set_power_state(pdev, PCI_D0);
7285 pci_restore_state(pdev);
7286 pci_save_state(pdev);
7287
7288 if (!pci_device_is_present(pdev))
7289 return -ENODEV;
7290 err = pci_enable_device_mem(pdev);
7291 if (err) {
7292 dev_err(&pdev->dev,
7293 "igb: Cannot enable PCI device from suspend\n");
7294 return err;
7295 }
7296 pci_set_master(pdev);
7297
7298 pci_enable_wake(pdev, PCI_D3hot, 0);
7299 pci_enable_wake(pdev, PCI_D3cold, 0);
7300
7301 if (igb_init_interrupt_scheme(adapter, true)) {
7302 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7303 rtnl_unlock();
7304 return -ENOMEM;
7305 }
7306
7307 igb_reset(adapter);
7308
7309 /* let the f/w know that the h/w is now under the control of the
7310 * driver.
7311 */
7312 igb_get_hw_control(adapter);
7313
7314 wr32(E1000_WUS, ~0);
7315
7316 if (netdev->flags & IFF_UP) {
7317 rtnl_lock();
7318 err = __igb_open(netdev, true);
7319 rtnl_unlock();
7320 if (err)
7321 return err;
7322 }
7323
7324 netif_device_attach(netdev);
7325 return 0;
7326}
7327
7328static int igb_runtime_idle(struct device *dev)
7329{
7330 struct pci_dev *pdev = to_pci_dev(dev);
7331 struct net_device *netdev = pci_get_drvdata(pdev);
7332 struct igb_adapter *adapter = netdev_priv(netdev);
7333
7334 if (!igb_has_link(adapter))
7335 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7336
7337 return -EBUSY;
7338}
7339
7340static int igb_runtime_suspend(struct device *dev)
7341{
7342 struct pci_dev *pdev = to_pci_dev(dev);
7343 int retval;
7344 bool wake;
7345
7346 retval = __igb_shutdown(pdev, &wake, 1);
7347 if (retval)
7348 return retval;
7349
7350 if (wake) {
7351 pci_prepare_to_sleep(pdev);
7352 } else {
7353 pci_wake_from_d3(pdev, false);
7354 pci_set_power_state(pdev, PCI_D3hot);
7355 }
7356
7357 return 0;
7358}
7359
7360static int igb_runtime_resume(struct device *dev)
7361{
7362 return igb_resume(dev);
7363}
7364#endif /* CONFIG_PM */
7365
7366static void igb_shutdown(struct pci_dev *pdev)
7367{
7368 bool wake;
7369
7370 __igb_shutdown(pdev, &wake, 0);
7371
7372 if (system_state == SYSTEM_POWER_OFF) {
7373 pci_wake_from_d3(pdev, wake);
7374 pci_set_power_state(pdev, PCI_D3hot);
7375 }
7376}
7377
7378#ifdef CONFIG_PCI_IOV
7379static int igb_sriov_reinit(struct pci_dev *dev)
7380{
7381 struct net_device *netdev = pci_get_drvdata(dev);
7382 struct igb_adapter *adapter = netdev_priv(netdev);
7383 struct pci_dev *pdev = adapter->pdev;
7384
7385 rtnl_lock();
7386
7387 if (netif_running(netdev))
7388 igb_close(netdev);
7389 else
7390 igb_reset(adapter);
7391
7392 igb_clear_interrupt_scheme(adapter);
7393
7394 igb_init_queue_configuration(adapter);
7395
7396 if (igb_init_interrupt_scheme(adapter, true)) {
7397 rtnl_unlock();
7398 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7399 return -ENOMEM;
7400 }
7401
7402 if (netif_running(netdev))
7403 igb_open(netdev);
7404
7405 rtnl_unlock();
7406
7407 return 0;
7408}
7409
7410static int igb_pci_disable_sriov(struct pci_dev *dev)
7411{
7412 int err = igb_disable_sriov(dev);
7413
7414 if (!err)
7415 err = igb_sriov_reinit(dev);
7416
7417 return err;
7418}
7419
7420static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7421{
7422 int err = igb_enable_sriov(dev, num_vfs);
7423
7424 if (err)
7425 goto out;
7426
7427 err = igb_sriov_reinit(dev);
7428 if (!err)
7429 return num_vfs;
7430
7431out:
7432 return err;
7433}
7434
7435#endif
7436static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7437{
7438#ifdef CONFIG_PCI_IOV
7439 if (num_vfs == 0)
7440 return igb_pci_disable_sriov(dev);
7441 else
7442 return igb_pci_enable_sriov(dev, num_vfs);
7443#endif
7444 return 0;
7445}
7446
7447#ifdef CONFIG_NET_POLL_CONTROLLER
7448/* Polling 'interrupt' - used by things like netconsole to send skbs
7449 * without having to re-enable interrupts. It's not called while
7450 * the interrupt routine is executing.
7451 */
7452static void igb_netpoll(struct net_device *netdev)
7453{
7454 struct igb_adapter *adapter = netdev_priv(netdev);
7455 struct e1000_hw *hw = &adapter->hw;
7456 struct igb_q_vector *q_vector;
7457 int i;
7458
7459 for (i = 0; i < adapter->num_q_vectors; i++) {
7460 q_vector = adapter->q_vector[i];
7461 if (adapter->flags & IGB_FLAG_HAS_MSIX)
7462 wr32(E1000_EIMC, q_vector->eims_value);
7463 else
7464 igb_irq_disable(adapter);
7465 napi_schedule(&q_vector->napi);
7466 }
7467}
7468#endif /* CONFIG_NET_POLL_CONTROLLER */
7469
7470/**
7471 * igb_io_error_detected - called when PCI error is detected
7472 * @pdev: Pointer to PCI device
7473 * @state: The current pci connection state
7474 *
7475 * This function is called after a PCI bus error affecting
7476 * this device has been detected.
7477 **/
7478static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7479 pci_channel_state_t state)
7480{
7481 struct net_device *netdev = pci_get_drvdata(pdev);
7482 struct igb_adapter *adapter = netdev_priv(netdev);
7483
7484 netif_device_detach(netdev);
7485
7486 if (state == pci_channel_io_perm_failure)
7487 return PCI_ERS_RESULT_DISCONNECT;
7488
7489 if (netif_running(netdev))
7490 igb_down(adapter);
7491 pci_disable_device(pdev);
7492
7493 /* Request a slot slot reset. */
7494 return PCI_ERS_RESULT_NEED_RESET;
7495}
7496
7497/**
7498 * igb_io_slot_reset - called after the pci bus has been reset.
7499 * @pdev: Pointer to PCI device
7500 *
7501 * Restart the card from scratch, as if from a cold-boot. Implementation
7502 * resembles the first-half of the igb_resume routine.
7503 **/
7504static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7505{
7506 struct net_device *netdev = pci_get_drvdata(pdev);
7507 struct igb_adapter *adapter = netdev_priv(netdev);
7508 struct e1000_hw *hw = &adapter->hw;
7509 pci_ers_result_t result;
7510 int err;
7511
7512 if (pci_enable_device_mem(pdev)) {
7513 dev_err(&pdev->dev,
7514 "Cannot re-enable PCI device after reset.\n");
7515 result = PCI_ERS_RESULT_DISCONNECT;
7516 } else {
7517 pci_set_master(pdev);
7518 pci_restore_state(pdev);
7519 pci_save_state(pdev);
7520
7521 pci_enable_wake(pdev, PCI_D3hot, 0);
7522 pci_enable_wake(pdev, PCI_D3cold, 0);
7523
7524 igb_reset(adapter);
7525 wr32(E1000_WUS, ~0);
7526 result = PCI_ERS_RESULT_RECOVERED;
7527 }
7528
7529 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7530 if (err) {
7531 dev_err(&pdev->dev,
7532 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7533 err);
7534 /* non-fatal, continue */
7535 }
7536
7537 return result;
7538}
7539
7540/**
7541 * igb_io_resume - called when traffic can start flowing again.
7542 * @pdev: Pointer to PCI device
7543 *
7544 * This callback is called when the error recovery driver tells us that
7545 * its OK to resume normal operation. Implementation resembles the
7546 * second-half of the igb_resume routine.
7547 */
7548static void igb_io_resume(struct pci_dev *pdev)
7549{
7550 struct net_device *netdev = pci_get_drvdata(pdev);
7551 struct igb_adapter *adapter = netdev_priv(netdev);
7552
7553 if (netif_running(netdev)) {
7554 if (igb_up(adapter)) {
7555 dev_err(&pdev->dev, "igb_up failed after reset\n");
7556 return;
7557 }
7558 }
7559
7560 netif_device_attach(netdev);
7561
7562 /* let the f/w know that the h/w is now under the control of the
7563 * driver.
7564 */
7565 igb_get_hw_control(adapter);
7566}
7567
7568static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7569 u8 qsel)
7570{
7571 struct e1000_hw *hw = &adapter->hw;
7572 u32 rar_low, rar_high;
7573
7574 /* HW expects these in little endian so we reverse the byte order
7575 * from network order (big endian) to CPU endian
7576 */
7577 rar_low = le32_to_cpup((__be32 *)(addr));
7578 rar_high = le16_to_cpup((__be16 *)(addr + 4));
7579
7580 /* Indicate to hardware the Address is Valid. */
7581 rar_high |= E1000_RAH_AV;
7582
7583 if (hw->mac.type == e1000_82575)
7584 rar_high |= E1000_RAH_POOL_1 * qsel;
7585 else
7586 rar_high |= E1000_RAH_POOL_1 << qsel;
7587
7588 wr32(E1000_RAL(index), rar_low);
7589 wrfl();
7590 wr32(E1000_RAH(index), rar_high);
7591 wrfl();
7592}
7593
7594static int igb_set_vf_mac(struct igb_adapter *adapter,
7595 int vf, unsigned char *mac_addr)
7596{
7597 struct e1000_hw *hw = &adapter->hw;
7598 /* VF MAC addresses start at end of receive addresses and moves
7599 * towards the first, as a result a collision should not be possible
7600 */
7601 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7602
7603 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7604
7605 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7606
7607 return 0;
7608}
7609
7610static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7611{
7612 struct igb_adapter *adapter = netdev_priv(netdev);
7613 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7614 return -EINVAL;
7615 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7616 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7617 dev_info(&adapter->pdev->dev,
7618 "Reload the VF driver to make this change effective.");
7619 if (test_bit(__IGB_DOWN, &adapter->state)) {
7620 dev_warn(&adapter->pdev->dev,
7621 "The VF MAC address has been set, but the PF device is not up.\n");
7622 dev_warn(&adapter->pdev->dev,
7623 "Bring the PF device up before attempting to use the VF device.\n");
7624 }
7625 return igb_set_vf_mac(adapter, vf, mac);
7626}
7627
7628static int igb_link_mbps(int internal_link_speed)
7629{
7630 switch (internal_link_speed) {
7631 case SPEED_100:
7632 return 100;
7633 case SPEED_1000:
7634 return 1000;
7635 default:
7636 return 0;
7637 }
7638}
7639
7640static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7641 int link_speed)
7642{
7643 int rf_dec, rf_int;
7644 u32 bcnrc_val;
7645
7646 if (tx_rate != 0) {
7647 /* Calculate the rate factor values to set */
7648 rf_int = link_speed / tx_rate;
7649 rf_dec = (link_speed - (rf_int * tx_rate));
7650 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7651 tx_rate;
7652
7653 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7654 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7655 E1000_RTTBCNRC_RF_INT_MASK);
7656 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7657 } else {
7658 bcnrc_val = 0;
7659 }
7660
7661 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7662 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7663 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7664 */
7665 wr32(E1000_RTTBCNRM, 0x14);
7666 wr32(E1000_RTTBCNRC, bcnrc_val);
7667}
7668
7669static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7670{
7671 int actual_link_speed, i;
7672 bool reset_rate = false;
7673
7674 /* VF TX rate limit was not set or not supported */
7675 if ((adapter->vf_rate_link_speed == 0) ||
7676 (adapter->hw.mac.type != e1000_82576))
7677 return;
7678
7679 actual_link_speed = igb_link_mbps(adapter->link_speed);
7680 if (actual_link_speed != adapter->vf_rate_link_speed) {
7681 reset_rate = true;
7682 adapter->vf_rate_link_speed = 0;
7683 dev_info(&adapter->pdev->dev,
7684 "Link speed has been changed. VF Transmit rate is disabled\n");
7685 }
7686
7687 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7688 if (reset_rate)
7689 adapter->vf_data[i].tx_rate = 0;
7690
7691 igb_set_vf_rate_limit(&adapter->hw, i,
7692 adapter->vf_data[i].tx_rate,
7693 actual_link_speed);
7694 }
7695}
7696
7697static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7698 int min_tx_rate, int max_tx_rate)
7699{
7700 struct igb_adapter *adapter = netdev_priv(netdev);
7701 struct e1000_hw *hw = &adapter->hw;
7702 int actual_link_speed;
7703
7704 if (hw->mac.type != e1000_82576)
7705 return -EOPNOTSUPP;
7706
7707 if (min_tx_rate)
7708 return -EINVAL;
7709
7710 actual_link_speed = igb_link_mbps(adapter->link_speed);
7711 if ((vf >= adapter->vfs_allocated_count) ||
7712 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7713 (max_tx_rate < 0) ||
7714 (max_tx_rate > actual_link_speed))
7715 return -EINVAL;
7716
7717 adapter->vf_rate_link_speed = actual_link_speed;
7718 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7719 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
7720
7721 return 0;
7722}
7723
7724static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7725 bool setting)
7726{
7727 struct igb_adapter *adapter = netdev_priv(netdev);
7728 struct e1000_hw *hw = &adapter->hw;
7729 u32 reg_val, reg_offset;
7730
7731 if (!adapter->vfs_allocated_count)
7732 return -EOPNOTSUPP;
7733
7734 if (vf >= adapter->vfs_allocated_count)
7735 return -EINVAL;
7736
7737 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7738 reg_val = rd32(reg_offset);
7739 if (setting)
7740 reg_val |= ((1 << vf) |
7741 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7742 else
7743 reg_val &= ~((1 << vf) |
7744 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7745 wr32(reg_offset, reg_val);
7746
7747 adapter->vf_data[vf].spoofchk_enabled = setting;
7748 return 0;
7749}
7750
7751static int igb_ndo_get_vf_config(struct net_device *netdev,
7752 int vf, struct ifla_vf_info *ivi)
7753{
7754 struct igb_adapter *adapter = netdev_priv(netdev);
7755 if (vf >= adapter->vfs_allocated_count)
7756 return -EINVAL;
7757 ivi->vf = vf;
7758 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7759 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
7760 ivi->min_tx_rate = 0;
7761 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7762 ivi->qos = adapter->vf_data[vf].pf_qos;
7763 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
7764 return 0;
7765}
7766
7767static void igb_vmm_control(struct igb_adapter *adapter)
7768{
7769 struct e1000_hw *hw = &adapter->hw;
7770 u32 reg;
7771
7772 switch (hw->mac.type) {
7773 case e1000_82575:
7774 case e1000_i210:
7775 case e1000_i211:
7776 case e1000_i354:
7777 default:
7778 /* replication is not supported for 82575 */
7779 return;
7780 case e1000_82576:
7781 /* notify HW that the MAC is adding vlan tags */
7782 reg = rd32(E1000_DTXCTL);
7783 reg |= E1000_DTXCTL_VLAN_ADDED;
7784 wr32(E1000_DTXCTL, reg);
7785 /* Fall through */
7786 case e1000_82580:
7787 /* enable replication vlan tag stripping */
7788 reg = rd32(E1000_RPLOLR);
7789 reg |= E1000_RPLOLR_STRVLAN;
7790 wr32(E1000_RPLOLR, reg);
7791 /* Fall through */
7792 case e1000_i350:
7793 /* none of the above registers are supported by i350 */
7794 break;
7795 }
7796
7797 if (adapter->vfs_allocated_count) {
7798 igb_vmdq_set_loopback_pf(hw, true);
7799 igb_vmdq_set_replication_pf(hw, true);
7800 igb_vmdq_set_anti_spoofing_pf(hw, true,
7801 adapter->vfs_allocated_count);
7802 } else {
7803 igb_vmdq_set_loopback_pf(hw, false);
7804 igb_vmdq_set_replication_pf(hw, false);
7805 }
7806}
7807
7808static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7809{
7810 struct e1000_hw *hw = &adapter->hw;
7811 u32 dmac_thr;
7812 u16 hwm;
7813
7814 if (hw->mac.type > e1000_82580) {
7815 if (adapter->flags & IGB_FLAG_DMAC) {
7816 u32 reg;
7817
7818 /* force threshold to 0. */
7819 wr32(E1000_DMCTXTH, 0);
7820
7821 /* DMA Coalescing high water mark needs to be greater
7822 * than the Rx threshold. Set hwm to PBA - max frame
7823 * size in 16B units, capping it at PBA - 6KB.
7824 */
7825 hwm = 64 * (pba - 6);
7826 reg = rd32(E1000_FCRTC);
7827 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7828 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7829 & E1000_FCRTC_RTH_COAL_MASK);
7830 wr32(E1000_FCRTC, reg);
7831
7832 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
7833 * frame size, capping it at PBA - 10KB.
7834 */
7835 dmac_thr = pba - 10;
7836 reg = rd32(E1000_DMACR);
7837 reg &= ~E1000_DMACR_DMACTHR_MASK;
7838 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7839 & E1000_DMACR_DMACTHR_MASK);
7840
7841 /* transition to L0x or L1 if available..*/
7842 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7843
7844 /* watchdog timer= +-1000 usec in 32usec intervals */
7845 reg |= (1000 >> 5);
7846
7847 /* Disable BMC-to-OS Watchdog Enable */
7848 if (hw->mac.type != e1000_i354)
7849 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7850
7851 wr32(E1000_DMACR, reg);
7852
7853 /* no lower threshold to disable
7854 * coalescing(smart fifb)-UTRESH=0
7855 */
7856 wr32(E1000_DMCRTRH, 0);
7857
7858 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7859
7860 wr32(E1000_DMCTLX, reg);
7861
7862 /* free space in tx packet buffer to wake from
7863 * DMA coal
7864 */
7865 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7866 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7867
7868 /* make low power state decision controlled
7869 * by DMA coal
7870 */
7871 reg = rd32(E1000_PCIEMISC);
7872 reg &= ~E1000_PCIEMISC_LX_DECISION;
7873 wr32(E1000_PCIEMISC, reg);
7874 } /* endif adapter->dmac is not disabled */
7875 } else if (hw->mac.type == e1000_82580) {
7876 u32 reg = rd32(E1000_PCIEMISC);
7877
7878 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7879 wr32(E1000_DMACR, 0);
7880 }
7881}
7882
7883/**
7884 * igb_read_i2c_byte - Reads 8 bit word over I2C
7885 * @hw: pointer to hardware structure
7886 * @byte_offset: byte offset to read
7887 * @dev_addr: device address
7888 * @data: value read
7889 *
7890 * Performs byte read operation over I2C interface at
7891 * a specified device address.
7892 **/
7893s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7894 u8 dev_addr, u8 *data)
7895{
7896 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7897 struct i2c_client *this_client = adapter->i2c_client;
7898 s32 status;
7899 u16 swfw_mask = 0;
7900
7901 if (!this_client)
7902 return E1000_ERR_I2C;
7903
7904 swfw_mask = E1000_SWFW_PHY0_SM;
7905
7906 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
7907 return E1000_ERR_SWFW_SYNC;
7908
7909 status = i2c_smbus_read_byte_data(this_client, byte_offset);
7910 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7911
7912 if (status < 0)
7913 return E1000_ERR_I2C;
7914 else {
7915 *data = status;
7916 return 0;
7917 }
7918}
7919
7920/**
7921 * igb_write_i2c_byte - Writes 8 bit word over I2C
7922 * @hw: pointer to hardware structure
7923 * @byte_offset: byte offset to write
7924 * @dev_addr: device address
7925 * @data: value to write
7926 *
7927 * Performs byte write operation over I2C interface at
7928 * a specified device address.
7929 **/
7930s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7931 u8 dev_addr, u8 data)
7932{
7933 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7934 struct i2c_client *this_client = adapter->i2c_client;
7935 s32 status;
7936 u16 swfw_mask = E1000_SWFW_PHY0_SM;
7937
7938 if (!this_client)
7939 return E1000_ERR_I2C;
7940
7941 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
7942 return E1000_ERR_SWFW_SYNC;
7943 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7944 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7945
7946 if (status)
7947 return E1000_ERR_I2C;
7948 else
7949 return 0;
7950
7951}
7952
7953int igb_reinit_queues(struct igb_adapter *adapter)
7954{
7955 struct net_device *netdev = adapter->netdev;
7956 struct pci_dev *pdev = adapter->pdev;
7957 int err = 0;
7958
7959 if (netif_running(netdev))
7960 igb_close(netdev);
7961
7962 igb_reset_interrupt_capability(adapter);
7963
7964 if (igb_init_interrupt_scheme(adapter, true)) {
7965 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7966 return -ENOMEM;
7967 }
7968
7969 if (netif_running(netdev))
7970 err = igb_open(netdev);
7971
7972 return err;
7973}
7974/* igb_main.c */
Linux kernel - Deliverables
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