| 1 | /* |
| 2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. |
| 3 | * |
| 4 | * This software is available to you under a choice of one of two |
| 5 | * licenses. You may choose to be licensed under the terms of the GNU |
| 6 | * General Public License (GPL) Version 2, available from the file |
| 7 | * COPYING in the main directory of this source tree, or the |
| 8 | * OpenIB.org BSD license below: |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or |
| 11 | * without modification, are permitted provided that the following |
| 12 | * conditions are met: |
| 13 | * |
| 14 | * - Redistributions of source code must retain the above |
| 15 | * copyright notice, this list of conditions and the following |
| 16 | * disclaimer. |
| 17 | * |
| 18 | * - Redistributions in binary form must reproduce the above |
| 19 | * copyright notice, this list of conditions and the following |
| 20 | * disclaimer in the documentation and/or other materials |
| 21 | * provided with the distribution. |
| 22 | * |
| 23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 30 | * SOFTWARE. |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #include <asm/page.h> |
| 35 | #include <linux/mlx4/cq.h> |
| 36 | #include <linux/slab.h> |
| 37 | #include <linux/mlx4/qp.h> |
| 38 | #include <linux/skbuff.h> |
| 39 | #include <linux/if_vlan.h> |
| 40 | #include <linux/prefetch.h> |
| 41 | #include <linux/vmalloc.h> |
| 42 | #include <linux/tcp.h> |
| 43 | #include <linux/ip.h> |
| 44 | #include <linux/moduleparam.h> |
| 45 | |
| 46 | #include "mlx4_en.h" |
| 47 | |
| 48 | int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, |
| 49 | struct mlx4_en_tx_ring **pring, u32 size, |
| 50 | u16 stride, int node, int queue_index) |
| 51 | { |
| 52 | struct mlx4_en_dev *mdev = priv->mdev; |
| 53 | struct mlx4_en_tx_ring *ring; |
| 54 | int tmp; |
| 55 | int err; |
| 56 | |
| 57 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); |
| 58 | if (!ring) { |
| 59 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
| 60 | if (!ring) { |
| 61 | en_err(priv, "Failed allocating TX ring\n"); |
| 62 | return -ENOMEM; |
| 63 | } |
| 64 | } |
| 65 | |
| 66 | ring->size = size; |
| 67 | ring->size_mask = size - 1; |
| 68 | ring->stride = stride; |
| 69 | |
| 70 | tmp = size * sizeof(struct mlx4_en_tx_info); |
| 71 | ring->tx_info = kmalloc_node(tmp, GFP_KERNEL | __GFP_NOWARN, node); |
| 72 | if (!ring->tx_info) { |
| 73 | ring->tx_info = vmalloc(tmp); |
| 74 | if (!ring->tx_info) { |
| 75 | err = -ENOMEM; |
| 76 | goto err_ring; |
| 77 | } |
| 78 | } |
| 79 | |
| 80 | en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", |
| 81 | ring->tx_info, tmp); |
| 82 | |
| 83 | ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node); |
| 84 | if (!ring->bounce_buf) { |
| 85 | ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); |
| 86 | if (!ring->bounce_buf) { |
| 87 | err = -ENOMEM; |
| 88 | goto err_info; |
| 89 | } |
| 90 | } |
| 91 | ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE); |
| 92 | |
| 93 | /* Allocate HW buffers on provided NUMA node */ |
| 94 | set_dev_node(&mdev->dev->pdev->dev, node); |
| 95 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size, |
| 96 | 2 * PAGE_SIZE); |
| 97 | set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node); |
| 98 | if (err) { |
| 99 | en_err(priv, "Failed allocating hwq resources\n"); |
| 100 | goto err_bounce; |
| 101 | } |
| 102 | |
| 103 | err = mlx4_en_map_buffer(&ring->wqres.buf); |
| 104 | if (err) { |
| 105 | en_err(priv, "Failed to map TX buffer\n"); |
| 106 | goto err_hwq_res; |
| 107 | } |
| 108 | |
| 109 | ring->buf = ring->wqres.buf.direct.buf; |
| 110 | |
| 111 | en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n", |
| 112 | ring, ring->buf, ring->size, ring->buf_size, |
| 113 | (unsigned long long) ring->wqres.buf.direct.map); |
| 114 | |
| 115 | err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn, |
| 116 | MLX4_RESERVE_ETH_BF_QP); |
| 117 | if (err) { |
| 118 | en_err(priv, "failed reserving qp for TX ring\n"); |
| 119 | goto err_map; |
| 120 | } |
| 121 | |
| 122 | err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp, GFP_KERNEL); |
| 123 | if (err) { |
| 124 | en_err(priv, "Failed allocating qp %d\n", ring->qpn); |
| 125 | goto err_reserve; |
| 126 | } |
| 127 | ring->qp.event = mlx4_en_sqp_event; |
| 128 | |
| 129 | err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); |
| 130 | if (err) { |
| 131 | en_dbg(DRV, priv, "working without blueflame (%d)\n", err); |
| 132 | ring->bf.uar = &mdev->priv_uar; |
| 133 | ring->bf.uar->map = mdev->uar_map; |
| 134 | ring->bf_enabled = false; |
| 135 | ring->bf_alloced = false; |
| 136 | priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; |
| 137 | } else { |
| 138 | ring->bf_alloced = true; |
| 139 | ring->bf_enabled = !!(priv->pflags & |
| 140 | MLX4_EN_PRIV_FLAGS_BLUEFLAME); |
| 141 | } |
| 142 | |
| 143 | ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; |
| 144 | ring->queue_index = queue_index; |
| 145 | |
| 146 | if (queue_index < priv->num_tx_rings_p_up && cpu_online(queue_index)) |
| 147 | cpumask_set_cpu(queue_index, &ring->affinity_mask); |
| 148 | |
| 149 | *pring = ring; |
| 150 | return 0; |
| 151 | |
| 152 | err_reserve: |
| 153 | mlx4_qp_release_range(mdev->dev, ring->qpn, 1); |
| 154 | err_map: |
| 155 | mlx4_en_unmap_buffer(&ring->wqres.buf); |
| 156 | err_hwq_res: |
| 157 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); |
| 158 | err_bounce: |
| 159 | kfree(ring->bounce_buf); |
| 160 | ring->bounce_buf = NULL; |
| 161 | err_info: |
| 162 | kvfree(ring->tx_info); |
| 163 | ring->tx_info = NULL; |
| 164 | err_ring: |
| 165 | kfree(ring); |
| 166 | *pring = NULL; |
| 167 | return err; |
| 168 | } |
| 169 | |
| 170 | void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, |
| 171 | struct mlx4_en_tx_ring **pring) |
| 172 | { |
| 173 | struct mlx4_en_dev *mdev = priv->mdev; |
| 174 | struct mlx4_en_tx_ring *ring = *pring; |
| 175 | en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); |
| 176 | |
| 177 | if (ring->bf_alloced) |
| 178 | mlx4_bf_free(mdev->dev, &ring->bf); |
| 179 | mlx4_qp_remove(mdev->dev, &ring->qp); |
| 180 | mlx4_qp_free(mdev->dev, &ring->qp); |
| 181 | mlx4_en_unmap_buffer(&ring->wqres.buf); |
| 182 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); |
| 183 | kfree(ring->bounce_buf); |
| 184 | ring->bounce_buf = NULL; |
| 185 | kvfree(ring->tx_info); |
| 186 | ring->tx_info = NULL; |
| 187 | kfree(ring); |
| 188 | *pring = NULL; |
| 189 | } |
| 190 | |
| 191 | int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, |
| 192 | struct mlx4_en_tx_ring *ring, |
| 193 | int cq, int user_prio) |
| 194 | { |
| 195 | struct mlx4_en_dev *mdev = priv->mdev; |
| 196 | int err; |
| 197 | |
| 198 | ring->cqn = cq; |
| 199 | ring->prod = 0; |
| 200 | ring->cons = 0xffffffff; |
| 201 | ring->last_nr_txbb = 1; |
| 202 | memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); |
| 203 | memset(ring->buf, 0, ring->buf_size); |
| 204 | |
| 205 | ring->qp_state = MLX4_QP_STATE_RST; |
| 206 | ring->doorbell_qpn = cpu_to_be32(ring->qp.qpn << 8); |
| 207 | ring->mr_key = cpu_to_be32(mdev->mr.key); |
| 208 | |
| 209 | mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn, |
| 210 | ring->cqn, user_prio, &ring->context); |
| 211 | if (ring->bf_alloced) |
| 212 | ring->context.usr_page = cpu_to_be32(ring->bf.uar->index); |
| 213 | |
| 214 | err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context, |
| 215 | &ring->qp, &ring->qp_state); |
| 216 | if (!user_prio && cpu_online(ring->queue_index)) |
| 217 | netif_set_xps_queue(priv->dev, &ring->affinity_mask, |
| 218 | ring->queue_index); |
| 219 | |
| 220 | return err; |
| 221 | } |
| 222 | |
| 223 | void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, |
| 224 | struct mlx4_en_tx_ring *ring) |
| 225 | { |
| 226 | struct mlx4_en_dev *mdev = priv->mdev; |
| 227 | |
| 228 | mlx4_qp_modify(mdev->dev, NULL, ring->qp_state, |
| 229 | MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp); |
| 230 | } |
| 231 | |
| 232 | static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, |
| 233 | struct mlx4_en_tx_ring *ring, int index, |
| 234 | u8 owner) |
| 235 | { |
| 236 | __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); |
| 237 | struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; |
| 238 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; |
| 239 | void *end = ring->buf + ring->buf_size; |
| 240 | __be32 *ptr = (__be32 *)tx_desc; |
| 241 | int i; |
| 242 | |
| 243 | /* Optimize the common case when there are no wraparounds */ |
| 244 | if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { |
| 245 | /* Stamp the freed descriptor */ |
| 246 | for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; |
| 247 | i += STAMP_STRIDE) { |
| 248 | *ptr = stamp; |
| 249 | ptr += STAMP_DWORDS; |
| 250 | } |
| 251 | } else { |
| 252 | /* Stamp the freed descriptor */ |
| 253 | for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; |
| 254 | i += STAMP_STRIDE) { |
| 255 | *ptr = stamp; |
| 256 | ptr += STAMP_DWORDS; |
| 257 | if ((void *)ptr >= end) { |
| 258 | ptr = ring->buf; |
| 259 | stamp ^= cpu_to_be32(0x80000000); |
| 260 | } |
| 261 | } |
| 262 | } |
| 263 | } |
| 264 | |
| 265 | |
| 266 | static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, |
| 267 | struct mlx4_en_tx_ring *ring, |
| 268 | int index, u8 owner, u64 timestamp) |
| 269 | { |
| 270 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; |
| 271 | struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; |
| 272 | struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; |
| 273 | void *end = ring->buf + ring->buf_size; |
| 274 | struct sk_buff *skb = tx_info->skb; |
| 275 | int nr_maps = tx_info->nr_maps; |
| 276 | int i; |
| 277 | |
| 278 | /* We do not touch skb here, so prefetch skb->users location |
| 279 | * to speedup consume_skb() |
| 280 | */ |
| 281 | prefetchw(&skb->users); |
| 282 | |
| 283 | if (unlikely(timestamp)) { |
| 284 | struct skb_shared_hwtstamps hwts; |
| 285 | |
| 286 | mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp); |
| 287 | skb_tstamp_tx(skb, &hwts); |
| 288 | } |
| 289 | |
| 290 | /* Optimize the common case when there are no wraparounds */ |
| 291 | if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { |
| 292 | if (!tx_info->inl) { |
| 293 | if (tx_info->linear) |
| 294 | dma_unmap_single(priv->ddev, |
| 295 | tx_info->map0_dma, |
| 296 | tx_info->map0_byte_count, |
| 297 | PCI_DMA_TODEVICE); |
| 298 | else |
| 299 | dma_unmap_page(priv->ddev, |
| 300 | tx_info->map0_dma, |
| 301 | tx_info->map0_byte_count, |
| 302 | PCI_DMA_TODEVICE); |
| 303 | for (i = 1; i < nr_maps; i++) { |
| 304 | data++; |
| 305 | dma_unmap_page(priv->ddev, |
| 306 | (dma_addr_t)be64_to_cpu(data->addr), |
| 307 | be32_to_cpu(data->byte_count), |
| 308 | PCI_DMA_TODEVICE); |
| 309 | } |
| 310 | } |
| 311 | } else { |
| 312 | if (!tx_info->inl) { |
| 313 | if ((void *) data >= end) { |
| 314 | data = ring->buf + ((void *)data - end); |
| 315 | } |
| 316 | |
| 317 | if (tx_info->linear) |
| 318 | dma_unmap_single(priv->ddev, |
| 319 | tx_info->map0_dma, |
| 320 | tx_info->map0_byte_count, |
| 321 | PCI_DMA_TODEVICE); |
| 322 | else |
| 323 | dma_unmap_page(priv->ddev, |
| 324 | tx_info->map0_dma, |
| 325 | tx_info->map0_byte_count, |
| 326 | PCI_DMA_TODEVICE); |
| 327 | for (i = 1; i < nr_maps; i++) { |
| 328 | data++; |
| 329 | /* Check for wraparound before unmapping */ |
| 330 | if ((void *) data >= end) |
| 331 | data = ring->buf; |
| 332 | dma_unmap_page(priv->ddev, |
| 333 | (dma_addr_t)be64_to_cpu(data->addr), |
| 334 | be32_to_cpu(data->byte_count), |
| 335 | PCI_DMA_TODEVICE); |
| 336 | } |
| 337 | } |
| 338 | } |
| 339 | dev_consume_skb_any(skb); |
| 340 | return tx_info->nr_txbb; |
| 341 | } |
| 342 | |
| 343 | |
| 344 | int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) |
| 345 | { |
| 346 | struct mlx4_en_priv *priv = netdev_priv(dev); |
| 347 | int cnt = 0; |
| 348 | |
| 349 | /* Skip last polled descriptor */ |
| 350 | ring->cons += ring->last_nr_txbb; |
| 351 | en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", |
| 352 | ring->cons, ring->prod); |
| 353 | |
| 354 | if ((u32) (ring->prod - ring->cons) > ring->size) { |
| 355 | if (netif_msg_tx_err(priv)) |
| 356 | en_warn(priv, "Tx consumer passed producer!\n"); |
| 357 | return 0; |
| 358 | } |
| 359 | |
| 360 | while (ring->cons != ring->prod) { |
| 361 | ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring, |
| 362 | ring->cons & ring->size_mask, |
| 363 | !!(ring->cons & ring->size), 0); |
| 364 | ring->cons += ring->last_nr_txbb; |
| 365 | cnt++; |
| 366 | } |
| 367 | |
| 368 | netdev_tx_reset_queue(ring->tx_queue); |
| 369 | |
| 370 | if (cnt) |
| 371 | en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); |
| 372 | |
| 373 | return cnt; |
| 374 | } |
| 375 | |
| 376 | static bool mlx4_en_process_tx_cq(struct net_device *dev, |
| 377 | struct mlx4_en_cq *cq) |
| 378 | { |
| 379 | struct mlx4_en_priv *priv = netdev_priv(dev); |
| 380 | struct mlx4_cq *mcq = &cq->mcq; |
| 381 | struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring]; |
| 382 | struct mlx4_cqe *cqe; |
| 383 | u16 index; |
| 384 | u16 new_index, ring_index, stamp_index; |
| 385 | u32 txbbs_skipped = 0; |
| 386 | u32 txbbs_stamp = 0; |
| 387 | u32 cons_index = mcq->cons_index; |
| 388 | int size = cq->size; |
| 389 | u32 size_mask = ring->size_mask; |
| 390 | struct mlx4_cqe *buf = cq->buf; |
| 391 | u32 packets = 0; |
| 392 | u32 bytes = 0; |
| 393 | int factor = priv->cqe_factor; |
| 394 | u64 timestamp = 0; |
| 395 | int done = 0; |
| 396 | int budget = priv->tx_work_limit; |
| 397 | u32 last_nr_txbb; |
| 398 | u32 ring_cons; |
| 399 | |
| 400 | if (!priv->port_up) |
| 401 | return true; |
| 402 | |
| 403 | netdev_txq_bql_complete_prefetchw(ring->tx_queue); |
| 404 | |
| 405 | index = cons_index & size_mask; |
| 406 | cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; |
| 407 | last_nr_txbb = ACCESS_ONCE(ring->last_nr_txbb); |
| 408 | ring_cons = ACCESS_ONCE(ring->cons); |
| 409 | ring_index = ring_cons & size_mask; |
| 410 | stamp_index = ring_index; |
| 411 | |
| 412 | /* Process all completed CQEs */ |
| 413 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, |
| 414 | cons_index & size) && (done < budget)) { |
| 415 | /* |
| 416 | * make sure we read the CQE after we read the |
| 417 | * ownership bit |
| 418 | */ |
| 419 | rmb(); |
| 420 | |
| 421 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == |
| 422 | MLX4_CQE_OPCODE_ERROR)) { |
| 423 | struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe; |
| 424 | |
| 425 | en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n", |
| 426 | cqe_err->vendor_err_syndrome, |
| 427 | cqe_err->syndrome); |
| 428 | } |
| 429 | |
| 430 | /* Skip over last polled CQE */ |
| 431 | new_index = be16_to_cpu(cqe->wqe_index) & size_mask; |
| 432 | |
| 433 | do { |
| 434 | txbbs_skipped += last_nr_txbb; |
| 435 | ring_index = (ring_index + last_nr_txbb) & size_mask; |
| 436 | if (ring->tx_info[ring_index].ts_requested) |
| 437 | timestamp = mlx4_en_get_cqe_ts(cqe); |
| 438 | |
| 439 | /* free next descriptor */ |
| 440 | last_nr_txbb = mlx4_en_free_tx_desc( |
| 441 | priv, ring, ring_index, |
| 442 | !!((ring_cons + txbbs_skipped) & |
| 443 | ring->size), timestamp); |
| 444 | |
| 445 | mlx4_en_stamp_wqe(priv, ring, stamp_index, |
| 446 | !!((ring_cons + txbbs_stamp) & |
| 447 | ring->size)); |
| 448 | stamp_index = ring_index; |
| 449 | txbbs_stamp = txbbs_skipped; |
| 450 | packets++; |
| 451 | bytes += ring->tx_info[ring_index].nr_bytes; |
| 452 | } while ((++done < budget) && (ring_index != new_index)); |
| 453 | |
| 454 | ++cons_index; |
| 455 | index = cons_index & size_mask; |
| 456 | cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; |
| 457 | } |
| 458 | |
| 459 | |
| 460 | /* |
| 461 | * To prevent CQ overflow we first update CQ consumer and only then |
| 462 | * the ring consumer. |
| 463 | */ |
| 464 | mcq->cons_index = cons_index; |
| 465 | mlx4_cq_set_ci(mcq); |
| 466 | wmb(); |
| 467 | |
| 468 | /* we want to dirty this cache line once */ |
| 469 | ACCESS_ONCE(ring->last_nr_txbb) = last_nr_txbb; |
| 470 | ACCESS_ONCE(ring->cons) = ring_cons + txbbs_skipped; |
| 471 | |
| 472 | netdev_tx_completed_queue(ring->tx_queue, packets, bytes); |
| 473 | |
| 474 | /* |
| 475 | * Wakeup Tx queue if this stopped, and at least 1 packet |
| 476 | * was completed |
| 477 | */ |
| 478 | if (netif_tx_queue_stopped(ring->tx_queue) && txbbs_skipped > 0) { |
| 479 | netif_tx_wake_queue(ring->tx_queue); |
| 480 | ring->wake_queue++; |
| 481 | } |
| 482 | return done < budget; |
| 483 | } |
| 484 | |
| 485 | void mlx4_en_tx_irq(struct mlx4_cq *mcq) |
| 486 | { |
| 487 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); |
| 488 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); |
| 489 | |
| 490 | if (likely(priv->port_up)) |
| 491 | napi_schedule_irqoff(&cq->napi); |
| 492 | else |
| 493 | mlx4_en_arm_cq(priv, cq); |
| 494 | } |
| 495 | |
| 496 | /* TX CQ polling - called by NAPI */ |
| 497 | int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget) |
| 498 | { |
| 499 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); |
| 500 | struct net_device *dev = cq->dev; |
| 501 | struct mlx4_en_priv *priv = netdev_priv(dev); |
| 502 | int clean_complete; |
| 503 | |
| 504 | clean_complete = mlx4_en_process_tx_cq(dev, cq); |
| 505 | if (!clean_complete) |
| 506 | return budget; |
| 507 | |
| 508 | napi_complete(napi); |
| 509 | mlx4_en_arm_cq(priv, cq); |
| 510 | |
| 511 | return 0; |
| 512 | } |
| 513 | |
| 514 | static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, |
| 515 | struct mlx4_en_tx_ring *ring, |
| 516 | u32 index, |
| 517 | unsigned int desc_size) |
| 518 | { |
| 519 | u32 copy = (ring->size - index) * TXBB_SIZE; |
| 520 | int i; |
| 521 | |
| 522 | for (i = desc_size - copy - 4; i >= 0; i -= 4) { |
| 523 | if ((i & (TXBB_SIZE - 1)) == 0) |
| 524 | wmb(); |
| 525 | |
| 526 | *((u32 *) (ring->buf + i)) = |
| 527 | *((u32 *) (ring->bounce_buf + copy + i)); |
| 528 | } |
| 529 | |
| 530 | for (i = copy - 4; i >= 4 ; i -= 4) { |
| 531 | if ((i & (TXBB_SIZE - 1)) == 0) |
| 532 | wmb(); |
| 533 | |
| 534 | *((u32 *) (ring->buf + index * TXBB_SIZE + i)) = |
| 535 | *((u32 *) (ring->bounce_buf + i)); |
| 536 | } |
| 537 | |
| 538 | /* Return real descriptor location */ |
| 539 | return ring->buf + index * TXBB_SIZE; |
| 540 | } |
| 541 | |
| 542 | /* Decide if skb can be inlined in tx descriptor to avoid dma mapping |
| 543 | * |
| 544 | * It seems strange we do not simply use skb_copy_bits(). |
| 545 | * This would allow to inline all skbs iff skb->len <= inline_thold |
| 546 | * |
| 547 | * Note that caller already checked skb was not a gso packet |
| 548 | */ |
| 549 | static bool is_inline(int inline_thold, const struct sk_buff *skb, |
| 550 | const struct skb_shared_info *shinfo, |
| 551 | void **pfrag) |
| 552 | { |
| 553 | void *ptr; |
| 554 | |
| 555 | if (skb->len > inline_thold || !inline_thold) |
| 556 | return false; |
| 557 | |
| 558 | if (shinfo->nr_frags == 1) { |
| 559 | ptr = skb_frag_address_safe(&shinfo->frags[0]); |
| 560 | if (unlikely(!ptr)) |
| 561 | return false; |
| 562 | *pfrag = ptr; |
| 563 | return true; |
| 564 | } |
| 565 | if (shinfo->nr_frags) |
| 566 | return false; |
| 567 | return true; |
| 568 | } |
| 569 | |
| 570 | static int inline_size(const struct sk_buff *skb) |
| 571 | { |
| 572 | if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) |
| 573 | <= MLX4_INLINE_ALIGN) |
| 574 | return ALIGN(skb->len + CTRL_SIZE + |
| 575 | sizeof(struct mlx4_wqe_inline_seg), 16); |
| 576 | else |
| 577 | return ALIGN(skb->len + CTRL_SIZE + 2 * |
| 578 | sizeof(struct mlx4_wqe_inline_seg), 16); |
| 579 | } |
| 580 | |
| 581 | static int get_real_size(const struct sk_buff *skb, |
| 582 | const struct skb_shared_info *shinfo, |
| 583 | struct net_device *dev, |
| 584 | int *lso_header_size, |
| 585 | bool *inline_ok, |
| 586 | void **pfrag) |
| 587 | { |
| 588 | struct mlx4_en_priv *priv = netdev_priv(dev); |
| 589 | int real_size; |
| 590 | |
| 591 | if (shinfo->gso_size) { |
| 592 | *inline_ok = false; |
| 593 | if (skb->encapsulation) |
| 594 | *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb); |
| 595 | else |
| 596 | *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); |
| 597 | real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE + |
| 598 | ALIGN(*lso_header_size + 4, DS_SIZE); |
| 599 | if (unlikely(*lso_header_size != skb_headlen(skb))) { |
| 600 | /* We add a segment for the skb linear buffer only if |
| 601 | * it contains data */ |
| 602 | if (*lso_header_size < skb_headlen(skb)) |
| 603 | real_size += DS_SIZE; |
| 604 | else { |
| 605 | if (netif_msg_tx_err(priv)) |
| 606 | en_warn(priv, "Non-linear headers\n"); |
| 607 | return 0; |
| 608 | } |
| 609 | } |
| 610 | } else { |
| 611 | *lso_header_size = 0; |
| 612 | *inline_ok = is_inline(priv->prof->inline_thold, skb, |
| 613 | shinfo, pfrag); |
| 614 | |
| 615 | if (*inline_ok) |
| 616 | real_size = inline_size(skb); |
| 617 | else |
| 618 | real_size = CTRL_SIZE + |
| 619 | (shinfo->nr_frags + 1) * DS_SIZE; |
| 620 | } |
| 621 | |
| 622 | return real_size; |
| 623 | } |
| 624 | |
| 625 | static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, |
| 626 | const struct sk_buff *skb, |
| 627 | const struct skb_shared_info *shinfo, |
| 628 | int real_size, u16 *vlan_tag, |
| 629 | int tx_ind, void *fragptr) |
| 630 | { |
| 631 | struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; |
| 632 | int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl; |
| 633 | unsigned int hlen = skb_headlen(skb); |
| 634 | |
| 635 | if (skb->len <= spc) { |
| 636 | if (likely(skb->len >= MIN_PKT_LEN)) { |
| 637 | inl->byte_count = cpu_to_be32(1 << 31 | skb->len); |
| 638 | } else { |
| 639 | inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN); |
| 640 | memset(((void *)(inl + 1)) + skb->len, 0, |
| 641 | MIN_PKT_LEN - skb->len); |
| 642 | } |
| 643 | skb_copy_from_linear_data(skb, inl + 1, hlen); |
| 644 | if (shinfo->nr_frags) |
| 645 | memcpy(((void *)(inl + 1)) + hlen, fragptr, |
| 646 | skb_frag_size(&shinfo->frags[0])); |
| 647 | |
| 648 | } else { |
| 649 | inl->byte_count = cpu_to_be32(1 << 31 | spc); |
| 650 | if (hlen <= spc) { |
| 651 | skb_copy_from_linear_data(skb, inl + 1, hlen); |
| 652 | if (hlen < spc) { |
| 653 | memcpy(((void *)(inl + 1)) + hlen, |
| 654 | fragptr, spc - hlen); |
| 655 | fragptr += spc - hlen; |
| 656 | } |
| 657 | inl = (void *) (inl + 1) + spc; |
| 658 | memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); |
| 659 | } else { |
| 660 | skb_copy_from_linear_data(skb, inl + 1, spc); |
| 661 | inl = (void *) (inl + 1) + spc; |
| 662 | skb_copy_from_linear_data_offset(skb, spc, inl + 1, |
| 663 | hlen - spc); |
| 664 | if (shinfo->nr_frags) |
| 665 | memcpy(((void *)(inl + 1)) + hlen - spc, |
| 666 | fragptr, |
| 667 | skb_frag_size(&shinfo->frags[0])); |
| 668 | } |
| 669 | |
| 670 | wmb(); |
| 671 | inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); |
| 672 | } |
| 673 | } |
| 674 | |
| 675 | u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, |
| 676 | void *accel_priv, select_queue_fallback_t fallback) |
| 677 | { |
| 678 | struct mlx4_en_priv *priv = netdev_priv(dev); |
| 679 | u16 rings_p_up = priv->num_tx_rings_p_up; |
| 680 | u8 up = 0; |
| 681 | |
| 682 | if (dev->num_tc) |
| 683 | return skb_tx_hash(dev, skb); |
| 684 | |
| 685 | if (vlan_tx_tag_present(skb)) |
| 686 | up = vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT; |
| 687 | |
| 688 | return fallback(dev, skb) % rings_p_up + up * rings_p_up; |
| 689 | } |
| 690 | |
| 691 | static void mlx4_bf_copy(void __iomem *dst, const void *src, |
| 692 | unsigned int bytecnt) |
| 693 | { |
| 694 | __iowrite64_copy(dst, src, bytecnt / 8); |
| 695 | } |
| 696 | |
| 697 | netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) |
| 698 | { |
| 699 | struct skb_shared_info *shinfo = skb_shinfo(skb); |
| 700 | struct mlx4_en_priv *priv = netdev_priv(dev); |
| 701 | struct device *ddev = priv->ddev; |
| 702 | struct mlx4_en_tx_ring *ring; |
| 703 | struct mlx4_en_tx_desc *tx_desc; |
| 704 | struct mlx4_wqe_data_seg *data; |
| 705 | struct mlx4_en_tx_info *tx_info; |
| 706 | int tx_ind = 0; |
| 707 | int nr_txbb; |
| 708 | int desc_size; |
| 709 | int real_size; |
| 710 | u32 index, bf_index; |
| 711 | __be32 op_own; |
| 712 | u16 vlan_tag = 0; |
| 713 | int i_frag; |
| 714 | int lso_header_size; |
| 715 | void *fragptr = NULL; |
| 716 | bool bounce = false; |
| 717 | bool send_doorbell; |
| 718 | bool stop_queue; |
| 719 | bool inline_ok; |
| 720 | u32 ring_cons; |
| 721 | |
| 722 | if (!priv->port_up) |
| 723 | goto tx_drop; |
| 724 | |
| 725 | tx_ind = skb_get_queue_mapping(skb); |
| 726 | ring = priv->tx_ring[tx_ind]; |
| 727 | |
| 728 | /* fetch ring->cons far ahead before needing it to avoid stall */ |
| 729 | ring_cons = ACCESS_ONCE(ring->cons); |
| 730 | |
| 731 | real_size = get_real_size(skb, shinfo, dev, &lso_header_size, |
| 732 | &inline_ok, &fragptr); |
| 733 | if (unlikely(!real_size)) |
| 734 | goto tx_drop; |
| 735 | |
| 736 | /* Align descriptor to TXBB size */ |
| 737 | desc_size = ALIGN(real_size, TXBB_SIZE); |
| 738 | nr_txbb = desc_size / TXBB_SIZE; |
| 739 | if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { |
| 740 | if (netif_msg_tx_err(priv)) |
| 741 | en_warn(priv, "Oversized header or SG list\n"); |
| 742 | goto tx_drop; |
| 743 | } |
| 744 | |
| 745 | if (vlan_tx_tag_present(skb)) |
| 746 | vlan_tag = vlan_tx_tag_get(skb); |
| 747 | |
| 748 | |
| 749 | netdev_txq_bql_enqueue_prefetchw(ring->tx_queue); |
| 750 | |
| 751 | /* Track current inflight packets for performance analysis */ |
| 752 | AVG_PERF_COUNTER(priv->pstats.inflight_avg, |
| 753 | (u32)(ring->prod - ring_cons - 1)); |
| 754 | |
| 755 | /* Packet is good - grab an index and transmit it */ |
| 756 | index = ring->prod & ring->size_mask; |
| 757 | bf_index = ring->prod; |
| 758 | |
| 759 | /* See if we have enough space for whole descriptor TXBB for setting |
| 760 | * SW ownership on next descriptor; if not, use a bounce buffer. */ |
| 761 | if (likely(index + nr_txbb <= ring->size)) |
| 762 | tx_desc = ring->buf + index * TXBB_SIZE; |
| 763 | else { |
| 764 | tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; |
| 765 | bounce = true; |
| 766 | } |
| 767 | |
| 768 | /* Save skb in tx_info ring */ |
| 769 | tx_info = &ring->tx_info[index]; |
| 770 | tx_info->skb = skb; |
| 771 | tx_info->nr_txbb = nr_txbb; |
| 772 | |
| 773 | data = &tx_desc->data; |
| 774 | if (lso_header_size) |
| 775 | data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4, |
| 776 | DS_SIZE)); |
| 777 | |
| 778 | /* valid only for none inline segments */ |
| 779 | tx_info->data_offset = (void *)data - (void *)tx_desc; |
| 780 | |
| 781 | tx_info->inl = inline_ok; |
| 782 | |
| 783 | tx_info->linear = (lso_header_size < skb_headlen(skb) && |
| 784 | !inline_ok) ? 1 : 0; |
| 785 | |
| 786 | tx_info->nr_maps = shinfo->nr_frags + tx_info->linear; |
| 787 | data += tx_info->nr_maps - 1; |
| 788 | |
| 789 | if (!tx_info->inl) { |
| 790 | dma_addr_t dma = 0; |
| 791 | u32 byte_count = 0; |
| 792 | |
| 793 | /* Map fragments if any */ |
| 794 | for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) { |
| 795 | const struct skb_frag_struct *frag; |
| 796 | |
| 797 | frag = &shinfo->frags[i_frag]; |
| 798 | byte_count = skb_frag_size(frag); |
| 799 | dma = skb_frag_dma_map(ddev, frag, |
| 800 | 0, byte_count, |
| 801 | DMA_TO_DEVICE); |
| 802 | if (dma_mapping_error(ddev, dma)) |
| 803 | goto tx_drop_unmap; |
| 804 | |
| 805 | data->addr = cpu_to_be64(dma); |
| 806 | data->lkey = ring->mr_key; |
| 807 | wmb(); |
| 808 | data->byte_count = cpu_to_be32(byte_count); |
| 809 | --data; |
| 810 | } |
| 811 | |
| 812 | /* Map linear part if needed */ |
| 813 | if (tx_info->linear) { |
| 814 | byte_count = skb_headlen(skb) - lso_header_size; |
| 815 | |
| 816 | dma = dma_map_single(ddev, skb->data + |
| 817 | lso_header_size, byte_count, |
| 818 | PCI_DMA_TODEVICE); |
| 819 | if (dma_mapping_error(ddev, dma)) |
| 820 | goto tx_drop_unmap; |
| 821 | |
| 822 | data->addr = cpu_to_be64(dma); |
| 823 | data->lkey = ring->mr_key; |
| 824 | wmb(); |
| 825 | data->byte_count = cpu_to_be32(byte_count); |
| 826 | } |
| 827 | /* tx completion can avoid cache line miss for common cases */ |
| 828 | tx_info->map0_dma = dma; |
| 829 | tx_info->map0_byte_count = byte_count; |
| 830 | } |
| 831 | |
| 832 | /* |
| 833 | * For timestamping add flag to skb_shinfo and |
| 834 | * set flag for further reference |
| 835 | */ |
| 836 | tx_info->ts_requested = 0; |
| 837 | if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON && |
| 838 | shinfo->tx_flags & SKBTX_HW_TSTAMP)) { |
| 839 | shinfo->tx_flags |= SKBTX_IN_PROGRESS; |
| 840 | tx_info->ts_requested = 1; |
| 841 | } |
| 842 | |
| 843 | /* Prepare ctrl segement apart opcode+ownership, which depends on |
| 844 | * whether LSO is used */ |
| 845 | tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; |
| 846 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { |
| 847 | if (!skb->encapsulation) |
| 848 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | |
| 849 | MLX4_WQE_CTRL_TCP_UDP_CSUM); |
| 850 | else |
| 851 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM); |
| 852 | ring->tx_csum++; |
| 853 | } |
| 854 | |
| 855 | if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) { |
| 856 | struct ethhdr *ethh; |
| 857 | |
| 858 | /* Copy dst mac address to wqe. This allows loopback in eSwitch, |
| 859 | * so that VFs and PF can communicate with each other |
| 860 | */ |
| 861 | ethh = (struct ethhdr *)skb->data; |
| 862 | tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest); |
| 863 | tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2)); |
| 864 | } |
| 865 | |
| 866 | /* Handle LSO (TSO) packets */ |
| 867 | if (lso_header_size) { |
| 868 | int i; |
| 869 | |
| 870 | /* Mark opcode as LSO */ |
| 871 | op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | |
| 872 | ((ring->prod & ring->size) ? |
| 873 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); |
| 874 | |
| 875 | /* Fill in the LSO prefix */ |
| 876 | tx_desc->lso.mss_hdr_size = cpu_to_be32( |
| 877 | shinfo->gso_size << 16 | lso_header_size); |
| 878 | |
| 879 | /* Copy headers; |
| 880 | * note that we already verified that it is linear */ |
| 881 | memcpy(tx_desc->lso.header, skb->data, lso_header_size); |
| 882 | |
| 883 | ring->tso_packets++; |
| 884 | |
| 885 | i = ((skb->len - lso_header_size) / shinfo->gso_size) + |
| 886 | !!((skb->len - lso_header_size) % shinfo->gso_size); |
| 887 | tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size; |
| 888 | ring->packets += i; |
| 889 | } else { |
| 890 | /* Normal (Non LSO) packet */ |
| 891 | op_own = cpu_to_be32(MLX4_OPCODE_SEND) | |
| 892 | ((ring->prod & ring->size) ? |
| 893 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); |
| 894 | tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); |
| 895 | ring->packets++; |
| 896 | } |
| 897 | ring->bytes += tx_info->nr_bytes; |
| 898 | netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes); |
| 899 | AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); |
| 900 | |
| 901 | if (tx_info->inl) |
| 902 | build_inline_wqe(tx_desc, skb, shinfo, real_size, &vlan_tag, |
| 903 | tx_ind, fragptr); |
| 904 | |
| 905 | if (skb->encapsulation) { |
| 906 | struct iphdr *ipv4 = (struct iphdr *)skb_inner_network_header(skb); |
| 907 | if (ipv4->protocol == IPPROTO_TCP || ipv4->protocol == IPPROTO_UDP) |
| 908 | op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP); |
| 909 | else |
| 910 | op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP); |
| 911 | } |
| 912 | |
| 913 | ring->prod += nr_txbb; |
| 914 | |
| 915 | /* If we used a bounce buffer then copy descriptor back into place */ |
| 916 | if (unlikely(bounce)) |
| 917 | tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); |
| 918 | |
| 919 | skb_tx_timestamp(skb); |
| 920 | |
| 921 | /* Check available TXBBs And 2K spare for prefetch */ |
| 922 | stop_queue = (int)(ring->prod - ring_cons) > |
| 923 | ring->size - HEADROOM - MAX_DESC_TXBBS; |
| 924 | if (unlikely(stop_queue)) { |
| 925 | netif_tx_stop_queue(ring->tx_queue); |
| 926 | ring->queue_stopped++; |
| 927 | } |
| 928 | send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue); |
| 929 | |
| 930 | real_size = (real_size / 16) & 0x3f; |
| 931 | |
| 932 | if (ring->bf_enabled && desc_size <= MAX_BF && !bounce && |
| 933 | !vlan_tx_tag_present(skb) && send_doorbell) { |
| 934 | tx_desc->ctrl.bf_qpn = ring->doorbell_qpn | |
| 935 | cpu_to_be32(real_size); |
| 936 | |
| 937 | op_own |= htonl((bf_index & 0xffff) << 8); |
| 938 | /* Ensure new descriptor hits memory |
| 939 | * before setting ownership of this descriptor to HW |
| 940 | */ |
| 941 | wmb(); |
| 942 | tx_desc->ctrl.owner_opcode = op_own; |
| 943 | |
| 944 | wmb(); |
| 945 | |
| 946 | mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl, |
| 947 | desc_size); |
| 948 | |
| 949 | wmb(); |
| 950 | |
| 951 | ring->bf.offset ^= ring->bf.buf_size; |
| 952 | } else { |
| 953 | tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag); |
| 954 | tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * |
| 955 | !!vlan_tx_tag_present(skb); |
| 956 | tx_desc->ctrl.fence_size = real_size; |
| 957 | |
| 958 | /* Ensure new descriptor hits memory |
| 959 | * before setting ownership of this descriptor to HW |
| 960 | */ |
| 961 | wmb(); |
| 962 | tx_desc->ctrl.owner_opcode = op_own; |
| 963 | if (send_doorbell) { |
| 964 | wmb(); |
| 965 | iowrite32(ring->doorbell_qpn, |
| 966 | ring->bf.uar->map + MLX4_SEND_DOORBELL); |
| 967 | } else { |
| 968 | ring->xmit_more++; |
| 969 | } |
| 970 | } |
| 971 | |
| 972 | if (unlikely(stop_queue)) { |
| 973 | /* If queue was emptied after the if (stop_queue) , and before |
| 974 | * the netif_tx_stop_queue() - need to wake the queue, |
| 975 | * or else it will remain stopped forever. |
| 976 | * Need a memory barrier to make sure ring->cons was not |
| 977 | * updated before queue was stopped. |
| 978 | */ |
| 979 | smp_rmb(); |
| 980 | |
| 981 | ring_cons = ACCESS_ONCE(ring->cons); |
| 982 | if (unlikely(((int)(ring->prod - ring_cons)) <= |
| 983 | ring->size - HEADROOM - MAX_DESC_TXBBS)) { |
| 984 | netif_tx_wake_queue(ring->tx_queue); |
| 985 | ring->wake_queue++; |
| 986 | } |
| 987 | } |
| 988 | return NETDEV_TX_OK; |
| 989 | |
| 990 | tx_drop_unmap: |
| 991 | en_err(priv, "DMA mapping error\n"); |
| 992 | |
| 993 | while (++i_frag < shinfo->nr_frags) { |
| 994 | ++data; |
| 995 | dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr), |
| 996 | be32_to_cpu(data->byte_count), |
| 997 | PCI_DMA_TODEVICE); |
| 998 | } |
| 999 | |
| 1000 | tx_drop: |
| 1001 | dev_kfree_skb_any(skb); |
| 1002 | priv->stats.tx_dropped++; |
| 1003 | return NETDEV_TX_OK; |
| 1004 | } |
| 1005 | |