| 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel 10 Gigabit PCI Express Linux driver |
| 4 | Copyright(c) 1999 - 2010 Intel Corporation. |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
| 23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 25 | |
| 26 | *******************************************************************************/ |
| 27 | |
| 28 | #include "ixgbe.h" |
| 29 | #include "ixgbe_type.h" |
| 30 | #include "ixgbe_dcb.h" |
| 31 | #include "ixgbe_dcb_82599.h" |
| 32 | |
| 33 | /** |
| 34 | * ixgbe_dcb_config_packet_buffers_82599 - Configure DCB packet buffers |
| 35 | * @hw: pointer to hardware structure |
| 36 | * @dcb_config: pointer to ixgbe_dcb_config structure |
| 37 | * |
| 38 | * Configure packet buffers for DCB mode. |
| 39 | */ |
| 40 | static s32 ixgbe_dcb_config_packet_buffers_82599(struct ixgbe_hw *hw, |
| 41 | struct ixgbe_dcb_config *dcb_config) |
| 42 | { |
| 43 | s32 ret_val = 0; |
| 44 | u32 value = IXGBE_RXPBSIZE_64KB; |
| 45 | u8 i = 0; |
| 46 | |
| 47 | /* Setup Rx packet buffer sizes */ |
| 48 | switch (dcb_config->rx_pba_cfg) { |
| 49 | case pba_80_48: |
| 50 | /* Setup the first four at 80KB */ |
| 51 | value = IXGBE_RXPBSIZE_80KB; |
| 52 | for (; i < 4; i++) |
| 53 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value); |
| 54 | /* Setup the last four at 48KB...don't re-init i */ |
| 55 | value = IXGBE_RXPBSIZE_48KB; |
| 56 | /* Fall Through */ |
| 57 | case pba_equal: |
| 58 | default: |
| 59 | for (; i < IXGBE_MAX_PACKET_BUFFERS; i++) |
| 60 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value); |
| 61 | |
| 62 | /* Setup Tx packet buffer sizes */ |
| 63 | for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { |
| 64 | IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), |
| 65 | IXGBE_TXPBSIZE_20KB); |
| 66 | IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), |
| 67 | IXGBE_TXPBTHRESH_DCB); |
| 68 | } |
| 69 | break; |
| 70 | } |
| 71 | |
| 72 | return ret_val; |
| 73 | } |
| 74 | |
| 75 | /** |
| 76 | * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter |
| 77 | * @hw: pointer to hardware structure |
| 78 | * @dcb_config: pointer to ixgbe_dcb_config structure |
| 79 | * |
| 80 | * Configure Rx Packet Arbiter and credits for each traffic class. |
| 81 | */ |
| 82 | static s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, |
| 83 | struct ixgbe_dcb_config *dcb_config) |
| 84 | { |
| 85 | struct tc_bw_alloc *p; |
| 86 | u32 reg = 0; |
| 87 | u32 credit_refill = 0; |
| 88 | u32 credit_max = 0; |
| 89 | u8 i = 0; |
| 90 | |
| 91 | /* |
| 92 | * Disable the arbiter before changing parameters |
| 93 | * (always enable recycle mode; WSP) |
| 94 | */ |
| 95 | reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS; |
| 96 | IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); |
| 97 | |
| 98 | /* Map all traffic classes to their UP, 1 to 1 */ |
| 99 | reg = 0; |
| 100 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) |
| 101 | reg |= (i << (i * IXGBE_RTRUP2TC_UP_SHIFT)); |
| 102 | IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); |
| 103 | |
| 104 | /* Configure traffic class credits and priority */ |
| 105 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { |
| 106 | p = &dcb_config->tc_config[i].path[DCB_RX_CONFIG]; |
| 107 | |
| 108 | credit_refill = p->data_credits_refill; |
| 109 | credit_max = p->data_credits_max; |
| 110 | reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT); |
| 111 | |
| 112 | reg |= (u32)(p->bwg_id) << IXGBE_RTRPT4C_BWG_SHIFT; |
| 113 | |
| 114 | if (p->prio_type == prio_link) |
| 115 | reg |= IXGBE_RTRPT4C_LSP; |
| 116 | |
| 117 | IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg); |
| 118 | } |
| 119 | |
| 120 | /* |
| 121 | * Configure Rx packet plane (recycle mode; WSP) and |
| 122 | * enable arbiter |
| 123 | */ |
| 124 | reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC; |
| 125 | IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); |
| 126 | |
| 127 | return 0; |
| 128 | } |
| 129 | |
| 130 | /** |
| 131 | * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter |
| 132 | * @hw: pointer to hardware structure |
| 133 | * @dcb_config: pointer to ixgbe_dcb_config structure |
| 134 | * |
| 135 | * Configure Tx Descriptor Arbiter and credits for each traffic class. |
| 136 | */ |
| 137 | static s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, |
| 138 | struct ixgbe_dcb_config *dcb_config) |
| 139 | { |
| 140 | struct tc_bw_alloc *p; |
| 141 | u32 reg, max_credits; |
| 142 | u8 i; |
| 143 | |
| 144 | /* Clear the per-Tx queue credits; we use per-TC instead */ |
| 145 | for (i = 0; i < 128; i++) { |
| 146 | IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); |
| 147 | IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0); |
| 148 | } |
| 149 | |
| 150 | /* Configure traffic class credits and priority */ |
| 151 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { |
| 152 | p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG]; |
| 153 | max_credits = dcb_config->tc_config[i].desc_credits_max; |
| 154 | reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT; |
| 155 | reg |= p->data_credits_refill; |
| 156 | reg |= (u32)(p->bwg_id) << IXGBE_RTTDT2C_BWG_SHIFT; |
| 157 | |
| 158 | if (p->prio_type == prio_group) |
| 159 | reg |= IXGBE_RTTDT2C_GSP; |
| 160 | |
| 161 | if (p->prio_type == prio_link) |
| 162 | reg |= IXGBE_RTTDT2C_LSP; |
| 163 | |
| 164 | IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg); |
| 165 | } |
| 166 | |
| 167 | /* |
| 168 | * Configure Tx descriptor plane (recycle mode; WSP) and |
| 169 | * enable arbiter |
| 170 | */ |
| 171 | reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM; |
| 172 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg); |
| 173 | |
| 174 | return 0; |
| 175 | } |
| 176 | |
| 177 | /** |
| 178 | * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter |
| 179 | * @hw: pointer to hardware structure |
| 180 | * @dcb_config: pointer to ixgbe_dcb_config structure |
| 181 | * |
| 182 | * Configure Tx Packet Arbiter and credits for each traffic class. |
| 183 | */ |
| 184 | static s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, |
| 185 | struct ixgbe_dcb_config *dcb_config) |
| 186 | { |
| 187 | struct tc_bw_alloc *p; |
| 188 | u32 reg; |
| 189 | u8 i; |
| 190 | |
| 191 | /* |
| 192 | * Disable the arbiter before changing parameters |
| 193 | * (always enable recycle mode; SP; arb delay) |
| 194 | */ |
| 195 | reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM | |
| 196 | (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) | |
| 197 | IXGBE_RTTPCS_ARBDIS; |
| 198 | IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg); |
| 199 | |
| 200 | /* Map all traffic classes to their UP, 1 to 1 */ |
| 201 | reg = 0; |
| 202 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) |
| 203 | reg |= (i << (i * IXGBE_RTTUP2TC_UP_SHIFT)); |
| 204 | IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg); |
| 205 | |
| 206 | /* Configure traffic class credits and priority */ |
| 207 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { |
| 208 | p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG]; |
| 209 | reg = p->data_credits_refill; |
| 210 | reg |= (u32)(p->data_credits_max) << IXGBE_RTTPT2C_MCL_SHIFT; |
| 211 | reg |= (u32)(p->bwg_id) << IXGBE_RTTPT2C_BWG_SHIFT; |
| 212 | |
| 213 | if (p->prio_type == prio_group) |
| 214 | reg |= IXGBE_RTTPT2C_GSP; |
| 215 | |
| 216 | if (p->prio_type == prio_link) |
| 217 | reg |= IXGBE_RTTPT2C_LSP; |
| 218 | |
| 219 | IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg); |
| 220 | } |
| 221 | |
| 222 | /* |
| 223 | * Configure Tx packet plane (recycle mode; SP; arb delay) and |
| 224 | * enable arbiter |
| 225 | */ |
| 226 | reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM | |
| 227 | (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT); |
| 228 | IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg); |
| 229 | |
| 230 | return 0; |
| 231 | } |
| 232 | |
| 233 | /** |
| 234 | * ixgbe_dcb_config_pfc_82599 - Configure priority flow control |
| 235 | * @hw: pointer to hardware structure |
| 236 | * @dcb_config: pointer to ixgbe_dcb_config structure |
| 237 | * |
| 238 | * Configure Priority Flow Control (PFC) for each traffic class. |
| 239 | */ |
| 240 | s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, |
| 241 | struct ixgbe_dcb_config *dcb_config) |
| 242 | { |
| 243 | u32 i, reg, rx_pba_size; |
| 244 | |
| 245 | /* If PFC is disabled globally then fall back to LFC. */ |
| 246 | if (!dcb_config->pfc_mode_enable) { |
| 247 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) |
| 248 | hw->mac.ops.fc_enable(hw, i); |
| 249 | goto out; |
| 250 | } |
| 251 | |
| 252 | /* Configure PFC Tx thresholds per TC */ |
| 253 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { |
| 254 | rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)); |
| 255 | rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT; |
| 256 | |
| 257 | reg = (rx_pba_size - hw->fc.low_water) << 10; |
| 258 | |
| 259 | if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full || |
| 260 | dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx) |
| 261 | reg |= IXGBE_FCRTL_XONE; |
| 262 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), reg); |
| 263 | |
| 264 | reg = (rx_pba_size - hw->fc.high_water) << 10; |
| 265 | if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full || |
| 266 | dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx) |
| 267 | reg |= IXGBE_FCRTH_FCEN; |
| 268 | IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg); |
| 269 | } |
| 270 | |
| 271 | /* Configure pause time (2 TCs per register) */ |
| 272 | reg = hw->fc.pause_time | (hw->fc.pause_time << 16); |
| 273 | for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) |
| 274 | IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); |
| 275 | |
| 276 | /* Configure flow control refresh threshold value */ |
| 277 | IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); |
| 278 | |
| 279 | /* Enable Transmit PFC */ |
| 280 | reg = IXGBE_FCCFG_TFCE_PRIORITY; |
| 281 | IXGBE_WRITE_REG(hw, IXGBE_FCCFG, reg); |
| 282 | |
| 283 | /* |
| 284 | * Enable Receive PFC |
| 285 | * We will always honor XOFF frames we receive when |
| 286 | * we are in PFC mode. |
| 287 | */ |
| 288 | reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); |
| 289 | reg &= ~IXGBE_MFLCN_RFCE; |
| 290 | reg |= IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_DPF; |
| 291 | IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg); |
| 292 | out: |
| 293 | return 0; |
| 294 | } |
| 295 | |
| 296 | /** |
| 297 | * ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics |
| 298 | * @hw: pointer to hardware structure |
| 299 | * |
| 300 | * Configure queue statistics registers, all queues belonging to same traffic |
| 301 | * class uses a single set of queue statistics counters. |
| 302 | */ |
| 303 | static s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw) |
| 304 | { |
| 305 | u32 reg = 0; |
| 306 | u8 i = 0; |
| 307 | |
| 308 | /* |
| 309 | * Receive Queues stats setting |
| 310 | * 32 RQSMR registers, each configuring 4 queues. |
| 311 | * Set all 16 queues of each TC to the same stat |
| 312 | * with TC 'n' going to stat 'n'. |
| 313 | */ |
| 314 | for (i = 0; i < 32; i++) { |
| 315 | reg = 0x01010101 * (i / 4); |
| 316 | IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); |
| 317 | } |
| 318 | /* |
| 319 | * Transmit Queues stats setting |
| 320 | * 32 TQSM registers, each controlling 4 queues. |
| 321 | * Set all queues of each TC to the same stat |
| 322 | * with TC 'n' going to stat 'n'. |
| 323 | * Tx queues are allocated non-uniformly to TCs: |
| 324 | * 32, 32, 16, 16, 8, 8, 8, 8. |
| 325 | */ |
| 326 | for (i = 0; i < 32; i++) { |
| 327 | if (i < 8) |
| 328 | reg = 0x00000000; |
| 329 | else if (i < 16) |
| 330 | reg = 0x01010101; |
| 331 | else if (i < 20) |
| 332 | reg = 0x02020202; |
| 333 | else if (i < 24) |
| 334 | reg = 0x03030303; |
| 335 | else if (i < 26) |
| 336 | reg = 0x04040404; |
| 337 | else if (i < 28) |
| 338 | reg = 0x05050505; |
| 339 | else if (i < 30) |
| 340 | reg = 0x06060606; |
| 341 | else |
| 342 | reg = 0x07070707; |
| 343 | IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg); |
| 344 | } |
| 345 | |
| 346 | return 0; |
| 347 | } |
| 348 | |
| 349 | /** |
| 350 | * ixgbe_dcb_config_82599 - Configure general DCB parameters |
| 351 | * @hw: pointer to hardware structure |
| 352 | * @dcb_config: pointer to ixgbe_dcb_config structure |
| 353 | * |
| 354 | * Configure general DCB parameters. |
| 355 | */ |
| 356 | static s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw) |
| 357 | { |
| 358 | u32 reg; |
| 359 | u32 q; |
| 360 | |
| 361 | /* Disable the Tx desc arbiter so that MTQC can be changed */ |
| 362 | reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS); |
| 363 | reg |= IXGBE_RTTDCS_ARBDIS; |
| 364 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg); |
| 365 | |
| 366 | /* Enable DCB for Rx with 8 TCs */ |
| 367 | reg = IXGBE_READ_REG(hw, IXGBE_MRQC); |
| 368 | switch (reg & IXGBE_MRQC_MRQE_MASK) { |
| 369 | case 0: |
| 370 | case IXGBE_MRQC_RT4TCEN: |
| 371 | /* RSS disabled cases */ |
| 372 | reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | IXGBE_MRQC_RT8TCEN; |
| 373 | break; |
| 374 | case IXGBE_MRQC_RSSEN: |
| 375 | case IXGBE_MRQC_RTRSS4TCEN: |
| 376 | /* RSS enabled cases */ |
| 377 | reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | IXGBE_MRQC_RTRSS8TCEN; |
| 378 | break; |
| 379 | default: |
| 380 | /* Unsupported value, assume stale data, overwrite no RSS */ |
| 381 | reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | IXGBE_MRQC_RT8TCEN; |
| 382 | } |
| 383 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg); |
| 384 | |
| 385 | /* Enable DCB for Tx with 8 TCs */ |
| 386 | reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; |
| 387 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg); |
| 388 | |
| 389 | /* Disable drop for all queues */ |
| 390 | for (q = 0; q < 128; q++) |
| 391 | IXGBE_WRITE_REG(hw, IXGBE_QDE, q << IXGBE_QDE_IDX_SHIFT); |
| 392 | |
| 393 | /* Enable the Tx desc arbiter */ |
| 394 | reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS); |
| 395 | reg &= ~IXGBE_RTTDCS_ARBDIS; |
| 396 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg); |
| 397 | |
| 398 | /* Enable Security TX Buffer IFG for DCB */ |
| 399 | reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); |
| 400 | reg |= IXGBE_SECTX_DCB; |
| 401 | IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg); |
| 402 | |
| 403 | return 0; |
| 404 | } |
| 405 | |
| 406 | /** |
| 407 | * ixgbe_dcb_hw_config_82599 - Configure and enable DCB |
| 408 | * @hw: pointer to hardware structure |
| 409 | * @dcb_config: pointer to ixgbe_dcb_config structure |
| 410 | * |
| 411 | * Configure dcb settings and enable dcb mode. |
| 412 | */ |
| 413 | s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, |
| 414 | struct ixgbe_dcb_config *dcb_config) |
| 415 | { |
| 416 | ixgbe_dcb_config_packet_buffers_82599(hw, dcb_config); |
| 417 | ixgbe_dcb_config_82599(hw); |
| 418 | ixgbe_dcb_config_rx_arbiter_82599(hw, dcb_config); |
| 419 | ixgbe_dcb_config_tx_desc_arbiter_82599(hw, dcb_config); |
| 420 | ixgbe_dcb_config_tx_data_arbiter_82599(hw, dcb_config); |
| 421 | ixgbe_dcb_config_pfc_82599(hw, dcb_config); |
| 422 | ixgbe_dcb_config_tc_stats_82599(hw); |
| 423 | |
| 424 | return 0; |
| 425 | } |
| 426 | |