| 1 | /* |
| 2 | * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports |
| 3 | * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> |
| 4 | * |
| 5 | * Based on the 64360 driver from: |
| 6 | * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> |
| 7 | * Rabeeh Khoury <rabeeh@marvell.com> |
| 8 | * |
| 9 | * Copyright (C) 2003 PMC-Sierra, Inc., |
| 10 | * written by Manish Lachwani |
| 11 | * |
| 12 | * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> |
| 13 | * |
| 14 | * Copyright (C) 2004-2006 MontaVista Software, Inc. |
| 15 | * Dale Farnsworth <dale@farnsworth.org> |
| 16 | * |
| 17 | * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> |
| 18 | * <sjhill@realitydiluted.com> |
| 19 | * |
| 20 | * Copyright (C) 2007-2008 Marvell Semiconductor |
| 21 | * Lennert Buytenhek <buytenh@marvell.com> |
| 22 | * |
| 23 | * This program is free software; you can redistribute it and/or |
| 24 | * modify it under the terms of the GNU General Public License |
| 25 | * as published by the Free Software Foundation; either version 2 |
| 26 | * of the License, or (at your option) any later version. |
| 27 | * |
| 28 | * This program is distributed in the hope that it will be useful, |
| 29 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 30 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 31 | * GNU General Public License for more details. |
| 32 | * |
| 33 | * You should have received a copy of the GNU General Public License |
| 34 | * along with this program; if not, write to the Free Software |
| 35 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 36 | */ |
| 37 | |
| 38 | #include <linux/init.h> |
| 39 | #include <linux/dma-mapping.h> |
| 40 | #include <linux/in.h> |
| 41 | #include <linux/ip.h> |
| 42 | #include <linux/tcp.h> |
| 43 | #include <linux/udp.h> |
| 44 | #include <linux/etherdevice.h> |
| 45 | #include <linux/delay.h> |
| 46 | #include <linux/ethtool.h> |
| 47 | #include <linux/platform_device.h> |
| 48 | #include <linux/module.h> |
| 49 | #include <linux/kernel.h> |
| 50 | #include <linux/spinlock.h> |
| 51 | #include <linux/workqueue.h> |
| 52 | #include <linux/phy.h> |
| 53 | #include <linux/mv643xx_eth.h> |
| 54 | #include <linux/io.h> |
| 55 | #include <linux/types.h> |
| 56 | #include <linux/inet_lro.h> |
| 57 | #include <asm/system.h> |
| 58 | |
| 59 | static char mv643xx_eth_driver_name[] = "mv643xx_eth"; |
| 60 | static char mv643xx_eth_driver_version[] = "1.4"; |
| 61 | |
| 62 | |
| 63 | /* |
| 64 | * Registers shared between all ports. |
| 65 | */ |
| 66 | #define PHY_ADDR 0x0000 |
| 67 | #define SMI_REG 0x0004 |
| 68 | #define SMI_BUSY 0x10000000 |
| 69 | #define SMI_READ_VALID 0x08000000 |
| 70 | #define SMI_OPCODE_READ 0x04000000 |
| 71 | #define SMI_OPCODE_WRITE 0x00000000 |
| 72 | #define ERR_INT_CAUSE 0x0080 |
| 73 | #define ERR_INT_SMI_DONE 0x00000010 |
| 74 | #define ERR_INT_MASK 0x0084 |
| 75 | #define WINDOW_BASE(w) (0x0200 + ((w) << 3)) |
| 76 | #define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) |
| 77 | #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) |
| 78 | #define WINDOW_BAR_ENABLE 0x0290 |
| 79 | #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) |
| 80 | |
| 81 | /* |
| 82 | * Main per-port registers. These live at offset 0x0400 for |
| 83 | * port #0, 0x0800 for port #1, and 0x0c00 for port #2. |
| 84 | */ |
| 85 | #define PORT_CONFIG 0x0000 |
| 86 | #define UNICAST_PROMISCUOUS_MODE 0x00000001 |
| 87 | #define PORT_CONFIG_EXT 0x0004 |
| 88 | #define MAC_ADDR_LOW 0x0014 |
| 89 | #define MAC_ADDR_HIGH 0x0018 |
| 90 | #define SDMA_CONFIG 0x001c |
| 91 | #define PORT_SERIAL_CONTROL 0x003c |
| 92 | #define PORT_STATUS 0x0044 |
| 93 | #define TX_FIFO_EMPTY 0x00000400 |
| 94 | #define TX_IN_PROGRESS 0x00000080 |
| 95 | #define PORT_SPEED_MASK 0x00000030 |
| 96 | #define PORT_SPEED_1000 0x00000010 |
| 97 | #define PORT_SPEED_100 0x00000020 |
| 98 | #define PORT_SPEED_10 0x00000000 |
| 99 | #define FLOW_CONTROL_ENABLED 0x00000008 |
| 100 | #define FULL_DUPLEX 0x00000004 |
| 101 | #define LINK_UP 0x00000002 |
| 102 | #define TXQ_COMMAND 0x0048 |
| 103 | #define TXQ_FIX_PRIO_CONF 0x004c |
| 104 | #define TX_BW_RATE 0x0050 |
| 105 | #define TX_BW_MTU 0x0058 |
| 106 | #define TX_BW_BURST 0x005c |
| 107 | #define INT_CAUSE 0x0060 |
| 108 | #define INT_TX_END 0x07f80000 |
| 109 | #define INT_RX 0x000003fc |
| 110 | #define INT_EXT 0x00000002 |
| 111 | #define INT_CAUSE_EXT 0x0064 |
| 112 | #define INT_EXT_LINK_PHY 0x00110000 |
| 113 | #define INT_EXT_TX 0x000000ff |
| 114 | #define INT_MASK 0x0068 |
| 115 | #define INT_MASK_EXT 0x006c |
| 116 | #define TX_FIFO_URGENT_THRESHOLD 0x0074 |
| 117 | #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc |
| 118 | #define TX_BW_RATE_MOVED 0x00e0 |
| 119 | #define TX_BW_MTU_MOVED 0x00e8 |
| 120 | #define TX_BW_BURST_MOVED 0x00ec |
| 121 | #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4)) |
| 122 | #define RXQ_COMMAND 0x0280 |
| 123 | #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2)) |
| 124 | #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4)) |
| 125 | #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4)) |
| 126 | #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4)) |
| 127 | |
| 128 | /* |
| 129 | * Misc per-port registers. |
| 130 | */ |
| 131 | #define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) |
| 132 | #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) |
| 133 | #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) |
| 134 | #define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) |
| 135 | |
| 136 | |
| 137 | /* |
| 138 | * SDMA configuration register. |
| 139 | */ |
| 140 | #define RX_BURST_SIZE_4_64BIT (2 << 1) |
| 141 | #define RX_BURST_SIZE_16_64BIT (4 << 1) |
| 142 | #define BLM_RX_NO_SWAP (1 << 4) |
| 143 | #define BLM_TX_NO_SWAP (1 << 5) |
| 144 | #define TX_BURST_SIZE_4_64BIT (2 << 22) |
| 145 | #define TX_BURST_SIZE_16_64BIT (4 << 22) |
| 146 | |
| 147 | #if defined(__BIG_ENDIAN) |
| 148 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ |
| 149 | (RX_BURST_SIZE_4_64BIT | \ |
| 150 | TX_BURST_SIZE_4_64BIT) |
| 151 | #elif defined(__LITTLE_ENDIAN) |
| 152 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ |
| 153 | (RX_BURST_SIZE_4_64BIT | \ |
| 154 | BLM_RX_NO_SWAP | \ |
| 155 | BLM_TX_NO_SWAP | \ |
| 156 | TX_BURST_SIZE_4_64BIT) |
| 157 | #else |
| 158 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined |
| 159 | #endif |
| 160 | |
| 161 | |
| 162 | /* |
| 163 | * Port serial control register. |
| 164 | */ |
| 165 | #define SET_MII_SPEED_TO_100 (1 << 24) |
| 166 | #define SET_GMII_SPEED_TO_1000 (1 << 23) |
| 167 | #define SET_FULL_DUPLEX_MODE (1 << 21) |
| 168 | #define MAX_RX_PACKET_9700BYTE (5 << 17) |
| 169 | #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13) |
| 170 | #define DO_NOT_FORCE_LINK_FAIL (1 << 10) |
| 171 | #define SERIAL_PORT_CONTROL_RESERVED (1 << 9) |
| 172 | #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) |
| 173 | #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2) |
| 174 | #define FORCE_LINK_PASS (1 << 1) |
| 175 | #define SERIAL_PORT_ENABLE (1 << 0) |
| 176 | |
| 177 | #define DEFAULT_RX_QUEUE_SIZE 128 |
| 178 | #define DEFAULT_TX_QUEUE_SIZE 256 |
| 179 | |
| 180 | |
| 181 | /* |
| 182 | * RX/TX descriptors. |
| 183 | */ |
| 184 | #if defined(__BIG_ENDIAN) |
| 185 | struct rx_desc { |
| 186 | u16 byte_cnt; /* Descriptor buffer byte count */ |
| 187 | u16 buf_size; /* Buffer size */ |
| 188 | u32 cmd_sts; /* Descriptor command status */ |
| 189 | u32 next_desc_ptr; /* Next descriptor pointer */ |
| 190 | u32 buf_ptr; /* Descriptor buffer pointer */ |
| 191 | }; |
| 192 | |
| 193 | struct tx_desc { |
| 194 | u16 byte_cnt; /* buffer byte count */ |
| 195 | u16 l4i_chk; /* CPU provided TCP checksum */ |
| 196 | u32 cmd_sts; /* Command/status field */ |
| 197 | u32 next_desc_ptr; /* Pointer to next descriptor */ |
| 198 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ |
| 199 | }; |
| 200 | #elif defined(__LITTLE_ENDIAN) |
| 201 | struct rx_desc { |
| 202 | u32 cmd_sts; /* Descriptor command status */ |
| 203 | u16 buf_size; /* Buffer size */ |
| 204 | u16 byte_cnt; /* Descriptor buffer byte count */ |
| 205 | u32 buf_ptr; /* Descriptor buffer pointer */ |
| 206 | u32 next_desc_ptr; /* Next descriptor pointer */ |
| 207 | }; |
| 208 | |
| 209 | struct tx_desc { |
| 210 | u32 cmd_sts; /* Command/status field */ |
| 211 | u16 l4i_chk; /* CPU provided TCP checksum */ |
| 212 | u16 byte_cnt; /* buffer byte count */ |
| 213 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ |
| 214 | u32 next_desc_ptr; /* Pointer to next descriptor */ |
| 215 | }; |
| 216 | #else |
| 217 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined |
| 218 | #endif |
| 219 | |
| 220 | /* RX & TX descriptor command */ |
| 221 | #define BUFFER_OWNED_BY_DMA 0x80000000 |
| 222 | |
| 223 | /* RX & TX descriptor status */ |
| 224 | #define ERROR_SUMMARY 0x00000001 |
| 225 | |
| 226 | /* RX descriptor status */ |
| 227 | #define LAYER_4_CHECKSUM_OK 0x40000000 |
| 228 | #define RX_ENABLE_INTERRUPT 0x20000000 |
| 229 | #define RX_FIRST_DESC 0x08000000 |
| 230 | #define RX_LAST_DESC 0x04000000 |
| 231 | #define RX_IP_HDR_OK 0x02000000 |
| 232 | #define RX_PKT_IS_IPV4 0x01000000 |
| 233 | #define RX_PKT_IS_ETHERNETV2 0x00800000 |
| 234 | #define RX_PKT_LAYER4_TYPE_MASK 0x00600000 |
| 235 | #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000 |
| 236 | #define RX_PKT_IS_VLAN_TAGGED 0x00080000 |
| 237 | |
| 238 | /* TX descriptor command */ |
| 239 | #define TX_ENABLE_INTERRUPT 0x00800000 |
| 240 | #define GEN_CRC 0x00400000 |
| 241 | #define TX_FIRST_DESC 0x00200000 |
| 242 | #define TX_LAST_DESC 0x00100000 |
| 243 | #define ZERO_PADDING 0x00080000 |
| 244 | #define GEN_IP_V4_CHECKSUM 0x00040000 |
| 245 | #define GEN_TCP_UDP_CHECKSUM 0x00020000 |
| 246 | #define UDP_FRAME 0x00010000 |
| 247 | #define MAC_HDR_EXTRA_4_BYTES 0x00008000 |
| 248 | #define MAC_HDR_EXTRA_8_BYTES 0x00000200 |
| 249 | |
| 250 | #define TX_IHL_SHIFT 11 |
| 251 | |
| 252 | |
| 253 | /* global *******************************************************************/ |
| 254 | struct mv643xx_eth_shared_private { |
| 255 | /* |
| 256 | * Ethernet controller base address. |
| 257 | */ |
| 258 | void __iomem *base; |
| 259 | |
| 260 | /* |
| 261 | * Points at the right SMI instance to use. |
| 262 | */ |
| 263 | struct mv643xx_eth_shared_private *smi; |
| 264 | |
| 265 | /* |
| 266 | * Provides access to local SMI interface. |
| 267 | */ |
| 268 | struct mii_bus *smi_bus; |
| 269 | |
| 270 | /* |
| 271 | * If we have access to the error interrupt pin (which is |
| 272 | * somewhat misnamed as it not only reflects internal errors |
| 273 | * but also reflects SMI completion), use that to wait for |
| 274 | * SMI access completion instead of polling the SMI busy bit. |
| 275 | */ |
| 276 | int err_interrupt; |
| 277 | wait_queue_head_t smi_busy_wait; |
| 278 | |
| 279 | /* |
| 280 | * Per-port MBUS window access register value. |
| 281 | */ |
| 282 | u32 win_protect; |
| 283 | |
| 284 | /* |
| 285 | * Hardware-specific parameters. |
| 286 | */ |
| 287 | unsigned int t_clk; |
| 288 | int extended_rx_coal_limit; |
| 289 | int tx_bw_control; |
| 290 | }; |
| 291 | |
| 292 | #define TX_BW_CONTROL_ABSENT 0 |
| 293 | #define TX_BW_CONTROL_OLD_LAYOUT 1 |
| 294 | #define TX_BW_CONTROL_NEW_LAYOUT 2 |
| 295 | |
| 296 | static int mv643xx_eth_open(struct net_device *dev); |
| 297 | static int mv643xx_eth_stop(struct net_device *dev); |
| 298 | |
| 299 | |
| 300 | /* per-port *****************************************************************/ |
| 301 | struct mib_counters { |
| 302 | u64 good_octets_received; |
| 303 | u32 bad_octets_received; |
| 304 | u32 internal_mac_transmit_err; |
| 305 | u32 good_frames_received; |
| 306 | u32 bad_frames_received; |
| 307 | u32 broadcast_frames_received; |
| 308 | u32 multicast_frames_received; |
| 309 | u32 frames_64_octets; |
| 310 | u32 frames_65_to_127_octets; |
| 311 | u32 frames_128_to_255_octets; |
| 312 | u32 frames_256_to_511_octets; |
| 313 | u32 frames_512_to_1023_octets; |
| 314 | u32 frames_1024_to_max_octets; |
| 315 | u64 good_octets_sent; |
| 316 | u32 good_frames_sent; |
| 317 | u32 excessive_collision; |
| 318 | u32 multicast_frames_sent; |
| 319 | u32 broadcast_frames_sent; |
| 320 | u32 unrec_mac_control_received; |
| 321 | u32 fc_sent; |
| 322 | u32 good_fc_received; |
| 323 | u32 bad_fc_received; |
| 324 | u32 undersize_received; |
| 325 | u32 fragments_received; |
| 326 | u32 oversize_received; |
| 327 | u32 jabber_received; |
| 328 | u32 mac_receive_error; |
| 329 | u32 bad_crc_event; |
| 330 | u32 collision; |
| 331 | u32 late_collision; |
| 332 | }; |
| 333 | |
| 334 | struct lro_counters { |
| 335 | u32 lro_aggregated; |
| 336 | u32 lro_flushed; |
| 337 | u32 lro_no_desc; |
| 338 | }; |
| 339 | |
| 340 | struct rx_queue { |
| 341 | int index; |
| 342 | |
| 343 | int rx_ring_size; |
| 344 | |
| 345 | int rx_desc_count; |
| 346 | int rx_curr_desc; |
| 347 | int rx_used_desc; |
| 348 | |
| 349 | struct rx_desc *rx_desc_area; |
| 350 | dma_addr_t rx_desc_dma; |
| 351 | int rx_desc_area_size; |
| 352 | struct sk_buff **rx_skb; |
| 353 | |
| 354 | struct net_lro_mgr lro_mgr; |
| 355 | struct net_lro_desc lro_arr[8]; |
| 356 | }; |
| 357 | |
| 358 | struct tx_queue { |
| 359 | int index; |
| 360 | |
| 361 | int tx_ring_size; |
| 362 | |
| 363 | int tx_desc_count; |
| 364 | int tx_curr_desc; |
| 365 | int tx_used_desc; |
| 366 | |
| 367 | struct tx_desc *tx_desc_area; |
| 368 | dma_addr_t tx_desc_dma; |
| 369 | int tx_desc_area_size; |
| 370 | |
| 371 | struct sk_buff_head tx_skb; |
| 372 | |
| 373 | unsigned long tx_packets; |
| 374 | unsigned long tx_bytes; |
| 375 | unsigned long tx_dropped; |
| 376 | }; |
| 377 | |
| 378 | struct mv643xx_eth_private { |
| 379 | struct mv643xx_eth_shared_private *shared; |
| 380 | void __iomem *base; |
| 381 | int port_num; |
| 382 | |
| 383 | struct net_device *dev; |
| 384 | |
| 385 | struct phy_device *phy; |
| 386 | |
| 387 | struct timer_list mib_counters_timer; |
| 388 | spinlock_t mib_counters_lock; |
| 389 | struct mib_counters mib_counters; |
| 390 | |
| 391 | struct lro_counters lro_counters; |
| 392 | |
| 393 | struct work_struct tx_timeout_task; |
| 394 | |
| 395 | struct napi_struct napi; |
| 396 | u8 oom; |
| 397 | u8 work_link; |
| 398 | u8 work_tx; |
| 399 | u8 work_tx_end; |
| 400 | u8 work_rx; |
| 401 | u8 work_rx_refill; |
| 402 | |
| 403 | int skb_size; |
| 404 | struct sk_buff_head rx_recycle; |
| 405 | |
| 406 | /* |
| 407 | * RX state. |
| 408 | */ |
| 409 | int rx_ring_size; |
| 410 | unsigned long rx_desc_sram_addr; |
| 411 | int rx_desc_sram_size; |
| 412 | int rxq_count; |
| 413 | struct timer_list rx_oom; |
| 414 | struct rx_queue rxq[8]; |
| 415 | |
| 416 | /* |
| 417 | * TX state. |
| 418 | */ |
| 419 | int tx_ring_size; |
| 420 | unsigned long tx_desc_sram_addr; |
| 421 | int tx_desc_sram_size; |
| 422 | int txq_count; |
| 423 | struct tx_queue txq[8]; |
| 424 | }; |
| 425 | |
| 426 | |
| 427 | /* port register accessors **************************************************/ |
| 428 | static inline u32 rdl(struct mv643xx_eth_private *mp, int offset) |
| 429 | { |
| 430 | return readl(mp->shared->base + offset); |
| 431 | } |
| 432 | |
| 433 | static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset) |
| 434 | { |
| 435 | return readl(mp->base + offset); |
| 436 | } |
| 437 | |
| 438 | static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data) |
| 439 | { |
| 440 | writel(data, mp->shared->base + offset); |
| 441 | } |
| 442 | |
| 443 | static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data) |
| 444 | { |
| 445 | writel(data, mp->base + offset); |
| 446 | } |
| 447 | |
| 448 | |
| 449 | /* rxq/txq helper functions *************************************************/ |
| 450 | static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq) |
| 451 | { |
| 452 | return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]); |
| 453 | } |
| 454 | |
| 455 | static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq) |
| 456 | { |
| 457 | return container_of(txq, struct mv643xx_eth_private, txq[txq->index]); |
| 458 | } |
| 459 | |
| 460 | static void rxq_enable(struct rx_queue *rxq) |
| 461 | { |
| 462 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
| 463 | wrlp(mp, RXQ_COMMAND, 1 << rxq->index); |
| 464 | } |
| 465 | |
| 466 | static void rxq_disable(struct rx_queue *rxq) |
| 467 | { |
| 468 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
| 469 | u8 mask = 1 << rxq->index; |
| 470 | |
| 471 | wrlp(mp, RXQ_COMMAND, mask << 8); |
| 472 | while (rdlp(mp, RXQ_COMMAND) & mask) |
| 473 | udelay(10); |
| 474 | } |
| 475 | |
| 476 | static void txq_reset_hw_ptr(struct tx_queue *txq) |
| 477 | { |
| 478 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
| 479 | u32 addr; |
| 480 | |
| 481 | addr = (u32)txq->tx_desc_dma; |
| 482 | addr += txq->tx_curr_desc * sizeof(struct tx_desc); |
| 483 | wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr); |
| 484 | } |
| 485 | |
| 486 | static void txq_enable(struct tx_queue *txq) |
| 487 | { |
| 488 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
| 489 | wrlp(mp, TXQ_COMMAND, 1 << txq->index); |
| 490 | } |
| 491 | |
| 492 | static void txq_disable(struct tx_queue *txq) |
| 493 | { |
| 494 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
| 495 | u8 mask = 1 << txq->index; |
| 496 | |
| 497 | wrlp(mp, TXQ_COMMAND, mask << 8); |
| 498 | while (rdlp(mp, TXQ_COMMAND) & mask) |
| 499 | udelay(10); |
| 500 | } |
| 501 | |
| 502 | static void txq_maybe_wake(struct tx_queue *txq) |
| 503 | { |
| 504 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
| 505 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
| 506 | |
| 507 | if (netif_tx_queue_stopped(nq)) { |
| 508 | __netif_tx_lock(nq, smp_processor_id()); |
| 509 | if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1) |
| 510 | netif_tx_wake_queue(nq); |
| 511 | __netif_tx_unlock(nq); |
| 512 | } |
| 513 | } |
| 514 | |
| 515 | |
| 516 | /* rx napi ******************************************************************/ |
| 517 | static int |
| 518 | mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph, |
| 519 | u64 *hdr_flags, void *priv) |
| 520 | { |
| 521 | unsigned long cmd_sts = (unsigned long)priv; |
| 522 | |
| 523 | /* |
| 524 | * Make sure that this packet is Ethernet II, is not VLAN |
| 525 | * tagged, is IPv4, has a valid IP header, and is TCP. |
| 526 | */ |
| 527 | if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 | |
| 528 | RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK | |
| 529 | RX_PKT_IS_VLAN_TAGGED)) != |
| 530 | (RX_IP_HDR_OK | RX_PKT_IS_IPV4 | |
| 531 | RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4)) |
| 532 | return -1; |
| 533 | |
| 534 | skb_reset_network_header(skb); |
| 535 | skb_set_transport_header(skb, ip_hdrlen(skb)); |
| 536 | *iphdr = ip_hdr(skb); |
| 537 | *tcph = tcp_hdr(skb); |
| 538 | *hdr_flags = LRO_IPV4 | LRO_TCP; |
| 539 | |
| 540 | return 0; |
| 541 | } |
| 542 | |
| 543 | static int rxq_process(struct rx_queue *rxq, int budget) |
| 544 | { |
| 545 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
| 546 | struct net_device_stats *stats = &mp->dev->stats; |
| 547 | int lro_flush_needed; |
| 548 | int rx; |
| 549 | |
| 550 | lro_flush_needed = 0; |
| 551 | rx = 0; |
| 552 | while (rx < budget && rxq->rx_desc_count) { |
| 553 | struct rx_desc *rx_desc; |
| 554 | unsigned int cmd_sts; |
| 555 | struct sk_buff *skb; |
| 556 | u16 byte_cnt; |
| 557 | |
| 558 | rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc]; |
| 559 | |
| 560 | cmd_sts = rx_desc->cmd_sts; |
| 561 | if (cmd_sts & BUFFER_OWNED_BY_DMA) |
| 562 | break; |
| 563 | rmb(); |
| 564 | |
| 565 | skb = rxq->rx_skb[rxq->rx_curr_desc]; |
| 566 | rxq->rx_skb[rxq->rx_curr_desc] = NULL; |
| 567 | |
| 568 | rxq->rx_curr_desc++; |
| 569 | if (rxq->rx_curr_desc == rxq->rx_ring_size) |
| 570 | rxq->rx_curr_desc = 0; |
| 571 | |
| 572 | dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr, |
| 573 | rx_desc->buf_size, DMA_FROM_DEVICE); |
| 574 | rxq->rx_desc_count--; |
| 575 | rx++; |
| 576 | |
| 577 | mp->work_rx_refill |= 1 << rxq->index; |
| 578 | |
| 579 | byte_cnt = rx_desc->byte_cnt; |
| 580 | |
| 581 | /* |
| 582 | * Update statistics. |
| 583 | * |
| 584 | * Note that the descriptor byte count includes 2 dummy |
| 585 | * bytes automatically inserted by the hardware at the |
| 586 | * start of the packet (which we don't count), and a 4 |
| 587 | * byte CRC at the end of the packet (which we do count). |
| 588 | */ |
| 589 | stats->rx_packets++; |
| 590 | stats->rx_bytes += byte_cnt - 2; |
| 591 | |
| 592 | /* |
| 593 | * In case we received a packet without first / last bits |
| 594 | * on, or the error summary bit is set, the packet needs |
| 595 | * to be dropped. |
| 596 | */ |
| 597 | if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY)) |
| 598 | != (RX_FIRST_DESC | RX_LAST_DESC)) |
| 599 | goto err; |
| 600 | |
| 601 | /* |
| 602 | * The -4 is for the CRC in the trailer of the |
| 603 | * received packet |
| 604 | */ |
| 605 | skb_put(skb, byte_cnt - 2 - 4); |
| 606 | |
| 607 | if (cmd_sts & LAYER_4_CHECKSUM_OK) |
| 608 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
| 609 | skb->protocol = eth_type_trans(skb, mp->dev); |
| 610 | |
| 611 | if (skb->dev->features & NETIF_F_LRO && |
| 612 | skb->ip_summed == CHECKSUM_UNNECESSARY) { |
| 613 | lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts); |
| 614 | lro_flush_needed = 1; |
| 615 | } else |
| 616 | netif_receive_skb(skb); |
| 617 | |
| 618 | continue; |
| 619 | |
| 620 | err: |
| 621 | stats->rx_dropped++; |
| 622 | |
| 623 | if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != |
| 624 | (RX_FIRST_DESC | RX_LAST_DESC)) { |
| 625 | if (net_ratelimit()) |
| 626 | dev_printk(KERN_ERR, &mp->dev->dev, |
| 627 | "received packet spanning " |
| 628 | "multiple descriptors\n"); |
| 629 | } |
| 630 | |
| 631 | if (cmd_sts & ERROR_SUMMARY) |
| 632 | stats->rx_errors++; |
| 633 | |
| 634 | dev_kfree_skb(skb); |
| 635 | } |
| 636 | |
| 637 | if (lro_flush_needed) |
| 638 | lro_flush_all(&rxq->lro_mgr); |
| 639 | |
| 640 | if (rx < budget) |
| 641 | mp->work_rx &= ~(1 << rxq->index); |
| 642 | |
| 643 | return rx; |
| 644 | } |
| 645 | |
| 646 | static int rxq_refill(struct rx_queue *rxq, int budget) |
| 647 | { |
| 648 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
| 649 | int refilled; |
| 650 | |
| 651 | refilled = 0; |
| 652 | while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) { |
| 653 | struct sk_buff *skb; |
| 654 | int unaligned; |
| 655 | int rx; |
| 656 | struct rx_desc *rx_desc; |
| 657 | |
| 658 | skb = __skb_dequeue(&mp->rx_recycle); |
| 659 | if (skb == NULL) |
| 660 | skb = dev_alloc_skb(mp->skb_size + |
| 661 | dma_get_cache_alignment() - 1); |
| 662 | |
| 663 | if (skb == NULL) { |
| 664 | mp->oom = 1; |
| 665 | goto oom; |
| 666 | } |
| 667 | |
| 668 | unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1); |
| 669 | if (unaligned) |
| 670 | skb_reserve(skb, dma_get_cache_alignment() - unaligned); |
| 671 | |
| 672 | refilled++; |
| 673 | rxq->rx_desc_count++; |
| 674 | |
| 675 | rx = rxq->rx_used_desc++; |
| 676 | if (rxq->rx_used_desc == rxq->rx_ring_size) |
| 677 | rxq->rx_used_desc = 0; |
| 678 | |
| 679 | rx_desc = rxq->rx_desc_area + rx; |
| 680 | |
| 681 | rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent, |
| 682 | skb->data, mp->skb_size, |
| 683 | DMA_FROM_DEVICE); |
| 684 | rx_desc->buf_size = mp->skb_size; |
| 685 | rxq->rx_skb[rx] = skb; |
| 686 | wmb(); |
| 687 | rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT; |
| 688 | wmb(); |
| 689 | |
| 690 | /* |
| 691 | * The hardware automatically prepends 2 bytes of |
| 692 | * dummy data to each received packet, so that the |
| 693 | * IP header ends up 16-byte aligned. |
| 694 | */ |
| 695 | skb_reserve(skb, 2); |
| 696 | } |
| 697 | |
| 698 | if (refilled < budget) |
| 699 | mp->work_rx_refill &= ~(1 << rxq->index); |
| 700 | |
| 701 | oom: |
| 702 | return refilled; |
| 703 | } |
| 704 | |
| 705 | |
| 706 | /* tx ***********************************************************************/ |
| 707 | static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) |
| 708 | { |
| 709 | int frag; |
| 710 | |
| 711 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
| 712 | skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; |
| 713 | if (fragp->size <= 8 && fragp->page_offset & 7) |
| 714 | return 1; |
| 715 | } |
| 716 | |
| 717 | return 0; |
| 718 | } |
| 719 | |
| 720 | static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb) |
| 721 | { |
| 722 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
| 723 | int nr_frags = skb_shinfo(skb)->nr_frags; |
| 724 | int frag; |
| 725 | |
| 726 | for (frag = 0; frag < nr_frags; frag++) { |
| 727 | skb_frag_t *this_frag; |
| 728 | int tx_index; |
| 729 | struct tx_desc *desc; |
| 730 | |
| 731 | this_frag = &skb_shinfo(skb)->frags[frag]; |
| 732 | tx_index = txq->tx_curr_desc++; |
| 733 | if (txq->tx_curr_desc == txq->tx_ring_size) |
| 734 | txq->tx_curr_desc = 0; |
| 735 | desc = &txq->tx_desc_area[tx_index]; |
| 736 | |
| 737 | /* |
| 738 | * The last fragment will generate an interrupt |
| 739 | * which will free the skb on TX completion. |
| 740 | */ |
| 741 | if (frag == nr_frags - 1) { |
| 742 | desc->cmd_sts = BUFFER_OWNED_BY_DMA | |
| 743 | ZERO_PADDING | TX_LAST_DESC | |
| 744 | TX_ENABLE_INTERRUPT; |
| 745 | } else { |
| 746 | desc->cmd_sts = BUFFER_OWNED_BY_DMA; |
| 747 | } |
| 748 | |
| 749 | desc->l4i_chk = 0; |
| 750 | desc->byte_cnt = this_frag->size; |
| 751 | desc->buf_ptr = dma_map_page(mp->dev->dev.parent, |
| 752 | this_frag->page, |
| 753 | this_frag->page_offset, |
| 754 | this_frag->size, DMA_TO_DEVICE); |
| 755 | } |
| 756 | } |
| 757 | |
| 758 | static inline __be16 sum16_as_be(__sum16 sum) |
| 759 | { |
| 760 | return (__force __be16)sum; |
| 761 | } |
| 762 | |
| 763 | static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb) |
| 764 | { |
| 765 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
| 766 | int nr_frags = skb_shinfo(skb)->nr_frags; |
| 767 | int tx_index; |
| 768 | struct tx_desc *desc; |
| 769 | u32 cmd_sts; |
| 770 | u16 l4i_chk; |
| 771 | int length; |
| 772 | |
| 773 | cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA; |
| 774 | l4i_chk = 0; |
| 775 | |
| 776 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
| 777 | int tag_bytes; |
| 778 | |
| 779 | BUG_ON(skb->protocol != htons(ETH_P_IP) && |
| 780 | skb->protocol != htons(ETH_P_8021Q)); |
| 781 | |
| 782 | tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN; |
| 783 | if (unlikely(tag_bytes & ~12)) { |
| 784 | if (skb_checksum_help(skb) == 0) |
| 785 | goto no_csum; |
| 786 | kfree_skb(skb); |
| 787 | return 1; |
| 788 | } |
| 789 | |
| 790 | if (tag_bytes & 4) |
| 791 | cmd_sts |= MAC_HDR_EXTRA_4_BYTES; |
| 792 | if (tag_bytes & 8) |
| 793 | cmd_sts |= MAC_HDR_EXTRA_8_BYTES; |
| 794 | |
| 795 | cmd_sts |= GEN_TCP_UDP_CHECKSUM | |
| 796 | GEN_IP_V4_CHECKSUM | |
| 797 | ip_hdr(skb)->ihl << TX_IHL_SHIFT; |
| 798 | |
| 799 | switch (ip_hdr(skb)->protocol) { |
| 800 | case IPPROTO_UDP: |
| 801 | cmd_sts |= UDP_FRAME; |
| 802 | l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check)); |
| 803 | break; |
| 804 | case IPPROTO_TCP: |
| 805 | l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check)); |
| 806 | break; |
| 807 | default: |
| 808 | BUG(); |
| 809 | } |
| 810 | } else { |
| 811 | no_csum: |
| 812 | /* Errata BTS #50, IHL must be 5 if no HW checksum */ |
| 813 | cmd_sts |= 5 << TX_IHL_SHIFT; |
| 814 | } |
| 815 | |
| 816 | tx_index = txq->tx_curr_desc++; |
| 817 | if (txq->tx_curr_desc == txq->tx_ring_size) |
| 818 | txq->tx_curr_desc = 0; |
| 819 | desc = &txq->tx_desc_area[tx_index]; |
| 820 | |
| 821 | if (nr_frags) { |
| 822 | txq_submit_frag_skb(txq, skb); |
| 823 | length = skb_headlen(skb); |
| 824 | } else { |
| 825 | cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT; |
| 826 | length = skb->len; |
| 827 | } |
| 828 | |
| 829 | desc->l4i_chk = l4i_chk; |
| 830 | desc->byte_cnt = length; |
| 831 | desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data, |
| 832 | length, DMA_TO_DEVICE); |
| 833 | |
| 834 | __skb_queue_tail(&txq->tx_skb, skb); |
| 835 | |
| 836 | /* ensure all other descriptors are written before first cmd_sts */ |
| 837 | wmb(); |
| 838 | desc->cmd_sts = cmd_sts; |
| 839 | |
| 840 | /* clear TX_END status */ |
| 841 | mp->work_tx_end &= ~(1 << txq->index); |
| 842 | |
| 843 | /* ensure all descriptors are written before poking hardware */ |
| 844 | wmb(); |
| 845 | txq_enable(txq); |
| 846 | |
| 847 | txq->tx_desc_count += nr_frags + 1; |
| 848 | |
| 849 | return 0; |
| 850 | } |
| 851 | |
| 852 | static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev) |
| 853 | { |
| 854 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
| 855 | int queue; |
| 856 | struct tx_queue *txq; |
| 857 | struct netdev_queue *nq; |
| 858 | |
| 859 | queue = skb_get_queue_mapping(skb); |
| 860 | txq = mp->txq + queue; |
| 861 | nq = netdev_get_tx_queue(dev, queue); |
| 862 | |
| 863 | if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { |
| 864 | txq->tx_dropped++; |
| 865 | dev_printk(KERN_DEBUG, &dev->dev, |
| 866 | "failed to linearize skb with tiny " |
| 867 | "unaligned fragment\n"); |
| 868 | return NETDEV_TX_BUSY; |
| 869 | } |
| 870 | |
| 871 | if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) { |
| 872 | if (net_ratelimit()) |
| 873 | dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n"); |
| 874 | kfree_skb(skb); |
| 875 | return NETDEV_TX_OK; |
| 876 | } |
| 877 | |
| 878 | if (!txq_submit_skb(txq, skb)) { |
| 879 | int entries_left; |
| 880 | |
| 881 | txq->tx_bytes += skb->len; |
| 882 | txq->tx_packets++; |
| 883 | dev->trans_start = jiffies; |
| 884 | |
| 885 | entries_left = txq->tx_ring_size - txq->tx_desc_count; |
| 886 | if (entries_left < MAX_SKB_FRAGS + 1) |
| 887 | netif_tx_stop_queue(nq); |
| 888 | } |
| 889 | |
| 890 | return NETDEV_TX_OK; |
| 891 | } |
| 892 | |
| 893 | |
| 894 | /* tx napi ******************************************************************/ |
| 895 | static void txq_kick(struct tx_queue *txq) |
| 896 | { |
| 897 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
| 898 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
| 899 | u32 hw_desc_ptr; |
| 900 | u32 expected_ptr; |
| 901 | |
| 902 | __netif_tx_lock(nq, smp_processor_id()); |
| 903 | |
| 904 | if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index)) |
| 905 | goto out; |
| 906 | |
| 907 | hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index)); |
| 908 | expected_ptr = (u32)txq->tx_desc_dma + |
| 909 | txq->tx_curr_desc * sizeof(struct tx_desc); |
| 910 | |
| 911 | if (hw_desc_ptr != expected_ptr) |
| 912 | txq_enable(txq); |
| 913 | |
| 914 | out: |
| 915 | __netif_tx_unlock(nq); |
| 916 | |
| 917 | mp->work_tx_end &= ~(1 << txq->index); |
| 918 | } |
| 919 | |
| 920 | static int txq_reclaim(struct tx_queue *txq, int budget, int force) |
| 921 | { |
| 922 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
| 923 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
| 924 | int reclaimed; |
| 925 | |
| 926 | __netif_tx_lock(nq, smp_processor_id()); |
| 927 | |
| 928 | reclaimed = 0; |
| 929 | while (reclaimed < budget && txq->tx_desc_count > 0) { |
| 930 | int tx_index; |
| 931 | struct tx_desc *desc; |
| 932 | u32 cmd_sts; |
| 933 | struct sk_buff *skb; |
| 934 | |
| 935 | tx_index = txq->tx_used_desc; |
| 936 | desc = &txq->tx_desc_area[tx_index]; |
| 937 | cmd_sts = desc->cmd_sts; |
| 938 | |
| 939 | if (cmd_sts & BUFFER_OWNED_BY_DMA) { |
| 940 | if (!force) |
| 941 | break; |
| 942 | desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA; |
| 943 | } |
| 944 | |
| 945 | txq->tx_used_desc = tx_index + 1; |
| 946 | if (txq->tx_used_desc == txq->tx_ring_size) |
| 947 | txq->tx_used_desc = 0; |
| 948 | |
| 949 | reclaimed++; |
| 950 | txq->tx_desc_count--; |
| 951 | |
| 952 | skb = NULL; |
| 953 | if (cmd_sts & TX_LAST_DESC) |
| 954 | skb = __skb_dequeue(&txq->tx_skb); |
| 955 | |
| 956 | if (cmd_sts & ERROR_SUMMARY) { |
| 957 | dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n"); |
| 958 | mp->dev->stats.tx_errors++; |
| 959 | } |
| 960 | |
| 961 | if (cmd_sts & TX_FIRST_DESC) { |
| 962 | dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr, |
| 963 | desc->byte_cnt, DMA_TO_DEVICE); |
| 964 | } else { |
| 965 | dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr, |
| 966 | desc->byte_cnt, DMA_TO_DEVICE); |
| 967 | } |
| 968 | |
| 969 | if (skb != NULL) { |
| 970 | if (skb_queue_len(&mp->rx_recycle) < |
| 971 | mp->rx_ring_size && |
| 972 | skb_recycle_check(skb, mp->skb_size + |
| 973 | dma_get_cache_alignment() - 1)) |
| 974 | __skb_queue_head(&mp->rx_recycle, skb); |
| 975 | else |
| 976 | dev_kfree_skb(skb); |
| 977 | } |
| 978 | } |
| 979 | |
| 980 | __netif_tx_unlock(nq); |
| 981 | |
| 982 | if (reclaimed < budget) |
| 983 | mp->work_tx &= ~(1 << txq->index); |
| 984 | |
| 985 | return reclaimed; |
| 986 | } |
| 987 | |
| 988 | |
| 989 | /* tx rate control **********************************************************/ |
| 990 | /* |
| 991 | * Set total maximum TX rate (shared by all TX queues for this port) |
| 992 | * to 'rate' bits per second, with a maximum burst of 'burst' bytes. |
| 993 | */ |
| 994 | static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst) |
| 995 | { |
| 996 | int token_rate; |
| 997 | int mtu; |
| 998 | int bucket_size; |
| 999 | |
| 1000 | token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); |
| 1001 | if (token_rate > 1023) |
| 1002 | token_rate = 1023; |
| 1003 | |
| 1004 | mtu = (mp->dev->mtu + 255) >> 8; |
| 1005 | if (mtu > 63) |
| 1006 | mtu = 63; |
| 1007 | |
| 1008 | bucket_size = (burst + 255) >> 8; |
| 1009 | if (bucket_size > 65535) |
| 1010 | bucket_size = 65535; |
| 1011 | |
| 1012 | switch (mp->shared->tx_bw_control) { |
| 1013 | case TX_BW_CONTROL_OLD_LAYOUT: |
| 1014 | wrlp(mp, TX_BW_RATE, token_rate); |
| 1015 | wrlp(mp, TX_BW_MTU, mtu); |
| 1016 | wrlp(mp, TX_BW_BURST, bucket_size); |
| 1017 | break; |
| 1018 | case TX_BW_CONTROL_NEW_LAYOUT: |
| 1019 | wrlp(mp, TX_BW_RATE_MOVED, token_rate); |
| 1020 | wrlp(mp, TX_BW_MTU_MOVED, mtu); |
| 1021 | wrlp(mp, TX_BW_BURST_MOVED, bucket_size); |
| 1022 | break; |
| 1023 | } |
| 1024 | } |
| 1025 | |
| 1026 | static void txq_set_rate(struct tx_queue *txq, int rate, int burst) |
| 1027 | { |
| 1028 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
| 1029 | int token_rate; |
| 1030 | int bucket_size; |
| 1031 | |
| 1032 | token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); |
| 1033 | if (token_rate > 1023) |
| 1034 | token_rate = 1023; |
| 1035 | |
| 1036 | bucket_size = (burst + 255) >> 8; |
| 1037 | if (bucket_size > 65535) |
| 1038 | bucket_size = 65535; |
| 1039 | |
| 1040 | wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14); |
| 1041 | wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate); |
| 1042 | } |
| 1043 | |
| 1044 | static void txq_set_fixed_prio_mode(struct tx_queue *txq) |
| 1045 | { |
| 1046 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
| 1047 | int off; |
| 1048 | u32 val; |
| 1049 | |
| 1050 | /* |
| 1051 | * Turn on fixed priority mode. |
| 1052 | */ |
| 1053 | off = 0; |
| 1054 | switch (mp->shared->tx_bw_control) { |
| 1055 | case TX_BW_CONTROL_OLD_LAYOUT: |
| 1056 | off = TXQ_FIX_PRIO_CONF; |
| 1057 | break; |
| 1058 | case TX_BW_CONTROL_NEW_LAYOUT: |
| 1059 | off = TXQ_FIX_PRIO_CONF_MOVED; |
| 1060 | break; |
| 1061 | } |
| 1062 | |
| 1063 | if (off) { |
| 1064 | val = rdlp(mp, off); |
| 1065 | val |= 1 << txq->index; |
| 1066 | wrlp(mp, off, val); |
| 1067 | } |
| 1068 | } |
| 1069 | |
| 1070 | static void txq_set_wrr(struct tx_queue *txq, int weight) |
| 1071 | { |
| 1072 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
| 1073 | int off; |
| 1074 | u32 val; |
| 1075 | |
| 1076 | /* |
| 1077 | * Turn off fixed priority mode. |
| 1078 | */ |
| 1079 | off = 0; |
| 1080 | switch (mp->shared->tx_bw_control) { |
| 1081 | case TX_BW_CONTROL_OLD_LAYOUT: |
| 1082 | off = TXQ_FIX_PRIO_CONF; |
| 1083 | break; |
| 1084 | case TX_BW_CONTROL_NEW_LAYOUT: |
| 1085 | off = TXQ_FIX_PRIO_CONF_MOVED; |
| 1086 | break; |
| 1087 | } |
| 1088 | |
| 1089 | if (off) { |
| 1090 | val = rdlp(mp, off); |
| 1091 | val &= ~(1 << txq->index); |
| 1092 | wrlp(mp, off, val); |
| 1093 | |
| 1094 | /* |
| 1095 | * Configure WRR weight for this queue. |
| 1096 | */ |
| 1097 | |
| 1098 | val = rdlp(mp, off); |
| 1099 | val = (val & ~0xff) | (weight & 0xff); |
| 1100 | wrlp(mp, TXQ_BW_WRR_CONF(txq->index), val); |
| 1101 | } |
| 1102 | } |
| 1103 | |
| 1104 | |
| 1105 | /* mii management interface *************************************************/ |
| 1106 | static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id) |
| 1107 | { |
| 1108 | struct mv643xx_eth_shared_private *msp = dev_id; |
| 1109 | |
| 1110 | if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) { |
| 1111 | writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE); |
| 1112 | wake_up(&msp->smi_busy_wait); |
| 1113 | return IRQ_HANDLED; |
| 1114 | } |
| 1115 | |
| 1116 | return IRQ_NONE; |
| 1117 | } |
| 1118 | |
| 1119 | static int smi_is_done(struct mv643xx_eth_shared_private *msp) |
| 1120 | { |
| 1121 | return !(readl(msp->base + SMI_REG) & SMI_BUSY); |
| 1122 | } |
| 1123 | |
| 1124 | static int smi_wait_ready(struct mv643xx_eth_shared_private *msp) |
| 1125 | { |
| 1126 | if (msp->err_interrupt == NO_IRQ) { |
| 1127 | int i; |
| 1128 | |
| 1129 | for (i = 0; !smi_is_done(msp); i++) { |
| 1130 | if (i == 10) |
| 1131 | return -ETIMEDOUT; |
| 1132 | msleep(10); |
| 1133 | } |
| 1134 | |
| 1135 | return 0; |
| 1136 | } |
| 1137 | |
| 1138 | if (!smi_is_done(msp)) { |
| 1139 | wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp), |
| 1140 | msecs_to_jiffies(100)); |
| 1141 | if (!smi_is_done(msp)) |
| 1142 | return -ETIMEDOUT; |
| 1143 | } |
| 1144 | |
| 1145 | return 0; |
| 1146 | } |
| 1147 | |
| 1148 | static int smi_bus_read(struct mii_bus *bus, int addr, int reg) |
| 1149 | { |
| 1150 | struct mv643xx_eth_shared_private *msp = bus->priv; |
| 1151 | void __iomem *smi_reg = msp->base + SMI_REG; |
| 1152 | int ret; |
| 1153 | |
| 1154 | if (smi_wait_ready(msp)) { |
| 1155 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
| 1156 | return -ETIMEDOUT; |
| 1157 | } |
| 1158 | |
| 1159 | writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg); |
| 1160 | |
| 1161 | if (smi_wait_ready(msp)) { |
| 1162 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
| 1163 | return -ETIMEDOUT; |
| 1164 | } |
| 1165 | |
| 1166 | ret = readl(smi_reg); |
| 1167 | if (!(ret & SMI_READ_VALID)) { |
| 1168 | printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n"); |
| 1169 | return -ENODEV; |
| 1170 | } |
| 1171 | |
| 1172 | return ret & 0xffff; |
| 1173 | } |
| 1174 | |
| 1175 | static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val) |
| 1176 | { |
| 1177 | struct mv643xx_eth_shared_private *msp = bus->priv; |
| 1178 | void __iomem *smi_reg = msp->base + SMI_REG; |
| 1179 | |
| 1180 | if (smi_wait_ready(msp)) { |
| 1181 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
| 1182 | return -ETIMEDOUT; |
| 1183 | } |
| 1184 | |
| 1185 | writel(SMI_OPCODE_WRITE | (reg << 21) | |
| 1186 | (addr << 16) | (val & 0xffff), smi_reg); |
| 1187 | |
| 1188 | if (smi_wait_ready(msp)) { |
| 1189 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
| 1190 | return -ETIMEDOUT; |
| 1191 | } |
| 1192 | |
| 1193 | return 0; |
| 1194 | } |
| 1195 | |
| 1196 | |
| 1197 | /* statistics ***************************************************************/ |
| 1198 | static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev) |
| 1199 | { |
| 1200 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
| 1201 | struct net_device_stats *stats = &dev->stats; |
| 1202 | unsigned long tx_packets = 0; |
| 1203 | unsigned long tx_bytes = 0; |
| 1204 | unsigned long tx_dropped = 0; |
| 1205 | int i; |
| 1206 | |
| 1207 | for (i = 0; i < mp->txq_count; i++) { |
| 1208 | struct tx_queue *txq = mp->txq + i; |
| 1209 | |
| 1210 | tx_packets += txq->tx_packets; |
| 1211 | tx_bytes += txq->tx_bytes; |
| 1212 | tx_dropped += txq->tx_dropped; |
| 1213 | } |
| 1214 | |
| 1215 | stats->tx_packets = tx_packets; |
| 1216 | stats->tx_bytes = tx_bytes; |
| 1217 | stats->tx_dropped = tx_dropped; |
| 1218 | |
| 1219 | return stats; |
| 1220 | } |
| 1221 | |
| 1222 | static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp) |
| 1223 | { |
| 1224 | u32 lro_aggregated = 0; |
| 1225 | u32 lro_flushed = 0; |
| 1226 | u32 lro_no_desc = 0; |
| 1227 | int i; |
| 1228 | |
| 1229 | for (i = 0; i < mp->rxq_count; i++) { |
| 1230 | struct rx_queue *rxq = mp->rxq + i; |
| 1231 | |
| 1232 | lro_aggregated += rxq->lro_mgr.stats.aggregated; |
| 1233 | lro_flushed += rxq->lro_mgr.stats.flushed; |
| 1234 | lro_no_desc += rxq->lro_mgr.stats.no_desc; |
| 1235 | } |
| 1236 | |
| 1237 | mp->lro_counters.lro_aggregated = lro_aggregated; |
| 1238 | mp->lro_counters.lro_flushed = lro_flushed; |
| 1239 | mp->lro_counters.lro_no_desc = lro_no_desc; |
| 1240 | } |
| 1241 | |
| 1242 | static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset) |
| 1243 | { |
| 1244 | return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); |
| 1245 | } |
| 1246 | |
| 1247 | static void mib_counters_clear(struct mv643xx_eth_private *mp) |
| 1248 | { |
| 1249 | int i; |
| 1250 | |
| 1251 | for (i = 0; i < 0x80; i += 4) |
| 1252 | mib_read(mp, i); |
| 1253 | } |
| 1254 | |
| 1255 | static void mib_counters_update(struct mv643xx_eth_private *mp) |
| 1256 | { |
| 1257 | struct mib_counters *p = &mp->mib_counters; |
| 1258 | |
| 1259 | spin_lock_bh(&mp->mib_counters_lock); |
| 1260 | p->good_octets_received += mib_read(mp, 0x00); |
| 1261 | p->bad_octets_received += mib_read(mp, 0x08); |
| 1262 | p->internal_mac_transmit_err += mib_read(mp, 0x0c); |
| 1263 | p->good_frames_received += mib_read(mp, 0x10); |
| 1264 | p->bad_frames_received += mib_read(mp, 0x14); |
| 1265 | p->broadcast_frames_received += mib_read(mp, 0x18); |
| 1266 | p->multicast_frames_received += mib_read(mp, 0x1c); |
| 1267 | p->frames_64_octets += mib_read(mp, 0x20); |
| 1268 | p->frames_65_to_127_octets += mib_read(mp, 0x24); |
| 1269 | p->frames_128_to_255_octets += mib_read(mp, 0x28); |
| 1270 | p->frames_256_to_511_octets += mib_read(mp, 0x2c); |
| 1271 | p->frames_512_to_1023_octets += mib_read(mp, 0x30); |
| 1272 | p->frames_1024_to_max_octets += mib_read(mp, 0x34); |
| 1273 | p->good_octets_sent += mib_read(mp, 0x38); |
| 1274 | p->good_frames_sent += mib_read(mp, 0x40); |
| 1275 | p->excessive_collision += mib_read(mp, 0x44); |
| 1276 | p->multicast_frames_sent += mib_read(mp, 0x48); |
| 1277 | p->broadcast_frames_sent += mib_read(mp, 0x4c); |
| 1278 | p->unrec_mac_control_received += mib_read(mp, 0x50); |
| 1279 | p->fc_sent += mib_read(mp, 0x54); |
| 1280 | p->good_fc_received += mib_read(mp, 0x58); |
| 1281 | p->bad_fc_received += mib_read(mp, 0x5c); |
| 1282 | p->undersize_received += mib_read(mp, 0x60); |
| 1283 | p->fragments_received += mib_read(mp, 0x64); |
| 1284 | p->oversize_received += mib_read(mp, 0x68); |
| 1285 | p->jabber_received += mib_read(mp, 0x6c); |
| 1286 | p->mac_receive_error += mib_read(mp, 0x70); |
| 1287 | p->bad_crc_event += mib_read(mp, 0x74); |
| 1288 | p->collision += mib_read(mp, 0x78); |
| 1289 | p->late_collision += mib_read(mp, 0x7c); |
| 1290 | spin_unlock_bh(&mp->mib_counters_lock); |
| 1291 | |
| 1292 | mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ); |
| 1293 | } |
| 1294 | |
| 1295 | static void mib_counters_timer_wrapper(unsigned long _mp) |
| 1296 | { |
| 1297 | struct mv643xx_eth_private *mp = (void *)_mp; |
| 1298 | |
| 1299 | mib_counters_update(mp); |
| 1300 | } |
| 1301 | |
| 1302 | |
| 1303 | /* interrupt coalescing *****************************************************/ |
| 1304 | /* |
| 1305 | * Hardware coalescing parameters are set in units of 64 t_clk |
| 1306 | * cycles. I.e.: |
| 1307 | * |
| 1308 | * coal_delay_in_usec = 64000000 * register_value / t_clk_rate |
| 1309 | * |
| 1310 | * register_value = coal_delay_in_usec * t_clk_rate / 64000000 |
| 1311 | * |
| 1312 | * In the ->set*() methods, we round the computed register value |
| 1313 | * to the nearest integer. |
| 1314 | */ |
| 1315 | static unsigned int get_rx_coal(struct mv643xx_eth_private *mp) |
| 1316 | { |
| 1317 | u32 val = rdlp(mp, SDMA_CONFIG); |
| 1318 | u64 temp; |
| 1319 | |
| 1320 | if (mp->shared->extended_rx_coal_limit) |
| 1321 | temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7); |
| 1322 | else |
| 1323 | temp = (val & 0x003fff00) >> 8; |
| 1324 | |
| 1325 | temp *= 64000000; |
| 1326 | do_div(temp, mp->shared->t_clk); |
| 1327 | |
| 1328 | return (unsigned int)temp; |
| 1329 | } |
| 1330 | |
| 1331 | static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec) |
| 1332 | { |
| 1333 | u64 temp; |
| 1334 | u32 val; |
| 1335 | |
| 1336 | temp = (u64)usec * mp->shared->t_clk; |
| 1337 | temp += 31999999; |
| 1338 | do_div(temp, 64000000); |
| 1339 | |
| 1340 | val = rdlp(mp, SDMA_CONFIG); |
| 1341 | if (mp->shared->extended_rx_coal_limit) { |
| 1342 | if (temp > 0xffff) |
| 1343 | temp = 0xffff; |
| 1344 | val &= ~0x023fff80; |
| 1345 | val |= (temp & 0x8000) << 10; |
| 1346 | val |= (temp & 0x7fff) << 7; |
| 1347 | } else { |
| 1348 | if (temp > 0x3fff) |
| 1349 | temp = 0x3fff; |
| 1350 | val &= ~0x003fff00; |
| 1351 | val |= (temp & 0x3fff) << 8; |
| 1352 | } |
| 1353 | wrlp(mp, SDMA_CONFIG, val); |
| 1354 | } |
| 1355 | |
| 1356 | static unsigned int get_tx_coal(struct mv643xx_eth_private *mp) |
| 1357 | { |
| 1358 | u64 temp; |
| 1359 | |
| 1360 | temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4; |
| 1361 | temp *= 64000000; |
| 1362 | do_div(temp, mp->shared->t_clk); |
| 1363 | |
| 1364 | return (unsigned int)temp; |
| 1365 | } |
| 1366 | |
| 1367 | static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec) |
| 1368 | { |
| 1369 | u64 temp; |
| 1370 | |
| 1371 | temp = (u64)usec * mp->shared->t_clk; |
| 1372 | temp += 31999999; |
| 1373 | do_div(temp, 64000000); |
| 1374 | |
| 1375 | if (temp > 0x3fff) |
| 1376 | temp = 0x3fff; |
| 1377 | |
| 1378 | wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4); |
| 1379 | } |
| 1380 | |
| 1381 | |
| 1382 | /* ethtool ******************************************************************/ |
| 1383 | struct mv643xx_eth_stats { |
| 1384 | char stat_string[ETH_GSTRING_LEN]; |
| 1385 | int sizeof_stat; |
| 1386 | int netdev_off; |
| 1387 | int mp_off; |
| 1388 | }; |
| 1389 | |
| 1390 | #define SSTAT(m) \ |
| 1391 | { #m, FIELD_SIZEOF(struct net_device_stats, m), \ |
| 1392 | offsetof(struct net_device, stats.m), -1 } |
| 1393 | |
| 1394 | #define MIBSTAT(m) \ |
| 1395 | { #m, FIELD_SIZEOF(struct mib_counters, m), \ |
| 1396 | -1, offsetof(struct mv643xx_eth_private, mib_counters.m) } |
| 1397 | |
| 1398 | #define LROSTAT(m) \ |
| 1399 | { #m, FIELD_SIZEOF(struct lro_counters, m), \ |
| 1400 | -1, offsetof(struct mv643xx_eth_private, lro_counters.m) } |
| 1401 | |
| 1402 | static const struct mv643xx_eth_stats mv643xx_eth_stats[] = { |
| 1403 | SSTAT(rx_packets), |
| 1404 | SSTAT(tx_packets), |
| 1405 | SSTAT(rx_bytes), |
| 1406 | SSTAT(tx_bytes), |
| 1407 | SSTAT(rx_errors), |
| 1408 | SSTAT(tx_errors), |
| 1409 | SSTAT(rx_dropped), |
| 1410 | SSTAT(tx_dropped), |
| 1411 | MIBSTAT(good_octets_received), |
| 1412 | MIBSTAT(bad_octets_received), |
| 1413 | MIBSTAT(internal_mac_transmit_err), |
| 1414 | MIBSTAT(good_frames_received), |
| 1415 | MIBSTAT(bad_frames_received), |
| 1416 | MIBSTAT(broadcast_frames_received), |
| 1417 | MIBSTAT(multicast_frames_received), |
| 1418 | MIBSTAT(frames_64_octets), |
| 1419 | MIBSTAT(frames_65_to_127_octets), |
| 1420 | MIBSTAT(frames_128_to_255_octets), |
| 1421 | MIBSTAT(frames_256_to_511_octets), |
| 1422 | MIBSTAT(frames_512_to_1023_octets), |
| 1423 | MIBSTAT(frames_1024_to_max_octets), |
| 1424 | MIBSTAT(good_octets_sent), |
| 1425 | MIBSTAT(good_frames_sent), |
| 1426 | MIBSTAT(excessive_collision), |
| 1427 | MIBSTAT(multicast_frames_sent), |
| 1428 | MIBSTAT(broadcast_frames_sent), |
| 1429 | MIBSTAT(unrec_mac_control_received), |
| 1430 | MIBSTAT(fc_sent), |
| 1431 | MIBSTAT(good_fc_received), |
| 1432 | MIBSTAT(bad_fc_received), |
| 1433 | MIBSTAT(undersize_received), |
| 1434 | MIBSTAT(fragments_received), |
| 1435 | MIBSTAT(oversize_received), |
| 1436 | MIBSTAT(jabber_received), |
| 1437 | MIBSTAT(mac_receive_error), |
| 1438 | MIBSTAT(bad_crc_event), |
| 1439 | MIBSTAT(collision), |
| 1440 | MIBSTAT(late_collision), |
| 1441 | LROSTAT(lro_aggregated), |
| 1442 | LROSTAT(lro_flushed), |
| 1443 | LROSTAT(lro_no_desc), |
| 1444 | }; |
| 1445 | |
| 1446 | static int |
| 1447 | mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp, |
| 1448 | struct ethtool_cmd *cmd) |
| 1449 | { |
| 1450 | int err; |
| 1451 | |
| 1452 | err = phy_read_status(mp->phy); |
| 1453 | if (err == 0) |
| 1454 | err = phy_ethtool_gset(mp->phy, cmd); |
| 1455 | |
| 1456 | /* |
| 1457 | * The MAC does not support 1000baseT_Half. |
| 1458 | */ |
| 1459 | cmd->supported &= ~SUPPORTED_1000baseT_Half; |
| 1460 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; |
| 1461 | |
| 1462 | return err; |
| 1463 | } |
| 1464 | |
| 1465 | static int |
| 1466 | mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp, |
| 1467 | struct ethtool_cmd *cmd) |
| 1468 | { |
| 1469 | u32 port_status; |
| 1470 | |
| 1471 | port_status = rdlp(mp, PORT_STATUS); |
| 1472 | |
| 1473 | cmd->supported = SUPPORTED_MII; |
| 1474 | cmd->advertising = ADVERTISED_MII; |
| 1475 | switch (port_status & PORT_SPEED_MASK) { |
| 1476 | case PORT_SPEED_10: |
| 1477 | cmd->speed = SPEED_10; |
| 1478 | break; |
| 1479 | case PORT_SPEED_100: |
| 1480 | cmd->speed = SPEED_100; |
| 1481 | break; |
| 1482 | case PORT_SPEED_1000: |
| 1483 | cmd->speed = SPEED_1000; |
| 1484 | break; |
| 1485 | default: |
| 1486 | cmd->speed = -1; |
| 1487 | break; |
| 1488 | } |
| 1489 | cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF; |
| 1490 | cmd->port = PORT_MII; |
| 1491 | cmd->phy_address = 0; |
| 1492 | cmd->transceiver = XCVR_INTERNAL; |
| 1493 | cmd->autoneg = AUTONEG_DISABLE; |
| 1494 | cmd->maxtxpkt = 1; |
| 1495 | cmd->maxrxpkt = 1; |
| 1496 | |
| 1497 | return 0; |
| 1498 | } |
| 1499 | |
| 1500 | static int |
| 1501 | mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
| 1502 | { |
| 1503 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
| 1504 | |
| 1505 | if (mp->phy != NULL) |
| 1506 | return mv643xx_eth_get_settings_phy(mp, cmd); |
| 1507 | else |
| 1508 | return mv643xx_eth_get_settings_phyless(mp, cmd); |
| 1509 | } |
| 1510 | |
| 1511 | static int |
| 1512 | mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
| 1513 | { |
| 1514 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
| 1515 | |
| 1516 | if (mp->phy == NULL) |
| 1517 | return -EINVAL; |
| 1518 | |
| 1519 | /* |
| 1520 | * The MAC does not support 1000baseT_Half. |
| 1521 | */ |
| 1522 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; |
| 1523 | |
| 1524 | return phy_ethtool_sset(mp->phy, cmd); |
| 1525 | } |
| 1526 | |
| 1527 | static void mv643xx_eth_get_drvinfo(struct net_device *dev, |
| 1528 | struct ethtool_drvinfo *drvinfo) |
| 1529 | { |
| 1530 | strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32); |
| 1531 | strncpy(drvinfo->version, mv643xx_eth_driver_version, 32); |
| 1532 | strncpy(drvinfo->fw_version, "N/A", 32); |
| 1533 | strncpy(drvinfo->bus_info, "platform", 32); |
| 1534 | drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats); |
| 1535 | } |
| 1536 | |
| 1537 | static int mv643xx_eth_nway_reset(struct net_device *dev) |
| 1538 | { |
| 1539 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
| 1540 | |
| 1541 | if (mp->phy == NULL) |
| 1542 | return -EINVAL; |
| 1543 | |
| 1544 | return genphy_restart_aneg(mp->phy); |
| 1545 | } |
| 1546 | |
| 1547 | static u32 mv643xx_eth_get_link(struct net_device *dev) |
| 1548 | { |
| 1549 | return !!netif_carrier_ok(dev); |
| 1550 | } |
| 1551 | |
| 1552 | static int |
| 1553 | mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
| 1554 | { |
| 1555 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
| 1556 | |
| 1557 | ec->rx_coalesce_usecs = get_rx_coal(mp); |
| 1558 | ec->tx_coalesce_usecs = get_tx_coal(mp); |
| 1559 | |
| 1560 | return 0; |
| 1561 | } |
| 1562 | |
| 1563 | static int |
| 1564 | mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
| 1565 | { |
| 1566 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
| 1567 | |
| 1568 | set_rx_coal(mp, ec->rx_coalesce_usecs); |
| 1569 | set_tx_coal(mp, ec->tx_coalesce_usecs); |
| 1570 | |
| 1571 | return 0; |
| 1572 | } |
| 1573 | |
| 1574 | static void |
| 1575 | mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er) |
| 1576 | { |
| 1577 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
| 1578 | |
| 1579 | er->rx_max_pending = 4096; |
| 1580 | er->tx_max_pending = 4096; |
| 1581 | er->rx_mini_max_pending = 0; |
| 1582 | er->rx_jumbo_max_pending = 0; |
| 1583 | |
| 1584 | er->rx_pending = mp->rx_ring_size; |
| 1585 | er->tx_pending = mp->tx_ring_size; |
| 1586 | er->rx_mini_pending = 0; |
| 1587 | er->rx_jumbo_pending = 0; |
| 1588 | } |
| 1589 | |
| 1590 | static int |
| 1591 | mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er) |
| 1592 | { |
| 1593 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
| 1594 | |
| 1595 | if (er->rx_mini_pending || er->rx_jumbo_pending) |
| 1596 | return -EINVAL; |
| 1597 | |
| 1598 | mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096; |
| 1599 | mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096; |
| 1600 | |
| 1601 | if (netif_running(dev)) { |
| 1602 | mv643xx_eth_stop(dev); |
| 1603 | if (mv643xx_eth_open(dev)) { |
| 1604 | dev_printk(KERN_ERR, &dev->dev, |
| 1605 | "fatal error on re-opening device after " |
| 1606 | "ring param change\n"); |
| 1607 | return -ENOMEM; |
| 1608 | } |
| 1609 | } |
| 1610 | |
| 1611 | return 0; |
| 1612 | } |
| 1613 | |
| 1614 | static u32 |
| 1615 | mv643xx_eth_get_rx_csum(struct net_device *dev) |
| 1616 | { |
| 1617 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
| 1618 | |
| 1619 | return !!(rdlp(mp, PORT_CONFIG) & 0x02000000); |
| 1620 | } |
| 1621 | |
| 1622 | static int |
| 1623 | mv643xx_eth_set_rx_csum(struct net_device *dev, u32 rx_csum) |
| 1624 | { |
| 1625 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
| 1626 | |
| 1627 | wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000); |
| 1628 | |
| 1629 | return 0; |
| 1630 | } |
| 1631 | |
| 1632 | static void mv643xx_eth_get_strings(struct net_device *dev, |
| 1633 | uint32_t stringset, uint8_t *data) |
| 1634 | { |
| 1635 | int i; |
| 1636 | |
| 1637 | if (stringset == ETH_SS_STATS) { |
| 1638 | for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { |
| 1639 | memcpy(data + i * ETH_GSTRING_LEN, |
| 1640 | mv643xx_eth_stats[i].stat_string, |
| 1641 | ETH_GSTRING_LEN); |
| 1642 | } |
| 1643 | } |
| 1644 | } |
| 1645 | |
| 1646 | static void mv643xx_eth_get_ethtool_stats(struct net_device *dev, |
| 1647 | struct ethtool_stats *stats, |
| 1648 | uint64_t *data) |
| 1649 | { |
| 1650 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
| 1651 | int i; |
| 1652 | |
| 1653 | mv643xx_eth_get_stats(dev); |
| 1654 | mib_counters_update(mp); |
| 1655 | mv643xx_eth_grab_lro_stats(mp); |
| 1656 | |
| 1657 | for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { |
| 1658 | const struct mv643xx_eth_stats *stat; |
| 1659 | void *p; |
| 1660 | |
| 1661 | stat = mv643xx_eth_stats + i; |
| 1662 | |
| 1663 | if (stat->netdev_off >= 0) |
| 1664 | p = ((void *)mp->dev) + stat->netdev_off; |
| 1665 | else |
| 1666 | p = ((void *)mp) + stat->mp_off; |
| 1667 | |
| 1668 | data[i] = (stat->sizeof_stat == 8) ? |
| 1669 | *(uint64_t *)p : *(uint32_t *)p; |
| 1670 | } |
| 1671 | } |
| 1672 | |
| 1673 | static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset) |
| 1674 | { |
| 1675 | if (sset == ETH_SS_STATS) |
| 1676 | return ARRAY_SIZE(mv643xx_eth_stats); |
| 1677 | |
| 1678 | return -EOPNOTSUPP; |
| 1679 | } |
| 1680 | |
| 1681 | static const struct ethtool_ops mv643xx_eth_ethtool_ops = { |
| 1682 | .get_settings = mv643xx_eth_get_settings, |
| 1683 | .set_settings = mv643xx_eth_set_settings, |
| 1684 | .get_drvinfo = mv643xx_eth_get_drvinfo, |
| 1685 | .nway_reset = mv643xx_eth_nway_reset, |
| 1686 | .get_link = mv643xx_eth_get_link, |
| 1687 | .get_coalesce = mv643xx_eth_get_coalesce, |
| 1688 | .set_coalesce = mv643xx_eth_set_coalesce, |
| 1689 | .get_ringparam = mv643xx_eth_get_ringparam, |
| 1690 | .set_ringparam = mv643xx_eth_set_ringparam, |
| 1691 | .get_rx_csum = mv643xx_eth_get_rx_csum, |
| 1692 | .set_rx_csum = mv643xx_eth_set_rx_csum, |
| 1693 | .set_tx_csum = ethtool_op_set_tx_csum, |
| 1694 | .set_sg = ethtool_op_set_sg, |
| 1695 | .get_strings = mv643xx_eth_get_strings, |
| 1696 | .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, |
| 1697 | .get_flags = ethtool_op_get_flags, |
| 1698 | .set_flags = ethtool_op_set_flags, |
| 1699 | .get_sset_count = mv643xx_eth_get_sset_count, |
| 1700 | }; |
| 1701 | |
| 1702 | |
| 1703 | /* address handling *********************************************************/ |
| 1704 | static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr) |
| 1705 | { |
| 1706 | unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH); |
| 1707 | unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW); |
| 1708 | |
| 1709 | addr[0] = (mac_h >> 24) & 0xff; |
| 1710 | addr[1] = (mac_h >> 16) & 0xff; |
| 1711 | addr[2] = (mac_h >> 8) & 0xff; |
| 1712 | addr[3] = mac_h & 0xff; |
| 1713 | addr[4] = (mac_l >> 8) & 0xff; |
| 1714 | addr[5] = mac_l & 0xff; |
| 1715 | } |
| 1716 | |
| 1717 | static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr) |
| 1718 | { |
| 1719 | wrlp(mp, MAC_ADDR_HIGH, |
| 1720 | (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]); |
| 1721 | wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]); |
| 1722 | } |
| 1723 | |
| 1724 | static u32 uc_addr_filter_mask(struct net_device *dev) |
| 1725 | { |
| 1726 | struct dev_addr_list *uc_ptr; |
| 1727 | u32 nibbles; |
| 1728 | |
| 1729 | if (dev->flags & IFF_PROMISC) |
| 1730 | return 0; |
| 1731 | |
| 1732 | nibbles = 1 << (dev->dev_addr[5] & 0x0f); |
| 1733 | for (uc_ptr = dev->uc_list; uc_ptr != NULL; uc_ptr = uc_ptr->next) { |
| 1734 | if (memcmp(dev->dev_addr, uc_ptr->da_addr, 5)) |
| 1735 | return 0; |
| 1736 | if ((dev->dev_addr[5] ^ uc_ptr->da_addr[5]) & 0xf0) |
| 1737 | return 0; |
| 1738 | |
| 1739 | nibbles |= 1 << (uc_ptr->da_addr[5] & 0x0f); |
| 1740 | } |
| 1741 | |
| 1742 | return nibbles; |
| 1743 | } |
| 1744 | |
| 1745 | static void mv643xx_eth_program_unicast_filter(struct net_device *dev) |
| 1746 | { |
| 1747 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
| 1748 | u32 port_config; |
| 1749 | u32 nibbles; |
| 1750 | int i; |
| 1751 | |
| 1752 | uc_addr_set(mp, dev->dev_addr); |
| 1753 | |
| 1754 | port_config = rdlp(mp, PORT_CONFIG); |
| 1755 | nibbles = uc_addr_filter_mask(dev); |
| 1756 | if (!nibbles) { |
| 1757 | port_config |= UNICAST_PROMISCUOUS_MODE; |
| 1758 | wrlp(mp, PORT_CONFIG, port_config); |
| 1759 | return; |
| 1760 | } |
| 1761 | |
| 1762 | for (i = 0; i < 16; i += 4) { |
| 1763 | int off = UNICAST_TABLE(mp->port_num) + i; |
| 1764 | u32 v; |
| 1765 | |
| 1766 | v = 0; |
| 1767 | if (nibbles & 1) |
| 1768 | v |= 0x00000001; |
| 1769 | if (nibbles & 2) |
| 1770 | v |= 0x00000100; |
| 1771 | if (nibbles & 4) |
| 1772 | v |= 0x00010000; |
| 1773 | if (nibbles & 8) |
| 1774 | v |= 0x01000000; |
| 1775 | nibbles >>= 4; |
| 1776 | |
| 1777 | wrl(mp, off, v); |
| 1778 | } |
| 1779 | |
| 1780 | port_config &= ~UNICAST_PROMISCUOUS_MODE; |
| 1781 | wrlp(mp, PORT_CONFIG, port_config); |
| 1782 | } |
| 1783 | |
| 1784 | static int addr_crc(unsigned char *addr) |
| 1785 | { |
| 1786 | int crc = 0; |
| 1787 | int i; |
| 1788 | |
| 1789 | for (i = 0; i < 6; i++) { |
| 1790 | int j; |
| 1791 | |
| 1792 | crc = (crc ^ addr[i]) << 8; |
| 1793 | for (j = 7; j >= 0; j--) { |
| 1794 | if (crc & (0x100 << j)) |
| 1795 | crc ^= 0x107 << j; |
| 1796 | } |
| 1797 | } |
| 1798 | |
| 1799 | return crc; |
| 1800 | } |
| 1801 | |
| 1802 | static void mv643xx_eth_program_multicast_filter(struct net_device *dev) |
| 1803 | { |
| 1804 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
| 1805 | u32 *mc_spec; |
| 1806 | u32 *mc_other; |
| 1807 | struct dev_addr_list *addr; |
| 1808 | int i; |
| 1809 | |
| 1810 | if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) { |
| 1811 | int port_num; |
| 1812 | u32 accept; |
| 1813 | int i; |
| 1814 | |
| 1815 | oom: |
| 1816 | port_num = mp->port_num; |
| 1817 | accept = 0x01010101; |
| 1818 | for (i = 0; i < 0x100; i += 4) { |
| 1819 | wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept); |
| 1820 | wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept); |
| 1821 | } |
| 1822 | return; |
| 1823 | } |
| 1824 | |
| 1825 | mc_spec = kmalloc(0x200, GFP_ATOMIC); |
| 1826 | if (mc_spec == NULL) |
| 1827 | goto oom; |
| 1828 | mc_other = mc_spec + (0x100 >> 2); |
| 1829 | |
| 1830 | memset(mc_spec, 0, 0x100); |
| 1831 | memset(mc_other, 0, 0x100); |
| 1832 | |
| 1833 | for (addr = dev->mc_list; addr != NULL; addr = addr->next) { |
| 1834 | u8 *a = addr->da_addr; |
| 1835 | u32 *table; |
| 1836 | int entry; |
| 1837 | |
| 1838 | if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) { |
| 1839 | table = mc_spec; |
| 1840 | entry = a[5]; |
| 1841 | } else { |
| 1842 | table = mc_other; |
| 1843 | entry = addr_crc(a); |
| 1844 | } |
| 1845 | |
| 1846 | table[entry >> 2] |= 1 << (8 * (entry & 3)); |
| 1847 | } |
| 1848 | |
| 1849 | for (i = 0; i < 0x100; i += 4) { |
| 1850 | wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]); |
| 1851 | wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]); |
| 1852 | } |
| 1853 | |
| 1854 | kfree(mc_spec); |
| 1855 | } |
| 1856 | |
| 1857 | static void mv643xx_eth_set_rx_mode(struct net_device *dev) |
| 1858 | { |
| 1859 | mv643xx_eth_program_unicast_filter(dev); |
| 1860 | mv643xx_eth_program_multicast_filter(dev); |
| 1861 | } |
| 1862 | |
| 1863 | static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) |
| 1864 | { |
| 1865 | struct sockaddr *sa = addr; |
| 1866 | |
| 1867 | memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN); |
| 1868 | |
| 1869 | netif_addr_lock_bh(dev); |
| 1870 | mv643xx_eth_program_unicast_filter(dev); |
| 1871 | netif_addr_unlock_bh(dev); |
| 1872 | |
| 1873 | return 0; |
| 1874 | } |
| 1875 | |
| 1876 | |
| 1877 | /* rx/tx queue initialisation ***********************************************/ |
| 1878 | static int rxq_init(struct mv643xx_eth_private *mp, int index) |
| 1879 | { |
| 1880 | struct rx_queue *rxq = mp->rxq + index; |
| 1881 | struct rx_desc *rx_desc; |
| 1882 | int size; |
| 1883 | int i; |
| 1884 | |
| 1885 | rxq->index = index; |
| 1886 | |
| 1887 | rxq->rx_ring_size = mp->rx_ring_size; |
| 1888 | |
| 1889 | rxq->rx_desc_count = 0; |
| 1890 | rxq->rx_curr_desc = 0; |
| 1891 | rxq->rx_used_desc = 0; |
| 1892 | |
| 1893 | size = rxq->rx_ring_size * sizeof(struct rx_desc); |
| 1894 | |
| 1895 | if (index == 0 && size <= mp->rx_desc_sram_size) { |
| 1896 | rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr, |
| 1897 | mp->rx_desc_sram_size); |
| 1898 | rxq->rx_desc_dma = mp->rx_desc_sram_addr; |
| 1899 | } else { |
| 1900 | rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent, |
| 1901 | size, &rxq->rx_desc_dma, |
| 1902 | GFP_KERNEL); |
| 1903 | } |
| 1904 | |
| 1905 | if (rxq->rx_desc_area == NULL) { |
| 1906 | dev_printk(KERN_ERR, &mp->dev->dev, |
| 1907 | "can't allocate rx ring (%d bytes)\n", size); |
| 1908 | goto out; |
| 1909 | } |
| 1910 | memset(rxq->rx_desc_area, 0, size); |
| 1911 | |
| 1912 | rxq->rx_desc_area_size = size; |
| 1913 | rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb), |
| 1914 | GFP_KERNEL); |
| 1915 | if (rxq->rx_skb == NULL) { |
| 1916 | dev_printk(KERN_ERR, &mp->dev->dev, |
| 1917 | "can't allocate rx skb ring\n"); |
| 1918 | goto out_free; |
| 1919 | } |
| 1920 | |
| 1921 | rx_desc = (struct rx_desc *)rxq->rx_desc_area; |
| 1922 | for (i = 0; i < rxq->rx_ring_size; i++) { |
| 1923 | int nexti; |
| 1924 | |
| 1925 | nexti = i + 1; |
| 1926 | if (nexti == rxq->rx_ring_size) |
| 1927 | nexti = 0; |
| 1928 | |
| 1929 | rx_desc[i].next_desc_ptr = rxq->rx_desc_dma + |
| 1930 | nexti * sizeof(struct rx_desc); |
| 1931 | } |
| 1932 | |
| 1933 | rxq->lro_mgr.dev = mp->dev; |
| 1934 | memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats)); |
| 1935 | rxq->lro_mgr.features = LRO_F_NAPI; |
| 1936 | rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY; |
| 1937 | rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY; |
| 1938 | rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr); |
| 1939 | rxq->lro_mgr.max_aggr = 32; |
| 1940 | rxq->lro_mgr.frag_align_pad = 0; |
| 1941 | rxq->lro_mgr.lro_arr = rxq->lro_arr; |
| 1942 | rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header; |
| 1943 | |
| 1944 | memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr)); |
| 1945 | |
| 1946 | return 0; |
| 1947 | |
| 1948 | |
| 1949 | out_free: |
| 1950 | if (index == 0 && size <= mp->rx_desc_sram_size) |
| 1951 | iounmap(rxq->rx_desc_area); |
| 1952 | else |
| 1953 | dma_free_coherent(mp->dev->dev.parent, size, |
| 1954 | rxq->rx_desc_area, |
| 1955 | rxq->rx_desc_dma); |
| 1956 | |
| 1957 | out: |
| 1958 | return -ENOMEM; |
| 1959 | } |
| 1960 | |
| 1961 | static void rxq_deinit(struct rx_queue *rxq) |
| 1962 | { |
| 1963 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
| 1964 | int i; |
| 1965 | |
| 1966 | rxq_disable(rxq); |
| 1967 | |
| 1968 | for (i = 0; i < rxq->rx_ring_size; i++) { |
| 1969 | if (rxq->rx_skb[i]) { |
| 1970 | dev_kfree_skb(rxq->rx_skb[i]); |
| 1971 | rxq->rx_desc_count--; |
| 1972 | } |
| 1973 | } |
| 1974 | |
| 1975 | if (rxq->rx_desc_count) { |
| 1976 | dev_printk(KERN_ERR, &mp->dev->dev, |
| 1977 | "error freeing rx ring -- %d skbs stuck\n", |
| 1978 | rxq->rx_desc_count); |
| 1979 | } |
| 1980 | |
| 1981 | if (rxq->index == 0 && |
| 1982 | rxq->rx_desc_area_size <= mp->rx_desc_sram_size) |
| 1983 | iounmap(rxq->rx_desc_area); |
| 1984 | else |
| 1985 | dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size, |
| 1986 | rxq->rx_desc_area, rxq->rx_desc_dma); |
| 1987 | |
| 1988 | kfree(rxq->rx_skb); |
| 1989 | } |
| 1990 | |
| 1991 | static int txq_init(struct mv643xx_eth_private *mp, int index) |
| 1992 | { |
| 1993 | struct tx_queue *txq = mp->txq + index; |
| 1994 | struct tx_desc *tx_desc; |
| 1995 | int size; |
| 1996 | int i; |
| 1997 | |
| 1998 | txq->index = index; |
| 1999 | |
| 2000 | txq->tx_ring_size = mp->tx_ring_size; |
| 2001 | |
| 2002 | txq->tx_desc_count = 0; |
| 2003 | txq->tx_curr_desc = 0; |
| 2004 | txq->tx_used_desc = 0; |
| 2005 | |
| 2006 | size = txq->tx_ring_size * sizeof(struct tx_desc); |
| 2007 | |
| 2008 | if (index == 0 && size <= mp->tx_desc_sram_size) { |
| 2009 | txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr, |
| 2010 | mp->tx_desc_sram_size); |
| 2011 | txq->tx_desc_dma = mp->tx_desc_sram_addr; |
| 2012 | } else { |
| 2013 | txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent, |
| 2014 | size, &txq->tx_desc_dma, |
| 2015 | GFP_KERNEL); |
| 2016 | } |
| 2017 | |
| 2018 | if (txq->tx_desc_area == NULL) { |
| 2019 | dev_printk(KERN_ERR, &mp->dev->dev, |
| 2020 | "can't allocate tx ring (%d bytes)\n", size); |
| 2021 | return -ENOMEM; |
| 2022 | } |
| 2023 | memset(txq->tx_desc_area, 0, size); |
| 2024 | |
| 2025 | txq->tx_desc_area_size = size; |
| 2026 | |
| 2027 | tx_desc = (struct tx_desc *)txq->tx_desc_area; |
| 2028 | for (i = 0; i < txq->tx_ring_size; i++) { |
| 2029 | struct tx_desc *txd = tx_desc + i; |
| 2030 | int nexti; |
| 2031 | |
| 2032 | nexti = i + 1; |
| 2033 | if (nexti == txq->tx_ring_size) |
| 2034 | nexti = 0; |
| 2035 | |
| 2036 | txd->cmd_sts = 0; |
| 2037 | txd->next_desc_ptr = txq->tx_desc_dma + |
| 2038 | nexti * sizeof(struct tx_desc); |
| 2039 | } |
| 2040 | |
| 2041 | skb_queue_head_init(&txq->tx_skb); |
| 2042 | |
| 2043 | return 0; |
| 2044 | } |
| 2045 | |
| 2046 | static void txq_deinit(struct tx_queue *txq) |
| 2047 | { |
| 2048 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
| 2049 | |
| 2050 | txq_disable(txq); |
| 2051 | txq_reclaim(txq, txq->tx_ring_size, 1); |
| 2052 | |
| 2053 | BUG_ON(txq->tx_used_desc != txq->tx_curr_desc); |
| 2054 | |
| 2055 | if (txq->index == 0 && |
| 2056 | txq->tx_desc_area_size <= mp->tx_desc_sram_size) |
| 2057 | iounmap(txq->tx_desc_area); |
| 2058 | else |
| 2059 | dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size, |
| 2060 | txq->tx_desc_area, txq->tx_desc_dma); |
| 2061 | } |
| 2062 | |
| 2063 | |
| 2064 | /* netdev ops and related ***************************************************/ |
| 2065 | static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp) |
| 2066 | { |
| 2067 | u32 int_cause; |
| 2068 | u32 int_cause_ext; |
| 2069 | |
| 2070 | int_cause = rdlp(mp, INT_CAUSE) & (INT_TX_END | INT_RX | INT_EXT); |
| 2071 | if (int_cause == 0) |
| 2072 | return 0; |
| 2073 | |
| 2074 | int_cause_ext = 0; |
| 2075 | if (int_cause & INT_EXT) |
| 2076 | int_cause_ext = rdlp(mp, INT_CAUSE_EXT); |
| 2077 | |
| 2078 | int_cause &= INT_TX_END | INT_RX; |
| 2079 | if (int_cause) { |
| 2080 | wrlp(mp, INT_CAUSE, ~int_cause); |
| 2081 | mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) & |
| 2082 | ~(rdlp(mp, TXQ_COMMAND) & 0xff); |
| 2083 | mp->work_rx |= (int_cause & INT_RX) >> 2; |
| 2084 | } |
| 2085 | |
| 2086 | int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX; |
| 2087 | if (int_cause_ext) { |
| 2088 | wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext); |
| 2089 | if (int_cause_ext & INT_EXT_LINK_PHY) |
| 2090 | mp->work_link = 1; |
| 2091 | mp->work_tx |= int_cause_ext & INT_EXT_TX; |
| 2092 | } |
| 2093 | |
| 2094 | return 1; |
| 2095 | } |
| 2096 | |
| 2097 | static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id) |
| 2098 | { |
| 2099 | struct net_device *dev = (struct net_device *)dev_id; |
| 2100 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
| 2101 | |
| 2102 | if (unlikely(!mv643xx_eth_collect_events(mp))) |
| 2103 | return IRQ_NONE; |
| 2104 | |
| 2105 | wrlp(mp, INT_MASK, 0); |
| 2106 | napi_schedule(&mp->napi); |
| 2107 | |
| 2108 | return IRQ_HANDLED; |
| 2109 | } |
| 2110 | |
| 2111 | static void handle_link_event(struct mv643xx_eth_private *mp) |
| 2112 | { |
| 2113 | struct net_device *dev = mp->dev; |
| 2114 | u32 port_status; |
| 2115 | int speed; |
| 2116 | int duplex; |
| 2117 | int fc; |
| 2118 | |
| 2119 | port_status = rdlp(mp, PORT_STATUS); |
| 2120 | if (!(port_status & LINK_UP)) { |
| 2121 | if (netif_carrier_ok(dev)) { |
| 2122 | int i; |
| 2123 | |
| 2124 | printk(KERN_INFO "%s: link down\n", dev->name); |
| 2125 | |
| 2126 | netif_carrier_off(dev); |
| 2127 | |
| 2128 | for (i = 0; i < mp->txq_count; i++) { |
| 2129 | struct tx_queue *txq = mp->txq + i; |
| 2130 | |
| 2131 | txq_reclaim(txq, txq->tx_ring_size, 1); |
| 2132 | txq_reset_hw_ptr(txq); |
| 2133 | } |
| 2134 | } |
| 2135 | return; |
| 2136 | } |
| 2137 | |
| 2138 | switch (port_status & PORT_SPEED_MASK) { |
| 2139 | case PORT_SPEED_10: |
| 2140 | speed = 10; |
| 2141 | break; |
| 2142 | case PORT_SPEED_100: |
| 2143 | speed = 100; |
| 2144 | break; |
| 2145 | case PORT_SPEED_1000: |
| 2146 | speed = 1000; |
| 2147 | break; |
| 2148 | default: |
| 2149 | speed = -1; |
| 2150 | break; |
| 2151 | } |
| 2152 | duplex = (port_status & FULL_DUPLEX) ? 1 : 0; |
| 2153 | fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0; |
| 2154 | |
| 2155 | printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, " |
| 2156 | "flow control %sabled\n", dev->name, |
| 2157 | speed, duplex ? "full" : "half", |
| 2158 | fc ? "en" : "dis"); |
| 2159 | |
| 2160 | if (!netif_carrier_ok(dev)) |
| 2161 | netif_carrier_on(dev); |
| 2162 | } |
| 2163 | |
| 2164 | static int mv643xx_eth_poll(struct napi_struct *napi, int budget) |
| 2165 | { |
| 2166 | struct mv643xx_eth_private *mp; |
| 2167 | int work_done; |
| 2168 | |
| 2169 | mp = container_of(napi, struct mv643xx_eth_private, napi); |
| 2170 | |
| 2171 | if (unlikely(mp->oom)) { |
| 2172 | mp->oom = 0; |
| 2173 | del_timer(&mp->rx_oom); |
| 2174 | } |
| 2175 | |
| 2176 | work_done = 0; |
| 2177 | while (work_done < budget) { |
| 2178 | u8 queue_mask; |
| 2179 | int queue; |
| 2180 | int work_tbd; |
| 2181 | |
| 2182 | if (mp->work_link) { |
| 2183 | mp->work_link = 0; |
| 2184 | handle_link_event(mp); |
| 2185 | continue; |
| 2186 | } |
| 2187 | |
| 2188 | queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx; |
| 2189 | if (likely(!mp->oom)) |
| 2190 | queue_mask |= mp->work_rx_refill; |
| 2191 | |
| 2192 | if (!queue_mask) { |
| 2193 | if (mv643xx_eth_collect_events(mp)) |
| 2194 | continue; |
| 2195 | break; |
| 2196 | } |
| 2197 | |
| 2198 | queue = fls(queue_mask) - 1; |
| 2199 | queue_mask = 1 << queue; |
| 2200 | |
| 2201 | work_tbd = budget - work_done; |
| 2202 | if (work_tbd > 16) |
| 2203 | work_tbd = 16; |
| 2204 | |
| 2205 | if (mp->work_tx_end & queue_mask) { |
| 2206 | txq_kick(mp->txq + queue); |
| 2207 | } else if (mp->work_tx & queue_mask) { |
| 2208 | work_done += txq_reclaim(mp->txq + queue, work_tbd, 0); |
| 2209 | txq_maybe_wake(mp->txq + queue); |
| 2210 | } else if (mp->work_rx & queue_mask) { |
| 2211 | work_done += rxq_process(mp->rxq + queue, work_tbd); |
| 2212 | } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) { |
| 2213 | work_done += rxq_refill(mp->rxq + queue, work_tbd); |
| 2214 | } else { |
| 2215 | BUG(); |
| 2216 | } |
| 2217 | } |
| 2218 | |
| 2219 | if (work_done < budget) { |
| 2220 | if (mp->oom) |
| 2221 | mod_timer(&mp->rx_oom, jiffies + (HZ / 10)); |
| 2222 | napi_complete(napi); |
| 2223 | wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT); |
| 2224 | } |
| 2225 | |
| 2226 | return work_done; |
| 2227 | } |
| 2228 | |
| 2229 | static inline void oom_timer_wrapper(unsigned long data) |
| 2230 | { |
| 2231 | struct mv643xx_eth_private *mp = (void *)data; |
| 2232 | |
| 2233 | napi_schedule(&mp->napi); |
| 2234 | } |
| 2235 | |
| 2236 | static void phy_reset(struct mv643xx_eth_private *mp) |
| 2237 | { |
| 2238 | int data; |
| 2239 | |
| 2240 | data = phy_read(mp->phy, MII_BMCR); |
| 2241 | if (data < 0) |
| 2242 | return; |
| 2243 | |
| 2244 | data |= BMCR_RESET; |
| 2245 | if (phy_write(mp->phy, MII_BMCR, data) < 0) |
| 2246 | return; |
| 2247 | |
| 2248 | do { |
| 2249 | data = phy_read(mp->phy, MII_BMCR); |
| 2250 | } while (data >= 0 && data & BMCR_RESET); |
| 2251 | } |
| 2252 | |
| 2253 | static void port_start(struct mv643xx_eth_private *mp) |
| 2254 | { |
| 2255 | u32 pscr; |
| 2256 | int i; |
| 2257 | |
| 2258 | /* |
| 2259 | * Perform PHY reset, if there is a PHY. |
| 2260 | */ |
| 2261 | if (mp->phy != NULL) { |
| 2262 | struct ethtool_cmd cmd; |
| 2263 | |
| 2264 | mv643xx_eth_get_settings(mp->dev, &cmd); |
| 2265 | phy_reset(mp); |
| 2266 | mv643xx_eth_set_settings(mp->dev, &cmd); |
| 2267 | } |
| 2268 | |
| 2269 | /* |
| 2270 | * Configure basic link parameters. |
| 2271 | */ |
| 2272 | pscr = rdlp(mp, PORT_SERIAL_CONTROL); |
| 2273 | |
| 2274 | pscr |= SERIAL_PORT_ENABLE; |
| 2275 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
| 2276 | |
| 2277 | pscr |= DO_NOT_FORCE_LINK_FAIL; |
| 2278 | if (mp->phy == NULL) |
| 2279 | pscr |= FORCE_LINK_PASS; |
| 2280 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
| 2281 | |
| 2282 | /* |
| 2283 | * Configure TX path and queues. |
| 2284 | */ |
| 2285 | tx_set_rate(mp, 1000000000, 16777216); |
| 2286 | for (i = 0; i < mp->txq_count; i++) { |
| 2287 | struct tx_queue *txq = mp->txq + i; |
| 2288 | |
| 2289 | txq_reset_hw_ptr(txq); |
| 2290 | txq_set_rate(txq, 1000000000, 16777216); |
| 2291 | txq_set_fixed_prio_mode(txq); |
| 2292 | } |
| 2293 | |
| 2294 | /* |
| 2295 | * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast |
| 2296 | * frames to RX queue #0, and include the pseudo-header when |
| 2297 | * calculating receive checksums. |
| 2298 | */ |
| 2299 | wrlp(mp, PORT_CONFIG, 0x02000000); |
| 2300 | |
| 2301 | /* |
| 2302 | * Treat BPDUs as normal multicasts, and disable partition mode. |
| 2303 | */ |
| 2304 | wrlp(mp, PORT_CONFIG_EXT, 0x00000000); |
| 2305 | |
| 2306 | /* |
| 2307 | * Add configured unicast addresses to address filter table. |
| 2308 | */ |
| 2309 | mv643xx_eth_program_unicast_filter(mp->dev); |
| 2310 | |
| 2311 | /* |
| 2312 | * Enable the receive queues. |
| 2313 | */ |
| 2314 | for (i = 0; i < mp->rxq_count; i++) { |
| 2315 | struct rx_queue *rxq = mp->rxq + i; |
| 2316 | u32 addr; |
| 2317 | |
| 2318 | addr = (u32)rxq->rx_desc_dma; |
| 2319 | addr += rxq->rx_curr_desc * sizeof(struct rx_desc); |
| 2320 | wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr); |
| 2321 | |
| 2322 | rxq_enable(rxq); |
| 2323 | } |
| 2324 | } |
| 2325 | |
| 2326 | static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp) |
| 2327 | { |
| 2328 | int skb_size; |
| 2329 | |
| 2330 | /* |
| 2331 | * Reserve 2+14 bytes for an ethernet header (the hardware |
| 2332 | * automatically prepends 2 bytes of dummy data to each |
| 2333 | * received packet), 16 bytes for up to four VLAN tags, and |
| 2334 | * 4 bytes for the trailing FCS -- 36 bytes total. |
| 2335 | */ |
| 2336 | skb_size = mp->dev->mtu + 36; |
| 2337 | |
| 2338 | /* |
| 2339 | * Make sure that the skb size is a multiple of 8 bytes, as |
| 2340 | * the lower three bits of the receive descriptor's buffer |
| 2341 | * size field are ignored by the hardware. |
| 2342 | */ |
| 2343 | mp->skb_size = (skb_size + 7) & ~7; |
| 2344 | } |
| 2345 | |
| 2346 | static int mv643xx_eth_open(struct net_device *dev) |
| 2347 | { |
| 2348 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
| 2349 | int err; |
| 2350 | int i; |
| 2351 | |
| 2352 | wrlp(mp, INT_CAUSE, 0); |
| 2353 | wrlp(mp, INT_CAUSE_EXT, 0); |
| 2354 | rdlp(mp, INT_CAUSE_EXT); |
| 2355 | |
| 2356 | err = request_irq(dev->irq, mv643xx_eth_irq, |
| 2357 | IRQF_SHARED, dev->name, dev); |
| 2358 | if (err) { |
| 2359 | dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n"); |
| 2360 | return -EAGAIN; |
| 2361 | } |
| 2362 | |
| 2363 | mv643xx_eth_recalc_skb_size(mp); |
| 2364 | |
| 2365 | napi_enable(&mp->napi); |
| 2366 | |
| 2367 | skb_queue_head_init(&mp->rx_recycle); |
| 2368 | |
| 2369 | for (i = 0; i < mp->rxq_count; i++) { |
| 2370 | err = rxq_init(mp, i); |
| 2371 | if (err) { |
| 2372 | while (--i >= 0) |
| 2373 | rxq_deinit(mp->rxq + i); |
| 2374 | goto out; |
| 2375 | } |
| 2376 | |
| 2377 | rxq_refill(mp->rxq + i, INT_MAX); |
| 2378 | } |
| 2379 | |
| 2380 | if (mp->oom) { |
| 2381 | mp->rx_oom.expires = jiffies + (HZ / 10); |
| 2382 | add_timer(&mp->rx_oom); |
| 2383 | } |
| 2384 | |
| 2385 | for (i = 0; i < mp->txq_count; i++) { |
| 2386 | err = txq_init(mp, i); |
| 2387 | if (err) { |
| 2388 | while (--i >= 0) |
| 2389 | txq_deinit(mp->txq + i); |
| 2390 | goto out_free; |
| 2391 | } |
| 2392 | } |
| 2393 | |
| 2394 | port_start(mp); |
| 2395 | |
| 2396 | wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX); |
| 2397 | wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT); |
| 2398 | |
| 2399 | return 0; |
| 2400 | |
| 2401 | |
| 2402 | out_free: |
| 2403 | for (i = 0; i < mp->rxq_count; i++) |
| 2404 | rxq_deinit(mp->rxq + i); |
| 2405 | out: |
| 2406 | free_irq(dev->irq, dev); |
| 2407 | |
| 2408 | return err; |
| 2409 | } |
| 2410 | |
| 2411 | static void port_reset(struct mv643xx_eth_private *mp) |
| 2412 | { |
| 2413 | unsigned int data; |
| 2414 | int i; |
| 2415 | |
| 2416 | for (i = 0; i < mp->rxq_count; i++) |
| 2417 | rxq_disable(mp->rxq + i); |
| 2418 | for (i = 0; i < mp->txq_count; i++) |
| 2419 | txq_disable(mp->txq + i); |
| 2420 | |
| 2421 | while (1) { |
| 2422 | u32 ps = rdlp(mp, PORT_STATUS); |
| 2423 | |
| 2424 | if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY) |
| 2425 | break; |
| 2426 | udelay(10); |
| 2427 | } |
| 2428 | |
| 2429 | /* Reset the Enable bit in the Configuration Register */ |
| 2430 | data = rdlp(mp, PORT_SERIAL_CONTROL); |
| 2431 | data &= ~(SERIAL_PORT_ENABLE | |
| 2432 | DO_NOT_FORCE_LINK_FAIL | |
| 2433 | FORCE_LINK_PASS); |
| 2434 | wrlp(mp, PORT_SERIAL_CONTROL, data); |
| 2435 | } |
| 2436 | |
| 2437 | static int mv643xx_eth_stop(struct net_device *dev) |
| 2438 | { |
| 2439 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
| 2440 | int i; |
| 2441 | |
| 2442 | wrlp(mp, INT_MASK_EXT, 0x00000000); |
| 2443 | wrlp(mp, INT_MASK, 0x00000000); |
| 2444 | rdlp(mp, INT_MASK); |
| 2445 | |
| 2446 | napi_disable(&mp->napi); |
| 2447 | |
| 2448 | del_timer_sync(&mp->rx_oom); |
| 2449 | |
| 2450 | netif_carrier_off(dev); |
| 2451 | |
| 2452 | free_irq(dev->irq, dev); |
| 2453 | |
| 2454 | port_reset(mp); |
| 2455 | mv643xx_eth_get_stats(dev); |
| 2456 | mib_counters_update(mp); |
| 2457 | del_timer_sync(&mp->mib_counters_timer); |
| 2458 | |
| 2459 | skb_queue_purge(&mp->rx_recycle); |
| 2460 | |
| 2461 | for (i = 0; i < mp->rxq_count; i++) |
| 2462 | rxq_deinit(mp->rxq + i); |
| 2463 | for (i = 0; i < mp->txq_count; i++) |
| 2464 | txq_deinit(mp->txq + i); |
| 2465 | |
| 2466 | return 0; |
| 2467 | } |
| 2468 | |
| 2469 | static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
| 2470 | { |
| 2471 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
| 2472 | |
| 2473 | if (mp->phy != NULL) |
| 2474 | return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd); |
| 2475 | |
| 2476 | return -EOPNOTSUPP; |
| 2477 | } |
| 2478 | |
| 2479 | static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) |
| 2480 | { |
| 2481 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
| 2482 | |
| 2483 | if (new_mtu < 64 || new_mtu > 9500) |
| 2484 | return -EINVAL; |
| 2485 | |
| 2486 | dev->mtu = new_mtu; |
| 2487 | mv643xx_eth_recalc_skb_size(mp); |
| 2488 | tx_set_rate(mp, 1000000000, 16777216); |
| 2489 | |
| 2490 | if (!netif_running(dev)) |
| 2491 | return 0; |
| 2492 | |
| 2493 | /* |
| 2494 | * Stop and then re-open the interface. This will allocate RX |
| 2495 | * skbs of the new MTU. |
| 2496 | * There is a possible danger that the open will not succeed, |
| 2497 | * due to memory being full. |
| 2498 | */ |
| 2499 | mv643xx_eth_stop(dev); |
| 2500 | if (mv643xx_eth_open(dev)) { |
| 2501 | dev_printk(KERN_ERR, &dev->dev, |
| 2502 | "fatal error on re-opening device after " |
| 2503 | "MTU change\n"); |
| 2504 | } |
| 2505 | |
| 2506 | return 0; |
| 2507 | } |
| 2508 | |
| 2509 | static void tx_timeout_task(struct work_struct *ugly) |
| 2510 | { |
| 2511 | struct mv643xx_eth_private *mp; |
| 2512 | |
| 2513 | mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task); |
| 2514 | if (netif_running(mp->dev)) { |
| 2515 | netif_tx_stop_all_queues(mp->dev); |
| 2516 | port_reset(mp); |
| 2517 | port_start(mp); |
| 2518 | netif_tx_wake_all_queues(mp->dev); |
| 2519 | } |
| 2520 | } |
| 2521 | |
| 2522 | static void mv643xx_eth_tx_timeout(struct net_device *dev) |
| 2523 | { |
| 2524 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
| 2525 | |
| 2526 | dev_printk(KERN_INFO, &dev->dev, "tx timeout\n"); |
| 2527 | |
| 2528 | schedule_work(&mp->tx_timeout_task); |
| 2529 | } |
| 2530 | |
| 2531 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 2532 | static void mv643xx_eth_netpoll(struct net_device *dev) |
| 2533 | { |
| 2534 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
| 2535 | |
| 2536 | wrlp(mp, INT_MASK, 0x00000000); |
| 2537 | rdlp(mp, INT_MASK); |
| 2538 | |
| 2539 | mv643xx_eth_irq(dev->irq, dev); |
| 2540 | |
| 2541 | wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT); |
| 2542 | } |
| 2543 | #endif |
| 2544 | |
| 2545 | |
| 2546 | /* platform glue ************************************************************/ |
| 2547 | static void |
| 2548 | mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp, |
| 2549 | struct mbus_dram_target_info *dram) |
| 2550 | { |
| 2551 | void __iomem *base = msp->base; |
| 2552 | u32 win_enable; |
| 2553 | u32 win_protect; |
| 2554 | int i; |
| 2555 | |
| 2556 | for (i = 0; i < 6; i++) { |
| 2557 | writel(0, base + WINDOW_BASE(i)); |
| 2558 | writel(0, base + WINDOW_SIZE(i)); |
| 2559 | if (i < 4) |
| 2560 | writel(0, base + WINDOW_REMAP_HIGH(i)); |
| 2561 | } |
| 2562 | |
| 2563 | win_enable = 0x3f; |
| 2564 | win_protect = 0; |
| 2565 | |
| 2566 | for (i = 0; i < dram->num_cs; i++) { |
| 2567 | struct mbus_dram_window *cs = dram->cs + i; |
| 2568 | |
| 2569 | writel((cs->base & 0xffff0000) | |
| 2570 | (cs->mbus_attr << 8) | |
| 2571 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); |
| 2572 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); |
| 2573 | |
| 2574 | win_enable &= ~(1 << i); |
| 2575 | win_protect |= 3 << (2 * i); |
| 2576 | } |
| 2577 | |
| 2578 | writel(win_enable, base + WINDOW_BAR_ENABLE); |
| 2579 | msp->win_protect = win_protect; |
| 2580 | } |
| 2581 | |
| 2582 | static void infer_hw_params(struct mv643xx_eth_shared_private *msp) |
| 2583 | { |
| 2584 | /* |
| 2585 | * Check whether we have a 14-bit coal limit field in bits |
| 2586 | * [21:8], or a 16-bit coal limit in bits [25,21:7] of the |
| 2587 | * SDMA config register. |
| 2588 | */ |
| 2589 | writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG); |
| 2590 | if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000) |
| 2591 | msp->extended_rx_coal_limit = 1; |
| 2592 | else |
| 2593 | msp->extended_rx_coal_limit = 0; |
| 2594 | |
| 2595 | /* |
| 2596 | * Check whether the MAC supports TX rate control, and if |
| 2597 | * yes, whether its associated registers are in the old or |
| 2598 | * the new place. |
| 2599 | */ |
| 2600 | writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED); |
| 2601 | if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) { |
| 2602 | msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT; |
| 2603 | } else { |
| 2604 | writel(7, msp->base + 0x0400 + TX_BW_RATE); |
| 2605 | if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7) |
| 2606 | msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT; |
| 2607 | else |
| 2608 | msp->tx_bw_control = TX_BW_CONTROL_ABSENT; |
| 2609 | } |
| 2610 | } |
| 2611 | |
| 2612 | static int mv643xx_eth_shared_probe(struct platform_device *pdev) |
| 2613 | { |
| 2614 | static int mv643xx_eth_version_printed; |
| 2615 | struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; |
| 2616 | struct mv643xx_eth_shared_private *msp; |
| 2617 | struct resource *res; |
| 2618 | int ret; |
| 2619 | |
| 2620 | if (!mv643xx_eth_version_printed++) |
| 2621 | printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet " |
| 2622 | "driver version %s\n", mv643xx_eth_driver_version); |
| 2623 | |
| 2624 | ret = -EINVAL; |
| 2625 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 2626 | if (res == NULL) |
| 2627 | goto out; |
| 2628 | |
| 2629 | ret = -ENOMEM; |
| 2630 | msp = kmalloc(sizeof(*msp), GFP_KERNEL); |
| 2631 | if (msp == NULL) |
| 2632 | goto out; |
| 2633 | memset(msp, 0, sizeof(*msp)); |
| 2634 | |
| 2635 | msp->base = ioremap(res->start, res->end - res->start + 1); |
| 2636 | if (msp->base == NULL) |
| 2637 | goto out_free; |
| 2638 | |
| 2639 | /* |
| 2640 | * Set up and register SMI bus. |
| 2641 | */ |
| 2642 | if (pd == NULL || pd->shared_smi == NULL) { |
| 2643 | msp->smi_bus = mdiobus_alloc(); |
| 2644 | if (msp->smi_bus == NULL) |
| 2645 | goto out_unmap; |
| 2646 | |
| 2647 | msp->smi_bus->priv = msp; |
| 2648 | msp->smi_bus->name = "mv643xx_eth smi"; |
| 2649 | msp->smi_bus->read = smi_bus_read; |
| 2650 | msp->smi_bus->write = smi_bus_write, |
| 2651 | snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id); |
| 2652 | msp->smi_bus->parent = &pdev->dev; |
| 2653 | msp->smi_bus->phy_mask = 0xffffffff; |
| 2654 | if (mdiobus_register(msp->smi_bus) < 0) |
| 2655 | goto out_free_mii_bus; |
| 2656 | msp->smi = msp; |
| 2657 | } else { |
| 2658 | msp->smi = platform_get_drvdata(pd->shared_smi); |
| 2659 | } |
| 2660 | |
| 2661 | msp->err_interrupt = NO_IRQ; |
| 2662 | init_waitqueue_head(&msp->smi_busy_wait); |
| 2663 | |
| 2664 | /* |
| 2665 | * Check whether the error interrupt is hooked up. |
| 2666 | */ |
| 2667 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 2668 | if (res != NULL) { |
| 2669 | int err; |
| 2670 | |
| 2671 | err = request_irq(res->start, mv643xx_eth_err_irq, |
| 2672 | IRQF_SHARED, "mv643xx_eth", msp); |
| 2673 | if (!err) { |
| 2674 | writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK); |
| 2675 | msp->err_interrupt = res->start; |
| 2676 | } |
| 2677 | } |
| 2678 | |
| 2679 | /* |
| 2680 | * (Re-)program MBUS remapping windows if we are asked to. |
| 2681 | */ |
| 2682 | if (pd != NULL && pd->dram != NULL) |
| 2683 | mv643xx_eth_conf_mbus_windows(msp, pd->dram); |
| 2684 | |
| 2685 | /* |
| 2686 | * Detect hardware parameters. |
| 2687 | */ |
| 2688 | msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000; |
| 2689 | infer_hw_params(msp); |
| 2690 | |
| 2691 | platform_set_drvdata(pdev, msp); |
| 2692 | |
| 2693 | return 0; |
| 2694 | |
| 2695 | out_free_mii_bus: |
| 2696 | mdiobus_free(msp->smi_bus); |
| 2697 | out_unmap: |
| 2698 | iounmap(msp->base); |
| 2699 | out_free: |
| 2700 | kfree(msp); |
| 2701 | out: |
| 2702 | return ret; |
| 2703 | } |
| 2704 | |
| 2705 | static int mv643xx_eth_shared_remove(struct platform_device *pdev) |
| 2706 | { |
| 2707 | struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev); |
| 2708 | struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; |
| 2709 | |
| 2710 | if (pd == NULL || pd->shared_smi == NULL) { |
| 2711 | mdiobus_unregister(msp->smi_bus); |
| 2712 | mdiobus_free(msp->smi_bus); |
| 2713 | } |
| 2714 | if (msp->err_interrupt != NO_IRQ) |
| 2715 | free_irq(msp->err_interrupt, msp); |
| 2716 | iounmap(msp->base); |
| 2717 | kfree(msp); |
| 2718 | |
| 2719 | return 0; |
| 2720 | } |
| 2721 | |
| 2722 | static struct platform_driver mv643xx_eth_shared_driver = { |
| 2723 | .probe = mv643xx_eth_shared_probe, |
| 2724 | .remove = mv643xx_eth_shared_remove, |
| 2725 | .driver = { |
| 2726 | .name = MV643XX_ETH_SHARED_NAME, |
| 2727 | .owner = THIS_MODULE, |
| 2728 | }, |
| 2729 | }; |
| 2730 | |
| 2731 | static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr) |
| 2732 | { |
| 2733 | int addr_shift = 5 * mp->port_num; |
| 2734 | u32 data; |
| 2735 | |
| 2736 | data = rdl(mp, PHY_ADDR); |
| 2737 | data &= ~(0x1f << addr_shift); |
| 2738 | data |= (phy_addr & 0x1f) << addr_shift; |
| 2739 | wrl(mp, PHY_ADDR, data); |
| 2740 | } |
| 2741 | |
| 2742 | static int phy_addr_get(struct mv643xx_eth_private *mp) |
| 2743 | { |
| 2744 | unsigned int data; |
| 2745 | |
| 2746 | data = rdl(mp, PHY_ADDR); |
| 2747 | |
| 2748 | return (data >> (5 * mp->port_num)) & 0x1f; |
| 2749 | } |
| 2750 | |
| 2751 | static void set_params(struct mv643xx_eth_private *mp, |
| 2752 | struct mv643xx_eth_platform_data *pd) |
| 2753 | { |
| 2754 | struct net_device *dev = mp->dev; |
| 2755 | |
| 2756 | if (is_valid_ether_addr(pd->mac_addr)) |
| 2757 | memcpy(dev->dev_addr, pd->mac_addr, 6); |
| 2758 | else |
| 2759 | uc_addr_get(mp, dev->dev_addr); |
| 2760 | |
| 2761 | mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE; |
| 2762 | if (pd->rx_queue_size) |
| 2763 | mp->rx_ring_size = pd->rx_queue_size; |
| 2764 | mp->rx_desc_sram_addr = pd->rx_sram_addr; |
| 2765 | mp->rx_desc_sram_size = pd->rx_sram_size; |
| 2766 | |
| 2767 | mp->rxq_count = pd->rx_queue_count ? : 1; |
| 2768 | |
| 2769 | mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE; |
| 2770 | if (pd->tx_queue_size) |
| 2771 | mp->tx_ring_size = pd->tx_queue_size; |
| 2772 | mp->tx_desc_sram_addr = pd->tx_sram_addr; |
| 2773 | mp->tx_desc_sram_size = pd->tx_sram_size; |
| 2774 | |
| 2775 | mp->txq_count = pd->tx_queue_count ? : 1; |
| 2776 | } |
| 2777 | |
| 2778 | static struct phy_device *phy_scan(struct mv643xx_eth_private *mp, |
| 2779 | int phy_addr) |
| 2780 | { |
| 2781 | struct mii_bus *bus = mp->shared->smi->smi_bus; |
| 2782 | struct phy_device *phydev; |
| 2783 | int start; |
| 2784 | int num; |
| 2785 | int i; |
| 2786 | |
| 2787 | if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) { |
| 2788 | start = phy_addr_get(mp) & 0x1f; |
| 2789 | num = 32; |
| 2790 | } else { |
| 2791 | start = phy_addr & 0x1f; |
| 2792 | num = 1; |
| 2793 | } |
| 2794 | |
| 2795 | phydev = NULL; |
| 2796 | for (i = 0; i < num; i++) { |
| 2797 | int addr = (start + i) & 0x1f; |
| 2798 | |
| 2799 | if (bus->phy_map[addr] == NULL) |
| 2800 | mdiobus_scan(bus, addr); |
| 2801 | |
| 2802 | if (phydev == NULL) { |
| 2803 | phydev = bus->phy_map[addr]; |
| 2804 | if (phydev != NULL) |
| 2805 | phy_addr_set(mp, addr); |
| 2806 | } |
| 2807 | } |
| 2808 | |
| 2809 | return phydev; |
| 2810 | } |
| 2811 | |
| 2812 | static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex) |
| 2813 | { |
| 2814 | struct phy_device *phy = mp->phy; |
| 2815 | |
| 2816 | phy_reset(mp); |
| 2817 | |
| 2818 | phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII); |
| 2819 | |
| 2820 | if (speed == 0) { |
| 2821 | phy->autoneg = AUTONEG_ENABLE; |
| 2822 | phy->speed = 0; |
| 2823 | phy->duplex = 0; |
| 2824 | phy->advertising = phy->supported | ADVERTISED_Autoneg; |
| 2825 | } else { |
| 2826 | phy->autoneg = AUTONEG_DISABLE; |
| 2827 | phy->advertising = 0; |
| 2828 | phy->speed = speed; |
| 2829 | phy->duplex = duplex; |
| 2830 | } |
| 2831 | phy_start_aneg(phy); |
| 2832 | } |
| 2833 | |
| 2834 | static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex) |
| 2835 | { |
| 2836 | u32 pscr; |
| 2837 | |
| 2838 | pscr = rdlp(mp, PORT_SERIAL_CONTROL); |
| 2839 | if (pscr & SERIAL_PORT_ENABLE) { |
| 2840 | pscr &= ~SERIAL_PORT_ENABLE; |
| 2841 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
| 2842 | } |
| 2843 | |
| 2844 | pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED; |
| 2845 | if (mp->phy == NULL) { |
| 2846 | pscr |= DISABLE_AUTO_NEG_SPEED_GMII; |
| 2847 | if (speed == SPEED_1000) |
| 2848 | pscr |= SET_GMII_SPEED_TO_1000; |
| 2849 | else if (speed == SPEED_100) |
| 2850 | pscr |= SET_MII_SPEED_TO_100; |
| 2851 | |
| 2852 | pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL; |
| 2853 | |
| 2854 | pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX; |
| 2855 | if (duplex == DUPLEX_FULL) |
| 2856 | pscr |= SET_FULL_DUPLEX_MODE; |
| 2857 | } |
| 2858 | |
| 2859 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
| 2860 | } |
| 2861 | |
| 2862 | static const struct net_device_ops mv643xx_eth_netdev_ops = { |
| 2863 | .ndo_open = mv643xx_eth_open, |
| 2864 | .ndo_stop = mv643xx_eth_stop, |
| 2865 | .ndo_start_xmit = mv643xx_eth_xmit, |
| 2866 | .ndo_set_rx_mode = mv643xx_eth_set_rx_mode, |
| 2867 | .ndo_set_mac_address = mv643xx_eth_set_mac_address, |
| 2868 | .ndo_do_ioctl = mv643xx_eth_ioctl, |
| 2869 | .ndo_change_mtu = mv643xx_eth_change_mtu, |
| 2870 | .ndo_tx_timeout = mv643xx_eth_tx_timeout, |
| 2871 | .ndo_get_stats = mv643xx_eth_get_stats, |
| 2872 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 2873 | .ndo_poll_controller = mv643xx_eth_netpoll, |
| 2874 | #endif |
| 2875 | }; |
| 2876 | |
| 2877 | static int mv643xx_eth_probe(struct platform_device *pdev) |
| 2878 | { |
| 2879 | struct mv643xx_eth_platform_data *pd; |
| 2880 | struct mv643xx_eth_private *mp; |
| 2881 | struct net_device *dev; |
| 2882 | struct resource *res; |
| 2883 | int err; |
| 2884 | |
| 2885 | pd = pdev->dev.platform_data; |
| 2886 | if (pd == NULL) { |
| 2887 | dev_printk(KERN_ERR, &pdev->dev, |
| 2888 | "no mv643xx_eth_platform_data\n"); |
| 2889 | return -ENODEV; |
| 2890 | } |
| 2891 | |
| 2892 | if (pd->shared == NULL) { |
| 2893 | dev_printk(KERN_ERR, &pdev->dev, |
| 2894 | "no mv643xx_eth_platform_data->shared\n"); |
| 2895 | return -ENODEV; |
| 2896 | } |
| 2897 | |
| 2898 | dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8); |
| 2899 | if (!dev) |
| 2900 | return -ENOMEM; |
| 2901 | |
| 2902 | mp = netdev_priv(dev); |
| 2903 | platform_set_drvdata(pdev, mp); |
| 2904 | |
| 2905 | mp->shared = platform_get_drvdata(pd->shared); |
| 2906 | mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10); |
| 2907 | mp->port_num = pd->port_number; |
| 2908 | |
| 2909 | mp->dev = dev; |
| 2910 | |
| 2911 | set_params(mp, pd); |
| 2912 | dev->real_num_tx_queues = mp->txq_count; |
| 2913 | |
| 2914 | if (pd->phy_addr != MV643XX_ETH_PHY_NONE) |
| 2915 | mp->phy = phy_scan(mp, pd->phy_addr); |
| 2916 | |
| 2917 | if (mp->phy != NULL) |
| 2918 | phy_init(mp, pd->speed, pd->duplex); |
| 2919 | |
| 2920 | SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops); |
| 2921 | |
| 2922 | init_pscr(mp, pd->speed, pd->duplex); |
| 2923 | |
| 2924 | |
| 2925 | mib_counters_clear(mp); |
| 2926 | |
| 2927 | init_timer(&mp->mib_counters_timer); |
| 2928 | mp->mib_counters_timer.data = (unsigned long)mp; |
| 2929 | mp->mib_counters_timer.function = mib_counters_timer_wrapper; |
| 2930 | mp->mib_counters_timer.expires = jiffies + 30 * HZ; |
| 2931 | add_timer(&mp->mib_counters_timer); |
| 2932 | |
| 2933 | spin_lock_init(&mp->mib_counters_lock); |
| 2934 | |
| 2935 | INIT_WORK(&mp->tx_timeout_task, tx_timeout_task); |
| 2936 | |
| 2937 | netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128); |
| 2938 | |
| 2939 | init_timer(&mp->rx_oom); |
| 2940 | mp->rx_oom.data = (unsigned long)mp; |
| 2941 | mp->rx_oom.function = oom_timer_wrapper; |
| 2942 | |
| 2943 | |
| 2944 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 2945 | BUG_ON(!res); |
| 2946 | dev->irq = res->start; |
| 2947 | |
| 2948 | dev->netdev_ops = &mv643xx_eth_netdev_ops; |
| 2949 | |
| 2950 | dev->watchdog_timeo = 2 * HZ; |
| 2951 | dev->base_addr = 0; |
| 2952 | |
| 2953 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; |
| 2954 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM; |
| 2955 | |
| 2956 | SET_NETDEV_DEV(dev, &pdev->dev); |
| 2957 | |
| 2958 | if (mp->shared->win_protect) |
| 2959 | wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect); |
| 2960 | |
| 2961 | netif_carrier_off(dev); |
| 2962 | |
| 2963 | wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE); |
| 2964 | |
| 2965 | set_rx_coal(mp, 250); |
| 2966 | set_tx_coal(mp, 0); |
| 2967 | |
| 2968 | err = register_netdev(dev); |
| 2969 | if (err) |
| 2970 | goto out; |
| 2971 | |
| 2972 | dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n", |
| 2973 | mp->port_num, dev->dev_addr); |
| 2974 | |
| 2975 | if (mp->tx_desc_sram_size > 0) |
| 2976 | dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n"); |
| 2977 | |
| 2978 | return 0; |
| 2979 | |
| 2980 | out: |
| 2981 | free_netdev(dev); |
| 2982 | |
| 2983 | return err; |
| 2984 | } |
| 2985 | |
| 2986 | static int mv643xx_eth_remove(struct platform_device *pdev) |
| 2987 | { |
| 2988 | struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); |
| 2989 | |
| 2990 | unregister_netdev(mp->dev); |
| 2991 | if (mp->phy != NULL) |
| 2992 | phy_detach(mp->phy); |
| 2993 | flush_scheduled_work(); |
| 2994 | free_netdev(mp->dev); |
| 2995 | |
| 2996 | platform_set_drvdata(pdev, NULL); |
| 2997 | |
| 2998 | return 0; |
| 2999 | } |
| 3000 | |
| 3001 | static void mv643xx_eth_shutdown(struct platform_device *pdev) |
| 3002 | { |
| 3003 | struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); |
| 3004 | |
| 3005 | /* Mask all interrupts on ethernet port */ |
| 3006 | wrlp(mp, INT_MASK, 0); |
| 3007 | rdlp(mp, INT_MASK); |
| 3008 | |
| 3009 | if (netif_running(mp->dev)) |
| 3010 | port_reset(mp); |
| 3011 | } |
| 3012 | |
| 3013 | static struct platform_driver mv643xx_eth_driver = { |
| 3014 | .probe = mv643xx_eth_probe, |
| 3015 | .remove = mv643xx_eth_remove, |
| 3016 | .shutdown = mv643xx_eth_shutdown, |
| 3017 | .driver = { |
| 3018 | .name = MV643XX_ETH_NAME, |
| 3019 | .owner = THIS_MODULE, |
| 3020 | }, |
| 3021 | }; |
| 3022 | |
| 3023 | static int __init mv643xx_eth_init_module(void) |
| 3024 | { |
| 3025 | int rc; |
| 3026 | |
| 3027 | rc = platform_driver_register(&mv643xx_eth_shared_driver); |
| 3028 | if (!rc) { |
| 3029 | rc = platform_driver_register(&mv643xx_eth_driver); |
| 3030 | if (rc) |
| 3031 | platform_driver_unregister(&mv643xx_eth_shared_driver); |
| 3032 | } |
| 3033 | |
| 3034 | return rc; |
| 3035 | } |
| 3036 | module_init(mv643xx_eth_init_module); |
| 3037 | |
| 3038 | static void __exit mv643xx_eth_cleanup_module(void) |
| 3039 | { |
| 3040 | platform_driver_unregister(&mv643xx_eth_driver); |
| 3041 | platform_driver_unregister(&mv643xx_eth_shared_driver); |
| 3042 | } |
| 3043 | module_exit(mv643xx_eth_cleanup_module); |
| 3044 | |
| 3045 | MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, " |
| 3046 | "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek"); |
| 3047 | MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); |
| 3048 | MODULE_LICENSE("GPL"); |
| 3049 | MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); |
| 3050 | MODULE_ALIAS("platform:" MV643XX_ETH_NAME); |