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phy: Micrel KS8995MA 5-ports 10/100 managed Ethernet switch support added
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / xmit.c
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1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/dma-mapping.h>
18#include "ath9k.h"
19#include "ar9003_mac.h"
20
21#define BITS_PER_BYTE 8
22#define OFDM_PLCP_BITS 22
23#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
24#define L_STF 8
25#define L_LTF 8
26#define L_SIG 4
27#define HT_SIG 8
28#define HT_STF 4
29#define HT_LTF(_ns) (4 * (_ns))
30#define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32#define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33#define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
34
35
36static u16 bits_per_symbol[][2] = {
37 /* 20MHz 40MHz */
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46};
47
48#define IS_HT_RATE(_rate) ((_rate) & 0x80)
49
50static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq);
54static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok);
57static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head, bool internal);
59static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
61 int txok);
62static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
63 int seqno);
64static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
65 struct ath_txq *txq,
66 struct ath_atx_tid *tid,
67 struct sk_buff *skb);
68
69enum {
70 MCS_HT20,
71 MCS_HT20_SGI,
72 MCS_HT40,
73 MCS_HT40_SGI,
74};
75
76static int ath_max_4ms_framelen[4][32] = {
77 [MCS_HT20] = {
78 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
79 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
80 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
81 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
82 },
83 [MCS_HT20_SGI] = {
84 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
85 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
86 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
87 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
88 },
89 [MCS_HT40] = {
90 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
91 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
92 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
93 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
94 },
95 [MCS_HT40_SGI] = {
96 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
97 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
98 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
99 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
100 }
101};
102
103/*********************/
104/* Aggregation logic */
105/*********************/
106
107static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
108{
109 struct ath_atx_ac *ac = tid->ac;
110
111 if (tid->paused)
112 return;
113
114 if (tid->sched)
115 return;
116
117 tid->sched = true;
118 list_add_tail(&tid->list, &ac->tid_q);
119
120 if (ac->sched)
121 return;
122
123 ac->sched = true;
124 list_add_tail(&ac->list, &txq->axq_acq);
125}
126
127static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
128{
129 struct ath_txq *txq = tid->ac->txq;
130
131 WARN_ON(!tid->paused);
132
133 spin_lock_bh(&txq->axq_lock);
134 tid->paused = false;
135
136 if (skb_queue_empty(&tid->buf_q))
137 goto unlock;
138
139 ath_tx_queue_tid(txq, tid);
140 ath_txq_schedule(sc, txq);
141unlock:
142 spin_unlock_bh(&txq->axq_lock);
143}
144
145static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
146{
147 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
148 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
149 sizeof(tx_info->rate_driver_data));
150 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
151}
152
153static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
154{
155 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
156 seqno << IEEE80211_SEQ_SEQ_SHIFT);
157}
158
159static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
160{
161 struct ath_txq *txq = tid->ac->txq;
162 struct sk_buff *skb;
163 struct ath_buf *bf;
164 struct list_head bf_head;
165 struct ath_tx_status ts;
166 struct ath_frame_info *fi;
167 bool sendbar = false;
168
169 INIT_LIST_HEAD(&bf_head);
170
171 memset(&ts, 0, sizeof(ts));
172
173 while ((skb = __skb_dequeue(&tid->buf_q))) {
174 fi = get_frame_info(skb);
175 bf = fi->bf;
176
177 if (bf && fi->retries) {
178 list_add_tail(&bf->list, &bf_head);
179 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
180 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
181 sendbar = true;
182 } else {
183 ath_tx_send_normal(sc, txq, NULL, skb);
184 }
185 }
186
187 if (tid->baw_head == tid->baw_tail) {
188 tid->state &= ~AGGR_ADDBA_COMPLETE;
189 tid->state &= ~AGGR_CLEANUP;
190 }
191
192 if (sendbar)
193 ath_send_bar(tid, tid->seq_start);
194}
195
196static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
197 int seqno)
198{
199 int index, cindex;
200
201 index = ATH_BA_INDEX(tid->seq_start, seqno);
202 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
203
204 __clear_bit(cindex, tid->tx_buf);
205
206 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
207 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
208 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
209 if (tid->bar_index >= 0)
210 tid->bar_index--;
211 }
212}
213
214static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
215 u16 seqno)
216{
217 int index, cindex;
218
219 index = ATH_BA_INDEX(tid->seq_start, seqno);
220 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
221 __set_bit(cindex, tid->tx_buf);
222
223 if (index >= ((tid->baw_tail - tid->baw_head) &
224 (ATH_TID_MAX_BUFS - 1))) {
225 tid->baw_tail = cindex;
226 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
227 }
228}
229
230/*
231 * TODO: For frame(s) that are in the retry state, we will reuse the
232 * sequence number(s) without setting the retry bit. The
233 * alternative is to give up on these and BAR the receiver's window
234 * forward.
235 */
236static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
237 struct ath_atx_tid *tid)
238
239{
240 struct sk_buff *skb;
241 struct ath_buf *bf;
242 struct list_head bf_head;
243 struct ath_tx_status ts;
244 struct ath_frame_info *fi;
245
246 memset(&ts, 0, sizeof(ts));
247 INIT_LIST_HEAD(&bf_head);
248
249 while ((skb = __skb_dequeue(&tid->buf_q))) {
250 fi = get_frame_info(skb);
251 bf = fi->bf;
252
253 if (!bf) {
254 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
255 continue;
256 }
257
258 list_add_tail(&bf->list, &bf_head);
259
260 if (fi->retries)
261 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
262
263 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
264 }
265
266 tid->seq_next = tid->seq_start;
267 tid->baw_tail = tid->baw_head;
268 tid->bar_index = -1;
269}
270
271static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
272 struct sk_buff *skb, int count)
273{
274 struct ath_frame_info *fi = get_frame_info(skb);
275 struct ath_buf *bf = fi->bf;
276 struct ieee80211_hdr *hdr;
277 int prev = fi->retries;
278
279 TX_STAT_INC(txq->axq_qnum, a_retries);
280 fi->retries += count;
281
282 if (prev > 0)
283 return;
284
285 hdr = (struct ieee80211_hdr *)skb->data;
286 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
287 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
288 sizeof(*hdr), DMA_TO_DEVICE);
289}
290
291static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
292{
293 struct ath_buf *bf = NULL;
294
295 spin_lock_bh(&sc->tx.txbuflock);
296
297 if (unlikely(list_empty(&sc->tx.txbuf))) {
298 spin_unlock_bh(&sc->tx.txbuflock);
299 return NULL;
300 }
301
302 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
303 list_del(&bf->list);
304
305 spin_unlock_bh(&sc->tx.txbuflock);
306
307 return bf;
308}
309
310static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
311{
312 spin_lock_bh(&sc->tx.txbuflock);
313 list_add_tail(&bf->list, &sc->tx.txbuf);
314 spin_unlock_bh(&sc->tx.txbuflock);
315}
316
317static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
318{
319 struct ath_buf *tbf;
320
321 tbf = ath_tx_get_buffer(sc);
322 if (WARN_ON(!tbf))
323 return NULL;
324
325 ATH_TXBUF_RESET(tbf);
326
327 tbf->bf_mpdu = bf->bf_mpdu;
328 tbf->bf_buf_addr = bf->bf_buf_addr;
329 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
330 tbf->bf_state = bf->bf_state;
331
332 return tbf;
333}
334
335static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
336 struct ath_tx_status *ts, int txok,
337 int *nframes, int *nbad)
338{
339 struct ath_frame_info *fi;
340 u16 seq_st = 0;
341 u32 ba[WME_BA_BMP_SIZE >> 5];
342 int ba_index;
343 int isaggr = 0;
344
345 *nbad = 0;
346 *nframes = 0;
347
348 isaggr = bf_isaggr(bf);
349 if (isaggr) {
350 seq_st = ts->ts_seqnum;
351 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
352 }
353
354 while (bf) {
355 fi = get_frame_info(bf->bf_mpdu);
356 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
357
358 (*nframes)++;
359 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
360 (*nbad)++;
361
362 bf = bf->bf_next;
363 }
364}
365
366
367static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
368 struct ath_buf *bf, struct list_head *bf_q,
369 struct ath_tx_status *ts, int txok, bool retry)
370{
371 struct ath_node *an = NULL;
372 struct sk_buff *skb;
373 struct ieee80211_sta *sta;
374 struct ieee80211_hw *hw = sc->hw;
375 struct ieee80211_hdr *hdr;
376 struct ieee80211_tx_info *tx_info;
377 struct ath_atx_tid *tid = NULL;
378 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
379 struct list_head bf_head;
380 struct sk_buff_head bf_pending;
381 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
382 u32 ba[WME_BA_BMP_SIZE >> 5];
383 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
384 bool rc_update = true;
385 struct ieee80211_tx_rate rates[4];
386 struct ath_frame_info *fi;
387 int nframes;
388 u8 tidno;
389 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
390 int i, retries;
391 int bar_index = -1;
392
393 skb = bf->bf_mpdu;
394 hdr = (struct ieee80211_hdr *)skb->data;
395
396 tx_info = IEEE80211_SKB_CB(skb);
397
398 memcpy(rates, tx_info->control.rates, sizeof(rates));
399
400 retries = ts->ts_longretry + 1;
401 for (i = 0; i < ts->ts_rateindex; i++)
402 retries += rates[i].count;
403
404 rcu_read_lock();
405
406 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
407 if (!sta) {
408 rcu_read_unlock();
409
410 INIT_LIST_HEAD(&bf_head);
411 while (bf) {
412 bf_next = bf->bf_next;
413
414 if (!bf->bf_stale || bf_next != NULL)
415 list_move_tail(&bf->list, &bf_head);
416
417 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
418
419 bf = bf_next;
420 }
421 return;
422 }
423
424 an = (struct ath_node *)sta->drv_priv;
425 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
426 tid = ATH_AN_2_TID(an, tidno);
427 seq_first = tid->seq_start;
428
429 /*
430 * The hardware occasionally sends a tx status for the wrong TID.
431 * In this case, the BA status cannot be considered valid and all
432 * subframes need to be retransmitted
433 */
434 if (tidno != ts->tid)
435 txok = false;
436
437 isaggr = bf_isaggr(bf);
438 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
439
440 if (isaggr && txok) {
441 if (ts->ts_flags & ATH9K_TX_BA) {
442 seq_st = ts->ts_seqnum;
443 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
444 } else {
445 /*
446 * AR5416 can become deaf/mute when BA
447 * issue happens. Chip needs to be reset.
448 * But AP code may have sychronization issues
449 * when perform internal reset in this routine.
450 * Only enable reset in STA mode for now.
451 */
452 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
453 needreset = 1;
454 }
455 }
456
457 __skb_queue_head_init(&bf_pending);
458
459 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
460 while (bf) {
461 u16 seqno = bf->bf_state.seqno;
462
463 txfail = txpending = sendbar = 0;
464 bf_next = bf->bf_next;
465
466 skb = bf->bf_mpdu;
467 tx_info = IEEE80211_SKB_CB(skb);
468 fi = get_frame_info(skb);
469
470 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
471 /* transmit completion, subframe is
472 * acked by block ack */
473 acked_cnt++;
474 } else if (!isaggr && txok) {
475 /* transmit completion */
476 acked_cnt++;
477 } else if ((tid->state & AGGR_CLEANUP) || !retry) {
478 /*
479 * cleanup in progress, just fail
480 * the un-acked sub-frames
481 */
482 txfail = 1;
483 } else if (flush) {
484 txpending = 1;
485 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
486 if (txok || !an->sleeping)
487 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
488 retries);
489
490 txpending = 1;
491 } else {
492 txfail = 1;
493 txfail_cnt++;
494 bar_index = max_t(int, bar_index,
495 ATH_BA_INDEX(seq_first, seqno));
496 }
497
498 /*
499 * Make sure the last desc is reclaimed if it
500 * not a holding desc.
501 */
502 INIT_LIST_HEAD(&bf_head);
503 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
504 bf_next != NULL || !bf_last->bf_stale)
505 list_move_tail(&bf->list, &bf_head);
506
507 if (!txpending || (tid->state & AGGR_CLEANUP)) {
508 /*
509 * complete the acked-ones/xretried ones; update
510 * block-ack window
511 */
512 ath_tx_update_baw(sc, tid, seqno);
513
514 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
515 memcpy(tx_info->control.rates, rates, sizeof(rates));
516 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
517 rc_update = false;
518 }
519
520 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
521 !txfail);
522 } else {
523 /* retry the un-acked ones */
524 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
525 bf->bf_next == NULL && bf_last->bf_stale) {
526 struct ath_buf *tbf;
527
528 tbf = ath_clone_txbuf(sc, bf_last);
529 /*
530 * Update tx baw and complete the
531 * frame with failed status if we
532 * run out of tx buf.
533 */
534 if (!tbf) {
535 ath_tx_update_baw(sc, tid, seqno);
536
537 ath_tx_complete_buf(sc, bf, txq,
538 &bf_head, ts, 0);
539 bar_index = max_t(int, bar_index,
540 ATH_BA_INDEX(seq_first, seqno));
541 break;
542 }
543
544 fi->bf = tbf;
545 }
546
547 /*
548 * Put this buffer to the temporary pending
549 * queue to retain ordering
550 */
551 __skb_queue_tail(&bf_pending, skb);
552 }
553
554 bf = bf_next;
555 }
556
557 if (bar_index >= 0) {
558 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
559 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
560 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
561 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
562 }
563
564 /* prepend un-acked frames to the beginning of the pending frame queue */
565 if (!skb_queue_empty(&bf_pending)) {
566 if (an->sleeping)
567 ieee80211_sta_set_buffered(sta, tid->tidno, true);
568
569 skb_queue_splice(&bf_pending, &tid->buf_q);
570 if (!an->sleeping) {
571 ath_tx_queue_tid(txq, tid);
572
573 if (ts->ts_status & ATH9K_TXERR_FILT)
574 tid->ac->clear_ps_filter = true;
575 }
576 }
577
578 if (tid->state & AGGR_CLEANUP)
579 ath_tx_flush_tid(sc, tid);
580
581 rcu_read_unlock();
582
583 if (needreset) {
584 RESET_STAT_INC(sc, RESET_TYPE_TX_ERROR);
585 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
586 }
587}
588
589static bool ath_lookup_legacy(struct ath_buf *bf)
590{
591 struct sk_buff *skb;
592 struct ieee80211_tx_info *tx_info;
593 struct ieee80211_tx_rate *rates;
594 int i;
595
596 skb = bf->bf_mpdu;
597 tx_info = IEEE80211_SKB_CB(skb);
598 rates = tx_info->control.rates;
599
600 for (i = 0; i < 4; i++) {
601 if (!rates[i].count || rates[i].idx < 0)
602 break;
603
604 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
605 return true;
606 }
607
608 return false;
609}
610
611static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
612 struct ath_atx_tid *tid)
613{
614 struct sk_buff *skb;
615 struct ieee80211_tx_info *tx_info;
616 struct ieee80211_tx_rate *rates;
617 struct ath_mci_profile *mci = &sc->btcoex.mci;
618 u32 max_4ms_framelen, frmlen;
619 u16 aggr_limit, legacy = 0;
620 int i;
621
622 skb = bf->bf_mpdu;
623 tx_info = IEEE80211_SKB_CB(skb);
624 rates = tx_info->control.rates;
625
626 /*
627 * Find the lowest frame length among the rate series that will have a
628 * 4ms transmit duration.
629 * TODO - TXOP limit needs to be considered.
630 */
631 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
632
633 for (i = 0; i < 4; i++) {
634 int modeidx;
635
636 if (!rates[i].count)
637 continue;
638
639 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
640 legacy = 1;
641 break;
642 }
643
644 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
645 modeidx = MCS_HT40;
646 else
647 modeidx = MCS_HT20;
648
649 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
650 modeidx++;
651
652 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
653 max_4ms_framelen = min(max_4ms_framelen, frmlen);
654 }
655
656 /*
657 * limit aggregate size by the minimum rate if rate selected is
658 * not a probe rate, if rate selected is a probe rate then
659 * avoid aggregation of this packet.
660 */
661 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
662 return 0;
663
664 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI) && mci->aggr_limit)
665 aggr_limit = (max_4ms_framelen * mci->aggr_limit) >> 4;
666 else if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
667 aggr_limit = min((max_4ms_framelen * 3) / 8,
668 (u32)ATH_AMPDU_LIMIT_MAX);
669 else
670 aggr_limit = min(max_4ms_framelen,
671 (u32)ATH_AMPDU_LIMIT_MAX);
672
673 /*
674 * h/w can accept aggregates up to 16 bit lengths (65535).
675 * The IE, however can hold up to 65536, which shows up here
676 * as zero. Ignore 65536 since we are constrained by hw.
677 */
678 if (tid->an->maxampdu)
679 aggr_limit = min(aggr_limit, tid->an->maxampdu);
680
681 return aggr_limit;
682}
683
684/*
685 * Returns the number of delimiters to be added to
686 * meet the minimum required mpdudensity.
687 */
688static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
689 struct ath_buf *bf, u16 frmlen,
690 bool first_subfrm)
691{
692#define FIRST_DESC_NDELIMS 60
693 struct sk_buff *skb = bf->bf_mpdu;
694 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
695 u32 nsymbits, nsymbols;
696 u16 minlen;
697 u8 flags, rix;
698 int width, streams, half_gi, ndelim, mindelim;
699 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
700
701 /* Select standard number of delimiters based on frame length alone */
702 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
703
704 /*
705 * If encryption enabled, hardware requires some more padding between
706 * subframes.
707 * TODO - this could be improved to be dependent on the rate.
708 * The hardware can keep up at lower rates, but not higher rates
709 */
710 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
711 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
712 ndelim += ATH_AGGR_ENCRYPTDELIM;
713
714 /*
715 * Add delimiter when using RTS/CTS with aggregation
716 * and non enterprise AR9003 card
717 */
718 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
719 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
720 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
721
722 /*
723 * Convert desired mpdu density from microeconds to bytes based
724 * on highest rate in rate series (i.e. first rate) to determine
725 * required minimum length for subframe. Take into account
726 * whether high rate is 20 or 40Mhz and half or full GI.
727 *
728 * If there is no mpdu density restriction, no further calculation
729 * is needed.
730 */
731
732 if (tid->an->mpdudensity == 0)
733 return ndelim;
734
735 rix = tx_info->control.rates[0].idx;
736 flags = tx_info->control.rates[0].flags;
737 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
738 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
739
740 if (half_gi)
741 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
742 else
743 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
744
745 if (nsymbols == 0)
746 nsymbols = 1;
747
748 streams = HT_RC_2_STREAMS(rix);
749 nsymbits = bits_per_symbol[rix % 8][width] * streams;
750 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
751
752 if (frmlen < minlen) {
753 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
754 ndelim = max(mindelim, ndelim);
755 }
756
757 return ndelim;
758}
759
760static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
761 struct ath_txq *txq,
762 struct ath_atx_tid *tid,
763 struct list_head *bf_q,
764 int *aggr_len)
765{
766#define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
767 struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL;
768 int rl = 0, nframes = 0, ndelim, prev_al = 0;
769 u16 aggr_limit = 0, al = 0, bpad = 0,
770 al_delta, h_baw = tid->baw_size / 2;
771 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
772 struct ieee80211_tx_info *tx_info;
773 struct ath_frame_info *fi;
774 struct sk_buff *skb;
775 u16 seqno;
776
777 do {
778 skb = skb_peek(&tid->buf_q);
779 fi = get_frame_info(skb);
780 bf = fi->bf;
781 if (!fi->bf)
782 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
783
784 if (!bf)
785 continue;
786
787 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
788 seqno = bf->bf_state.seqno;
789
790 /* do not step over block-ack window */
791 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
792 status = ATH_AGGR_BAW_CLOSED;
793 break;
794 }
795
796 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
797 struct ath_tx_status ts = {};
798 struct list_head bf_head;
799
800 INIT_LIST_HEAD(&bf_head);
801 list_add(&bf->list, &bf_head);
802 __skb_unlink(skb, &tid->buf_q);
803 ath_tx_update_baw(sc, tid, seqno);
804 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
805 continue;
806 }
807
808 if (!bf_first)
809 bf_first = bf;
810
811 if (!rl) {
812 aggr_limit = ath_lookup_rate(sc, bf, tid);
813 rl = 1;
814 }
815
816 /* do not exceed aggregation limit */
817 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
818
819 if (nframes &&
820 ((aggr_limit < (al + bpad + al_delta + prev_al)) ||
821 ath_lookup_legacy(bf))) {
822 status = ATH_AGGR_LIMITED;
823 break;
824 }
825
826 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
827 if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE))
828 break;
829
830 /* do not exceed subframe limit */
831 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
832 status = ATH_AGGR_LIMITED;
833 break;
834 }
835
836 /* add padding for previous frame to aggregation length */
837 al += bpad + al_delta;
838
839 /*
840 * Get the delimiters needed to meet the MPDU
841 * density for this node.
842 */
843 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
844 !nframes);
845 bpad = PADBYTES(al_delta) + (ndelim << 2);
846
847 nframes++;
848 bf->bf_next = NULL;
849
850 /* link buffers of this frame to the aggregate */
851 if (!fi->retries)
852 ath_tx_addto_baw(sc, tid, seqno);
853 bf->bf_state.ndelim = ndelim;
854
855 __skb_unlink(skb, &tid->buf_q);
856 list_add_tail(&bf->list, bf_q);
857 if (bf_prev)
858 bf_prev->bf_next = bf;
859
860 bf_prev = bf;
861
862 } while (!skb_queue_empty(&tid->buf_q));
863
864 *aggr_len = al;
865
866 return status;
867#undef PADBYTES
868}
869
870/*
871 * rix - rate index
872 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
873 * width - 0 for 20 MHz, 1 for 40 MHz
874 * half_gi - to use 4us v/s 3.6 us for symbol time
875 */
876static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
877 int width, int half_gi, bool shortPreamble)
878{
879 u32 nbits, nsymbits, duration, nsymbols;
880 int streams;
881
882 /* find number of symbols: PLCP + data */
883 streams = HT_RC_2_STREAMS(rix);
884 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
885 nsymbits = bits_per_symbol[rix % 8][width] * streams;
886 nsymbols = (nbits + nsymbits - 1) / nsymbits;
887
888 if (!half_gi)
889 duration = SYMBOL_TIME(nsymbols);
890 else
891 duration = SYMBOL_TIME_HALFGI(nsymbols);
892
893 /* addup duration for legacy/ht training and signal fields */
894 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
895
896 return duration;
897}
898
899static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
900 struct ath_tx_info *info, int len)
901{
902 struct ath_hw *ah = sc->sc_ah;
903 struct sk_buff *skb;
904 struct ieee80211_tx_info *tx_info;
905 struct ieee80211_tx_rate *rates;
906 const struct ieee80211_rate *rate;
907 struct ieee80211_hdr *hdr;
908 int i;
909 u8 rix = 0;
910
911 skb = bf->bf_mpdu;
912 tx_info = IEEE80211_SKB_CB(skb);
913 rates = tx_info->control.rates;
914 hdr = (struct ieee80211_hdr *)skb->data;
915
916 /* set dur_update_en for l-sig computation except for PS-Poll frames */
917 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
918
919 /*
920 * We check if Short Preamble is needed for the CTS rate by
921 * checking the BSS's global flag.
922 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
923 */
924 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
925 info->rtscts_rate = rate->hw_value;
926 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
927 info->rtscts_rate |= rate->hw_value_short;
928
929 for (i = 0; i < 4; i++) {
930 bool is_40, is_sgi, is_sp;
931 int phy;
932
933 if (!rates[i].count || (rates[i].idx < 0))
934 continue;
935
936 rix = rates[i].idx;
937 info->rates[i].Tries = rates[i].count;
938
939 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
940 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
941 info->flags |= ATH9K_TXDESC_RTSENA;
942 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
943 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
944 info->flags |= ATH9K_TXDESC_CTSENA;
945 }
946
947 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
948 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
949 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
950 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
951
952 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
953 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
954 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
955
956 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
957 /* MCS rates */
958 info->rates[i].Rate = rix | 0x80;
959 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
960 ah->txchainmask, info->rates[i].Rate);
961 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
962 is_40, is_sgi, is_sp);
963 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
964 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
965 continue;
966 }
967
968 /* legacy rates */
969 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
970 !(rate->flags & IEEE80211_RATE_ERP_G))
971 phy = WLAN_RC_PHY_CCK;
972 else
973 phy = WLAN_RC_PHY_OFDM;
974
975 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
976 info->rates[i].Rate = rate->hw_value;
977 if (rate->hw_value_short) {
978 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
979 info->rates[i].Rate |= rate->hw_value_short;
980 } else {
981 is_sp = false;
982 }
983
984 if (bf->bf_state.bfs_paprd)
985 info->rates[i].ChSel = ah->txchainmask;
986 else
987 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
988 ah->txchainmask, info->rates[i].Rate);
989
990 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
991 phy, rate->bitrate * 100, len, rix, is_sp);
992 }
993
994 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
995 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
996 info->flags &= ~ATH9K_TXDESC_RTSENA;
997
998 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
999 if (info->flags & ATH9K_TXDESC_RTSENA)
1000 info->flags &= ~ATH9K_TXDESC_CTSENA;
1001}
1002
1003static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1004{
1005 struct ieee80211_hdr *hdr;
1006 enum ath9k_pkt_type htype;
1007 __le16 fc;
1008
1009 hdr = (struct ieee80211_hdr *)skb->data;
1010 fc = hdr->frame_control;
1011
1012 if (ieee80211_is_beacon(fc))
1013 htype = ATH9K_PKT_TYPE_BEACON;
1014 else if (ieee80211_is_probe_resp(fc))
1015 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1016 else if (ieee80211_is_atim(fc))
1017 htype = ATH9K_PKT_TYPE_ATIM;
1018 else if (ieee80211_is_pspoll(fc))
1019 htype = ATH9K_PKT_TYPE_PSPOLL;
1020 else
1021 htype = ATH9K_PKT_TYPE_NORMAL;
1022
1023 return htype;
1024}
1025
1026static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1027 struct ath_txq *txq, int len)
1028{
1029 struct ath_hw *ah = sc->sc_ah;
1030 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1031 struct ath_buf *bf_first = bf;
1032 struct ath_tx_info info;
1033 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1034
1035 memset(&info, 0, sizeof(info));
1036 info.is_first = true;
1037 info.is_last = true;
1038 info.txpower = MAX_RATE_POWER;
1039 info.qcu = txq->axq_qnum;
1040
1041 info.flags = ATH9K_TXDESC_INTREQ;
1042 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1043 info.flags |= ATH9K_TXDESC_NOACK;
1044 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1045 info.flags |= ATH9K_TXDESC_LDPC;
1046
1047 ath_buf_set_rate(sc, bf, &info, len);
1048
1049 if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
1050 info.flags |= ATH9K_TXDESC_CLRDMASK;
1051
1052 if (bf->bf_state.bfs_paprd)
1053 info.flags |= (u32) bf->bf_state.bfs_paprd << ATH9K_TXDESC_PAPRD_S;
1054
1055
1056 while (bf) {
1057 struct sk_buff *skb = bf->bf_mpdu;
1058 struct ath_frame_info *fi = get_frame_info(skb);
1059
1060 info.type = get_hw_packet_type(skb);
1061 if (bf->bf_next)
1062 info.link = bf->bf_next->bf_daddr;
1063 else
1064 info.link = 0;
1065
1066 info.buf_addr[0] = bf->bf_buf_addr;
1067 info.buf_len[0] = skb->len;
1068 info.pkt_len = fi->framelen;
1069 info.keyix = fi->keyix;
1070 info.keytype = fi->keytype;
1071
1072 if (aggr) {
1073 if (bf == bf_first)
1074 info.aggr = AGGR_BUF_FIRST;
1075 else if (!bf->bf_next)
1076 info.aggr = AGGR_BUF_LAST;
1077 else
1078 info.aggr = AGGR_BUF_MIDDLE;
1079
1080 info.ndelim = bf->bf_state.ndelim;
1081 info.aggr_len = len;
1082 }
1083
1084 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1085 bf = bf->bf_next;
1086 }
1087}
1088
1089static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1090 struct ath_atx_tid *tid)
1091{
1092 struct ath_buf *bf;
1093 enum ATH_AGGR_STATUS status;
1094 struct ieee80211_tx_info *tx_info;
1095 struct list_head bf_q;
1096 int aggr_len;
1097
1098 do {
1099 if (skb_queue_empty(&tid->buf_q))
1100 return;
1101
1102 INIT_LIST_HEAD(&bf_q);
1103
1104 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
1105
1106 /*
1107 * no frames picked up to be aggregated;
1108 * block-ack window is not open.
1109 */
1110 if (list_empty(&bf_q))
1111 break;
1112
1113 bf = list_first_entry(&bf_q, struct ath_buf, list);
1114 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
1115 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1116
1117 if (tid->ac->clear_ps_filter) {
1118 tid->ac->clear_ps_filter = false;
1119 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1120 } else {
1121 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
1122 }
1123
1124 /* if only one frame, send as non-aggregate */
1125 if (bf == bf->bf_lastbf) {
1126 aggr_len = get_frame_info(bf->bf_mpdu)->framelen;
1127 bf->bf_state.bf_type = BUF_AMPDU;
1128 } else {
1129 TX_STAT_INC(txq->axq_qnum, a_aggr);
1130 }
1131
1132 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1133 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1134 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
1135 status != ATH_AGGR_BAW_CLOSED);
1136}
1137
1138int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1139 u16 tid, u16 *ssn)
1140{
1141 struct ath_atx_tid *txtid;
1142 struct ath_node *an;
1143
1144 an = (struct ath_node *)sta->drv_priv;
1145 txtid = ATH_AN_2_TID(an, tid);
1146
1147 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
1148 return -EAGAIN;
1149
1150 txtid->state |= AGGR_ADDBA_PROGRESS;
1151 txtid->paused = true;
1152 *ssn = txtid->seq_start = txtid->seq_next;
1153 txtid->bar_index = -1;
1154
1155 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1156 txtid->baw_head = txtid->baw_tail = 0;
1157
1158 return 0;
1159}
1160
1161void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1162{
1163 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1164 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1165 struct ath_txq *txq = txtid->ac->txq;
1166
1167 if (txtid->state & AGGR_CLEANUP)
1168 return;
1169
1170 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
1171 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1172 return;
1173 }
1174
1175 spin_lock_bh(&txq->axq_lock);
1176 txtid->paused = true;
1177
1178 /*
1179 * If frames are still being transmitted for this TID, they will be
1180 * cleaned up during tx completion. To prevent race conditions, this
1181 * TID can only be reused after all in-progress subframes have been
1182 * completed.
1183 */
1184 if (txtid->baw_head != txtid->baw_tail)
1185 txtid->state |= AGGR_CLEANUP;
1186 else
1187 txtid->state &= ~AGGR_ADDBA_COMPLETE;
1188
1189 ath_tx_flush_tid(sc, txtid);
1190 spin_unlock_bh(&txq->axq_lock);
1191}
1192
1193void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1194 struct ath_node *an)
1195{
1196 struct ath_atx_tid *tid;
1197 struct ath_atx_ac *ac;
1198 struct ath_txq *txq;
1199 bool buffered;
1200 int tidno;
1201
1202 for (tidno = 0, tid = &an->tid[tidno];
1203 tidno < WME_NUM_TID; tidno++, tid++) {
1204
1205 if (!tid->sched)
1206 continue;
1207
1208 ac = tid->ac;
1209 txq = ac->txq;
1210
1211 spin_lock_bh(&txq->axq_lock);
1212
1213 buffered = !skb_queue_empty(&tid->buf_q);
1214
1215 tid->sched = false;
1216 list_del(&tid->list);
1217
1218 if (ac->sched) {
1219 ac->sched = false;
1220 list_del(&ac->list);
1221 }
1222
1223 spin_unlock_bh(&txq->axq_lock);
1224
1225 ieee80211_sta_set_buffered(sta, tidno, buffered);
1226 }
1227}
1228
1229void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1230{
1231 struct ath_atx_tid *tid;
1232 struct ath_atx_ac *ac;
1233 struct ath_txq *txq;
1234 int tidno;
1235
1236 for (tidno = 0, tid = &an->tid[tidno];
1237 tidno < WME_NUM_TID; tidno++, tid++) {
1238
1239 ac = tid->ac;
1240 txq = ac->txq;
1241
1242 spin_lock_bh(&txq->axq_lock);
1243 ac->clear_ps_filter = true;
1244
1245 if (!skb_queue_empty(&tid->buf_q) && !tid->paused) {
1246 ath_tx_queue_tid(txq, tid);
1247 ath_txq_schedule(sc, txq);
1248 }
1249
1250 spin_unlock_bh(&txq->axq_lock);
1251 }
1252}
1253
1254void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1255{
1256 struct ath_atx_tid *txtid;
1257 struct ath_node *an;
1258
1259 an = (struct ath_node *)sta->drv_priv;
1260
1261 if (sc->sc_flags & SC_OP_TXAGGR) {
1262 txtid = ATH_AN_2_TID(an, tid);
1263 txtid->baw_size =
1264 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1265 txtid->state |= AGGR_ADDBA_COMPLETE;
1266 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1267 ath_tx_resume_tid(sc, txtid);
1268 }
1269}
1270
1271/********************/
1272/* Queue Management */
1273/********************/
1274
1275static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1276 struct ath_txq *txq)
1277{
1278 struct ath_atx_ac *ac, *ac_tmp;
1279 struct ath_atx_tid *tid, *tid_tmp;
1280
1281 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1282 list_del(&ac->list);
1283 ac->sched = false;
1284 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
1285 list_del(&tid->list);
1286 tid->sched = false;
1287 ath_tid_drain(sc, txq, tid);
1288 }
1289 }
1290}
1291
1292struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1293{
1294 struct ath_hw *ah = sc->sc_ah;
1295 struct ath9k_tx_queue_info qi;
1296 static const int subtype_txq_to_hwq[] = {
1297 [WME_AC_BE] = ATH_TXQ_AC_BE,
1298 [WME_AC_BK] = ATH_TXQ_AC_BK,
1299 [WME_AC_VI] = ATH_TXQ_AC_VI,
1300 [WME_AC_VO] = ATH_TXQ_AC_VO,
1301 };
1302 int axq_qnum, i;
1303
1304 memset(&qi, 0, sizeof(qi));
1305 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1306 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1307 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1308 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1309 qi.tqi_physCompBuf = 0;
1310
1311 /*
1312 * Enable interrupts only for EOL and DESC conditions.
1313 * We mark tx descriptors to receive a DESC interrupt
1314 * when a tx queue gets deep; otherwise waiting for the
1315 * EOL to reap descriptors. Note that this is done to
1316 * reduce interrupt load and this only defers reaping
1317 * descriptors, never transmitting frames. Aside from
1318 * reducing interrupts this also permits more concurrency.
1319 * The only potential downside is if the tx queue backs
1320 * up in which case the top half of the kernel may backup
1321 * due to a lack of tx descriptors.
1322 *
1323 * The UAPSD queue is an exception, since we take a desc-
1324 * based intr on the EOSP frames.
1325 */
1326 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1327 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
1328 TXQ_FLAG_TXERRINT_ENABLE;
1329 } else {
1330 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1331 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1332 else
1333 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1334 TXQ_FLAG_TXDESCINT_ENABLE;
1335 }
1336 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1337 if (axq_qnum == -1) {
1338 /*
1339 * NB: don't print a message, this happens
1340 * normally on parts with too few tx queues
1341 */
1342 return NULL;
1343 }
1344 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1345 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1346
1347 txq->axq_qnum = axq_qnum;
1348 txq->mac80211_qnum = -1;
1349 txq->axq_link = NULL;
1350 INIT_LIST_HEAD(&txq->axq_q);
1351 INIT_LIST_HEAD(&txq->axq_acq);
1352 spin_lock_init(&txq->axq_lock);
1353 txq->axq_depth = 0;
1354 txq->axq_ampdu_depth = 0;
1355 txq->axq_tx_inprogress = false;
1356 sc->tx.txqsetup |= 1<<axq_qnum;
1357
1358 txq->txq_headidx = txq->txq_tailidx = 0;
1359 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1360 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1361 }
1362 return &sc->tx.txq[axq_qnum];
1363}
1364
1365int ath_txq_update(struct ath_softc *sc, int qnum,
1366 struct ath9k_tx_queue_info *qinfo)
1367{
1368 struct ath_hw *ah = sc->sc_ah;
1369 int error = 0;
1370 struct ath9k_tx_queue_info qi;
1371
1372 if (qnum == sc->beacon.beaconq) {
1373 /*
1374 * XXX: for beacon queue, we just save the parameter.
1375 * It will be picked up by ath_beaconq_config when
1376 * it's necessary.
1377 */
1378 sc->beacon.beacon_qi = *qinfo;
1379 return 0;
1380 }
1381
1382 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1383
1384 ath9k_hw_get_txq_props(ah, qnum, &qi);
1385 qi.tqi_aifs = qinfo->tqi_aifs;
1386 qi.tqi_cwmin = qinfo->tqi_cwmin;
1387 qi.tqi_cwmax = qinfo->tqi_cwmax;
1388 qi.tqi_burstTime = qinfo->tqi_burstTime;
1389 qi.tqi_readyTime = qinfo->tqi_readyTime;
1390
1391 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1392 ath_err(ath9k_hw_common(sc->sc_ah),
1393 "Unable to update hardware queue %u!\n", qnum);
1394 error = -EIO;
1395 } else {
1396 ath9k_hw_resettxqueue(ah, qnum);
1397 }
1398
1399 return error;
1400}
1401
1402int ath_cabq_update(struct ath_softc *sc)
1403{
1404 struct ath9k_tx_queue_info qi;
1405 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1406 int qnum = sc->beacon.cabq->axq_qnum;
1407
1408 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1409 /*
1410 * Ensure the readytime % is within the bounds.
1411 */
1412 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1413 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1414 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1415 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1416
1417 qi.tqi_readyTime = (cur_conf->beacon_interval *
1418 sc->config.cabqReadytime) / 100;
1419 ath_txq_update(sc, qnum, &qi);
1420
1421 return 0;
1422}
1423
1424static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1425{
1426 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
1427 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1428}
1429
1430static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1431 struct list_head *list, bool retry_tx)
1432{
1433 struct ath_buf *bf, *lastbf;
1434 struct list_head bf_head;
1435 struct ath_tx_status ts;
1436
1437 memset(&ts, 0, sizeof(ts));
1438 ts.ts_status = ATH9K_TX_FLUSH;
1439 INIT_LIST_HEAD(&bf_head);
1440
1441 while (!list_empty(list)) {
1442 bf = list_first_entry(list, struct ath_buf, list);
1443
1444 if (bf->bf_stale) {
1445 list_del(&bf->list);
1446
1447 ath_tx_return_buffer(sc, bf);
1448 continue;
1449 }
1450
1451 lastbf = bf->bf_lastbf;
1452 list_cut_position(&bf_head, list, &lastbf->list);
1453
1454 txq->axq_depth--;
1455 if (bf_is_ampdu_not_probing(bf))
1456 txq->axq_ampdu_depth--;
1457
1458 if (bf_isampdu(bf))
1459 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1460 retry_tx);
1461 else
1462 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
1463 }
1464}
1465
1466/*
1467 * Drain a given TX queue (could be Beacon or Data)
1468 *
1469 * This assumes output has been stopped and
1470 * we do not need to block ath_tx_tasklet.
1471 */
1472void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1473{
1474 spin_lock_bh(&txq->axq_lock);
1475 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1476 int idx = txq->txq_tailidx;
1477
1478 while (!list_empty(&txq->txq_fifo[idx])) {
1479 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx],
1480 retry_tx);
1481
1482 INCR(idx, ATH_TXFIFO_DEPTH);
1483 }
1484 txq->txq_tailidx = idx;
1485 }
1486
1487 txq->axq_link = NULL;
1488 txq->axq_tx_inprogress = false;
1489 ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx);
1490
1491 /* flush any pending frames if aggregation is enabled */
1492 if ((sc->sc_flags & SC_OP_TXAGGR) && !retry_tx)
1493 ath_txq_drain_pending_buffers(sc, txq);
1494
1495 spin_unlock_bh(&txq->axq_lock);
1496}
1497
1498bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1499{
1500 struct ath_hw *ah = sc->sc_ah;
1501 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1502 struct ath_txq *txq;
1503 int i;
1504 u32 npend = 0;
1505
1506 if (sc->sc_flags & SC_OP_INVALID)
1507 return true;
1508
1509 ath9k_hw_abort_tx_dma(ah);
1510
1511 /* Check if any queue remains active */
1512 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1513 if (!ATH_TXQ_SETUP(sc, i))
1514 continue;
1515
1516 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1517 npend |= BIT(i);
1518 }
1519
1520 if (npend)
1521 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1522
1523 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1524 if (!ATH_TXQ_SETUP(sc, i))
1525 continue;
1526
1527 /*
1528 * The caller will resume queues with ieee80211_wake_queues.
1529 * Mark the queue as not stopped to prevent ath_tx_complete
1530 * from waking the queue too early.
1531 */
1532 txq = &sc->tx.txq[i];
1533 txq->stopped = false;
1534 ath_draintxq(sc, txq, retry_tx);
1535 }
1536
1537 return !npend;
1538}
1539
1540void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1541{
1542 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1543 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1544}
1545
1546/* For each axq_acq entry, for each tid, try to schedule packets
1547 * for transmit until ampdu_depth has reached min Q depth.
1548 */
1549void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1550{
1551 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1552 struct ath_atx_tid *tid, *last_tid;
1553
1554 if (work_pending(&sc->hw_reset_work) || list_empty(&txq->axq_acq) ||
1555 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1556 return;
1557
1558 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1559 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1560
1561 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1562 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1563 list_del(&ac->list);
1564 ac->sched = false;
1565
1566 while (!list_empty(&ac->tid_q)) {
1567 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1568 list);
1569 list_del(&tid->list);
1570 tid->sched = false;
1571
1572 if (tid->paused)
1573 continue;
1574
1575 ath_tx_sched_aggr(sc, txq, tid);
1576
1577 /*
1578 * add tid to round-robin queue if more frames
1579 * are pending for the tid
1580 */
1581 if (!skb_queue_empty(&tid->buf_q))
1582 ath_tx_queue_tid(txq, tid);
1583
1584 if (tid == last_tid ||
1585 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1586 break;
1587 }
1588
1589 if (!list_empty(&ac->tid_q) && !ac->sched) {
1590 ac->sched = true;
1591 list_add_tail(&ac->list, &txq->axq_acq);
1592 }
1593
1594 if (ac == last_ac ||
1595 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1596 return;
1597 }
1598}
1599
1600/***********/
1601/* TX, DMA */
1602/***********/
1603
1604/*
1605 * Insert a chain of ath_buf (descriptors) on a txq and
1606 * assume the descriptors are already chained together by caller.
1607 */
1608static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1609 struct list_head *head, bool internal)
1610{
1611 struct ath_hw *ah = sc->sc_ah;
1612 struct ath_common *common = ath9k_hw_common(ah);
1613 struct ath_buf *bf, *bf_last;
1614 bool puttxbuf = false;
1615 bool edma;
1616
1617 /*
1618 * Insert the frame on the outbound list and
1619 * pass it on to the hardware.
1620 */
1621
1622 if (list_empty(head))
1623 return;
1624
1625 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1626 bf = list_first_entry(head, struct ath_buf, list);
1627 bf_last = list_entry(head->prev, struct ath_buf, list);
1628
1629 ath_dbg(common, ATH_DBG_QUEUE,
1630 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1631
1632 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1633 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1634 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1635 puttxbuf = true;
1636 } else {
1637 list_splice_tail_init(head, &txq->axq_q);
1638
1639 if (txq->axq_link) {
1640 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1641 ath_dbg(common, ATH_DBG_XMIT,
1642 "link[%u] (%p)=%llx (%p)\n",
1643 txq->axq_qnum, txq->axq_link,
1644 ito64(bf->bf_daddr), bf->bf_desc);
1645 } else if (!edma)
1646 puttxbuf = true;
1647
1648 txq->axq_link = bf_last->bf_desc;
1649 }
1650
1651 if (puttxbuf) {
1652 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1653 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1654 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1655 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1656 }
1657
1658 if (!edma) {
1659 TX_STAT_INC(txq->axq_qnum, txstart);
1660 ath9k_hw_txstart(ah, txq->axq_qnum);
1661 }
1662
1663 if (!internal) {
1664 txq->axq_depth++;
1665 if (bf_is_ampdu_not_probing(bf))
1666 txq->axq_ampdu_depth++;
1667 }
1668}
1669
1670static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1671 struct sk_buff *skb, struct ath_tx_control *txctl)
1672{
1673 struct ath_frame_info *fi = get_frame_info(skb);
1674 struct list_head bf_head;
1675 struct ath_buf *bf;
1676
1677 /*
1678 * Do not queue to h/w when any of the following conditions is true:
1679 * - there are pending frames in software queue
1680 * - the TID is currently paused for ADDBA/BAR request
1681 * - seqno is not within block-ack window
1682 * - h/w queue depth exceeds low water mark
1683 */
1684 if (!skb_queue_empty(&tid->buf_q) || tid->paused ||
1685 !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) ||
1686 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1687 /*
1688 * Add this frame to software queue for scheduling later
1689 * for aggregation.
1690 */
1691 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1692 __skb_queue_tail(&tid->buf_q, skb);
1693 if (!txctl->an || !txctl->an->sleeping)
1694 ath_tx_queue_tid(txctl->txq, tid);
1695 return;
1696 }
1697
1698 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
1699 if (!bf)
1700 return;
1701
1702 bf->bf_state.bf_type = BUF_AMPDU;
1703 INIT_LIST_HEAD(&bf_head);
1704 list_add(&bf->list, &bf_head);
1705
1706 /* Add sub-frame to BAW */
1707 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
1708
1709 /* Queue to h/w without aggregation */
1710 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1711 bf->bf_lastbf = bf;
1712 ath_tx_fill_desc(sc, bf, txctl->txq, fi->framelen);
1713 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
1714}
1715
1716static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1717 struct ath_atx_tid *tid, struct sk_buff *skb)
1718{
1719 struct ath_frame_info *fi = get_frame_info(skb);
1720 struct list_head bf_head;
1721 struct ath_buf *bf;
1722
1723 bf = fi->bf;
1724 if (!bf)
1725 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
1726
1727 if (!bf)
1728 return;
1729
1730 INIT_LIST_HEAD(&bf_head);
1731 list_add_tail(&bf->list, &bf_head);
1732 bf->bf_state.bf_type = 0;
1733
1734 bf->bf_lastbf = bf;
1735 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1736 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1737 TX_STAT_INC(txq->axq_qnum, queued);
1738}
1739
1740static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1741 int framelen)
1742{
1743 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1744 struct ieee80211_sta *sta = tx_info->control.sta;
1745 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1746 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1747 struct ath_frame_info *fi = get_frame_info(skb);
1748 struct ath_node *an = NULL;
1749 enum ath9k_key_type keytype;
1750
1751 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1752
1753 if (sta)
1754 an = (struct ath_node *) sta->drv_priv;
1755
1756 memset(fi, 0, sizeof(*fi));
1757 if (hw_key)
1758 fi->keyix = hw_key->hw_key_idx;
1759 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1760 fi->keyix = an->ps_key;
1761 else
1762 fi->keyix = ATH9K_TXKEYIX_INVALID;
1763 fi->keytype = keytype;
1764 fi->framelen = framelen;
1765}
1766
1767u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1768{
1769 struct ath_hw *ah = sc->sc_ah;
1770 struct ath9k_channel *curchan = ah->curchan;
1771 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
1772 (curchan->channelFlags & CHANNEL_5GHZ) &&
1773 (chainmask == 0x7) && (rate < 0x90))
1774 return 0x3;
1775 else
1776 return chainmask;
1777}
1778
1779/*
1780 * Assign a descriptor (and sequence number if necessary,
1781 * and map buffer for DMA. Frees skb on error
1782 */
1783static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
1784 struct ath_txq *txq,
1785 struct ath_atx_tid *tid,
1786 struct sk_buff *skb)
1787{
1788 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1789 struct ath_frame_info *fi = get_frame_info(skb);
1790 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1791 struct ath_buf *bf;
1792 u16 seqno;
1793
1794 bf = ath_tx_get_buffer(sc);
1795 if (!bf) {
1796 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
1797 goto error;
1798 }
1799
1800 ATH_TXBUF_RESET(bf);
1801
1802 if (tid) {
1803 seqno = tid->seq_next;
1804 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1805 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1806 bf->bf_state.seqno = seqno;
1807 }
1808
1809 bf->bf_mpdu = skb;
1810
1811 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1812 skb->len, DMA_TO_DEVICE);
1813 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1814 bf->bf_mpdu = NULL;
1815 bf->bf_buf_addr = 0;
1816 ath_err(ath9k_hw_common(sc->sc_ah),
1817 "dma_mapping_error() on TX\n");
1818 ath_tx_return_buffer(sc, bf);
1819 goto error;
1820 }
1821
1822 fi->bf = bf;
1823
1824 return bf;
1825
1826error:
1827 dev_kfree_skb_any(skb);
1828 return NULL;
1829}
1830
1831/* FIXME: tx power */
1832static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb,
1833 struct ath_tx_control *txctl)
1834{
1835 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1836 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1837 struct ath_atx_tid *tid = NULL;
1838 struct ath_buf *bf;
1839 u8 tidno;
1840
1841 if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an &&
1842 ieee80211_is_data_qos(hdr->frame_control)) {
1843 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1844 IEEE80211_QOS_CTL_TID_MASK;
1845 tid = ATH_AN_2_TID(txctl->an, tidno);
1846
1847 WARN_ON(tid->ac->txq != txctl->txq);
1848 }
1849
1850 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1851 /*
1852 * Try aggregation if it's a unicast data frame
1853 * and the destination is HT capable.
1854 */
1855 ath_tx_send_ampdu(sc, tid, skb, txctl);
1856 } else {
1857 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
1858 if (!bf)
1859 return;
1860
1861 bf->bf_state.bfs_paprd = txctl->paprd;
1862
1863 if (txctl->paprd)
1864 bf->bf_state.bfs_paprd_timestamp = jiffies;
1865
1866 ath_tx_send_normal(sc, txctl->txq, tid, skb);
1867 }
1868}
1869
1870/* Upon failure caller should free skb */
1871int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1872 struct ath_tx_control *txctl)
1873{
1874 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1875 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1876 struct ieee80211_sta *sta = info->control.sta;
1877 struct ieee80211_vif *vif = info->control.vif;
1878 struct ath_softc *sc = hw->priv;
1879 struct ath_txq *txq = txctl->txq;
1880 int padpos, padsize;
1881 int frmlen = skb->len + FCS_LEN;
1882 int q;
1883
1884 /* NOTE: sta can be NULL according to net/mac80211.h */
1885 if (sta)
1886 txctl->an = (struct ath_node *)sta->drv_priv;
1887
1888 if (info->control.hw_key)
1889 frmlen += info->control.hw_key->icv_len;
1890
1891 /*
1892 * As a temporary workaround, assign seq# here; this will likely need
1893 * to be cleaned up to work better with Beacon transmission and virtual
1894 * BSSes.
1895 */
1896 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1897 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1898 sc->tx.seq_no += 0x10;
1899 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1900 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1901 }
1902
1903 /* Add the padding after the header if this is not already done */
1904 padpos = ath9k_cmn_padpos(hdr->frame_control);
1905 padsize = padpos & 3;
1906 if (padsize && skb->len > padpos) {
1907 if (skb_headroom(skb) < padsize)
1908 return -ENOMEM;
1909
1910 skb_push(skb, padsize);
1911 memmove(skb->data, skb->data + padsize, padpos);
1912 hdr = (struct ieee80211_hdr *) skb->data;
1913 }
1914
1915 if ((vif && vif->type != NL80211_IFTYPE_AP &&
1916 vif->type != NL80211_IFTYPE_AP_VLAN) ||
1917 !ieee80211_is_data(hdr->frame_control))
1918 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1919
1920 setup_frame_info(hw, skb, frmlen);
1921
1922 /*
1923 * At this point, the vif, hw_key and sta pointers in the tx control
1924 * info are no longer valid (overwritten by the ath_frame_info data.
1925 */
1926
1927 q = skb_get_queue_mapping(skb);
1928 spin_lock_bh(&txq->axq_lock);
1929 if (txq == sc->tx.txq_map[q] &&
1930 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1931 ieee80211_stop_queue(sc->hw, q);
1932 txq->stopped = 1;
1933 }
1934
1935 ath_tx_start_dma(sc, skb, txctl);
1936
1937 spin_unlock_bh(&txq->axq_lock);
1938
1939 return 0;
1940}
1941
1942/*****************/
1943/* TX Completion */
1944/*****************/
1945
1946static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1947 int tx_flags, struct ath_txq *txq)
1948{
1949 struct ieee80211_hw *hw = sc->hw;
1950 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1951 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1952 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1953 int q, padpos, padsize;
1954
1955 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1956
1957 if (!(tx_flags & ATH_TX_ERROR))
1958 /* Frame was ACKed */
1959 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1960
1961 padpos = ath9k_cmn_padpos(hdr->frame_control);
1962 padsize = padpos & 3;
1963 if (padsize && skb->len>padpos+padsize) {
1964 /*
1965 * Remove MAC header padding before giving the frame back to
1966 * mac80211.
1967 */
1968 memmove(skb->data + padsize, skb->data, padpos);
1969 skb_pull(skb, padsize);
1970 }
1971
1972 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
1973 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1974 ath_dbg(common, ATH_DBG_PS,
1975 "Going back to sleep after having received TX status (0x%lx)\n",
1976 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1977 PS_WAIT_FOR_CAB |
1978 PS_WAIT_FOR_PSPOLL_DATA |
1979 PS_WAIT_FOR_TX_ACK));
1980 }
1981
1982 q = skb_get_queue_mapping(skb);
1983 if (txq == sc->tx.txq_map[q]) {
1984 if (WARN_ON(--txq->pending_frames < 0))
1985 txq->pending_frames = 0;
1986
1987 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1988 ieee80211_wake_queue(sc->hw, q);
1989 txq->stopped = 0;
1990 }
1991 }
1992
1993 ieee80211_tx_status(hw, skb);
1994}
1995
1996static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1997 struct ath_txq *txq, struct list_head *bf_q,
1998 struct ath_tx_status *ts, int txok)
1999{
2000 struct sk_buff *skb = bf->bf_mpdu;
2001 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2002 unsigned long flags;
2003 int tx_flags = 0;
2004
2005 if (!txok)
2006 tx_flags |= ATH_TX_ERROR;
2007
2008 if (ts->ts_status & ATH9K_TXERR_FILT)
2009 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2010
2011 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2012 bf->bf_buf_addr = 0;
2013
2014 if (bf->bf_state.bfs_paprd) {
2015 if (time_after(jiffies,
2016 bf->bf_state.bfs_paprd_timestamp +
2017 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2018 dev_kfree_skb_any(skb);
2019 else
2020 complete(&sc->paprd_complete);
2021 } else {
2022 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2023 ath_tx_complete(sc, skb, tx_flags, txq);
2024 }
2025 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2026 * accidentally reference it later.
2027 */
2028 bf->bf_mpdu = NULL;
2029
2030 /*
2031 * Return the list of ath_buf of this mpdu to free queue
2032 */
2033 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2034 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2035 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2036}
2037
2038static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2039 struct ath_tx_status *ts, int nframes, int nbad,
2040 int txok)
2041{
2042 struct sk_buff *skb = bf->bf_mpdu;
2043 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2044 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2045 struct ieee80211_hw *hw = sc->hw;
2046 struct ath_hw *ah = sc->sc_ah;
2047 u8 i, tx_rateindex;
2048
2049 if (txok)
2050 tx_info->status.ack_signal = ts->ts_rssi;
2051
2052 tx_rateindex = ts->ts_rateindex;
2053 WARN_ON(tx_rateindex >= hw->max_rates);
2054
2055 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2056 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2057
2058 BUG_ON(nbad > nframes);
2059 }
2060 tx_info->status.ampdu_len = nframes;
2061 tx_info->status.ampdu_ack_len = nframes - nbad;
2062
2063 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2064 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2065 /*
2066 * If an underrun error is seen assume it as an excessive
2067 * retry only if max frame trigger level has been reached
2068 * (2 KB for single stream, and 4 KB for dual stream).
2069 * Adjust the long retry as if the frame was tried
2070 * hw->max_rate_tries times to affect how rate control updates
2071 * PER for the failed rate.
2072 * In case of congestion on the bus penalizing this type of
2073 * underruns should help hardware actually transmit new frames
2074 * successfully by eventually preferring slower rates.
2075 * This itself should also alleviate congestion on the bus.
2076 */
2077 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2078 ATH9K_TX_DELIM_UNDERRUN)) &&
2079 ieee80211_is_data(hdr->frame_control) &&
2080 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2081 tx_info->status.rates[tx_rateindex].count =
2082 hw->max_rate_tries;
2083 }
2084
2085 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2086 tx_info->status.rates[i].count = 0;
2087 tx_info->status.rates[i].idx = -1;
2088 }
2089
2090 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2091}
2092
2093static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
2094 struct ath_tx_status *ts, struct ath_buf *bf,
2095 struct list_head *bf_head)
2096{
2097 int txok;
2098
2099 txq->axq_depth--;
2100 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
2101 txq->axq_tx_inprogress = false;
2102 if (bf_is_ampdu_not_probing(bf))
2103 txq->axq_ampdu_depth--;
2104
2105 if (!bf_isampdu(bf)) {
2106 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
2107 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
2108 } else
2109 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
2110
2111 if (sc->sc_flags & SC_OP_TXAGGR)
2112 ath_txq_schedule(sc, txq);
2113}
2114
2115static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2116{
2117 struct ath_hw *ah = sc->sc_ah;
2118 struct ath_common *common = ath9k_hw_common(ah);
2119 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2120 struct list_head bf_head;
2121 struct ath_desc *ds;
2122 struct ath_tx_status ts;
2123 int status;
2124
2125 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2126 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2127 txq->axq_link);
2128
2129 spin_lock_bh(&txq->axq_lock);
2130 for (;;) {
2131 if (work_pending(&sc->hw_reset_work))
2132 break;
2133
2134 if (list_empty(&txq->axq_q)) {
2135 txq->axq_link = NULL;
2136 if (sc->sc_flags & SC_OP_TXAGGR)
2137 ath_txq_schedule(sc, txq);
2138 break;
2139 }
2140 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2141
2142 /*
2143 * There is a race condition that a BH gets scheduled
2144 * after sw writes TxE and before hw re-load the last
2145 * descriptor to get the newly chained one.
2146 * Software must keep the last DONE descriptor as a
2147 * holding descriptor - software does so by marking
2148 * it with the STALE flag.
2149 */
2150 bf_held = NULL;
2151 if (bf->bf_stale) {
2152 bf_held = bf;
2153 if (list_is_last(&bf_held->list, &txq->axq_q))
2154 break;
2155
2156 bf = list_entry(bf_held->list.next, struct ath_buf,
2157 list);
2158 }
2159
2160 lastbf = bf->bf_lastbf;
2161 ds = lastbf->bf_desc;
2162
2163 memset(&ts, 0, sizeof(ts));
2164 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2165 if (status == -EINPROGRESS)
2166 break;
2167
2168 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2169
2170 /*
2171 * Remove ath_buf's of the same transmit unit from txq,
2172 * however leave the last descriptor back as the holding
2173 * descriptor for hw.
2174 */
2175 lastbf->bf_stale = true;
2176 INIT_LIST_HEAD(&bf_head);
2177 if (!list_is_singular(&lastbf->list))
2178 list_cut_position(&bf_head,
2179 &txq->axq_q, lastbf->list.prev);
2180
2181 if (bf_held) {
2182 list_del(&bf_held->list);
2183 ath_tx_return_buffer(sc, bf_held);
2184 }
2185
2186 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2187 }
2188 spin_unlock_bh(&txq->axq_lock);
2189}
2190
2191static void ath_tx_complete_poll_work(struct work_struct *work)
2192{
2193 struct ath_softc *sc = container_of(work, struct ath_softc,
2194 tx_complete_work.work);
2195 struct ath_txq *txq;
2196 int i;
2197 bool needreset = false;
2198#ifdef CONFIG_ATH9K_DEBUGFS
2199 sc->tx_complete_poll_work_seen++;
2200#endif
2201
2202 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2203 if (ATH_TXQ_SETUP(sc, i)) {
2204 txq = &sc->tx.txq[i];
2205 spin_lock_bh(&txq->axq_lock);
2206 if (txq->axq_depth) {
2207 if (txq->axq_tx_inprogress) {
2208 needreset = true;
2209 spin_unlock_bh(&txq->axq_lock);
2210 break;
2211 } else {
2212 txq->axq_tx_inprogress = true;
2213 }
2214 }
2215 spin_unlock_bh(&txq->axq_lock);
2216 }
2217
2218 if (needreset) {
2219 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2220 "tx hung, resetting the chip\n");
2221 RESET_STAT_INC(sc, RESET_TYPE_TX_HANG);
2222 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
2223 }
2224
2225 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2226 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2227}
2228
2229
2230
2231void ath_tx_tasklet(struct ath_softc *sc)
2232{
2233 int i;
2234 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2235
2236 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2237
2238 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2239 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2240 ath_tx_processq(sc, &sc->tx.txq[i]);
2241 }
2242}
2243
2244void ath_tx_edma_tasklet(struct ath_softc *sc)
2245{
2246 struct ath_tx_status ts;
2247 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2248 struct ath_hw *ah = sc->sc_ah;
2249 struct ath_txq *txq;
2250 struct ath_buf *bf, *lastbf;
2251 struct list_head bf_head;
2252 int status;
2253
2254 for (;;) {
2255 if (work_pending(&sc->hw_reset_work))
2256 break;
2257
2258 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2259 if (status == -EINPROGRESS)
2260 break;
2261 if (status == -EIO) {
2262 ath_dbg(common, ATH_DBG_XMIT,
2263 "Error processing tx status\n");
2264 break;
2265 }
2266
2267 /* Skip beacon completions */
2268 if (ts.qid == sc->beacon.beaconq)
2269 continue;
2270
2271 txq = &sc->tx.txq[ts.qid];
2272
2273 spin_lock_bh(&txq->axq_lock);
2274
2275 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2276 spin_unlock_bh(&txq->axq_lock);
2277 return;
2278 }
2279
2280 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2281 struct ath_buf, list);
2282 lastbf = bf->bf_lastbf;
2283
2284 INIT_LIST_HEAD(&bf_head);
2285 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2286 &lastbf->list);
2287
2288 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2289 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2290
2291 if (!list_empty(&txq->axq_q)) {
2292 struct list_head bf_q;
2293
2294 INIT_LIST_HEAD(&bf_q);
2295 txq->axq_link = NULL;
2296 list_splice_tail_init(&txq->axq_q, &bf_q);
2297 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2298 }
2299 }
2300
2301 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2302 spin_unlock_bh(&txq->axq_lock);
2303 }
2304}
2305
2306/*****************/
2307/* Init, Cleanup */
2308/*****************/
2309
2310static int ath_txstatus_setup(struct ath_softc *sc, int size)
2311{
2312 struct ath_descdma *dd = &sc->txsdma;
2313 u8 txs_len = sc->sc_ah->caps.txs_len;
2314
2315 dd->dd_desc_len = size * txs_len;
2316 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2317 &dd->dd_desc_paddr, GFP_KERNEL);
2318 if (!dd->dd_desc)
2319 return -ENOMEM;
2320
2321 return 0;
2322}
2323
2324static int ath_tx_edma_init(struct ath_softc *sc)
2325{
2326 int err;
2327
2328 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2329 if (!err)
2330 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2331 sc->txsdma.dd_desc_paddr,
2332 ATH_TXSTATUS_RING_SIZE);
2333
2334 return err;
2335}
2336
2337static void ath_tx_edma_cleanup(struct ath_softc *sc)
2338{
2339 struct ath_descdma *dd = &sc->txsdma;
2340
2341 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2342 dd->dd_desc_paddr);
2343}
2344
2345int ath_tx_init(struct ath_softc *sc, int nbufs)
2346{
2347 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2348 int error = 0;
2349
2350 spin_lock_init(&sc->tx.txbuflock);
2351
2352 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2353 "tx", nbufs, 1, 1);
2354 if (error != 0) {
2355 ath_err(common,
2356 "Failed to allocate tx descriptors: %d\n", error);
2357 goto err;
2358 }
2359
2360 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2361 "beacon", ATH_BCBUF, 1, 1);
2362 if (error != 0) {
2363 ath_err(common,
2364 "Failed to allocate beacon descriptors: %d\n", error);
2365 goto err;
2366 }
2367
2368 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2369
2370 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2371 error = ath_tx_edma_init(sc);
2372 if (error)
2373 goto err;
2374 }
2375
2376err:
2377 if (error != 0)
2378 ath_tx_cleanup(sc);
2379
2380 return error;
2381}
2382
2383void ath_tx_cleanup(struct ath_softc *sc)
2384{
2385 if (sc->beacon.bdma.dd_desc_len != 0)
2386 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2387
2388 if (sc->tx.txdma.dd_desc_len != 0)
2389 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2390
2391 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2392 ath_tx_edma_cleanup(sc);
2393}
2394
2395void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2396{
2397 struct ath_atx_tid *tid;
2398 struct ath_atx_ac *ac;
2399 int tidno, acno;
2400
2401 for (tidno = 0, tid = &an->tid[tidno];
2402 tidno < WME_NUM_TID;
2403 tidno++, tid++) {
2404 tid->an = an;
2405 tid->tidno = tidno;
2406 tid->seq_start = tid->seq_next = 0;
2407 tid->baw_size = WME_MAX_BA;
2408 tid->baw_head = tid->baw_tail = 0;
2409 tid->sched = false;
2410 tid->paused = false;
2411 tid->state &= ~AGGR_CLEANUP;
2412 __skb_queue_head_init(&tid->buf_q);
2413 acno = TID_TO_WME_AC(tidno);
2414 tid->ac = &an->ac[acno];
2415 tid->state &= ~AGGR_ADDBA_COMPLETE;
2416 tid->state &= ~AGGR_ADDBA_PROGRESS;
2417 }
2418
2419 for (acno = 0, ac = &an->ac[acno];
2420 acno < WME_NUM_AC; acno++, ac++) {
2421 ac->sched = false;
2422 ac->txq = sc->tx.txq_map[acno];
2423 INIT_LIST_HEAD(&ac->tid_q);
2424 }
2425}
2426
2427void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2428{
2429 struct ath_atx_ac *ac;
2430 struct ath_atx_tid *tid;
2431 struct ath_txq *txq;
2432 int tidno;
2433
2434 for (tidno = 0, tid = &an->tid[tidno];
2435 tidno < WME_NUM_TID; tidno++, tid++) {
2436
2437 ac = tid->ac;
2438 txq = ac->txq;
2439
2440 spin_lock_bh(&txq->axq_lock);
2441
2442 if (tid->sched) {
2443 list_del(&tid->list);
2444 tid->sched = false;
2445 }
2446
2447 if (ac->sched) {
2448 list_del(&ac->list);
2449 tid->ac->sched = false;
2450 }
2451
2452 ath_tid_drain(sc, txq, tid);
2453 tid->state &= ~AGGR_ADDBA_COMPLETE;
2454 tid->state &= ~AGGR_CLEANUP;
2455
2456 spin_unlock_bh(&txq->axq_lock);
2457 }
2458}
Linux kernel - Deliverables
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