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atheros: add common debug printing
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / xmit.c
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1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "ath9k.h"
18
19#define BITS_PER_BYTE 8
20#define OFDM_PLCP_BITS 22
21#define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
22#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
23#define L_STF 8
24#define L_LTF 8
25#define L_SIG 4
26#define HT_SIG 8
27#define HT_STF 4
28#define HT_LTF(_ns) (4 * (_ns))
29#define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31#define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32#define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
33
34#define OFDM_SIFS_TIME 16
35
36static u32 bits_per_symbol[][2] = {
37 /* 20MHz 40MHz */
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
54};
55
56#define IS_HT_RATE(_rate) ((_rate) & 0x80)
57
58static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
59 struct ath_atx_tid *tid,
60 struct list_head *bf_head);
61static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_txq *txq,
63 struct list_head *bf_q,
64 int txok, int sendbar);
65static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
66 struct list_head *head);
67static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
68static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
69 int txok);
70static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
71 int nbad, int txok, bool update_rc);
72
73/*********************/
74/* Aggregation logic */
75/*********************/
76
77static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
78{
79 struct ath_atx_ac *ac = tid->ac;
80
81 if (tid->paused)
82 return;
83
84 if (tid->sched)
85 return;
86
87 tid->sched = true;
88 list_add_tail(&tid->list, &ac->tid_q);
89
90 if (ac->sched)
91 return;
92
93 ac->sched = true;
94 list_add_tail(&ac->list, &txq->axq_acq);
95}
96
97static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
98{
99 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
100
101 spin_lock_bh(&txq->axq_lock);
102 tid->paused++;
103 spin_unlock_bh(&txq->axq_lock);
104}
105
106static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
107{
108 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
109
110 ASSERT(tid->paused > 0);
111 spin_lock_bh(&txq->axq_lock);
112
113 tid->paused--;
114
115 if (tid->paused > 0)
116 goto unlock;
117
118 if (list_empty(&tid->buf_q))
119 goto unlock;
120
121 ath_tx_queue_tid(txq, tid);
122 ath_txq_schedule(sc, txq);
123unlock:
124 spin_unlock_bh(&txq->axq_lock);
125}
126
127static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
128{
129 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
130 struct ath_buf *bf;
131 struct list_head bf_head;
132 INIT_LIST_HEAD(&bf_head);
133
134 ASSERT(tid->paused > 0);
135 spin_lock_bh(&txq->axq_lock);
136
137 tid->paused--;
138
139 if (tid->paused > 0) {
140 spin_unlock_bh(&txq->axq_lock);
141 return;
142 }
143
144 while (!list_empty(&tid->buf_q)) {
145 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
146 ASSERT(!bf_isretried(bf));
147 list_move_tail(&bf->list, &bf_head);
148 ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
149 }
150
151 spin_unlock_bh(&txq->axq_lock);
152}
153
154static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
155 int seqno)
156{
157 int index, cindex;
158
159 index = ATH_BA_INDEX(tid->seq_start, seqno);
160 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
161
162 tid->tx_buf[cindex] = NULL;
163
164 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
165 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
166 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
167 }
168}
169
170static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
171 struct ath_buf *bf)
172{
173 int index, cindex;
174
175 if (bf_isretried(bf))
176 return;
177
178 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
179 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
180
181 ASSERT(tid->tx_buf[cindex] == NULL);
182 tid->tx_buf[cindex] = bf;
183
184 if (index >= ((tid->baw_tail - tid->baw_head) &
185 (ATH_TID_MAX_BUFS - 1))) {
186 tid->baw_tail = cindex;
187 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
188 }
189}
190
191/*
192 * TODO: For frame(s) that are in the retry state, we will reuse the
193 * sequence number(s) without setting the retry bit. The
194 * alternative is to give up on these and BAR the receiver's window
195 * forward.
196 */
197static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
198 struct ath_atx_tid *tid)
199
200{
201 struct ath_buf *bf;
202 struct list_head bf_head;
203 INIT_LIST_HEAD(&bf_head);
204
205 for (;;) {
206 if (list_empty(&tid->buf_q))
207 break;
208
209 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
210 list_move_tail(&bf->list, &bf_head);
211
212 if (bf_isretried(bf))
213 ath_tx_update_baw(sc, tid, bf->bf_seqno);
214
215 spin_unlock(&txq->axq_lock);
216 ath_tx_complete_buf(sc, bf, txq, &bf_head, 0, 0);
217 spin_lock(&txq->axq_lock);
218 }
219
220 tid->seq_next = tid->seq_start;
221 tid->baw_tail = tid->baw_head;
222}
223
224static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
225 struct ath_buf *bf)
226{
227 struct sk_buff *skb;
228 struct ieee80211_hdr *hdr;
229
230 bf->bf_state.bf_type |= BUF_RETRY;
231 bf->bf_retries++;
232 TX_STAT_INC(txq->axq_qnum, a_retries);
233
234 skb = bf->bf_mpdu;
235 hdr = (struct ieee80211_hdr *)skb->data;
236 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
237}
238
239static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
240{
241 struct ath_buf *tbf;
242
243 spin_lock_bh(&sc->tx.txbuflock);
244 if (WARN_ON(list_empty(&sc->tx.txbuf))) {
245 spin_unlock_bh(&sc->tx.txbuflock);
246 return NULL;
247 }
248 tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
249 list_del(&tbf->list);
250 spin_unlock_bh(&sc->tx.txbuflock);
251
252 ATH_TXBUF_RESET(tbf);
253
254 tbf->bf_mpdu = bf->bf_mpdu;
255 tbf->bf_buf_addr = bf->bf_buf_addr;
256 *(tbf->bf_desc) = *(bf->bf_desc);
257 tbf->bf_state = bf->bf_state;
258 tbf->bf_dmacontext = bf->bf_dmacontext;
259
260 return tbf;
261}
262
263static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
264 struct ath_buf *bf, struct list_head *bf_q,
265 int txok)
266{
267 struct ath_node *an = NULL;
268 struct sk_buff *skb;
269 struct ieee80211_sta *sta;
270 struct ieee80211_hdr *hdr;
271 struct ath_atx_tid *tid = NULL;
272 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
273 struct ath_desc *ds = bf_last->bf_desc;
274 struct list_head bf_head, bf_pending;
275 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
276 u32 ba[WME_BA_BMP_SIZE >> 5];
277 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
278 bool rc_update = true;
279
280 skb = bf->bf_mpdu;
281 hdr = (struct ieee80211_hdr *)skb->data;
282
283 rcu_read_lock();
284
285 sta = ieee80211_find_sta(sc->hw, hdr->addr1);
286 if (!sta) {
287 rcu_read_unlock();
288 return;
289 }
290
291 an = (struct ath_node *)sta->drv_priv;
292 tid = ATH_AN_2_TID(an, bf->bf_tidno);
293
294 isaggr = bf_isaggr(bf);
295 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
296
297 if (isaggr && txok) {
298 if (ATH_DS_TX_BA(ds)) {
299 seq_st = ATH_DS_BA_SEQ(ds);
300 memcpy(ba, ATH_DS_BA_BITMAP(ds),
301 WME_BA_BMP_SIZE >> 3);
302 } else {
303 /*
304 * AR5416 can become deaf/mute when BA
305 * issue happens. Chip needs to be reset.
306 * But AP code may have sychronization issues
307 * when perform internal reset in this routine.
308 * Only enable reset in STA mode for now.
309 */
310 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
311 needreset = 1;
312 }
313 }
314
315 INIT_LIST_HEAD(&bf_pending);
316 INIT_LIST_HEAD(&bf_head);
317
318 nbad = ath_tx_num_badfrms(sc, bf, txok);
319 while (bf) {
320 txfail = txpending = 0;
321 bf_next = bf->bf_next;
322
323 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
324 /* transmit completion, subframe is
325 * acked by block ack */
326 acked_cnt++;
327 } else if (!isaggr && txok) {
328 /* transmit completion */
329 acked_cnt++;
330 } else {
331 if (!(tid->state & AGGR_CLEANUP) &&
332 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
333 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
334 ath_tx_set_retry(sc, txq, bf);
335 txpending = 1;
336 } else {
337 bf->bf_state.bf_type |= BUF_XRETRY;
338 txfail = 1;
339 sendbar = 1;
340 txfail_cnt++;
341 }
342 } else {
343 /*
344 * cleanup in progress, just fail
345 * the un-acked sub-frames
346 */
347 txfail = 1;
348 }
349 }
350
351 if (bf_next == NULL) {
352 /*
353 * Make sure the last desc is reclaimed if it
354 * not a holding desc.
355 */
356 if (!bf_last->bf_stale)
357 list_move_tail(&bf->list, &bf_head);
358 else
359 INIT_LIST_HEAD(&bf_head);
360 } else {
361 ASSERT(!list_empty(bf_q));
362 list_move_tail(&bf->list, &bf_head);
363 }
364
365 if (!txpending) {
366 /*
367 * complete the acked-ones/xretried ones; update
368 * block-ack window
369 */
370 spin_lock_bh(&txq->axq_lock);
371 ath_tx_update_baw(sc, tid, bf->bf_seqno);
372 spin_unlock_bh(&txq->axq_lock);
373
374 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
375 ath_tx_rc_status(bf, ds, nbad, txok, true);
376 rc_update = false;
377 } else {
378 ath_tx_rc_status(bf, ds, nbad, txok, false);
379 }
380
381 ath_tx_complete_buf(sc, bf, txq, &bf_head, !txfail, sendbar);
382 } else {
383 /* retry the un-acked ones */
384 if (bf->bf_next == NULL && bf_last->bf_stale) {
385 struct ath_buf *tbf;
386
387 tbf = ath_clone_txbuf(sc, bf_last);
388 /*
389 * Update tx baw and complete the frame with
390 * failed status if we run out of tx buf
391 */
392 if (!tbf) {
393 spin_lock_bh(&txq->axq_lock);
394 ath_tx_update_baw(sc, tid,
395 bf->bf_seqno);
396 spin_unlock_bh(&txq->axq_lock);
397
398 bf->bf_state.bf_type |= BUF_XRETRY;
399 ath_tx_rc_status(bf, ds, nbad,
400 0, false);
401 ath_tx_complete_buf(sc, bf, txq,
402 &bf_head, 0, 0);
403 break;
404 }
405
406 ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc);
407 list_add_tail(&tbf->list, &bf_head);
408 } else {
409 /*
410 * Clear descriptor status words for
411 * software retry
412 */
413 ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc);
414 }
415
416 /*
417 * Put this buffer to the temporary pending
418 * queue to retain ordering
419 */
420 list_splice_tail_init(&bf_head, &bf_pending);
421 }
422
423 bf = bf_next;
424 }
425
426 if (tid->state & AGGR_CLEANUP) {
427 if (tid->baw_head == tid->baw_tail) {
428 tid->state &= ~AGGR_ADDBA_COMPLETE;
429 tid->state &= ~AGGR_CLEANUP;
430
431 /* send buffered frames as singles */
432 ath_tx_flush_tid(sc, tid);
433 }
434 rcu_read_unlock();
435 return;
436 }
437
438 /* prepend un-acked frames to the beginning of the pending frame queue */
439 if (!list_empty(&bf_pending)) {
440 spin_lock_bh(&txq->axq_lock);
441 list_splice(&bf_pending, &tid->buf_q);
442 ath_tx_queue_tid(txq, tid);
443 spin_unlock_bh(&txq->axq_lock);
444 }
445
446 rcu_read_unlock();
447
448 if (needreset)
449 ath_reset(sc, false);
450}
451
452static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
453 struct ath_atx_tid *tid)
454{
455 const struct ath_rate_table *rate_table = sc->cur_rate_table;
456 struct sk_buff *skb;
457 struct ieee80211_tx_info *tx_info;
458 struct ieee80211_tx_rate *rates;
459 struct ath_tx_info_priv *tx_info_priv;
460 u32 max_4ms_framelen, frmlen;
461 u16 aggr_limit, legacy = 0;
462 int i;
463
464 skb = bf->bf_mpdu;
465 tx_info = IEEE80211_SKB_CB(skb);
466 rates = tx_info->control.rates;
467 tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0];
468
469 /*
470 * Find the lowest frame length among the rate series that will have a
471 * 4ms transmit duration.
472 * TODO - TXOP limit needs to be considered.
473 */
474 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
475
476 for (i = 0; i < 4; i++) {
477 if (rates[i].count) {
478 if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) {
479 legacy = 1;
480 break;
481 }
482
483 frmlen = rate_table->info[rates[i].idx].max_4ms_framelen;
484 max_4ms_framelen = min(max_4ms_framelen, frmlen);
485 }
486 }
487
488 /*
489 * limit aggregate size by the minimum rate if rate selected is
490 * not a probe rate, if rate selected is a probe rate then
491 * avoid aggregation of this packet.
492 */
493 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
494 return 0;
495
496 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
497 aggr_limit = min((max_4ms_framelen * 3) / 8,
498 (u32)ATH_AMPDU_LIMIT_MAX);
499 else
500 aggr_limit = min(max_4ms_framelen,
501 (u32)ATH_AMPDU_LIMIT_MAX);
502
503 /*
504 * h/w can accept aggregates upto 16 bit lengths (65535).
505 * The IE, however can hold upto 65536, which shows up here
506 * as zero. Ignore 65536 since we are constrained by hw.
507 */
508 if (tid->an->maxampdu)
509 aggr_limit = min(aggr_limit, tid->an->maxampdu);
510
511 return aggr_limit;
512}
513
514/*
515 * Returns the number of delimiters to be added to
516 * meet the minimum required mpdudensity.
517 */
518static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
519 struct ath_buf *bf, u16 frmlen)
520{
521 const struct ath_rate_table *rt = sc->cur_rate_table;
522 struct sk_buff *skb = bf->bf_mpdu;
523 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
524 u32 nsymbits, nsymbols;
525 u16 minlen;
526 u8 rc, flags, rix;
527 int width, half_gi, ndelim, mindelim;
528
529 /* Select standard number of delimiters based on frame length alone */
530 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
531
532 /*
533 * If encryption enabled, hardware requires some more padding between
534 * subframes.
535 * TODO - this could be improved to be dependent on the rate.
536 * The hardware can keep up at lower rates, but not higher rates
537 */
538 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
539 ndelim += ATH_AGGR_ENCRYPTDELIM;
540
541 /*
542 * Convert desired mpdu density from microeconds to bytes based
543 * on highest rate in rate series (i.e. first rate) to determine
544 * required minimum length for subframe. Take into account
545 * whether high rate is 20 or 40Mhz and half or full GI.
546 *
547 * If there is no mpdu density restriction, no further calculation
548 * is needed.
549 */
550
551 if (tid->an->mpdudensity == 0)
552 return ndelim;
553
554 rix = tx_info->control.rates[0].idx;
555 flags = tx_info->control.rates[0].flags;
556 rc = rt->info[rix].ratecode;
557 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
558 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
559
560 if (half_gi)
561 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
562 else
563 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
564
565 if (nsymbols == 0)
566 nsymbols = 1;
567
568 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
569 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
570
571 if (frmlen < minlen) {
572 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
573 ndelim = max(mindelim, ndelim);
574 }
575
576 return ndelim;
577}
578
579static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
580 struct ath_txq *txq,
581 struct ath_atx_tid *tid,
582 struct list_head *bf_q)
583{
584#define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
585 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
586 int rl = 0, nframes = 0, ndelim, prev_al = 0;
587 u16 aggr_limit = 0, al = 0, bpad = 0,
588 al_delta, h_baw = tid->baw_size / 2;
589 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
590
591 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
592
593 do {
594 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
595
596 /* do not step over block-ack window */
597 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
598 status = ATH_AGGR_BAW_CLOSED;
599 break;
600 }
601
602 if (!rl) {
603 aggr_limit = ath_lookup_rate(sc, bf, tid);
604 rl = 1;
605 }
606
607 /* do not exceed aggregation limit */
608 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
609
610 if (nframes &&
611 (aggr_limit < (al + bpad + al_delta + prev_al))) {
612 status = ATH_AGGR_LIMITED;
613 break;
614 }
615
616 /* do not exceed subframe limit */
617 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
618 status = ATH_AGGR_LIMITED;
619 break;
620 }
621 nframes++;
622
623 /* add padding for previous frame to aggregation length */
624 al += bpad + al_delta;
625
626 /*
627 * Get the delimiters needed to meet the MPDU
628 * density for this node.
629 */
630 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
631 bpad = PADBYTES(al_delta) + (ndelim << 2);
632
633 bf->bf_next = NULL;
634 bf->bf_desc->ds_link = 0;
635
636 /* link buffers of this frame to the aggregate */
637 ath_tx_addto_baw(sc, tid, bf);
638 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
639 list_move_tail(&bf->list, bf_q);
640 if (bf_prev) {
641 bf_prev->bf_next = bf;
642 bf_prev->bf_desc->ds_link = bf->bf_daddr;
643 }
644 bf_prev = bf;
645
646 } while (!list_empty(&tid->buf_q));
647
648 bf_first->bf_al = al;
649 bf_first->bf_nframes = nframes;
650
651 return status;
652#undef PADBYTES
653}
654
655static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
656 struct ath_atx_tid *tid)
657{
658 struct ath_buf *bf;
659 enum ATH_AGGR_STATUS status;
660 struct list_head bf_q;
661
662 do {
663 if (list_empty(&tid->buf_q))
664 return;
665
666 INIT_LIST_HEAD(&bf_q);
667
668 status = ath_tx_form_aggr(sc, txq, tid, &bf_q);
669
670 /*
671 * no frames picked up to be aggregated;
672 * block-ack window is not open.
673 */
674 if (list_empty(&bf_q))
675 break;
676
677 bf = list_first_entry(&bf_q, struct ath_buf, list);
678 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
679
680 /* if only one frame, send as non-aggregate */
681 if (bf->bf_nframes == 1) {
682 bf->bf_state.bf_type &= ~BUF_AGGR;
683 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
684 ath_buf_set_rate(sc, bf);
685 ath_tx_txqaddbuf(sc, txq, &bf_q);
686 continue;
687 }
688
689 /* setup first desc of aggregate */
690 bf->bf_state.bf_type |= BUF_AGGR;
691 ath_buf_set_rate(sc, bf);
692 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
693
694 /* anchor last desc of aggregate */
695 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
696
697 txq->axq_aggr_depth++;
698 ath_tx_txqaddbuf(sc, txq, &bf_q);
699 TX_STAT_INC(txq->axq_qnum, a_aggr);
700
701 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
702 status != ATH_AGGR_BAW_CLOSED);
703}
704
705void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
706 u16 tid, u16 *ssn)
707{
708 struct ath_atx_tid *txtid;
709 struct ath_node *an;
710
711 an = (struct ath_node *)sta->drv_priv;
712 txtid = ATH_AN_2_TID(an, tid);
713 txtid->state |= AGGR_ADDBA_PROGRESS;
714 ath_tx_pause_tid(sc, txtid);
715 *ssn = txtid->seq_start;
716}
717
718void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
719{
720 struct ath_node *an = (struct ath_node *)sta->drv_priv;
721 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
722 struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
723 struct ath_buf *bf;
724 struct list_head bf_head;
725 INIT_LIST_HEAD(&bf_head);
726
727 if (txtid->state & AGGR_CLEANUP)
728 return;
729
730 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
731 txtid->state &= ~AGGR_ADDBA_PROGRESS;
732 return;
733 }
734
735 ath_tx_pause_tid(sc, txtid);
736
737 /* drop all software retried frames and mark this TID */
738 spin_lock_bh(&txq->axq_lock);
739 while (!list_empty(&txtid->buf_q)) {
740 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
741 if (!bf_isretried(bf)) {
742 /*
743 * NB: it's based on the assumption that
744 * software retried frame will always stay
745 * at the head of software queue.
746 */
747 break;
748 }
749 list_move_tail(&bf->list, &bf_head);
750 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
751 ath_tx_complete_buf(sc, bf, txq, &bf_head, 0, 0);
752 }
753 spin_unlock_bh(&txq->axq_lock);
754
755 if (txtid->baw_head != txtid->baw_tail) {
756 txtid->state |= AGGR_CLEANUP;
757 } else {
758 txtid->state &= ~AGGR_ADDBA_COMPLETE;
759 ath_tx_flush_tid(sc, txtid);
760 }
761}
762
763void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
764{
765 struct ath_atx_tid *txtid;
766 struct ath_node *an;
767
768 an = (struct ath_node *)sta->drv_priv;
769
770 if (sc->sc_flags & SC_OP_TXAGGR) {
771 txtid = ATH_AN_2_TID(an, tid);
772 txtid->baw_size =
773 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
774 txtid->state |= AGGR_ADDBA_COMPLETE;
775 txtid->state &= ~AGGR_ADDBA_PROGRESS;
776 ath_tx_resume_tid(sc, txtid);
777 }
778}
779
780bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
781{
782 struct ath_atx_tid *txtid;
783
784 if (!(sc->sc_flags & SC_OP_TXAGGR))
785 return false;
786
787 txtid = ATH_AN_2_TID(an, tidno);
788
789 if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS)))
790 return true;
791 return false;
792}
793
794/********************/
795/* Queue Management */
796/********************/
797
798static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
799 struct ath_txq *txq)
800{
801 struct ath_atx_ac *ac, *ac_tmp;
802 struct ath_atx_tid *tid, *tid_tmp;
803
804 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
805 list_del(&ac->list);
806 ac->sched = false;
807 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
808 list_del(&tid->list);
809 tid->sched = false;
810 ath_tid_drain(sc, txq, tid);
811 }
812 }
813}
814
815struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
816{
817 struct ath_hw *ah = sc->sc_ah;
818 struct ath_common *common = ath9k_hw_common(ah);
819 struct ath9k_tx_queue_info qi;
820 int qnum;
821
822 memset(&qi, 0, sizeof(qi));
823 qi.tqi_subtype = subtype;
824 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
825 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
826 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
827 qi.tqi_physCompBuf = 0;
828
829 /*
830 * Enable interrupts only for EOL and DESC conditions.
831 * We mark tx descriptors to receive a DESC interrupt
832 * when a tx queue gets deep; otherwise waiting for the
833 * EOL to reap descriptors. Note that this is done to
834 * reduce interrupt load and this only defers reaping
835 * descriptors, never transmitting frames. Aside from
836 * reducing interrupts this also permits more concurrency.
837 * The only potential downside is if the tx queue backs
838 * up in which case the top half of the kernel may backup
839 * due to a lack of tx descriptors.
840 *
841 * The UAPSD queue is an exception, since we take a desc-
842 * based intr on the EOSP frames.
843 */
844 if (qtype == ATH9K_TX_QUEUE_UAPSD)
845 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
846 else
847 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
848 TXQ_FLAG_TXDESCINT_ENABLE;
849 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
850 if (qnum == -1) {
851 /*
852 * NB: don't print a message, this happens
853 * normally on parts with too few tx queues
854 */
855 return NULL;
856 }
857 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
858 ath_print(common, ATH_DBG_FATAL,
859 "qnum %u out of range, max %u!\n",
860 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
861 ath9k_hw_releasetxqueue(ah, qnum);
862 return NULL;
863 }
864 if (!ATH_TXQ_SETUP(sc, qnum)) {
865 struct ath_txq *txq = &sc->tx.txq[qnum];
866
867 txq->axq_qnum = qnum;
868 txq->axq_link = NULL;
869 INIT_LIST_HEAD(&txq->axq_q);
870 INIT_LIST_HEAD(&txq->axq_acq);
871 spin_lock_init(&txq->axq_lock);
872 txq->axq_depth = 0;
873 txq->axq_aggr_depth = 0;
874 txq->axq_linkbuf = NULL;
875 txq->axq_tx_inprogress = false;
876 sc->tx.txqsetup |= 1<<qnum;
877 }
878 return &sc->tx.txq[qnum];
879}
880
881int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
882{
883 int qnum;
884
885 switch (qtype) {
886 case ATH9K_TX_QUEUE_DATA:
887 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
888 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
889 "HAL AC %u out of range, max %zu!\n",
890 haltype, ARRAY_SIZE(sc->tx.hwq_map));
891 return -1;
892 }
893 qnum = sc->tx.hwq_map[haltype];
894 break;
895 case ATH9K_TX_QUEUE_BEACON:
896 qnum = sc->beacon.beaconq;
897 break;
898 case ATH9K_TX_QUEUE_CAB:
899 qnum = sc->beacon.cabq->axq_qnum;
900 break;
901 default:
902 qnum = -1;
903 }
904 return qnum;
905}
906
907struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
908{
909 struct ath_txq *txq = NULL;
910 int qnum;
911
912 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
913 txq = &sc->tx.txq[qnum];
914
915 spin_lock_bh(&txq->axq_lock);
916
917 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
918 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_XMIT,
919 "TX queue: %d is full, depth: %d\n",
920 qnum, txq->axq_depth);
921 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
922 txq->stopped = 1;
923 spin_unlock_bh(&txq->axq_lock);
924 return NULL;
925 }
926
927 spin_unlock_bh(&txq->axq_lock);
928
929 return txq;
930}
931
932int ath_txq_update(struct ath_softc *sc, int qnum,
933 struct ath9k_tx_queue_info *qinfo)
934{
935 struct ath_hw *ah = sc->sc_ah;
936 int error = 0;
937 struct ath9k_tx_queue_info qi;
938
939 if (qnum == sc->beacon.beaconq) {
940 /*
941 * XXX: for beacon queue, we just save the parameter.
942 * It will be picked up by ath_beaconq_config when
943 * it's necessary.
944 */
945 sc->beacon.beacon_qi = *qinfo;
946 return 0;
947 }
948
949 ASSERT(sc->tx.txq[qnum].axq_qnum == qnum);
950
951 ath9k_hw_get_txq_props(ah, qnum, &qi);
952 qi.tqi_aifs = qinfo->tqi_aifs;
953 qi.tqi_cwmin = qinfo->tqi_cwmin;
954 qi.tqi_cwmax = qinfo->tqi_cwmax;
955 qi.tqi_burstTime = qinfo->tqi_burstTime;
956 qi.tqi_readyTime = qinfo->tqi_readyTime;
957
958 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
959 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
960 "Unable to update hardware queue %u!\n", qnum);
961 error = -EIO;
962 } else {
963 ath9k_hw_resettxqueue(ah, qnum);
964 }
965
966 return error;
967}
968
969int ath_cabq_update(struct ath_softc *sc)
970{
971 struct ath9k_tx_queue_info qi;
972 int qnum = sc->beacon.cabq->axq_qnum;
973
974 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
975 /*
976 * Ensure the readytime % is within the bounds.
977 */
978 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
979 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
980 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
981 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
982
983 qi.tqi_readyTime = (sc->beacon_interval *
984 sc->config.cabqReadytime) / 100;
985 ath_txq_update(sc, qnum, &qi);
986
987 return 0;
988}
989
990/*
991 * Drain a given TX queue (could be Beacon or Data)
992 *
993 * This assumes output has been stopped and
994 * we do not need to block ath_tx_tasklet.
995 */
996void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
997{
998 struct ath_buf *bf, *lastbf;
999 struct list_head bf_head;
1000
1001 INIT_LIST_HEAD(&bf_head);
1002
1003 for (;;) {
1004 spin_lock_bh(&txq->axq_lock);
1005
1006 if (list_empty(&txq->axq_q)) {
1007 txq->axq_link = NULL;
1008 txq->axq_linkbuf = NULL;
1009 spin_unlock_bh(&txq->axq_lock);
1010 break;
1011 }
1012
1013 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1014
1015 if (bf->bf_stale) {
1016 list_del(&bf->list);
1017 spin_unlock_bh(&txq->axq_lock);
1018
1019 spin_lock_bh(&sc->tx.txbuflock);
1020 list_add_tail(&bf->list, &sc->tx.txbuf);
1021 spin_unlock_bh(&sc->tx.txbuflock);
1022 continue;
1023 }
1024
1025 lastbf = bf->bf_lastbf;
1026 if (!retry_tx)
1027 lastbf->bf_desc->ds_txstat.ts_flags =
1028 ATH9K_TX_SW_ABORTED;
1029
1030 /* remove ath_buf's of the same mpdu from txq */
1031 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1032 txq->axq_depth--;
1033
1034 spin_unlock_bh(&txq->axq_lock);
1035
1036 if (bf_isampdu(bf))
1037 ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0);
1038 else
1039 ath_tx_complete_buf(sc, bf, txq, &bf_head, 0, 0);
1040 }
1041
1042 spin_lock_bh(&txq->axq_lock);
1043 txq->axq_tx_inprogress = false;
1044 spin_unlock_bh(&txq->axq_lock);
1045
1046 /* flush any pending frames if aggregation is enabled */
1047 if (sc->sc_flags & SC_OP_TXAGGR) {
1048 if (!retry_tx) {
1049 spin_lock_bh(&txq->axq_lock);
1050 ath_txq_drain_pending_buffers(sc, txq);
1051 spin_unlock_bh(&txq->axq_lock);
1052 }
1053 }
1054}
1055
1056void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1057{
1058 struct ath_hw *ah = sc->sc_ah;
1059 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1060 struct ath_txq *txq;
1061 int i, npend = 0;
1062
1063 if (sc->sc_flags & SC_OP_INVALID)
1064 return;
1065
1066 /* Stop beacon queue */
1067 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1068
1069 /* Stop data queues */
1070 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1071 if (ATH_TXQ_SETUP(sc, i)) {
1072 txq = &sc->tx.txq[i];
1073 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1074 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1075 }
1076 }
1077
1078 if (npend) {
1079 int r;
1080
1081 ath_print(common, ATH_DBG_XMIT,
1082 "Unable to stop TxDMA. Reset HAL!\n");
1083
1084 spin_lock_bh(&sc->sc_resetlock);
1085 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true);
1086 if (r)
1087 ath_print(common, ATH_DBG_FATAL,
1088 "Unable to reset hardware; reset status %d\n",
1089 r);
1090 spin_unlock_bh(&sc->sc_resetlock);
1091 }
1092
1093 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1094 if (ATH_TXQ_SETUP(sc, i))
1095 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1096 }
1097}
1098
1099void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1100{
1101 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1102 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1103}
1104
1105void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1106{
1107 struct ath_atx_ac *ac;
1108 struct ath_atx_tid *tid;
1109
1110 if (list_empty(&txq->axq_acq))
1111 return;
1112
1113 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1114 list_del(&ac->list);
1115 ac->sched = false;
1116
1117 do {
1118 if (list_empty(&ac->tid_q))
1119 return;
1120
1121 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
1122 list_del(&tid->list);
1123 tid->sched = false;
1124
1125 if (tid->paused)
1126 continue;
1127
1128 ath_tx_sched_aggr(sc, txq, tid);
1129
1130 /*
1131 * add tid to round-robin queue if more frames
1132 * are pending for the tid
1133 */
1134 if (!list_empty(&tid->buf_q))
1135 ath_tx_queue_tid(txq, tid);
1136
1137 break;
1138 } while (!list_empty(&ac->tid_q));
1139
1140 if (!list_empty(&ac->tid_q)) {
1141 if (!ac->sched) {
1142 ac->sched = true;
1143 list_add_tail(&ac->list, &txq->axq_acq);
1144 }
1145 }
1146}
1147
1148int ath_tx_setup(struct ath_softc *sc, int haltype)
1149{
1150 struct ath_txq *txq;
1151
1152 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1153 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1154 "HAL AC %u out of range, max %zu!\n",
1155 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1156 return 0;
1157 }
1158 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
1159 if (txq != NULL) {
1160 sc->tx.hwq_map[haltype] = txq->axq_qnum;
1161 return 1;
1162 } else
1163 return 0;
1164}
1165
1166/***********/
1167/* TX, DMA */
1168/***********/
1169
1170/*
1171 * Insert a chain of ath_buf (descriptors) on a txq and
1172 * assume the descriptors are already chained together by caller.
1173 */
1174static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1175 struct list_head *head)
1176{
1177 struct ath_hw *ah = sc->sc_ah;
1178 struct ath_common *common = ath9k_hw_common(ah);
1179 struct ath_buf *bf;
1180
1181 /*
1182 * Insert the frame on the outbound list and
1183 * pass it on to the hardware.
1184 */
1185
1186 if (list_empty(head))
1187 return;
1188
1189 bf = list_first_entry(head, struct ath_buf, list);
1190
1191 list_splice_tail_init(head, &txq->axq_q);
1192 txq->axq_depth++;
1193 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
1194
1195 ath_print(common, ATH_DBG_QUEUE,
1196 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1197
1198 if (txq->axq_link == NULL) {
1199 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1200 ath_print(common, ATH_DBG_XMIT,
1201 "TXDP[%u] = %llx (%p)\n",
1202 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1203 } else {
1204 *txq->axq_link = bf->bf_daddr;
1205 ath_print(common, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
1206 txq->axq_qnum, txq->axq_link,
1207 ito64(bf->bf_daddr), bf->bf_desc);
1208 }
1209 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
1210 ath9k_hw_txstart(ah, txq->axq_qnum);
1211}
1212
1213static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
1214{
1215 struct ath_buf *bf = NULL;
1216
1217 spin_lock_bh(&sc->tx.txbuflock);
1218
1219 if (unlikely(list_empty(&sc->tx.txbuf))) {
1220 spin_unlock_bh(&sc->tx.txbuflock);
1221 return NULL;
1222 }
1223
1224 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
1225 list_del(&bf->list);
1226
1227 spin_unlock_bh(&sc->tx.txbuflock);
1228
1229 return bf;
1230}
1231
1232static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1233 struct list_head *bf_head,
1234 struct ath_tx_control *txctl)
1235{
1236 struct ath_buf *bf;
1237
1238 bf = list_first_entry(bf_head, struct ath_buf, list);
1239 bf->bf_state.bf_type |= BUF_AMPDU;
1240 TX_STAT_INC(txctl->txq->axq_qnum, a_queued);
1241
1242 /*
1243 * Do not queue to h/w when any of the following conditions is true:
1244 * - there are pending frames in software queue
1245 * - the TID is currently paused for ADDBA/BAR request
1246 * - seqno is not within block-ack window
1247 * - h/w queue depth exceeds low water mark
1248 */
1249 if (!list_empty(&tid->buf_q) || tid->paused ||
1250 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1251 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1252 /*
1253 * Add this frame to software queue for scheduling later
1254 * for aggregation.
1255 */
1256 list_move_tail(&bf->list, &tid->buf_q);
1257 ath_tx_queue_tid(txctl->txq, tid);
1258 return;
1259 }
1260
1261 /* Add sub-frame to BAW */
1262 ath_tx_addto_baw(sc, tid, bf);
1263
1264 /* Queue to h/w without aggregation */
1265 bf->bf_nframes = 1;
1266 bf->bf_lastbf = bf;
1267 ath_buf_set_rate(sc, bf);
1268 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
1269}
1270
1271static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
1272 struct ath_atx_tid *tid,
1273 struct list_head *bf_head)
1274{
1275 struct ath_buf *bf;
1276
1277 bf = list_first_entry(bf_head, struct ath_buf, list);
1278 bf->bf_state.bf_type &= ~BUF_AMPDU;
1279
1280 /* update starting sequence number for subsequent ADDBA request */
1281 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1282
1283 bf->bf_nframes = 1;
1284 bf->bf_lastbf = bf;
1285 ath_buf_set_rate(sc, bf);
1286 ath_tx_txqaddbuf(sc, txq, bf_head);
1287 TX_STAT_INC(txq->axq_qnum, queued);
1288}
1289
1290static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1291 struct list_head *bf_head)
1292{
1293 struct ath_buf *bf;
1294
1295 bf = list_first_entry(bf_head, struct ath_buf, list);
1296
1297 bf->bf_lastbf = bf;
1298 bf->bf_nframes = 1;
1299 ath_buf_set_rate(sc, bf);
1300 ath_tx_txqaddbuf(sc, txq, bf_head);
1301 TX_STAT_INC(txq->axq_qnum, queued);
1302}
1303
1304static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1305{
1306 struct ieee80211_hdr *hdr;
1307 enum ath9k_pkt_type htype;
1308 __le16 fc;
1309
1310 hdr = (struct ieee80211_hdr *)skb->data;
1311 fc = hdr->frame_control;
1312
1313 if (ieee80211_is_beacon(fc))
1314 htype = ATH9K_PKT_TYPE_BEACON;
1315 else if (ieee80211_is_probe_resp(fc))
1316 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1317 else if (ieee80211_is_atim(fc))
1318 htype = ATH9K_PKT_TYPE_ATIM;
1319 else if (ieee80211_is_pspoll(fc))
1320 htype = ATH9K_PKT_TYPE_PSPOLL;
1321 else
1322 htype = ATH9K_PKT_TYPE_NORMAL;
1323
1324 return htype;
1325}
1326
1327static bool is_pae(struct sk_buff *skb)
1328{
1329 struct ieee80211_hdr *hdr;
1330 __le16 fc;
1331
1332 hdr = (struct ieee80211_hdr *)skb->data;
1333 fc = hdr->frame_control;
1334
1335 if (ieee80211_is_data(fc)) {
1336 if (ieee80211_is_nullfunc(fc) ||
1337 /* Port Access Entity (IEEE 802.1X) */
1338 (skb->protocol == cpu_to_be16(ETH_P_PAE))) {
1339 return true;
1340 }
1341 }
1342
1343 return false;
1344}
1345
1346static int get_hw_crypto_keytype(struct sk_buff *skb)
1347{
1348 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1349
1350 if (tx_info->control.hw_key) {
1351 if (tx_info->control.hw_key->alg == ALG_WEP)
1352 return ATH9K_KEY_TYPE_WEP;
1353 else if (tx_info->control.hw_key->alg == ALG_TKIP)
1354 return ATH9K_KEY_TYPE_TKIP;
1355 else if (tx_info->control.hw_key->alg == ALG_CCMP)
1356 return ATH9K_KEY_TYPE_AES;
1357 }
1358
1359 return ATH9K_KEY_TYPE_CLEAR;
1360}
1361
1362static void assign_aggr_tid_seqno(struct sk_buff *skb,
1363 struct ath_buf *bf)
1364{
1365 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1366 struct ieee80211_hdr *hdr;
1367 struct ath_node *an;
1368 struct ath_atx_tid *tid;
1369 __le16 fc;
1370 u8 *qc;
1371
1372 if (!tx_info->control.sta)
1373 return;
1374
1375 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1376 hdr = (struct ieee80211_hdr *)skb->data;
1377 fc = hdr->frame_control;
1378
1379 if (ieee80211_is_data_qos(fc)) {
1380 qc = ieee80211_get_qos_ctl(hdr);
1381 bf->bf_tidno = qc[0] & 0xf;
1382 }
1383
1384 /*
1385 * For HT capable stations, we save tidno for later use.
1386 * We also override seqno set by upper layer with the one
1387 * in tx aggregation state.
1388 *
1389 * If fragmentation is on, the sequence number is
1390 * not overridden, since it has been
1391 * incremented by the fragmentation routine.
1392 *
1393 * FIXME: check if the fragmentation threshold exceeds
1394 * IEEE80211 max.
1395 */
1396 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1397 hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
1398 IEEE80211_SEQ_SEQ_SHIFT);
1399 bf->bf_seqno = tid->seq_next;
1400 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1401}
1402
1403static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
1404 struct ath_txq *txq)
1405{
1406 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1407 int flags = 0;
1408
1409 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1410 flags |= ATH9K_TXDESC_INTREQ;
1411
1412 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1413 flags |= ATH9K_TXDESC_NOACK;
1414
1415 return flags;
1416}
1417
1418/*
1419 * rix - rate index
1420 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1421 * width - 0 for 20 MHz, 1 for 40 MHz
1422 * half_gi - to use 4us v/s 3.6 us for symbol time
1423 */
1424static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1425 int width, int half_gi, bool shortPreamble)
1426{
1427 const struct ath_rate_table *rate_table = sc->cur_rate_table;
1428 u32 nbits, nsymbits, duration, nsymbols;
1429 u8 rc;
1430 int streams, pktlen;
1431
1432 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
1433 rc = rate_table->info[rix].ratecode;
1434
1435 /* for legacy rates, use old function to compute packet duration */
1436 if (!IS_HT_RATE(rc))
1437 return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen,
1438 rix, shortPreamble);
1439
1440 /* find number of symbols: PLCP + data */
1441 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1442 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
1443 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1444
1445 if (!half_gi)
1446 duration = SYMBOL_TIME(nsymbols);
1447 else
1448 duration = SYMBOL_TIME_HALFGI(nsymbols);
1449
1450 /* addup duration for legacy/ht training and signal fields */
1451 streams = HT_RC_2_STREAMS(rc);
1452 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1453
1454 return duration;
1455}
1456
1457static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1458{
1459 const struct ath_rate_table *rt = sc->cur_rate_table;
1460 struct ath9k_11n_rate_series series[4];
1461 struct sk_buff *skb;
1462 struct ieee80211_tx_info *tx_info;
1463 struct ieee80211_tx_rate *rates;
1464 struct ieee80211_hdr *hdr;
1465 int i, flags = 0;
1466 u8 rix = 0, ctsrate = 0;
1467 bool is_pspoll;
1468
1469 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1470
1471 skb = bf->bf_mpdu;
1472 tx_info = IEEE80211_SKB_CB(skb);
1473 rates = tx_info->control.rates;
1474 hdr = (struct ieee80211_hdr *)skb->data;
1475 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1476
1477 /*
1478 * We check if Short Preamble is needed for the CTS rate by
1479 * checking the BSS's global flag.
1480 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1481 */
1482 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1483 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode |
1484 rt->info[tx_info->control.rts_cts_rate_idx].short_preamble;
1485 else
1486 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode;
1487
1488 /*
1489 * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive.
1490 * Check the first rate in the series to decide whether RTS/CTS
1491 * or CTS-to-self has to be used.
1492 */
1493 if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)
1494 flags = ATH9K_TXDESC_CTSENA;
1495 else if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1496 flags = ATH9K_TXDESC_RTSENA;
1497
1498 /* FIXME: Handle aggregation protection */
1499 if (sc->config.ath_aggr_prot &&
1500 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
1501 flags = ATH9K_TXDESC_RTSENA;
1502 }
1503
1504 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1505 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
1506 flags &= ~(ATH9K_TXDESC_RTSENA);
1507
1508 for (i = 0; i < 4; i++) {
1509 if (!rates[i].count || (rates[i].idx < 0))
1510 continue;
1511
1512 rix = rates[i].idx;
1513 series[i].Tries = rates[i].count;
1514 series[i].ChSel = sc->tx_chainmask;
1515
1516 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1517 series[i].Rate = rt->info[rix].ratecode |
1518 rt->info[rix].short_preamble;
1519 else
1520 series[i].Rate = rt->info[rix].ratecode;
1521
1522 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1523 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1524 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1525 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1526 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1527 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1528
1529 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
1530 (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0,
1531 (rates[i].flags & IEEE80211_TX_RC_SHORT_GI),
1532 (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE));
1533 }
1534
1535 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1536 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1537 bf->bf_lastbf->bf_desc,
1538 !is_pspoll, ctsrate,
1539 0, series, 4, flags);
1540
1541 if (sc->config.ath_aggr_prot && flags)
1542 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1543}
1544
1545static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1546 struct sk_buff *skb,
1547 struct ath_tx_control *txctl)
1548{
1549 struct ath_wiphy *aphy = hw->priv;
1550 struct ath_softc *sc = aphy->sc;
1551 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1552 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1553 struct ath_tx_info_priv *tx_info_priv;
1554 int hdrlen;
1555 __le16 fc;
1556
1557 tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC);
1558 if (unlikely(!tx_info_priv))
1559 return -ENOMEM;
1560 tx_info->rate_driver_data[0] = tx_info_priv;
1561 tx_info_priv->aphy = aphy;
1562 tx_info_priv->frame_type = txctl->frame_type;
1563 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1564 fc = hdr->frame_control;
1565
1566 ATH_TXBUF_RESET(bf);
1567
1568 bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3);
1569
1570 if (conf_is_ht(&sc->hw->conf) && !is_pae(skb))
1571 bf->bf_state.bf_type |= BUF_HT;
1572
1573 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
1574
1575 bf->bf_keytype = get_hw_crypto_keytype(skb);
1576 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1577 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1578 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1579 } else {
1580 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1581 }
1582
1583 if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR))
1584 assign_aggr_tid_seqno(skb, bf);
1585
1586 bf->bf_mpdu = skb;
1587
1588 bf->bf_dmacontext = dma_map_single(sc->dev, skb->data,
1589 skb->len, DMA_TO_DEVICE);
1590 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
1591 bf->bf_mpdu = NULL;
1592 kfree(tx_info_priv);
1593 tx_info->rate_driver_data[0] = NULL;
1594 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1595 "dma_mapping_error() on TX\n");
1596 return -ENOMEM;
1597 }
1598
1599 bf->bf_buf_addr = bf->bf_dmacontext;
1600 return 0;
1601}
1602
1603/* FIXME: tx power */
1604static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1605 struct ath_tx_control *txctl)
1606{
1607 struct sk_buff *skb = bf->bf_mpdu;
1608 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1609 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1610 struct ath_node *an = NULL;
1611 struct list_head bf_head;
1612 struct ath_desc *ds;
1613 struct ath_atx_tid *tid;
1614 struct ath_hw *ah = sc->sc_ah;
1615 int frm_type;
1616 __le16 fc;
1617
1618 frm_type = get_hw_packet_type(skb);
1619 fc = hdr->frame_control;
1620
1621 INIT_LIST_HEAD(&bf_head);
1622 list_add_tail(&bf->list, &bf_head);
1623
1624 ds = bf->bf_desc;
1625 ds->ds_link = 0;
1626 ds->ds_data = bf->bf_buf_addr;
1627
1628 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1629 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
1630
1631 ath9k_hw_filltxdesc(ah, ds,
1632 skb->len, /* segment length */
1633 true, /* first segment */
1634 true, /* last segment */
1635 ds); /* first descriptor */
1636
1637 spin_lock_bh(&txctl->txq->axq_lock);
1638
1639 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
1640 tx_info->control.sta) {
1641 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1642 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1643
1644 if (!ieee80211_is_data_qos(fc)) {
1645 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1646 goto tx_done;
1647 }
1648
1649 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
1650 /*
1651 * Try aggregation if it's a unicast data frame
1652 * and the destination is HT capable.
1653 */
1654 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1655 } else {
1656 /*
1657 * Send this frame as regular when ADDBA
1658 * exchange is neither complete nor pending.
1659 */
1660 ath_tx_send_ht_normal(sc, txctl->txq,
1661 tid, &bf_head);
1662 }
1663 } else {
1664 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1665 }
1666
1667tx_done:
1668 spin_unlock_bh(&txctl->txq->axq_lock);
1669}
1670
1671/* Upon failure caller should free skb */
1672int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1673 struct ath_tx_control *txctl)
1674{
1675 struct ath_wiphy *aphy = hw->priv;
1676 struct ath_softc *sc = aphy->sc;
1677 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1678 struct ath_buf *bf;
1679 int r;
1680
1681 bf = ath_tx_get_buffer(sc);
1682 if (!bf) {
1683 ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
1684 return -1;
1685 }
1686
1687 r = ath_tx_setup_buffer(hw, bf, skb, txctl);
1688 if (unlikely(r)) {
1689 struct ath_txq *txq = txctl->txq;
1690
1691 ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n");
1692
1693 /* upon ath_tx_processq() this TX queue will be resumed, we
1694 * guarantee this will happen by knowing beforehand that
1695 * we will at least have to run TX completionon one buffer
1696 * on the queue */
1697 spin_lock_bh(&txq->axq_lock);
1698 if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) {
1699 ieee80211_stop_queue(sc->hw,
1700 skb_get_queue_mapping(skb));
1701 txq->stopped = 1;
1702 }
1703 spin_unlock_bh(&txq->axq_lock);
1704
1705 spin_lock_bh(&sc->tx.txbuflock);
1706 list_add_tail(&bf->list, &sc->tx.txbuf);
1707 spin_unlock_bh(&sc->tx.txbuflock);
1708
1709 return r;
1710 }
1711
1712 ath_tx_start_dma(sc, bf, txctl);
1713
1714 return 0;
1715}
1716
1717void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1718{
1719 struct ath_wiphy *aphy = hw->priv;
1720 struct ath_softc *sc = aphy->sc;
1721 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1722 int hdrlen, padsize;
1723 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1724 struct ath_tx_control txctl;
1725
1726 memset(&txctl, 0, sizeof(struct ath_tx_control));
1727
1728 /*
1729 * As a temporary workaround, assign seq# here; this will likely need
1730 * to be cleaned up to work better with Beacon transmission and virtual
1731 * BSSes.
1732 */
1733 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1734 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1735 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1736 sc->tx.seq_no += 0x10;
1737 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1738 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1739 }
1740
1741 /* Add the padding after the header if this is not already done */
1742 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1743 if (hdrlen & 3) {
1744 padsize = hdrlen % 4;
1745 if (skb_headroom(skb) < padsize) {
1746 ath_print(common, ATH_DBG_XMIT,
1747 "TX CABQ padding failed\n");
1748 dev_kfree_skb_any(skb);
1749 return;
1750 }
1751 skb_push(skb, padsize);
1752 memmove(skb->data, skb->data + padsize, hdrlen);
1753 }
1754
1755 txctl.txq = sc->beacon.cabq;
1756
1757 ath_print(common, ATH_DBG_XMIT,
1758 "transmitting CABQ packet, skb: %p\n", skb);
1759
1760 if (ath_tx_start(hw, skb, &txctl) != 0) {
1761 ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n");
1762 goto exit;
1763 }
1764
1765 return;
1766exit:
1767 dev_kfree_skb_any(skb);
1768}
1769
1770/*****************/
1771/* TX Completion */
1772/*****************/
1773
1774static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1775 int tx_flags)
1776{
1777 struct ieee80211_hw *hw = sc->hw;
1778 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1779 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1780 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1781 int hdrlen, padsize;
1782 int frame_type = ATH9K_NOT_INTERNAL;
1783
1784 ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1785
1786 if (tx_info_priv) {
1787 hw = tx_info_priv->aphy->hw;
1788 frame_type = tx_info_priv->frame_type;
1789 }
1790
1791 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
1792 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
1793 kfree(tx_info_priv);
1794 tx_info->rate_driver_data[0] = NULL;
1795 }
1796
1797 if (tx_flags & ATH_TX_BAR)
1798 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1799
1800 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1801 /* Frame was ACKed */
1802 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1803 }
1804
1805 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1806 padsize = hdrlen & 3;
1807 if (padsize && hdrlen >= 24) {
1808 /*
1809 * Remove MAC header padding before giving the frame back to
1810 * mac80211.
1811 */
1812 memmove(skb->data + padsize, skb->data, hdrlen);
1813 skb_pull(skb, padsize);
1814 }
1815
1816 if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) {
1817 sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK;
1818 ath_print(common, ATH_DBG_PS,
1819 "Going back to sleep after having "
1820 "received TX status (0x%x)\n",
1821 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
1822 SC_OP_WAIT_FOR_CAB |
1823 SC_OP_WAIT_FOR_PSPOLL_DATA |
1824 SC_OP_WAIT_FOR_TX_ACK));
1825 }
1826
1827 if (frame_type == ATH9K_NOT_INTERNAL)
1828 ieee80211_tx_status(hw, skb);
1829 else
1830 ath9k_tx_status(hw, skb);
1831}
1832
1833static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1834 struct ath_txq *txq,
1835 struct list_head *bf_q,
1836 int txok, int sendbar)
1837{
1838 struct sk_buff *skb = bf->bf_mpdu;
1839 unsigned long flags;
1840 int tx_flags = 0;
1841
1842 if (sendbar)
1843 tx_flags = ATH_TX_BAR;
1844
1845 if (!txok) {
1846 tx_flags |= ATH_TX_ERROR;
1847
1848 if (bf_isxretried(bf))
1849 tx_flags |= ATH_TX_XRETRY;
1850 }
1851
1852 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
1853 ath_tx_complete(sc, skb, tx_flags);
1854 ath_debug_stat_tx(sc, txq, bf);
1855
1856 /*
1857 * Return the list of ath_buf of this mpdu to free queue
1858 */
1859 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1860 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1861 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1862}
1863
1864static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
1865 int txok)
1866{
1867 struct ath_buf *bf_last = bf->bf_lastbf;
1868 struct ath_desc *ds = bf_last->bf_desc;
1869 u16 seq_st = 0;
1870 u32 ba[WME_BA_BMP_SIZE >> 5];
1871 int ba_index;
1872 int nbad = 0;
1873 int isaggr = 0;
1874
1875 if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
1876 return 0;
1877
1878 isaggr = bf_isaggr(bf);
1879 if (isaggr) {
1880 seq_st = ATH_DS_BA_SEQ(ds);
1881 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
1882 }
1883
1884 while (bf) {
1885 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
1886 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
1887 nbad++;
1888
1889 bf = bf->bf_next;
1890 }
1891
1892 return nbad;
1893}
1894
1895static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
1896 int nbad, int txok, bool update_rc)
1897{
1898 struct sk_buff *skb = bf->bf_mpdu;
1899 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1900 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1901 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1902 struct ieee80211_hw *hw = tx_info_priv->aphy->hw;
1903 u8 i, tx_rateindex;
1904
1905 if (txok)
1906 tx_info->status.ack_signal = ds->ds_txstat.ts_rssi;
1907
1908 tx_rateindex = ds->ds_txstat.ts_rateindex;
1909 WARN_ON(tx_rateindex >= hw->max_rates);
1910
1911 tx_info_priv->update_rc = update_rc;
1912 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
1913 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1914
1915 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
1916 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
1917 if (ieee80211_is_data(hdr->frame_control)) {
1918 memcpy(&tx_info_priv->tx, &ds->ds_txstat,
1919 sizeof(tx_info_priv->tx));
1920 tx_info_priv->n_frames = bf->bf_nframes;
1921 tx_info_priv->n_bad_frames = nbad;
1922 }
1923 }
1924
1925 for (i = tx_rateindex + 1; i < hw->max_rates; i++)
1926 tx_info->status.rates[i].count = 0;
1927
1928 tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1;
1929}
1930
1931static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1932{
1933 int qnum;
1934
1935 spin_lock_bh(&txq->axq_lock);
1936 if (txq->stopped &&
1937 sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) {
1938 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1939 if (qnum != -1) {
1940 ieee80211_wake_queue(sc->hw, qnum);
1941 txq->stopped = 0;
1942 }
1943 }
1944 spin_unlock_bh(&txq->axq_lock);
1945}
1946
1947static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1948{
1949 struct ath_hw *ah = sc->sc_ah;
1950 struct ath_common *common = ath9k_hw_common(ah);
1951 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1952 struct list_head bf_head;
1953 struct ath_desc *ds;
1954 int txok;
1955 int status;
1956
1957 ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
1958 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1959 txq->axq_link);
1960
1961 for (;;) {
1962 spin_lock_bh(&txq->axq_lock);
1963 if (list_empty(&txq->axq_q)) {
1964 txq->axq_link = NULL;
1965 txq->axq_linkbuf = NULL;
1966 spin_unlock_bh(&txq->axq_lock);
1967 break;
1968 }
1969 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1970
1971 /*
1972 * There is a race condition that a BH gets scheduled
1973 * after sw writes TxE and before hw re-load the last
1974 * descriptor to get the newly chained one.
1975 * Software must keep the last DONE descriptor as a
1976 * holding descriptor - software does so by marking
1977 * it with the STALE flag.
1978 */
1979 bf_held = NULL;
1980 if (bf->bf_stale) {
1981 bf_held = bf;
1982 if (list_is_last(&bf_held->list, &txq->axq_q)) {
1983 spin_unlock_bh(&txq->axq_lock);
1984 break;
1985 } else {
1986 bf = list_entry(bf_held->list.next,
1987 struct ath_buf, list);
1988 }
1989 }
1990
1991 lastbf = bf->bf_lastbf;
1992 ds = lastbf->bf_desc;
1993
1994 status = ath9k_hw_txprocdesc(ah, ds);
1995 if (status == -EINPROGRESS) {
1996 spin_unlock_bh(&txq->axq_lock);
1997 break;
1998 }
1999 if (bf->bf_desc == txq->axq_lastdsWithCTS)
2000 txq->axq_lastdsWithCTS = NULL;
2001 if (ds == txq->axq_gatingds)
2002 txq->axq_gatingds = NULL;
2003
2004 /*
2005 * Remove ath_buf's of the same transmit unit from txq,
2006 * however leave the last descriptor back as the holding
2007 * descriptor for hw.
2008 */
2009 lastbf->bf_stale = true;
2010 INIT_LIST_HEAD(&bf_head);
2011 if (!list_is_singular(&lastbf->list))
2012 list_cut_position(&bf_head,
2013 &txq->axq_q, lastbf->list.prev);
2014
2015 txq->axq_depth--;
2016 if (bf_isaggr(bf))
2017 txq->axq_aggr_depth--;
2018
2019 txok = (ds->ds_txstat.ts_status == 0);
2020 txq->axq_tx_inprogress = false;
2021 spin_unlock_bh(&txq->axq_lock);
2022
2023 if (bf_held) {
2024 spin_lock_bh(&sc->tx.txbuflock);
2025 list_move_tail(&bf_held->list, &sc->tx.txbuf);
2026 spin_unlock_bh(&sc->tx.txbuflock);
2027 }
2028
2029 if (!bf_isampdu(bf)) {
2030 /*
2031 * This frame is sent out as a single frame.
2032 * Use hardware retry status for this frame.
2033 */
2034 bf->bf_retries = ds->ds_txstat.ts_longretry;
2035 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
2036 bf->bf_state.bf_type |= BUF_XRETRY;
2037 ath_tx_rc_status(bf, ds, 0, txok, true);
2038 }
2039
2040 if (bf_isampdu(bf))
2041 ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok);
2042 else
2043 ath_tx_complete_buf(sc, bf, txq, &bf_head, txok, 0);
2044
2045 ath_wake_mac80211_queue(sc, txq);
2046
2047 spin_lock_bh(&txq->axq_lock);
2048 if (sc->sc_flags & SC_OP_TXAGGR)
2049 ath_txq_schedule(sc, txq);
2050 spin_unlock_bh(&txq->axq_lock);
2051 }
2052}
2053
2054static void ath_tx_complete_poll_work(struct work_struct *work)
2055{
2056 struct ath_softc *sc = container_of(work, struct ath_softc,
2057 tx_complete_work.work);
2058 struct ath_txq *txq;
2059 int i;
2060 bool needreset = false;
2061
2062 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2063 if (ATH_TXQ_SETUP(sc, i)) {
2064 txq = &sc->tx.txq[i];
2065 spin_lock_bh(&txq->axq_lock);
2066 if (txq->axq_depth) {
2067 if (txq->axq_tx_inprogress) {
2068 needreset = true;
2069 spin_unlock_bh(&txq->axq_lock);
2070 break;
2071 } else {
2072 txq->axq_tx_inprogress = true;
2073 }
2074 }
2075 spin_unlock_bh(&txq->axq_lock);
2076 }
2077
2078 if (needreset) {
2079 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2080 "tx hung, resetting the chip\n");
2081 ath_reset(sc, false);
2082 }
2083
2084 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2085 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2086}
2087
2088
2089
2090void ath_tx_tasklet(struct ath_softc *sc)
2091{
2092 int i;
2093 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2094
2095 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2096
2097 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2098 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2099 ath_tx_processq(sc, &sc->tx.txq[i]);
2100 }
2101}
2102
2103/*****************/
2104/* Init, Cleanup */
2105/*****************/
2106
2107int ath_tx_init(struct ath_softc *sc, int nbufs)
2108{
2109 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2110 int error = 0;
2111
2112 spin_lock_init(&sc->tx.txbuflock);
2113
2114 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2115 "tx", nbufs, 1);
2116 if (error != 0) {
2117 ath_print(common, ATH_DBG_FATAL,
2118 "Failed to allocate tx descriptors: %d\n", error);
2119 goto err;
2120 }
2121
2122 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2123 "beacon", ATH_BCBUF, 1);
2124 if (error != 0) {
2125 ath_print(common, ATH_DBG_FATAL,
2126 "Failed to allocate beacon descriptors: %d\n", error);
2127 goto err;
2128 }
2129
2130 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2131
2132err:
2133 if (error != 0)
2134 ath_tx_cleanup(sc);
2135
2136 return error;
2137}
2138
2139void ath_tx_cleanup(struct ath_softc *sc)
2140{
2141 if (sc->beacon.bdma.dd_desc_len != 0)
2142 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2143
2144 if (sc->tx.txdma.dd_desc_len != 0)
2145 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2146}
2147
2148void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2149{
2150 struct ath_atx_tid *tid;
2151 struct ath_atx_ac *ac;
2152 int tidno, acno;
2153
2154 for (tidno = 0, tid = &an->tid[tidno];
2155 tidno < WME_NUM_TID;
2156 tidno++, tid++) {
2157 tid->an = an;
2158 tid->tidno = tidno;
2159 tid->seq_start = tid->seq_next = 0;
2160 tid->baw_size = WME_MAX_BA;
2161 tid->baw_head = tid->baw_tail = 0;
2162 tid->sched = false;
2163 tid->paused = false;
2164 tid->state &= ~AGGR_CLEANUP;
2165 INIT_LIST_HEAD(&tid->buf_q);
2166 acno = TID_TO_WME_AC(tidno);
2167 tid->ac = &an->ac[acno];
2168 tid->state &= ~AGGR_ADDBA_COMPLETE;
2169 tid->state &= ~AGGR_ADDBA_PROGRESS;
2170 }
2171
2172 for (acno = 0, ac = &an->ac[acno];
2173 acno < WME_NUM_AC; acno++, ac++) {
2174 ac->sched = false;
2175 INIT_LIST_HEAD(&ac->tid_q);
2176
2177 switch (acno) {
2178 case WME_AC_BE:
2179 ac->qnum = ath_tx_get_qnum(sc,
2180 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2181 break;
2182 case WME_AC_BK:
2183 ac->qnum = ath_tx_get_qnum(sc,
2184 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2185 break;
2186 case WME_AC_VI:
2187 ac->qnum = ath_tx_get_qnum(sc,
2188 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2189 break;
2190 case WME_AC_VO:
2191 ac->qnum = ath_tx_get_qnum(sc,
2192 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2193 break;
2194 }
2195 }
2196}
2197
2198void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2199{
2200 int i;
2201 struct ath_atx_ac *ac, *ac_tmp;
2202 struct ath_atx_tid *tid, *tid_tmp;
2203 struct ath_txq *txq;
2204
2205 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2206 if (ATH_TXQ_SETUP(sc, i)) {
2207 txq = &sc->tx.txq[i];
2208
2209 spin_lock(&txq->axq_lock);
2210
2211 list_for_each_entry_safe(ac,
2212 ac_tmp, &txq->axq_acq, list) {
2213 tid = list_first_entry(&ac->tid_q,
2214 struct ath_atx_tid, list);
2215 if (tid && tid->an != an)
2216 continue;
2217 list_del(&ac->list);
2218 ac->sched = false;
2219
2220 list_for_each_entry_safe(tid,
2221 tid_tmp, &ac->tid_q, list) {
2222 list_del(&tid->list);
2223 tid->sched = false;
2224 ath_tid_drain(sc, txq, tid);
2225 tid->state &= ~AGGR_ADDBA_COMPLETE;
2226 tid->state &= ~AGGR_CLEANUP;
2227 }
2228 }
2229
2230 spin_unlock(&txq->axq_lock);
2231 }
2232 }
2233}
Linux kernel - Deliverables
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