| 1 | /* Copyright (c) 2014 Broadcom Corporation |
| 2 | * |
| 3 | * Permission to use, copy, modify, and/or distribute this software for any |
| 4 | * purpose with or without fee is hereby granted, provided that the above |
| 5 | * copyright notice and this permission notice appear in all copies. |
| 6 | * |
| 7 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 8 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 9 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
| 10 | * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 11 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION |
| 12 | * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN |
| 13 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 14 | */ |
| 15 | |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/module.h> |
| 18 | #include <linux/firmware.h> |
| 19 | #include <linux/pci.h> |
| 20 | #include <linux/vmalloc.h> |
| 21 | #include <linux/delay.h> |
| 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/bcma/bcma.h> |
| 24 | #include <linux/sched.h> |
| 25 | #include <asm/unaligned.h> |
| 26 | |
| 27 | #include <soc.h> |
| 28 | #include <chipcommon.h> |
| 29 | #include <brcmu_utils.h> |
| 30 | #include <brcmu_wifi.h> |
| 31 | #include <brcm_hw_ids.h> |
| 32 | |
| 33 | #include "debug.h" |
| 34 | #include "bus.h" |
| 35 | #include "commonring.h" |
| 36 | #include "msgbuf.h" |
| 37 | #include "pcie.h" |
| 38 | #include "firmware.h" |
| 39 | #include "chip.h" |
| 40 | |
| 41 | |
| 42 | enum brcmf_pcie_state { |
| 43 | BRCMFMAC_PCIE_STATE_DOWN, |
| 44 | BRCMFMAC_PCIE_STATE_UP |
| 45 | }; |
| 46 | |
| 47 | |
| 48 | #define BRCMF_PCIE_43602_FW_NAME "brcm/brcmfmac43602-pcie.bin" |
| 49 | #define BRCMF_PCIE_43602_NVRAM_NAME "brcm/brcmfmac43602-pcie.txt" |
| 50 | #define BRCMF_PCIE_4356_FW_NAME "brcm/brcmfmac4356-pcie.bin" |
| 51 | #define BRCMF_PCIE_4356_NVRAM_NAME "brcm/brcmfmac4356-pcie.txt" |
| 52 | #define BRCMF_PCIE_43570_FW_NAME "brcm/brcmfmac43570-pcie.bin" |
| 53 | #define BRCMF_PCIE_43570_NVRAM_NAME "brcm/brcmfmac43570-pcie.txt" |
| 54 | #define BRCMF_PCIE_4358_FW_NAME "brcm/brcmfmac4358-pcie.bin" |
| 55 | #define BRCMF_PCIE_4358_NVRAM_NAME "brcm/brcmfmac4358-pcie.txt" |
| 56 | |
| 57 | #define BRCMF_PCIE_FW_UP_TIMEOUT 2000 /* msec */ |
| 58 | |
| 59 | #define BRCMF_PCIE_TCM_MAP_SIZE (4096 * 1024) |
| 60 | #define BRCMF_PCIE_REG_MAP_SIZE (32 * 1024) |
| 61 | |
| 62 | /* backplane addres space accessed by BAR0 */ |
| 63 | #define BRCMF_PCIE_BAR0_WINDOW 0x80 |
| 64 | #define BRCMF_PCIE_BAR0_REG_SIZE 0x1000 |
| 65 | #define BRCMF_PCIE_BAR0_WRAPPERBASE 0x70 |
| 66 | |
| 67 | #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET 0x1000 |
| 68 | #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET 0x2000 |
| 69 | |
| 70 | #define BRCMF_PCIE_ARMCR4REG_BANKIDX 0x40 |
| 71 | #define BRCMF_PCIE_ARMCR4REG_BANKPDA 0x4C |
| 72 | |
| 73 | #define BRCMF_PCIE_REG_INTSTATUS 0x90 |
| 74 | #define BRCMF_PCIE_REG_INTMASK 0x94 |
| 75 | #define BRCMF_PCIE_REG_SBMBX 0x98 |
| 76 | |
| 77 | #define BRCMF_PCIE_PCIE2REG_INTMASK 0x24 |
| 78 | #define BRCMF_PCIE_PCIE2REG_MAILBOXINT 0x48 |
| 79 | #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C |
| 80 | #define BRCMF_PCIE_PCIE2REG_CONFIGADDR 0x120 |
| 81 | #define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124 |
| 82 | #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX 0x140 |
| 83 | |
| 84 | #define BRCMF_PCIE_GENREV1 1 |
| 85 | #define BRCMF_PCIE_GENREV2 2 |
| 86 | |
| 87 | #define BRCMF_PCIE2_INTA 0x01 |
| 88 | #define BRCMF_PCIE2_INTB 0x02 |
| 89 | |
| 90 | #define BRCMF_PCIE_INT_0 0x01 |
| 91 | #define BRCMF_PCIE_INT_1 0x02 |
| 92 | #define BRCMF_PCIE_INT_DEF (BRCMF_PCIE_INT_0 | \ |
| 93 | BRCMF_PCIE_INT_1) |
| 94 | |
| 95 | #define BRCMF_PCIE_MB_INT_FN0_0 0x0100 |
| 96 | #define BRCMF_PCIE_MB_INT_FN0_1 0x0200 |
| 97 | #define BRCMF_PCIE_MB_INT_D2H0_DB0 0x10000 |
| 98 | #define BRCMF_PCIE_MB_INT_D2H0_DB1 0x20000 |
| 99 | #define BRCMF_PCIE_MB_INT_D2H1_DB0 0x40000 |
| 100 | #define BRCMF_PCIE_MB_INT_D2H1_DB1 0x80000 |
| 101 | #define BRCMF_PCIE_MB_INT_D2H2_DB0 0x100000 |
| 102 | #define BRCMF_PCIE_MB_INT_D2H2_DB1 0x200000 |
| 103 | #define BRCMF_PCIE_MB_INT_D2H3_DB0 0x400000 |
| 104 | #define BRCMF_PCIE_MB_INT_D2H3_DB1 0x800000 |
| 105 | |
| 106 | #define BRCMF_PCIE_MB_INT_D2H_DB (BRCMF_PCIE_MB_INT_D2H0_DB0 | \ |
| 107 | BRCMF_PCIE_MB_INT_D2H0_DB1 | \ |
| 108 | BRCMF_PCIE_MB_INT_D2H1_DB0 | \ |
| 109 | BRCMF_PCIE_MB_INT_D2H1_DB1 | \ |
| 110 | BRCMF_PCIE_MB_INT_D2H2_DB0 | \ |
| 111 | BRCMF_PCIE_MB_INT_D2H2_DB1 | \ |
| 112 | BRCMF_PCIE_MB_INT_D2H3_DB0 | \ |
| 113 | BRCMF_PCIE_MB_INT_D2H3_DB1) |
| 114 | |
| 115 | #define BRCMF_PCIE_MIN_SHARED_VERSION 4 |
| 116 | #define BRCMF_PCIE_MAX_SHARED_VERSION 5 |
| 117 | #define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF |
| 118 | #define BRCMF_PCIE_SHARED_TXPUSH_SUPPORT 0x4000 |
| 119 | |
| 120 | #define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000 |
| 121 | #define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000 |
| 122 | |
| 123 | #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET 34 |
| 124 | #define BRCMF_SHARED_RING_BASE_OFFSET 52 |
| 125 | #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET 36 |
| 126 | #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET 20 |
| 127 | #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET 40 |
| 128 | #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET 44 |
| 129 | #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET 48 |
| 130 | #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET 52 |
| 131 | #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET 56 |
| 132 | #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET 64 |
| 133 | #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET 68 |
| 134 | |
| 135 | #define BRCMF_RING_H2D_RING_COUNT_OFFSET 0 |
| 136 | #define BRCMF_RING_D2H_RING_COUNT_OFFSET 1 |
| 137 | #define BRCMF_RING_H2D_RING_MEM_OFFSET 4 |
| 138 | #define BRCMF_RING_H2D_RING_STATE_OFFSET 8 |
| 139 | |
| 140 | #define BRCMF_RING_MEM_BASE_ADDR_OFFSET 8 |
| 141 | #define BRCMF_RING_MAX_ITEM_OFFSET 4 |
| 142 | #define BRCMF_RING_LEN_ITEMS_OFFSET 6 |
| 143 | #define BRCMF_RING_MEM_SZ 16 |
| 144 | #define BRCMF_RING_STATE_SZ 8 |
| 145 | |
| 146 | #define BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET 4 |
| 147 | #define BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET 8 |
| 148 | #define BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET 12 |
| 149 | #define BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET 16 |
| 150 | #define BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET 0 |
| 151 | #define BRCMF_SHARED_RING_MAX_SUB_QUEUES 52 |
| 152 | |
| 153 | #define BRCMF_DEF_MAX_RXBUFPOST 255 |
| 154 | |
| 155 | #define BRCMF_CONSOLE_BUFADDR_OFFSET 8 |
| 156 | #define BRCMF_CONSOLE_BUFSIZE_OFFSET 12 |
| 157 | #define BRCMF_CONSOLE_WRITEIDX_OFFSET 16 |
| 158 | |
| 159 | #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN 8 |
| 160 | #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN 1024 |
| 161 | |
| 162 | #define BRCMF_D2H_DEV_D3_ACK 0x00000001 |
| 163 | #define BRCMF_D2H_DEV_DS_ENTER_REQ 0x00000002 |
| 164 | #define BRCMF_D2H_DEV_DS_EXIT_NOTE 0x00000004 |
| 165 | |
| 166 | #define BRCMF_H2D_HOST_D3_INFORM 0x00000001 |
| 167 | #define BRCMF_H2D_HOST_DS_ACK 0x00000002 |
| 168 | #define BRCMF_H2D_HOST_D0_INFORM_IN_USE 0x00000008 |
| 169 | #define BRCMF_H2D_HOST_D0_INFORM 0x00000010 |
| 170 | |
| 171 | #define BRCMF_PCIE_MBDATA_TIMEOUT 2000 |
| 172 | |
| 173 | #define BRCMF_PCIE_CFGREG_STATUS_CMD 0x4 |
| 174 | #define BRCMF_PCIE_CFGREG_PM_CSR 0x4C |
| 175 | #define BRCMF_PCIE_CFGREG_MSI_CAP 0x58 |
| 176 | #define BRCMF_PCIE_CFGREG_MSI_ADDR_L 0x5C |
| 177 | #define BRCMF_PCIE_CFGREG_MSI_ADDR_H 0x60 |
| 178 | #define BRCMF_PCIE_CFGREG_MSI_DATA 0x64 |
| 179 | #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL 0xBC |
| 180 | #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2 0xDC |
| 181 | #define BRCMF_PCIE_CFGREG_RBAR_CTRL 0x228 |
| 182 | #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1 0x248 |
| 183 | #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG 0x4E0 |
| 184 | #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG 0x4F4 |
| 185 | #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB 3 |
| 186 | |
| 187 | |
| 188 | MODULE_FIRMWARE(BRCMF_PCIE_43602_FW_NAME); |
| 189 | MODULE_FIRMWARE(BRCMF_PCIE_43602_NVRAM_NAME); |
| 190 | MODULE_FIRMWARE(BRCMF_PCIE_4356_FW_NAME); |
| 191 | MODULE_FIRMWARE(BRCMF_PCIE_4356_NVRAM_NAME); |
| 192 | MODULE_FIRMWARE(BRCMF_PCIE_43570_FW_NAME); |
| 193 | MODULE_FIRMWARE(BRCMF_PCIE_43570_NVRAM_NAME); |
| 194 | MODULE_FIRMWARE(BRCMF_PCIE_4358_FW_NAME); |
| 195 | MODULE_FIRMWARE(BRCMF_PCIE_4358_NVRAM_NAME); |
| 196 | |
| 197 | |
| 198 | struct brcmf_pcie_console { |
| 199 | u32 base_addr; |
| 200 | u32 buf_addr; |
| 201 | u32 bufsize; |
| 202 | u32 read_idx; |
| 203 | u8 log_str[256]; |
| 204 | u8 log_idx; |
| 205 | }; |
| 206 | |
| 207 | struct brcmf_pcie_shared_info { |
| 208 | u32 tcm_base_address; |
| 209 | u32 flags; |
| 210 | struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS]; |
| 211 | struct brcmf_pcie_ringbuf *flowrings; |
| 212 | u16 max_rxbufpost; |
| 213 | u32 nrof_flowrings; |
| 214 | u32 rx_dataoffset; |
| 215 | u32 htod_mb_data_addr; |
| 216 | u32 dtoh_mb_data_addr; |
| 217 | u32 ring_info_addr; |
| 218 | struct brcmf_pcie_console console; |
| 219 | void *scratch; |
| 220 | dma_addr_t scratch_dmahandle; |
| 221 | void *ringupd; |
| 222 | dma_addr_t ringupd_dmahandle; |
| 223 | }; |
| 224 | |
| 225 | struct brcmf_pcie_core_info { |
| 226 | u32 base; |
| 227 | u32 wrapbase; |
| 228 | }; |
| 229 | |
| 230 | struct brcmf_pciedev_info { |
| 231 | enum brcmf_pcie_state state; |
| 232 | bool in_irq; |
| 233 | bool irq_requested; |
| 234 | struct pci_dev *pdev; |
| 235 | char fw_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN]; |
| 236 | char nvram_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN]; |
| 237 | void __iomem *regs; |
| 238 | void __iomem *tcm; |
| 239 | u32 tcm_size; |
| 240 | u32 ram_base; |
| 241 | u32 ram_size; |
| 242 | struct brcmf_chip *ci; |
| 243 | u32 coreid; |
| 244 | u32 generic_corerev; |
| 245 | struct brcmf_pcie_shared_info shared; |
| 246 | void (*ringbell)(struct brcmf_pciedev_info *devinfo); |
| 247 | wait_queue_head_t mbdata_resp_wait; |
| 248 | bool mbdata_completed; |
| 249 | bool irq_allocated; |
| 250 | bool wowl_enabled; |
| 251 | }; |
| 252 | |
| 253 | struct brcmf_pcie_ringbuf { |
| 254 | struct brcmf_commonring commonring; |
| 255 | dma_addr_t dma_handle; |
| 256 | u32 w_idx_addr; |
| 257 | u32 r_idx_addr; |
| 258 | struct brcmf_pciedev_info *devinfo; |
| 259 | u8 id; |
| 260 | }; |
| 261 | |
| 262 | |
| 263 | static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = { |
| 264 | BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM, |
| 265 | BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM, |
| 266 | BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM, |
| 267 | BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM, |
| 268 | BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM |
| 269 | }; |
| 270 | |
| 271 | static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = { |
| 272 | BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE, |
| 273 | BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE, |
| 274 | BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE, |
| 275 | BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE, |
| 276 | BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE |
| 277 | }; |
| 278 | |
| 279 | |
| 280 | /* dma flushing needs implementation for mips and arm platforms. Should |
| 281 | * be put in util. Note, this is not real flushing. It is virtual non |
| 282 | * cached memory. Only write buffers should have to be drained. Though |
| 283 | * this may be different depending on platform...... |
| 284 | */ |
| 285 | #define brcmf_dma_flush(addr, len) |
| 286 | #define brcmf_dma_invalidate_cache(addr, len) |
| 287 | |
| 288 | |
| 289 | static u32 |
| 290 | brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset) |
| 291 | { |
| 292 | void __iomem *address = devinfo->regs + reg_offset; |
| 293 | |
| 294 | return (ioread32(address)); |
| 295 | } |
| 296 | |
| 297 | |
| 298 | static void |
| 299 | brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset, |
| 300 | u32 value) |
| 301 | { |
| 302 | void __iomem *address = devinfo->regs + reg_offset; |
| 303 | |
| 304 | iowrite32(value, address); |
| 305 | } |
| 306 | |
| 307 | |
| 308 | static u8 |
| 309 | brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset) |
| 310 | { |
| 311 | void __iomem *address = devinfo->tcm + mem_offset; |
| 312 | |
| 313 | return (ioread8(address)); |
| 314 | } |
| 315 | |
| 316 | |
| 317 | static u16 |
| 318 | brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset) |
| 319 | { |
| 320 | void __iomem *address = devinfo->tcm + mem_offset; |
| 321 | |
| 322 | return (ioread16(address)); |
| 323 | } |
| 324 | |
| 325 | |
| 326 | static void |
| 327 | brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset, |
| 328 | u16 value) |
| 329 | { |
| 330 | void __iomem *address = devinfo->tcm + mem_offset; |
| 331 | |
| 332 | iowrite16(value, address); |
| 333 | } |
| 334 | |
| 335 | |
| 336 | static u32 |
| 337 | brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset) |
| 338 | { |
| 339 | void __iomem *address = devinfo->tcm + mem_offset; |
| 340 | |
| 341 | return (ioread32(address)); |
| 342 | } |
| 343 | |
| 344 | |
| 345 | static void |
| 346 | brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset, |
| 347 | u32 value) |
| 348 | { |
| 349 | void __iomem *address = devinfo->tcm + mem_offset; |
| 350 | |
| 351 | iowrite32(value, address); |
| 352 | } |
| 353 | |
| 354 | |
| 355 | static u32 |
| 356 | brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset) |
| 357 | { |
| 358 | void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset; |
| 359 | |
| 360 | return (ioread32(addr)); |
| 361 | } |
| 362 | |
| 363 | |
| 364 | static void |
| 365 | brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset, |
| 366 | u32 value) |
| 367 | { |
| 368 | void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset; |
| 369 | |
| 370 | iowrite32(value, addr); |
| 371 | } |
| 372 | |
| 373 | |
| 374 | static void |
| 375 | brcmf_pcie_copy_mem_todev(struct brcmf_pciedev_info *devinfo, u32 mem_offset, |
| 376 | void *srcaddr, u32 len) |
| 377 | { |
| 378 | void __iomem *address = devinfo->tcm + mem_offset; |
| 379 | __le32 *src32; |
| 380 | __le16 *src16; |
| 381 | u8 *src8; |
| 382 | |
| 383 | if (((ulong)address & 4) || ((ulong)srcaddr & 4) || (len & 4)) { |
| 384 | if (((ulong)address & 2) || ((ulong)srcaddr & 2) || (len & 2)) { |
| 385 | src8 = (u8 *)srcaddr; |
| 386 | while (len) { |
| 387 | iowrite8(*src8, address); |
| 388 | address++; |
| 389 | src8++; |
| 390 | len--; |
| 391 | } |
| 392 | } else { |
| 393 | len = len / 2; |
| 394 | src16 = (__le16 *)srcaddr; |
| 395 | while (len) { |
| 396 | iowrite16(le16_to_cpu(*src16), address); |
| 397 | address += 2; |
| 398 | src16++; |
| 399 | len--; |
| 400 | } |
| 401 | } |
| 402 | } else { |
| 403 | len = len / 4; |
| 404 | src32 = (__le32 *)srcaddr; |
| 405 | while (len) { |
| 406 | iowrite32(le32_to_cpu(*src32), address); |
| 407 | address += 4; |
| 408 | src32++; |
| 409 | len--; |
| 410 | } |
| 411 | } |
| 412 | } |
| 413 | |
| 414 | |
| 415 | #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \ |
| 416 | CHIPCREGOFFS(reg), value) |
| 417 | |
| 418 | |
| 419 | static void |
| 420 | brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid) |
| 421 | { |
| 422 | const struct pci_dev *pdev = devinfo->pdev; |
| 423 | struct brcmf_core *core; |
| 424 | u32 bar0_win; |
| 425 | |
| 426 | core = brcmf_chip_get_core(devinfo->ci, coreid); |
| 427 | if (core) { |
| 428 | bar0_win = core->base; |
| 429 | pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win); |
| 430 | if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, |
| 431 | &bar0_win) == 0) { |
| 432 | if (bar0_win != core->base) { |
| 433 | bar0_win = core->base; |
| 434 | pci_write_config_dword(pdev, |
| 435 | BRCMF_PCIE_BAR0_WINDOW, |
| 436 | bar0_win); |
| 437 | } |
| 438 | } |
| 439 | } else { |
| 440 | brcmf_err("Unsupported core selected %x\n", coreid); |
| 441 | } |
| 442 | } |
| 443 | |
| 444 | |
| 445 | static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo) |
| 446 | { |
| 447 | u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD, |
| 448 | BRCMF_PCIE_CFGREG_PM_CSR, |
| 449 | BRCMF_PCIE_CFGREG_MSI_CAP, |
| 450 | BRCMF_PCIE_CFGREG_MSI_ADDR_L, |
| 451 | BRCMF_PCIE_CFGREG_MSI_ADDR_H, |
| 452 | BRCMF_PCIE_CFGREG_MSI_DATA, |
| 453 | BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2, |
| 454 | BRCMF_PCIE_CFGREG_RBAR_CTRL, |
| 455 | BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1, |
| 456 | BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG, |
| 457 | BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG }; |
| 458 | u32 i; |
| 459 | u32 val; |
| 460 | u32 lsc; |
| 461 | |
| 462 | if (!devinfo->ci) |
| 463 | return; |
| 464 | |
| 465 | brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); |
| 466 | brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, |
| 467 | BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL); |
| 468 | lsc = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA); |
| 469 | val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB); |
| 470 | brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, val); |
| 471 | |
| 472 | brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON); |
| 473 | WRITECC32(devinfo, watchdog, 4); |
| 474 | msleep(100); |
| 475 | |
| 476 | brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); |
| 477 | brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, |
| 478 | BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL); |
| 479 | brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, lsc); |
| 480 | |
| 481 | brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); |
| 482 | for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) { |
| 483 | brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, |
| 484 | cfg_offset[i]); |
| 485 | val = brcmf_pcie_read_reg32(devinfo, |
| 486 | BRCMF_PCIE_PCIE2REG_CONFIGDATA); |
| 487 | brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n", |
| 488 | cfg_offset[i], val); |
| 489 | brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, |
| 490 | val); |
| 491 | } |
| 492 | } |
| 493 | |
| 494 | |
| 495 | static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo) |
| 496 | { |
| 497 | u32 config; |
| 498 | |
| 499 | brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); |
| 500 | if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_INTMASK) != 0) |
| 501 | brcmf_pcie_reset_device(devinfo); |
| 502 | /* BAR1 window may not be sized properly */ |
| 503 | brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); |
| 504 | brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0); |
| 505 | config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA); |
| 506 | brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config); |
| 507 | |
| 508 | device_wakeup_enable(&devinfo->pdev->dev); |
| 509 | } |
| 510 | |
| 511 | |
| 512 | static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo) |
| 513 | { |
| 514 | if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) { |
| 515 | brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4); |
| 516 | brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX, |
| 517 | 5); |
| 518 | brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA, |
| 519 | 0); |
| 520 | brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX, |
| 521 | 7); |
| 522 | brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA, |
| 523 | 0); |
| 524 | } |
| 525 | return 0; |
| 526 | } |
| 527 | |
| 528 | |
| 529 | static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo, |
| 530 | u32 resetintr) |
| 531 | { |
| 532 | struct brcmf_core *core; |
| 533 | |
| 534 | if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) { |
| 535 | core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM); |
| 536 | brcmf_chip_resetcore(core, 0, 0, 0); |
| 537 | } |
| 538 | |
| 539 | return !brcmf_chip_set_active(devinfo->ci, resetintr); |
| 540 | } |
| 541 | |
| 542 | |
| 543 | static int |
| 544 | brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data) |
| 545 | { |
| 546 | struct brcmf_pcie_shared_info *shared; |
| 547 | u32 addr; |
| 548 | u32 cur_htod_mb_data; |
| 549 | u32 i; |
| 550 | |
| 551 | shared = &devinfo->shared; |
| 552 | addr = shared->htod_mb_data_addr; |
| 553 | cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); |
| 554 | |
| 555 | if (cur_htod_mb_data != 0) |
| 556 | brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n", |
| 557 | cur_htod_mb_data); |
| 558 | |
| 559 | i = 0; |
| 560 | while (cur_htod_mb_data != 0) { |
| 561 | msleep(10); |
| 562 | i++; |
| 563 | if (i > 100) |
| 564 | return -EIO; |
| 565 | cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); |
| 566 | } |
| 567 | |
| 568 | brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data); |
| 569 | pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1); |
| 570 | pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1); |
| 571 | |
| 572 | return 0; |
| 573 | } |
| 574 | |
| 575 | |
| 576 | static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo) |
| 577 | { |
| 578 | struct brcmf_pcie_shared_info *shared; |
| 579 | u32 addr; |
| 580 | u32 dtoh_mb_data; |
| 581 | |
| 582 | shared = &devinfo->shared; |
| 583 | addr = shared->dtoh_mb_data_addr; |
| 584 | dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); |
| 585 | |
| 586 | if (!dtoh_mb_data) |
| 587 | return; |
| 588 | |
| 589 | brcmf_pcie_write_tcm32(devinfo, addr, 0); |
| 590 | |
| 591 | brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data); |
| 592 | if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ) { |
| 593 | brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n"); |
| 594 | brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK); |
| 595 | brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n"); |
| 596 | } |
| 597 | if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE) |
| 598 | brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n"); |
| 599 | if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) { |
| 600 | brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n"); |
| 601 | if (waitqueue_active(&devinfo->mbdata_resp_wait)) { |
| 602 | devinfo->mbdata_completed = true; |
| 603 | wake_up(&devinfo->mbdata_resp_wait); |
| 604 | } |
| 605 | } |
| 606 | } |
| 607 | |
| 608 | |
| 609 | static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo) |
| 610 | { |
| 611 | struct brcmf_pcie_shared_info *shared; |
| 612 | struct brcmf_pcie_console *console; |
| 613 | u32 addr; |
| 614 | |
| 615 | shared = &devinfo->shared; |
| 616 | console = &shared->console; |
| 617 | addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET; |
| 618 | console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr); |
| 619 | |
| 620 | addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET; |
| 621 | console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr); |
| 622 | addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET; |
| 623 | console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr); |
| 624 | |
| 625 | brcmf_dbg(PCIE, "Console: base %x, buf %x, size %d\n", |
| 626 | console->base_addr, console->buf_addr, console->bufsize); |
| 627 | } |
| 628 | |
| 629 | |
| 630 | static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo) |
| 631 | { |
| 632 | struct brcmf_pcie_console *console; |
| 633 | u32 addr; |
| 634 | u8 ch; |
| 635 | u32 newidx; |
| 636 | |
| 637 | console = &devinfo->shared.console; |
| 638 | addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET; |
| 639 | newidx = brcmf_pcie_read_tcm32(devinfo, addr); |
| 640 | while (newidx != console->read_idx) { |
| 641 | addr = console->buf_addr + console->read_idx; |
| 642 | ch = brcmf_pcie_read_tcm8(devinfo, addr); |
| 643 | console->read_idx++; |
| 644 | if (console->read_idx == console->bufsize) |
| 645 | console->read_idx = 0; |
| 646 | if (ch == '\r') |
| 647 | continue; |
| 648 | console->log_str[console->log_idx] = ch; |
| 649 | console->log_idx++; |
| 650 | if ((ch != '\n') && |
| 651 | (console->log_idx == (sizeof(console->log_str) - 2))) { |
| 652 | ch = '\n'; |
| 653 | console->log_str[console->log_idx] = ch; |
| 654 | console->log_idx++; |
| 655 | } |
| 656 | if (ch == '\n') { |
| 657 | console->log_str[console->log_idx] = 0; |
| 658 | brcmf_dbg(PCIE, "CONSOLE: %s", console->log_str); |
| 659 | console->log_idx = 0; |
| 660 | } |
| 661 | } |
| 662 | } |
| 663 | |
| 664 | |
| 665 | static __used void brcmf_pcie_ringbell_v1(struct brcmf_pciedev_info *devinfo) |
| 666 | { |
| 667 | u32 reg_value; |
| 668 | |
| 669 | brcmf_dbg(PCIE, "RING !\n"); |
| 670 | reg_value = brcmf_pcie_read_reg32(devinfo, |
| 671 | BRCMF_PCIE_PCIE2REG_MAILBOXINT); |
| 672 | reg_value |= BRCMF_PCIE2_INTB; |
| 673 | brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, |
| 674 | reg_value); |
| 675 | } |
| 676 | |
| 677 | |
| 678 | static void brcmf_pcie_ringbell_v2(struct brcmf_pciedev_info *devinfo) |
| 679 | { |
| 680 | brcmf_dbg(PCIE, "RING !\n"); |
| 681 | /* Any arbitrary value will do, lets use 1 */ |
| 682 | brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1); |
| 683 | } |
| 684 | |
| 685 | |
| 686 | static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo) |
| 687 | { |
| 688 | if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) |
| 689 | pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK, |
| 690 | 0); |
| 691 | else |
| 692 | brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK, |
| 693 | 0); |
| 694 | } |
| 695 | |
| 696 | |
| 697 | static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo) |
| 698 | { |
| 699 | if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) |
| 700 | pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK, |
| 701 | BRCMF_PCIE_INT_DEF); |
| 702 | else |
| 703 | brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK, |
| 704 | BRCMF_PCIE_MB_INT_D2H_DB | |
| 705 | BRCMF_PCIE_MB_INT_FN0_0 | |
| 706 | BRCMF_PCIE_MB_INT_FN0_1); |
| 707 | } |
| 708 | |
| 709 | |
| 710 | static irqreturn_t brcmf_pcie_quick_check_isr_v1(int irq, void *arg) |
| 711 | { |
| 712 | struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg; |
| 713 | u32 status; |
| 714 | |
| 715 | status = 0; |
| 716 | pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTSTATUS, &status); |
| 717 | if (status) { |
| 718 | brcmf_pcie_intr_disable(devinfo); |
| 719 | brcmf_dbg(PCIE, "Enter\n"); |
| 720 | return IRQ_WAKE_THREAD; |
| 721 | } |
| 722 | return IRQ_NONE; |
| 723 | } |
| 724 | |
| 725 | |
| 726 | static irqreturn_t brcmf_pcie_quick_check_isr_v2(int irq, void *arg) |
| 727 | { |
| 728 | struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg; |
| 729 | |
| 730 | if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) { |
| 731 | brcmf_pcie_intr_disable(devinfo); |
| 732 | brcmf_dbg(PCIE, "Enter\n"); |
| 733 | return IRQ_WAKE_THREAD; |
| 734 | } |
| 735 | return IRQ_NONE; |
| 736 | } |
| 737 | |
| 738 | |
| 739 | static irqreturn_t brcmf_pcie_isr_thread_v1(int irq, void *arg) |
| 740 | { |
| 741 | struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg; |
| 742 | const struct pci_dev *pdev = devinfo->pdev; |
| 743 | u32 status; |
| 744 | |
| 745 | devinfo->in_irq = true; |
| 746 | status = 0; |
| 747 | pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status); |
| 748 | brcmf_dbg(PCIE, "Enter %x\n", status); |
| 749 | if (status) { |
| 750 | pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status); |
| 751 | if (devinfo->state == BRCMFMAC_PCIE_STATE_UP) |
| 752 | brcmf_proto_msgbuf_rx_trigger(&devinfo->pdev->dev); |
| 753 | } |
| 754 | if (devinfo->state == BRCMFMAC_PCIE_STATE_UP) |
| 755 | brcmf_pcie_intr_enable(devinfo); |
| 756 | devinfo->in_irq = false; |
| 757 | return IRQ_HANDLED; |
| 758 | } |
| 759 | |
| 760 | |
| 761 | static irqreturn_t brcmf_pcie_isr_thread_v2(int irq, void *arg) |
| 762 | { |
| 763 | struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg; |
| 764 | u32 status; |
| 765 | |
| 766 | devinfo->in_irq = true; |
| 767 | status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT); |
| 768 | brcmf_dbg(PCIE, "Enter %x\n", status); |
| 769 | if (status) { |
| 770 | brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, |
| 771 | status); |
| 772 | if (status & (BRCMF_PCIE_MB_INT_FN0_0 | |
| 773 | BRCMF_PCIE_MB_INT_FN0_1)) |
| 774 | brcmf_pcie_handle_mb_data(devinfo); |
| 775 | if (status & BRCMF_PCIE_MB_INT_D2H_DB) { |
| 776 | if (devinfo->state == BRCMFMAC_PCIE_STATE_UP) |
| 777 | brcmf_proto_msgbuf_rx_trigger( |
| 778 | &devinfo->pdev->dev); |
| 779 | } |
| 780 | } |
| 781 | brcmf_pcie_bus_console_read(devinfo); |
| 782 | if (devinfo->state == BRCMFMAC_PCIE_STATE_UP) |
| 783 | brcmf_pcie_intr_enable(devinfo); |
| 784 | devinfo->in_irq = false; |
| 785 | return IRQ_HANDLED; |
| 786 | } |
| 787 | |
| 788 | |
| 789 | static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo) |
| 790 | { |
| 791 | struct pci_dev *pdev; |
| 792 | |
| 793 | pdev = devinfo->pdev; |
| 794 | |
| 795 | brcmf_pcie_intr_disable(devinfo); |
| 796 | |
| 797 | brcmf_dbg(PCIE, "Enter\n"); |
| 798 | /* is it a v1 or v2 implementation */ |
| 799 | devinfo->irq_requested = false; |
| 800 | pci_enable_msi(pdev); |
| 801 | if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) { |
| 802 | if (request_threaded_irq(pdev->irq, |
| 803 | brcmf_pcie_quick_check_isr_v1, |
| 804 | brcmf_pcie_isr_thread_v1, |
| 805 | IRQF_SHARED, "brcmf_pcie_intr", |
| 806 | devinfo)) { |
| 807 | pci_disable_msi(pdev); |
| 808 | brcmf_err("Failed to request IRQ %d\n", pdev->irq); |
| 809 | return -EIO; |
| 810 | } |
| 811 | } else { |
| 812 | if (request_threaded_irq(pdev->irq, |
| 813 | brcmf_pcie_quick_check_isr_v2, |
| 814 | brcmf_pcie_isr_thread_v2, |
| 815 | IRQF_SHARED, "brcmf_pcie_intr", |
| 816 | devinfo)) { |
| 817 | pci_disable_msi(pdev); |
| 818 | brcmf_err("Failed to request IRQ %d\n", pdev->irq); |
| 819 | return -EIO; |
| 820 | } |
| 821 | } |
| 822 | devinfo->irq_requested = true; |
| 823 | devinfo->irq_allocated = true; |
| 824 | return 0; |
| 825 | } |
| 826 | |
| 827 | |
| 828 | static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo) |
| 829 | { |
| 830 | struct pci_dev *pdev; |
| 831 | u32 status; |
| 832 | u32 count; |
| 833 | |
| 834 | if (!devinfo->irq_allocated) |
| 835 | return; |
| 836 | |
| 837 | pdev = devinfo->pdev; |
| 838 | |
| 839 | brcmf_pcie_intr_disable(devinfo); |
| 840 | if (!devinfo->irq_requested) |
| 841 | return; |
| 842 | devinfo->irq_requested = false; |
| 843 | free_irq(pdev->irq, devinfo); |
| 844 | pci_disable_msi(pdev); |
| 845 | |
| 846 | msleep(50); |
| 847 | count = 0; |
| 848 | while ((devinfo->in_irq) && (count < 20)) { |
| 849 | msleep(50); |
| 850 | count++; |
| 851 | } |
| 852 | if (devinfo->in_irq) |
| 853 | brcmf_err("Still in IRQ (processing) !!!\n"); |
| 854 | |
| 855 | if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) { |
| 856 | status = 0; |
| 857 | pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status); |
| 858 | pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status); |
| 859 | } else { |
| 860 | status = brcmf_pcie_read_reg32(devinfo, |
| 861 | BRCMF_PCIE_PCIE2REG_MAILBOXINT); |
| 862 | brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, |
| 863 | status); |
| 864 | } |
| 865 | devinfo->irq_allocated = false; |
| 866 | } |
| 867 | |
| 868 | |
| 869 | static int brcmf_pcie_ring_mb_write_rptr(void *ctx) |
| 870 | { |
| 871 | struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; |
| 872 | struct brcmf_pciedev_info *devinfo = ring->devinfo; |
| 873 | struct brcmf_commonring *commonring = &ring->commonring; |
| 874 | |
| 875 | if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) |
| 876 | return -EIO; |
| 877 | |
| 878 | brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr, |
| 879 | commonring->w_ptr, ring->id); |
| 880 | |
| 881 | brcmf_pcie_write_tcm16(devinfo, ring->r_idx_addr, commonring->r_ptr); |
| 882 | |
| 883 | return 0; |
| 884 | } |
| 885 | |
| 886 | |
| 887 | static int brcmf_pcie_ring_mb_write_wptr(void *ctx) |
| 888 | { |
| 889 | struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; |
| 890 | struct brcmf_pciedev_info *devinfo = ring->devinfo; |
| 891 | struct brcmf_commonring *commonring = &ring->commonring; |
| 892 | |
| 893 | if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) |
| 894 | return -EIO; |
| 895 | |
| 896 | brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr, |
| 897 | commonring->r_ptr, ring->id); |
| 898 | |
| 899 | brcmf_pcie_write_tcm16(devinfo, ring->w_idx_addr, commonring->w_ptr); |
| 900 | |
| 901 | return 0; |
| 902 | } |
| 903 | |
| 904 | |
| 905 | static int brcmf_pcie_ring_mb_ring_bell(void *ctx) |
| 906 | { |
| 907 | struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; |
| 908 | struct brcmf_pciedev_info *devinfo = ring->devinfo; |
| 909 | |
| 910 | if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) |
| 911 | return -EIO; |
| 912 | |
| 913 | devinfo->ringbell(devinfo); |
| 914 | |
| 915 | return 0; |
| 916 | } |
| 917 | |
| 918 | |
| 919 | static int brcmf_pcie_ring_mb_update_rptr(void *ctx) |
| 920 | { |
| 921 | struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; |
| 922 | struct brcmf_pciedev_info *devinfo = ring->devinfo; |
| 923 | struct brcmf_commonring *commonring = &ring->commonring; |
| 924 | |
| 925 | if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) |
| 926 | return -EIO; |
| 927 | |
| 928 | commonring->r_ptr = brcmf_pcie_read_tcm16(devinfo, ring->r_idx_addr); |
| 929 | |
| 930 | brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr, |
| 931 | commonring->w_ptr, ring->id); |
| 932 | |
| 933 | return 0; |
| 934 | } |
| 935 | |
| 936 | |
| 937 | static int brcmf_pcie_ring_mb_update_wptr(void *ctx) |
| 938 | { |
| 939 | struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; |
| 940 | struct brcmf_pciedev_info *devinfo = ring->devinfo; |
| 941 | struct brcmf_commonring *commonring = &ring->commonring; |
| 942 | |
| 943 | if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) |
| 944 | return -EIO; |
| 945 | |
| 946 | commonring->w_ptr = brcmf_pcie_read_tcm16(devinfo, ring->w_idx_addr); |
| 947 | |
| 948 | brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr, |
| 949 | commonring->r_ptr, ring->id); |
| 950 | |
| 951 | return 0; |
| 952 | } |
| 953 | |
| 954 | |
| 955 | static void * |
| 956 | brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo, |
| 957 | u32 size, u32 tcm_dma_phys_addr, |
| 958 | dma_addr_t *dma_handle) |
| 959 | { |
| 960 | void *ring; |
| 961 | u64 address; |
| 962 | |
| 963 | ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle, |
| 964 | GFP_KERNEL); |
| 965 | if (!ring) |
| 966 | return NULL; |
| 967 | |
| 968 | address = (u64)*dma_handle; |
| 969 | brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr, |
| 970 | address & 0xffffffff); |
| 971 | brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32); |
| 972 | |
| 973 | memset(ring, 0, size); |
| 974 | |
| 975 | return (ring); |
| 976 | } |
| 977 | |
| 978 | |
| 979 | static struct brcmf_pcie_ringbuf * |
| 980 | brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id, |
| 981 | u32 tcm_ring_phys_addr) |
| 982 | { |
| 983 | void *dma_buf; |
| 984 | dma_addr_t dma_handle; |
| 985 | struct brcmf_pcie_ringbuf *ring; |
| 986 | u32 size; |
| 987 | u32 addr; |
| 988 | |
| 989 | size = brcmf_ring_max_item[ring_id] * brcmf_ring_itemsize[ring_id]; |
| 990 | dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size, |
| 991 | tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET, |
| 992 | &dma_handle); |
| 993 | if (!dma_buf) |
| 994 | return NULL; |
| 995 | |
| 996 | addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET; |
| 997 | brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]); |
| 998 | addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET; |
| 999 | brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_itemsize[ring_id]); |
| 1000 | |
| 1001 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
| 1002 | if (!ring) { |
| 1003 | dma_free_coherent(&devinfo->pdev->dev, size, dma_buf, |
| 1004 | dma_handle); |
| 1005 | return NULL; |
| 1006 | } |
| 1007 | brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id], |
| 1008 | brcmf_ring_itemsize[ring_id], dma_buf); |
| 1009 | ring->dma_handle = dma_handle; |
| 1010 | ring->devinfo = devinfo; |
| 1011 | brcmf_commonring_register_cb(&ring->commonring, |
| 1012 | brcmf_pcie_ring_mb_ring_bell, |
| 1013 | brcmf_pcie_ring_mb_update_rptr, |
| 1014 | brcmf_pcie_ring_mb_update_wptr, |
| 1015 | brcmf_pcie_ring_mb_write_rptr, |
| 1016 | brcmf_pcie_ring_mb_write_wptr, ring); |
| 1017 | |
| 1018 | return (ring); |
| 1019 | } |
| 1020 | |
| 1021 | |
| 1022 | static void brcmf_pcie_release_ringbuffer(struct device *dev, |
| 1023 | struct brcmf_pcie_ringbuf *ring) |
| 1024 | { |
| 1025 | void *dma_buf; |
| 1026 | u32 size; |
| 1027 | |
| 1028 | if (!ring) |
| 1029 | return; |
| 1030 | |
| 1031 | dma_buf = ring->commonring.buf_addr; |
| 1032 | if (dma_buf) { |
| 1033 | size = ring->commonring.depth * ring->commonring.item_len; |
| 1034 | dma_free_coherent(dev, size, dma_buf, ring->dma_handle); |
| 1035 | } |
| 1036 | kfree(ring); |
| 1037 | } |
| 1038 | |
| 1039 | |
| 1040 | static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo) |
| 1041 | { |
| 1042 | u32 i; |
| 1043 | |
| 1044 | for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) { |
| 1045 | brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev, |
| 1046 | devinfo->shared.commonrings[i]); |
| 1047 | devinfo->shared.commonrings[i] = NULL; |
| 1048 | } |
| 1049 | kfree(devinfo->shared.flowrings); |
| 1050 | devinfo->shared.flowrings = NULL; |
| 1051 | } |
| 1052 | |
| 1053 | |
| 1054 | static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo) |
| 1055 | { |
| 1056 | struct brcmf_pcie_ringbuf *ring; |
| 1057 | struct brcmf_pcie_ringbuf *rings; |
| 1058 | u32 ring_addr; |
| 1059 | u32 d2h_w_idx_ptr; |
| 1060 | u32 d2h_r_idx_ptr; |
| 1061 | u32 h2d_w_idx_ptr; |
| 1062 | u32 h2d_r_idx_ptr; |
| 1063 | u32 addr; |
| 1064 | u32 ring_mem_ptr; |
| 1065 | u32 i; |
| 1066 | u16 max_sub_queues; |
| 1067 | |
| 1068 | ring_addr = devinfo->shared.ring_info_addr; |
| 1069 | brcmf_dbg(PCIE, "Base ring addr = 0x%08x\n", ring_addr); |
| 1070 | |
| 1071 | addr = ring_addr + BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET; |
| 1072 | d2h_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr); |
| 1073 | addr = ring_addr + BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET; |
| 1074 | d2h_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr); |
| 1075 | addr = ring_addr + BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET; |
| 1076 | h2d_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr); |
| 1077 | addr = ring_addr + BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET; |
| 1078 | h2d_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr); |
| 1079 | |
| 1080 | addr = ring_addr + BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET; |
| 1081 | ring_mem_ptr = brcmf_pcie_read_tcm32(devinfo, addr); |
| 1082 | |
| 1083 | for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) { |
| 1084 | ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr); |
| 1085 | if (!ring) |
| 1086 | goto fail; |
| 1087 | ring->w_idx_addr = h2d_w_idx_ptr; |
| 1088 | ring->r_idx_addr = h2d_r_idx_ptr; |
| 1089 | ring->id = i; |
| 1090 | devinfo->shared.commonrings[i] = ring; |
| 1091 | |
| 1092 | h2d_w_idx_ptr += sizeof(u32); |
| 1093 | h2d_r_idx_ptr += sizeof(u32); |
| 1094 | ring_mem_ptr += BRCMF_RING_MEM_SZ; |
| 1095 | } |
| 1096 | |
| 1097 | for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS; |
| 1098 | i < BRCMF_NROF_COMMON_MSGRINGS; i++) { |
| 1099 | ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr); |
| 1100 | if (!ring) |
| 1101 | goto fail; |
| 1102 | ring->w_idx_addr = d2h_w_idx_ptr; |
| 1103 | ring->r_idx_addr = d2h_r_idx_ptr; |
| 1104 | ring->id = i; |
| 1105 | devinfo->shared.commonrings[i] = ring; |
| 1106 | |
| 1107 | d2h_w_idx_ptr += sizeof(u32); |
| 1108 | d2h_r_idx_ptr += sizeof(u32); |
| 1109 | ring_mem_ptr += BRCMF_RING_MEM_SZ; |
| 1110 | } |
| 1111 | |
| 1112 | addr = ring_addr + BRCMF_SHARED_RING_MAX_SUB_QUEUES; |
| 1113 | max_sub_queues = brcmf_pcie_read_tcm16(devinfo, addr); |
| 1114 | devinfo->shared.nrof_flowrings = |
| 1115 | max_sub_queues - BRCMF_NROF_H2D_COMMON_MSGRINGS; |
| 1116 | rings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*ring), |
| 1117 | GFP_KERNEL); |
| 1118 | if (!rings) |
| 1119 | goto fail; |
| 1120 | |
| 1121 | brcmf_dbg(PCIE, "Nr of flowrings is %d\n", |
| 1122 | devinfo->shared.nrof_flowrings); |
| 1123 | |
| 1124 | for (i = 0; i < devinfo->shared.nrof_flowrings; i++) { |
| 1125 | ring = &rings[i]; |
| 1126 | ring->devinfo = devinfo; |
| 1127 | ring->id = i + BRCMF_NROF_COMMON_MSGRINGS; |
| 1128 | brcmf_commonring_register_cb(&ring->commonring, |
| 1129 | brcmf_pcie_ring_mb_ring_bell, |
| 1130 | brcmf_pcie_ring_mb_update_rptr, |
| 1131 | brcmf_pcie_ring_mb_update_wptr, |
| 1132 | brcmf_pcie_ring_mb_write_rptr, |
| 1133 | brcmf_pcie_ring_mb_write_wptr, |
| 1134 | ring); |
| 1135 | ring->w_idx_addr = h2d_w_idx_ptr; |
| 1136 | ring->r_idx_addr = h2d_r_idx_ptr; |
| 1137 | h2d_w_idx_ptr += sizeof(u32); |
| 1138 | h2d_r_idx_ptr += sizeof(u32); |
| 1139 | } |
| 1140 | devinfo->shared.flowrings = rings; |
| 1141 | |
| 1142 | return 0; |
| 1143 | |
| 1144 | fail: |
| 1145 | brcmf_err("Allocating commonring buffers failed\n"); |
| 1146 | brcmf_pcie_release_ringbuffers(devinfo); |
| 1147 | return -ENOMEM; |
| 1148 | } |
| 1149 | |
| 1150 | |
| 1151 | static void |
| 1152 | brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo) |
| 1153 | { |
| 1154 | if (devinfo->shared.scratch) |
| 1155 | dma_free_coherent(&devinfo->pdev->dev, |
| 1156 | BRCMF_DMA_D2H_SCRATCH_BUF_LEN, |
| 1157 | devinfo->shared.scratch, |
| 1158 | devinfo->shared.scratch_dmahandle); |
| 1159 | if (devinfo->shared.ringupd) |
| 1160 | dma_free_coherent(&devinfo->pdev->dev, |
| 1161 | BRCMF_DMA_D2H_RINGUPD_BUF_LEN, |
| 1162 | devinfo->shared.ringupd, |
| 1163 | devinfo->shared.ringupd_dmahandle); |
| 1164 | } |
| 1165 | |
| 1166 | static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo) |
| 1167 | { |
| 1168 | u64 address; |
| 1169 | u32 addr; |
| 1170 | |
| 1171 | devinfo->shared.scratch = dma_alloc_coherent(&devinfo->pdev->dev, |
| 1172 | BRCMF_DMA_D2H_SCRATCH_BUF_LEN, |
| 1173 | &devinfo->shared.scratch_dmahandle, GFP_KERNEL); |
| 1174 | if (!devinfo->shared.scratch) |
| 1175 | goto fail; |
| 1176 | |
| 1177 | memset(devinfo->shared.scratch, 0, BRCMF_DMA_D2H_SCRATCH_BUF_LEN); |
| 1178 | brcmf_dma_flush(devinfo->shared.scratch, BRCMF_DMA_D2H_SCRATCH_BUF_LEN); |
| 1179 | |
| 1180 | addr = devinfo->shared.tcm_base_address + |
| 1181 | BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET; |
| 1182 | address = (u64)devinfo->shared.scratch_dmahandle; |
| 1183 | brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); |
| 1184 | brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); |
| 1185 | addr = devinfo->shared.tcm_base_address + |
| 1186 | BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET; |
| 1187 | brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN); |
| 1188 | |
| 1189 | devinfo->shared.ringupd = dma_alloc_coherent(&devinfo->pdev->dev, |
| 1190 | BRCMF_DMA_D2H_RINGUPD_BUF_LEN, |
| 1191 | &devinfo->shared.ringupd_dmahandle, GFP_KERNEL); |
| 1192 | if (!devinfo->shared.ringupd) |
| 1193 | goto fail; |
| 1194 | |
| 1195 | memset(devinfo->shared.ringupd, 0, BRCMF_DMA_D2H_RINGUPD_BUF_LEN); |
| 1196 | brcmf_dma_flush(devinfo->shared.ringupd, BRCMF_DMA_D2H_RINGUPD_BUF_LEN); |
| 1197 | |
| 1198 | addr = devinfo->shared.tcm_base_address + |
| 1199 | BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET; |
| 1200 | address = (u64)devinfo->shared.ringupd_dmahandle; |
| 1201 | brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); |
| 1202 | brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); |
| 1203 | addr = devinfo->shared.tcm_base_address + |
| 1204 | BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET; |
| 1205 | brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN); |
| 1206 | return 0; |
| 1207 | |
| 1208 | fail: |
| 1209 | brcmf_err("Allocating scratch buffers failed\n"); |
| 1210 | brcmf_pcie_release_scratchbuffers(devinfo); |
| 1211 | return -ENOMEM; |
| 1212 | } |
| 1213 | |
| 1214 | |
| 1215 | static void brcmf_pcie_down(struct device *dev) |
| 1216 | { |
| 1217 | } |
| 1218 | |
| 1219 | |
| 1220 | static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb) |
| 1221 | { |
| 1222 | return 0; |
| 1223 | } |
| 1224 | |
| 1225 | |
| 1226 | static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg, |
| 1227 | uint len) |
| 1228 | { |
| 1229 | return 0; |
| 1230 | } |
| 1231 | |
| 1232 | |
| 1233 | static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg, |
| 1234 | uint len) |
| 1235 | { |
| 1236 | return 0; |
| 1237 | } |
| 1238 | |
| 1239 | |
| 1240 | static void brcmf_pcie_wowl_config(struct device *dev, bool enabled) |
| 1241 | { |
| 1242 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
| 1243 | struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; |
| 1244 | struct brcmf_pciedev_info *devinfo = buspub->devinfo; |
| 1245 | |
| 1246 | brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled); |
| 1247 | devinfo->wowl_enabled = enabled; |
| 1248 | if (enabled) |
| 1249 | device_set_wakeup_enable(&devinfo->pdev->dev, true); |
| 1250 | else |
| 1251 | device_set_wakeup_enable(&devinfo->pdev->dev, false); |
| 1252 | } |
| 1253 | |
| 1254 | |
| 1255 | static struct brcmf_bus_ops brcmf_pcie_bus_ops = { |
| 1256 | .txdata = brcmf_pcie_tx, |
| 1257 | .stop = brcmf_pcie_down, |
| 1258 | .txctl = brcmf_pcie_tx_ctlpkt, |
| 1259 | .rxctl = brcmf_pcie_rx_ctlpkt, |
| 1260 | .wowl_config = brcmf_pcie_wowl_config, |
| 1261 | }; |
| 1262 | |
| 1263 | |
| 1264 | static int |
| 1265 | brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo, |
| 1266 | u32 sharedram_addr) |
| 1267 | { |
| 1268 | struct brcmf_pcie_shared_info *shared; |
| 1269 | u32 addr; |
| 1270 | u32 version; |
| 1271 | |
| 1272 | shared = &devinfo->shared; |
| 1273 | shared->tcm_base_address = sharedram_addr; |
| 1274 | |
| 1275 | shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr); |
| 1276 | version = shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK; |
| 1277 | brcmf_dbg(PCIE, "PCIe protocol version %d\n", version); |
| 1278 | if ((version > BRCMF_PCIE_MAX_SHARED_VERSION) || |
| 1279 | (version < BRCMF_PCIE_MIN_SHARED_VERSION)) { |
| 1280 | brcmf_err("Unsupported PCIE version %d\n", version); |
| 1281 | return -EINVAL; |
| 1282 | } |
| 1283 | if (shared->flags & BRCMF_PCIE_SHARED_TXPUSH_SUPPORT) { |
| 1284 | brcmf_err("Unsupported legacy TX mode 0x%x\n", |
| 1285 | shared->flags & BRCMF_PCIE_SHARED_TXPUSH_SUPPORT); |
| 1286 | return -EINVAL; |
| 1287 | } |
| 1288 | |
| 1289 | addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET; |
| 1290 | shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr); |
| 1291 | if (shared->max_rxbufpost == 0) |
| 1292 | shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST; |
| 1293 | |
| 1294 | addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET; |
| 1295 | shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr); |
| 1296 | |
| 1297 | addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET; |
| 1298 | shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr); |
| 1299 | |
| 1300 | addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET; |
| 1301 | shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr); |
| 1302 | |
| 1303 | addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET; |
| 1304 | shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr); |
| 1305 | |
| 1306 | brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n", |
| 1307 | shared->max_rxbufpost, shared->rx_dataoffset); |
| 1308 | |
| 1309 | brcmf_pcie_bus_console_init(devinfo); |
| 1310 | |
| 1311 | return 0; |
| 1312 | } |
| 1313 | |
| 1314 | |
| 1315 | static int brcmf_pcie_get_fwnames(struct brcmf_pciedev_info *devinfo) |
| 1316 | { |
| 1317 | char *fw_name; |
| 1318 | char *nvram_name; |
| 1319 | uint fw_len, nv_len; |
| 1320 | char end; |
| 1321 | |
| 1322 | brcmf_dbg(PCIE, "Enter, chip 0x%04x chiprev %d\n", devinfo->ci->chip, |
| 1323 | devinfo->ci->chiprev); |
| 1324 | |
| 1325 | switch (devinfo->ci->chip) { |
| 1326 | case BRCM_CC_43602_CHIP_ID: |
| 1327 | fw_name = BRCMF_PCIE_43602_FW_NAME; |
| 1328 | nvram_name = BRCMF_PCIE_43602_NVRAM_NAME; |
| 1329 | break; |
| 1330 | case BRCM_CC_4356_CHIP_ID: |
| 1331 | fw_name = BRCMF_PCIE_4356_FW_NAME; |
| 1332 | nvram_name = BRCMF_PCIE_4356_NVRAM_NAME; |
| 1333 | break; |
| 1334 | case BRCM_CC_43567_CHIP_ID: |
| 1335 | case BRCM_CC_43569_CHIP_ID: |
| 1336 | case BRCM_CC_43570_CHIP_ID: |
| 1337 | fw_name = BRCMF_PCIE_43570_FW_NAME; |
| 1338 | nvram_name = BRCMF_PCIE_43570_NVRAM_NAME; |
| 1339 | break; |
| 1340 | case BRCM_CC_4358_CHIP_ID: |
| 1341 | fw_name = BRCMF_PCIE_4358_FW_NAME; |
| 1342 | nvram_name = BRCMF_PCIE_4358_NVRAM_NAME; |
| 1343 | break; |
| 1344 | default: |
| 1345 | brcmf_err("Unsupported chip 0x%04x\n", devinfo->ci->chip); |
| 1346 | return -ENODEV; |
| 1347 | } |
| 1348 | |
| 1349 | fw_len = sizeof(devinfo->fw_name) - 1; |
| 1350 | nv_len = sizeof(devinfo->nvram_name) - 1; |
| 1351 | /* check if firmware path is provided by module parameter */ |
| 1352 | if (brcmf_firmware_path[0] != '\0') { |
| 1353 | strncpy(devinfo->fw_name, brcmf_firmware_path, fw_len); |
| 1354 | strncpy(devinfo->nvram_name, brcmf_firmware_path, nv_len); |
| 1355 | fw_len -= strlen(devinfo->fw_name); |
| 1356 | nv_len -= strlen(devinfo->nvram_name); |
| 1357 | |
| 1358 | end = brcmf_firmware_path[strlen(brcmf_firmware_path) - 1]; |
| 1359 | if (end != '/') { |
| 1360 | strncat(devinfo->fw_name, "/", fw_len); |
| 1361 | strncat(devinfo->nvram_name, "/", nv_len); |
| 1362 | fw_len--; |
| 1363 | nv_len--; |
| 1364 | } |
| 1365 | } |
| 1366 | strncat(devinfo->fw_name, fw_name, fw_len); |
| 1367 | strncat(devinfo->nvram_name, nvram_name, nv_len); |
| 1368 | |
| 1369 | return 0; |
| 1370 | } |
| 1371 | |
| 1372 | |
| 1373 | static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo, |
| 1374 | const struct firmware *fw, void *nvram, |
| 1375 | u32 nvram_len) |
| 1376 | { |
| 1377 | u32 sharedram_addr; |
| 1378 | u32 sharedram_addr_written; |
| 1379 | u32 loop_counter; |
| 1380 | int err; |
| 1381 | u32 address; |
| 1382 | u32 resetintr; |
| 1383 | |
| 1384 | devinfo->ringbell = brcmf_pcie_ringbell_v2; |
| 1385 | devinfo->generic_corerev = BRCMF_PCIE_GENREV2; |
| 1386 | |
| 1387 | brcmf_dbg(PCIE, "Halt ARM.\n"); |
| 1388 | err = brcmf_pcie_enter_download_state(devinfo); |
| 1389 | if (err) |
| 1390 | return err; |
| 1391 | |
| 1392 | brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name); |
| 1393 | brcmf_pcie_copy_mem_todev(devinfo, devinfo->ci->rambase, |
| 1394 | (void *)fw->data, fw->size); |
| 1395 | |
| 1396 | resetintr = get_unaligned_le32(fw->data); |
| 1397 | release_firmware(fw); |
| 1398 | |
| 1399 | /* reset last 4 bytes of RAM address. to be used for shared |
| 1400 | * area. This identifies when FW is running |
| 1401 | */ |
| 1402 | brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0); |
| 1403 | |
| 1404 | if (nvram) { |
| 1405 | brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name); |
| 1406 | address = devinfo->ci->rambase + devinfo->ci->ramsize - |
| 1407 | nvram_len; |
| 1408 | brcmf_pcie_copy_mem_todev(devinfo, address, nvram, nvram_len); |
| 1409 | brcmf_fw_nvram_free(nvram); |
| 1410 | } else { |
| 1411 | brcmf_dbg(PCIE, "No matching NVRAM file found %s\n", |
| 1412 | devinfo->nvram_name); |
| 1413 | } |
| 1414 | |
| 1415 | sharedram_addr_written = brcmf_pcie_read_ram32(devinfo, |
| 1416 | devinfo->ci->ramsize - |
| 1417 | 4); |
| 1418 | brcmf_dbg(PCIE, "Bring ARM in running state\n"); |
| 1419 | err = brcmf_pcie_exit_download_state(devinfo, resetintr); |
| 1420 | if (err) |
| 1421 | return err; |
| 1422 | |
| 1423 | brcmf_dbg(PCIE, "Wait for FW init\n"); |
| 1424 | sharedram_addr = sharedram_addr_written; |
| 1425 | loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50; |
| 1426 | while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) { |
| 1427 | msleep(50); |
| 1428 | sharedram_addr = brcmf_pcie_read_ram32(devinfo, |
| 1429 | devinfo->ci->ramsize - |
| 1430 | 4); |
| 1431 | loop_counter--; |
| 1432 | } |
| 1433 | if (sharedram_addr == sharedram_addr_written) { |
| 1434 | brcmf_err("FW failed to initialize\n"); |
| 1435 | return -ENODEV; |
| 1436 | } |
| 1437 | brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr); |
| 1438 | |
| 1439 | return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr)); |
| 1440 | } |
| 1441 | |
| 1442 | |
| 1443 | static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo) |
| 1444 | { |
| 1445 | struct pci_dev *pdev; |
| 1446 | int err; |
| 1447 | phys_addr_t bar0_addr, bar1_addr; |
| 1448 | ulong bar1_size; |
| 1449 | |
| 1450 | pdev = devinfo->pdev; |
| 1451 | |
| 1452 | err = pci_enable_device(pdev); |
| 1453 | if (err) { |
| 1454 | brcmf_err("pci_enable_device failed err=%d\n", err); |
| 1455 | return err; |
| 1456 | } |
| 1457 | |
| 1458 | pci_set_master(pdev); |
| 1459 | |
| 1460 | /* Bar-0 mapped address */ |
| 1461 | bar0_addr = pci_resource_start(pdev, 0); |
| 1462 | /* Bar-1 mapped address */ |
| 1463 | bar1_addr = pci_resource_start(pdev, 2); |
| 1464 | /* read Bar-1 mapped memory range */ |
| 1465 | bar1_size = pci_resource_len(pdev, 2); |
| 1466 | if ((bar1_size == 0) || (bar1_addr == 0)) { |
| 1467 | brcmf_err("BAR1 Not enabled, device size=%ld, addr=%#016llx\n", |
| 1468 | bar1_size, (unsigned long long)bar1_addr); |
| 1469 | return -EINVAL; |
| 1470 | } |
| 1471 | |
| 1472 | devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE); |
| 1473 | devinfo->tcm = ioremap_nocache(bar1_addr, BRCMF_PCIE_TCM_MAP_SIZE); |
| 1474 | devinfo->tcm_size = BRCMF_PCIE_TCM_MAP_SIZE; |
| 1475 | |
| 1476 | if (!devinfo->regs || !devinfo->tcm) { |
| 1477 | brcmf_err("ioremap() failed (%p,%p)\n", devinfo->regs, |
| 1478 | devinfo->tcm); |
| 1479 | return -EINVAL; |
| 1480 | } |
| 1481 | brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n", |
| 1482 | devinfo->regs, (unsigned long long)bar0_addr); |
| 1483 | brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx\n", |
| 1484 | devinfo->tcm, (unsigned long long)bar1_addr); |
| 1485 | |
| 1486 | return 0; |
| 1487 | } |
| 1488 | |
| 1489 | |
| 1490 | static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo) |
| 1491 | { |
| 1492 | if (devinfo->tcm) |
| 1493 | iounmap(devinfo->tcm); |
| 1494 | if (devinfo->regs) |
| 1495 | iounmap(devinfo->regs); |
| 1496 | |
| 1497 | pci_disable_device(devinfo->pdev); |
| 1498 | } |
| 1499 | |
| 1500 | |
| 1501 | static int brcmf_pcie_attach_bus(struct device *dev) |
| 1502 | { |
| 1503 | int ret; |
| 1504 | |
| 1505 | /* Attach to the common driver interface */ |
| 1506 | ret = brcmf_attach(dev); |
| 1507 | if (ret) { |
| 1508 | brcmf_err("brcmf_attach failed\n"); |
| 1509 | } else { |
| 1510 | ret = brcmf_bus_start(dev); |
| 1511 | if (ret) |
| 1512 | brcmf_err("dongle is not responding\n"); |
| 1513 | } |
| 1514 | |
| 1515 | return ret; |
| 1516 | } |
| 1517 | |
| 1518 | |
| 1519 | static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr) |
| 1520 | { |
| 1521 | u32 ret_addr; |
| 1522 | |
| 1523 | ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1); |
| 1524 | addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1); |
| 1525 | pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr); |
| 1526 | |
| 1527 | return ret_addr; |
| 1528 | } |
| 1529 | |
| 1530 | |
| 1531 | static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr) |
| 1532 | { |
| 1533 | struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; |
| 1534 | |
| 1535 | addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr); |
| 1536 | return brcmf_pcie_read_reg32(devinfo, addr); |
| 1537 | } |
| 1538 | |
| 1539 | |
| 1540 | static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value) |
| 1541 | { |
| 1542 | struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; |
| 1543 | |
| 1544 | addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr); |
| 1545 | brcmf_pcie_write_reg32(devinfo, addr, value); |
| 1546 | } |
| 1547 | |
| 1548 | |
| 1549 | static int brcmf_pcie_buscoreprep(void *ctx) |
| 1550 | { |
| 1551 | struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; |
| 1552 | int err; |
| 1553 | |
| 1554 | err = brcmf_pcie_get_resource(devinfo); |
| 1555 | if (err == 0) { |
| 1556 | /* Set CC watchdog to reset all the cores on the chip to bring |
| 1557 | * back dongle to a sane state. |
| 1558 | */ |
| 1559 | brcmf_pcie_buscore_write32(ctx, CORE_CC_REG(SI_ENUM_BASE, |
| 1560 | watchdog), 4); |
| 1561 | msleep(100); |
| 1562 | } |
| 1563 | |
| 1564 | return err; |
| 1565 | } |
| 1566 | |
| 1567 | |
| 1568 | static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip, |
| 1569 | u32 rstvec) |
| 1570 | { |
| 1571 | struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; |
| 1572 | |
| 1573 | brcmf_pcie_write_tcm32(devinfo, 0, rstvec); |
| 1574 | } |
| 1575 | |
| 1576 | |
| 1577 | static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = { |
| 1578 | .prepare = brcmf_pcie_buscoreprep, |
| 1579 | .activate = brcmf_pcie_buscore_activate, |
| 1580 | .read32 = brcmf_pcie_buscore_read32, |
| 1581 | .write32 = brcmf_pcie_buscore_write32, |
| 1582 | }; |
| 1583 | |
| 1584 | static void brcmf_pcie_setup(struct device *dev, const struct firmware *fw, |
| 1585 | void *nvram, u32 nvram_len) |
| 1586 | { |
| 1587 | struct brcmf_bus *bus = dev_get_drvdata(dev); |
| 1588 | struct brcmf_pciedev *pcie_bus_dev = bus->bus_priv.pcie; |
| 1589 | struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo; |
| 1590 | struct brcmf_commonring **flowrings; |
| 1591 | int ret; |
| 1592 | u32 i; |
| 1593 | |
| 1594 | brcmf_pcie_attach(devinfo); |
| 1595 | |
| 1596 | ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len); |
| 1597 | if (ret) |
| 1598 | goto fail; |
| 1599 | |
| 1600 | devinfo->state = BRCMFMAC_PCIE_STATE_UP; |
| 1601 | |
| 1602 | ret = brcmf_pcie_init_ringbuffers(devinfo); |
| 1603 | if (ret) |
| 1604 | goto fail; |
| 1605 | |
| 1606 | ret = brcmf_pcie_init_scratchbuffers(devinfo); |
| 1607 | if (ret) |
| 1608 | goto fail; |
| 1609 | |
| 1610 | brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); |
| 1611 | ret = brcmf_pcie_request_irq(devinfo); |
| 1612 | if (ret) |
| 1613 | goto fail; |
| 1614 | |
| 1615 | /* hook the commonrings in the bus structure. */ |
| 1616 | for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) |
| 1617 | bus->msgbuf->commonrings[i] = |
| 1618 | &devinfo->shared.commonrings[i]->commonring; |
| 1619 | |
| 1620 | flowrings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*flowrings), |
| 1621 | GFP_KERNEL); |
| 1622 | if (!flowrings) |
| 1623 | goto fail; |
| 1624 | |
| 1625 | for (i = 0; i < devinfo->shared.nrof_flowrings; i++) |
| 1626 | flowrings[i] = &devinfo->shared.flowrings[i].commonring; |
| 1627 | bus->msgbuf->flowrings = flowrings; |
| 1628 | |
| 1629 | bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset; |
| 1630 | bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost; |
| 1631 | bus->msgbuf->nrof_flowrings = devinfo->shared.nrof_flowrings; |
| 1632 | |
| 1633 | init_waitqueue_head(&devinfo->mbdata_resp_wait); |
| 1634 | |
| 1635 | brcmf_pcie_intr_enable(devinfo); |
| 1636 | if (brcmf_pcie_attach_bus(bus->dev) == 0) |
| 1637 | return; |
| 1638 | |
| 1639 | brcmf_pcie_bus_console_read(devinfo); |
| 1640 | |
| 1641 | fail: |
| 1642 | device_release_driver(dev); |
| 1643 | } |
| 1644 | |
| 1645 | static int |
| 1646 | brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
| 1647 | { |
| 1648 | int ret; |
| 1649 | struct brcmf_pciedev_info *devinfo; |
| 1650 | struct brcmf_pciedev *pcie_bus_dev; |
| 1651 | struct brcmf_bus *bus; |
| 1652 | u16 domain_nr; |
| 1653 | u16 bus_nr; |
| 1654 | |
| 1655 | domain_nr = pci_domain_nr(pdev->bus) + 1; |
| 1656 | bus_nr = pdev->bus->number; |
| 1657 | brcmf_dbg(PCIE, "Enter %x:%x (%d/%d)\n", pdev->vendor, pdev->device, |
| 1658 | domain_nr, bus_nr); |
| 1659 | |
| 1660 | ret = -ENOMEM; |
| 1661 | devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL); |
| 1662 | if (devinfo == NULL) |
| 1663 | return ret; |
| 1664 | |
| 1665 | devinfo->pdev = pdev; |
| 1666 | pcie_bus_dev = NULL; |
| 1667 | devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops); |
| 1668 | if (IS_ERR(devinfo->ci)) { |
| 1669 | ret = PTR_ERR(devinfo->ci); |
| 1670 | devinfo->ci = NULL; |
| 1671 | goto fail; |
| 1672 | } |
| 1673 | |
| 1674 | pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL); |
| 1675 | if (pcie_bus_dev == NULL) { |
| 1676 | ret = -ENOMEM; |
| 1677 | goto fail; |
| 1678 | } |
| 1679 | |
| 1680 | bus = kzalloc(sizeof(*bus), GFP_KERNEL); |
| 1681 | if (!bus) { |
| 1682 | ret = -ENOMEM; |
| 1683 | goto fail; |
| 1684 | } |
| 1685 | bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL); |
| 1686 | if (!bus->msgbuf) { |
| 1687 | ret = -ENOMEM; |
| 1688 | kfree(bus); |
| 1689 | goto fail; |
| 1690 | } |
| 1691 | |
| 1692 | /* hook it all together. */ |
| 1693 | pcie_bus_dev->devinfo = devinfo; |
| 1694 | pcie_bus_dev->bus = bus; |
| 1695 | bus->dev = &pdev->dev; |
| 1696 | bus->bus_priv.pcie = pcie_bus_dev; |
| 1697 | bus->ops = &brcmf_pcie_bus_ops; |
| 1698 | bus->proto_type = BRCMF_PROTO_MSGBUF; |
| 1699 | bus->chip = devinfo->coreid; |
| 1700 | bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot); |
| 1701 | dev_set_drvdata(&pdev->dev, bus); |
| 1702 | |
| 1703 | ret = brcmf_pcie_get_fwnames(devinfo); |
| 1704 | if (ret) |
| 1705 | goto fail_bus; |
| 1706 | |
| 1707 | ret = brcmf_fw_get_firmwares_pcie(bus->dev, BRCMF_FW_REQUEST_NVRAM | |
| 1708 | BRCMF_FW_REQ_NV_OPTIONAL, |
| 1709 | devinfo->fw_name, devinfo->nvram_name, |
| 1710 | brcmf_pcie_setup, domain_nr, bus_nr); |
| 1711 | if (ret == 0) |
| 1712 | return 0; |
| 1713 | fail_bus: |
| 1714 | kfree(bus->msgbuf); |
| 1715 | kfree(bus); |
| 1716 | fail: |
| 1717 | brcmf_err("failed %x:%x\n", pdev->vendor, pdev->device); |
| 1718 | brcmf_pcie_release_resource(devinfo); |
| 1719 | if (devinfo->ci) |
| 1720 | brcmf_chip_detach(devinfo->ci); |
| 1721 | kfree(pcie_bus_dev); |
| 1722 | kfree(devinfo); |
| 1723 | return ret; |
| 1724 | } |
| 1725 | |
| 1726 | |
| 1727 | static void |
| 1728 | brcmf_pcie_remove(struct pci_dev *pdev) |
| 1729 | { |
| 1730 | struct brcmf_pciedev_info *devinfo; |
| 1731 | struct brcmf_bus *bus; |
| 1732 | |
| 1733 | brcmf_dbg(PCIE, "Enter\n"); |
| 1734 | |
| 1735 | bus = dev_get_drvdata(&pdev->dev); |
| 1736 | if (bus == NULL) |
| 1737 | return; |
| 1738 | |
| 1739 | devinfo = bus->bus_priv.pcie->devinfo; |
| 1740 | |
| 1741 | devinfo->state = BRCMFMAC_PCIE_STATE_DOWN; |
| 1742 | if (devinfo->ci) |
| 1743 | brcmf_pcie_intr_disable(devinfo); |
| 1744 | |
| 1745 | brcmf_detach(&pdev->dev); |
| 1746 | |
| 1747 | kfree(bus->bus_priv.pcie); |
| 1748 | kfree(bus->msgbuf->flowrings); |
| 1749 | kfree(bus->msgbuf); |
| 1750 | kfree(bus); |
| 1751 | |
| 1752 | brcmf_pcie_release_irq(devinfo); |
| 1753 | brcmf_pcie_release_scratchbuffers(devinfo); |
| 1754 | brcmf_pcie_release_ringbuffers(devinfo); |
| 1755 | brcmf_pcie_reset_device(devinfo); |
| 1756 | brcmf_pcie_release_resource(devinfo); |
| 1757 | |
| 1758 | if (devinfo->ci) |
| 1759 | brcmf_chip_detach(devinfo->ci); |
| 1760 | |
| 1761 | kfree(devinfo); |
| 1762 | dev_set_drvdata(&pdev->dev, NULL); |
| 1763 | } |
| 1764 | |
| 1765 | |
| 1766 | #ifdef CONFIG_PM |
| 1767 | |
| 1768 | |
| 1769 | static int brcmf_pcie_suspend(struct pci_dev *pdev, pm_message_t state) |
| 1770 | { |
| 1771 | struct brcmf_pciedev_info *devinfo; |
| 1772 | struct brcmf_bus *bus; |
| 1773 | int err; |
| 1774 | |
| 1775 | brcmf_dbg(PCIE, "Enter, state=%d, pdev=%p\n", state.event, pdev); |
| 1776 | |
| 1777 | bus = dev_get_drvdata(&pdev->dev); |
| 1778 | devinfo = bus->bus_priv.pcie->devinfo; |
| 1779 | |
| 1780 | brcmf_bus_change_state(bus, BRCMF_BUS_DOWN); |
| 1781 | |
| 1782 | devinfo->mbdata_completed = false; |
| 1783 | brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM); |
| 1784 | |
| 1785 | wait_event_timeout(devinfo->mbdata_resp_wait, |
| 1786 | devinfo->mbdata_completed, |
| 1787 | msecs_to_jiffies(BRCMF_PCIE_MBDATA_TIMEOUT)); |
| 1788 | if (!devinfo->mbdata_completed) { |
| 1789 | brcmf_err("Timeout on response for entering D3 substate\n"); |
| 1790 | return -EIO; |
| 1791 | } |
| 1792 | brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM_IN_USE); |
| 1793 | |
| 1794 | err = pci_save_state(pdev); |
| 1795 | if (err) |
| 1796 | brcmf_err("pci_save_state failed, err=%d\n", err); |
| 1797 | if ((err) || (!devinfo->wowl_enabled)) { |
| 1798 | brcmf_chip_detach(devinfo->ci); |
| 1799 | devinfo->ci = NULL; |
| 1800 | brcmf_pcie_remove(pdev); |
| 1801 | return 0; |
| 1802 | } |
| 1803 | |
| 1804 | return pci_prepare_to_sleep(pdev); |
| 1805 | } |
| 1806 | |
| 1807 | static int brcmf_pcie_resume(struct pci_dev *pdev) |
| 1808 | { |
| 1809 | struct brcmf_pciedev_info *devinfo; |
| 1810 | struct brcmf_bus *bus; |
| 1811 | int err; |
| 1812 | |
| 1813 | bus = dev_get_drvdata(&pdev->dev); |
| 1814 | brcmf_dbg(PCIE, "Enter, pdev=%p, bus=%p\n", pdev, bus); |
| 1815 | |
| 1816 | err = pci_set_power_state(pdev, PCI_D0); |
| 1817 | if (err) { |
| 1818 | brcmf_err("pci_set_power_state failed, err=%d\n", err); |
| 1819 | goto cleanup; |
| 1820 | } |
| 1821 | pci_restore_state(pdev); |
| 1822 | pci_enable_wake(pdev, PCI_D3hot, false); |
| 1823 | pci_enable_wake(pdev, PCI_D3cold, false); |
| 1824 | |
| 1825 | /* Check if device is still up and running, if so we are ready */ |
| 1826 | if (bus) { |
| 1827 | devinfo = bus->bus_priv.pcie->devinfo; |
| 1828 | if (brcmf_pcie_read_reg32(devinfo, |
| 1829 | BRCMF_PCIE_PCIE2REG_INTMASK) != 0) { |
| 1830 | if (brcmf_pcie_send_mb_data(devinfo, |
| 1831 | BRCMF_H2D_HOST_D0_INFORM)) |
| 1832 | goto cleanup; |
| 1833 | brcmf_dbg(PCIE, "Hot resume, continue....\n"); |
| 1834 | brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); |
| 1835 | brcmf_bus_change_state(bus, BRCMF_BUS_UP); |
| 1836 | brcmf_pcie_intr_enable(devinfo); |
| 1837 | return 0; |
| 1838 | } |
| 1839 | } |
| 1840 | |
| 1841 | cleanup: |
| 1842 | if (bus) { |
| 1843 | devinfo = bus->bus_priv.pcie->devinfo; |
| 1844 | brcmf_chip_detach(devinfo->ci); |
| 1845 | devinfo->ci = NULL; |
| 1846 | brcmf_pcie_remove(pdev); |
| 1847 | } |
| 1848 | err = brcmf_pcie_probe(pdev, NULL); |
| 1849 | if (err) |
| 1850 | brcmf_err("probe after resume failed, err=%d\n", err); |
| 1851 | |
| 1852 | return err; |
| 1853 | } |
| 1854 | |
| 1855 | |
| 1856 | #endif /* CONFIG_PM */ |
| 1857 | |
| 1858 | |
| 1859 | #define BRCMF_PCIE_DEVICE(dev_id) { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\ |
| 1860 | PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 } |
| 1861 | |
| 1862 | static struct pci_device_id brcmf_pcie_devid_table[] = { |
| 1863 | BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID), |
| 1864 | BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID), |
| 1865 | BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID), |
| 1866 | BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID), |
| 1867 | BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID), |
| 1868 | BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID), |
| 1869 | BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID), |
| 1870 | BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID), |
| 1871 | { /* end: all zeroes */ } |
| 1872 | }; |
| 1873 | |
| 1874 | |
| 1875 | MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table); |
| 1876 | |
| 1877 | |
| 1878 | static struct pci_driver brcmf_pciedrvr = { |
| 1879 | .node = {}, |
| 1880 | .name = KBUILD_MODNAME, |
| 1881 | .id_table = brcmf_pcie_devid_table, |
| 1882 | .probe = brcmf_pcie_probe, |
| 1883 | .remove = brcmf_pcie_remove, |
| 1884 | #ifdef CONFIG_PM |
| 1885 | .suspend = brcmf_pcie_suspend, |
| 1886 | .resume = brcmf_pcie_resume |
| 1887 | #endif /* CONFIG_PM */ |
| 1888 | }; |
| 1889 | |
| 1890 | |
| 1891 | void brcmf_pcie_register(void) |
| 1892 | { |
| 1893 | int err; |
| 1894 | |
| 1895 | brcmf_dbg(PCIE, "Enter\n"); |
| 1896 | err = pci_register_driver(&brcmf_pciedrvr); |
| 1897 | if (err) |
| 1898 | brcmf_err("PCIE driver registration failed, err=%d\n", err); |
| 1899 | } |
| 1900 | |
| 1901 | |
| 1902 | void brcmf_pcie_exit(void) |
| 1903 | { |
| 1904 | brcmf_dbg(PCIE, "Enter\n"); |
| 1905 | pci_unregister_driver(&brcmf_pciedrvr); |
| 1906 | } |