| 1 | /* |
| 2 | * Copyright (c) 2011 Broadcom Corporation |
| 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
| 11 | * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION |
| 13 | * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN |
| 14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ |
| 16 | |
| 17 | #ifndef _BRCMFMAC_SDIO_CHIP_H_ |
| 18 | #define _BRCMFMAC_SDIO_CHIP_H_ |
| 19 | |
| 20 | /* |
| 21 | * Core reg address translation. |
| 22 | * Both macro's returns a 32 bits byte address on the backplane bus. |
| 23 | */ |
| 24 | #define CORE_CC_REG(base, field) \ |
| 25 | (base + offsetof(struct chipcregs, field)) |
| 26 | #define CORE_BUS_REG(base, field) \ |
| 27 | (base + offsetof(struct sdpcmd_regs, field)) |
| 28 | #define CORE_SB(base, field) \ |
| 29 | (base + SBCONFIGOFF + offsetof(struct sbconfig, field)) |
| 30 | |
| 31 | /* SDIO function 1 register CHIPCLKCSR */ |
| 32 | /* Force ALP request to backplane */ |
| 33 | #define SBSDIO_FORCE_ALP 0x01 |
| 34 | /* Force HT request to backplane */ |
| 35 | #define SBSDIO_FORCE_HT 0x02 |
| 36 | /* Force ILP request to backplane */ |
| 37 | #define SBSDIO_FORCE_ILP 0x04 |
| 38 | /* Make ALP ready (power up xtal) */ |
| 39 | #define SBSDIO_ALP_AVAIL_REQ 0x08 |
| 40 | /* Make HT ready (power up PLL) */ |
| 41 | #define SBSDIO_HT_AVAIL_REQ 0x10 |
| 42 | /* Squelch clock requests from HW */ |
| 43 | #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 |
| 44 | /* Status: ALP is ready */ |
| 45 | #define SBSDIO_ALP_AVAIL 0x40 |
| 46 | /* Status: HT is ready */ |
| 47 | #define SBSDIO_HT_AVAIL 0x80 |
| 48 | #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL) |
| 49 | #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS) |
| 50 | #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS) |
| 51 | #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval)) |
| 52 | #define SBSDIO_CLKAV(regval, alponly) \ |
| 53 | (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval))) |
| 54 | |
| 55 | #define BRCMF_MAX_CORENUM 6 |
| 56 | |
| 57 | struct chip_core_info { |
| 58 | u16 id; |
| 59 | u16 rev; |
| 60 | u32 base; |
| 61 | u32 wrapbase; |
| 62 | u32 caps; |
| 63 | u32 cib; |
| 64 | }; |
| 65 | |
| 66 | struct chip_info { |
| 67 | u32 chip; |
| 68 | u32 chiprev; |
| 69 | u32 socitype; |
| 70 | /* core info */ |
| 71 | /* always put chipcommon core at 0, bus core at 1 */ |
| 72 | struct chip_core_info c_inf[BRCMF_MAX_CORENUM]; |
| 73 | u32 pmurev; |
| 74 | u32 pmucaps; |
| 75 | u32 ramsize; |
| 76 | |
| 77 | bool (*iscoreup)(struct brcmf_sdio_dev *sdiodev, struct chip_info *ci, |
| 78 | u16 coreid); |
| 79 | u32 (*corerev)(struct brcmf_sdio_dev *sdiodev, struct chip_info *ci, |
| 80 | u16 coreid); |
| 81 | void (*coredisable)(struct brcmf_sdio_dev *sdiodev, |
| 82 | struct chip_info *ci, u16 coreid); |
| 83 | void (*resetcore)(struct brcmf_sdio_dev *sdiodev, |
| 84 | struct chip_info *ci, u16 coreid); |
| 85 | }; |
| 86 | |
| 87 | struct sbconfig { |
| 88 | u32 PAD[2]; |
| 89 | u32 sbipsflag; /* initiator port ocp slave flag */ |
| 90 | u32 PAD[3]; |
| 91 | u32 sbtpsflag; /* target port ocp slave flag */ |
| 92 | u32 PAD[11]; |
| 93 | u32 sbtmerrloga; /* (sonics >= 2.3) */ |
| 94 | u32 PAD; |
| 95 | u32 sbtmerrlog; /* (sonics >= 2.3) */ |
| 96 | u32 PAD[3]; |
| 97 | u32 sbadmatch3; /* address match3 */ |
| 98 | u32 PAD; |
| 99 | u32 sbadmatch2; /* address match2 */ |
| 100 | u32 PAD; |
| 101 | u32 sbadmatch1; /* address match1 */ |
| 102 | u32 PAD[7]; |
| 103 | u32 sbimstate; /* initiator agent state */ |
| 104 | u32 sbintvec; /* interrupt mask */ |
| 105 | u32 sbtmstatelow; /* target state */ |
| 106 | u32 sbtmstatehigh; /* target state */ |
| 107 | u32 sbbwa0; /* bandwidth allocation table0 */ |
| 108 | u32 PAD; |
| 109 | u32 sbimconfiglow; /* initiator configuration */ |
| 110 | u32 sbimconfighigh; /* initiator configuration */ |
| 111 | u32 sbadmatch0; /* address match0 */ |
| 112 | u32 PAD; |
| 113 | u32 sbtmconfiglow; /* target configuration */ |
| 114 | u32 sbtmconfighigh; /* target configuration */ |
| 115 | u32 sbbconfig; /* broadcast configuration */ |
| 116 | u32 PAD; |
| 117 | u32 sbbstate; /* broadcast state */ |
| 118 | u32 PAD[3]; |
| 119 | u32 sbactcnfg; /* activate configuration */ |
| 120 | u32 PAD[3]; |
| 121 | u32 sbflagst; /* current sbflags */ |
| 122 | u32 PAD[3]; |
| 123 | u32 sbidlow; /* identification */ |
| 124 | u32 sbidhigh; /* identification */ |
| 125 | }; |
| 126 | |
| 127 | /* sdio core registers */ |
| 128 | struct sdpcmd_regs { |
| 129 | u32 corecontrol; /* 0x00, rev8 */ |
| 130 | u32 corestatus; /* rev8 */ |
| 131 | u32 PAD[1]; |
| 132 | u32 biststatus; /* rev8 */ |
| 133 | |
| 134 | /* PCMCIA access */ |
| 135 | u16 pcmciamesportaladdr; /* 0x010, rev8 */ |
| 136 | u16 PAD[1]; |
| 137 | u16 pcmciamesportalmask; /* rev8 */ |
| 138 | u16 PAD[1]; |
| 139 | u16 pcmciawrframebc; /* rev8 */ |
| 140 | u16 PAD[1]; |
| 141 | u16 pcmciaunderflowtimer; /* rev8 */ |
| 142 | u16 PAD[1]; |
| 143 | |
| 144 | /* interrupt */ |
| 145 | u32 intstatus; /* 0x020, rev8 */ |
| 146 | u32 hostintmask; /* rev8 */ |
| 147 | u32 intmask; /* rev8 */ |
| 148 | u32 sbintstatus; /* rev8 */ |
| 149 | u32 sbintmask; /* rev8 */ |
| 150 | u32 funcintmask; /* rev4 */ |
| 151 | u32 PAD[2]; |
| 152 | u32 tosbmailbox; /* 0x040, rev8 */ |
| 153 | u32 tohostmailbox; /* rev8 */ |
| 154 | u32 tosbmailboxdata; /* rev8 */ |
| 155 | u32 tohostmailboxdata; /* rev8 */ |
| 156 | |
| 157 | /* synchronized access to registers in SDIO clock domain */ |
| 158 | u32 sdioaccess; /* 0x050, rev8 */ |
| 159 | u32 PAD[3]; |
| 160 | |
| 161 | /* PCMCIA frame control */ |
| 162 | u8 pcmciaframectrl; /* 0x060, rev8 */ |
| 163 | u8 PAD[3]; |
| 164 | u8 pcmciawatermark; /* rev8 */ |
| 165 | u8 PAD[155]; |
| 166 | |
| 167 | /* interrupt batching control */ |
| 168 | u32 intrcvlazy; /* 0x100, rev8 */ |
| 169 | u32 PAD[3]; |
| 170 | |
| 171 | /* counters */ |
| 172 | u32 cmd52rd; /* 0x110, rev8 */ |
| 173 | u32 cmd52wr; /* rev8 */ |
| 174 | u32 cmd53rd; /* rev8 */ |
| 175 | u32 cmd53wr; /* rev8 */ |
| 176 | u32 abort; /* rev8 */ |
| 177 | u32 datacrcerror; /* rev8 */ |
| 178 | u32 rdoutofsync; /* rev8 */ |
| 179 | u32 wroutofsync; /* rev8 */ |
| 180 | u32 writebusy; /* rev8 */ |
| 181 | u32 readwait; /* rev8 */ |
| 182 | u32 readterm; /* rev8 */ |
| 183 | u32 writeterm; /* rev8 */ |
| 184 | u32 PAD[40]; |
| 185 | u32 clockctlstatus; /* rev8 */ |
| 186 | u32 PAD[7]; |
| 187 | |
| 188 | u32 PAD[128]; /* DMA engines */ |
| 189 | |
| 190 | /* SDIO/PCMCIA CIS region */ |
| 191 | char cis[512]; /* 0x400-0x5ff, rev6 */ |
| 192 | |
| 193 | /* PCMCIA function control registers */ |
| 194 | char pcmciafcr[256]; /* 0x600-6ff, rev6 */ |
| 195 | u16 PAD[55]; |
| 196 | |
| 197 | /* PCMCIA backplane access */ |
| 198 | u16 backplanecsr; /* 0x76E, rev6 */ |
| 199 | u16 backplaneaddr0; /* rev6 */ |
| 200 | u16 backplaneaddr1; /* rev6 */ |
| 201 | u16 backplaneaddr2; /* rev6 */ |
| 202 | u16 backplaneaddr3; /* rev6 */ |
| 203 | u16 backplanedata0; /* rev6 */ |
| 204 | u16 backplanedata1; /* rev6 */ |
| 205 | u16 backplanedata2; /* rev6 */ |
| 206 | u16 backplanedata3; /* rev6 */ |
| 207 | u16 PAD[31]; |
| 208 | |
| 209 | /* sprom "size" & "blank" info */ |
| 210 | u16 spromstatus; /* 0x7BE, rev2 */ |
| 211 | u32 PAD[464]; |
| 212 | |
| 213 | u16 PAD[0x80]; |
| 214 | }; |
| 215 | |
| 216 | extern int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev, |
| 217 | struct chip_info **ci_ptr, u32 regs); |
| 218 | extern void brcmf_sdio_chip_detach(struct chip_info **ci_ptr); |
| 219 | extern void brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev, |
| 220 | struct chip_info *ci, |
| 221 | u32 drivestrength); |
| 222 | extern u8 brcmf_sdio_chip_getinfidx(struct chip_info *ci, u16 coreid); |
| 223 | extern void brcmf_sdio_chip_enter_download(struct brcmf_sdio_dev *sdiodev, |
| 224 | struct chip_info *ci); |
| 225 | extern bool brcmf_sdio_chip_exit_download(struct brcmf_sdio_dev *sdiodev, |
| 226 | struct chip_info *ci, char *nvram_dat, |
| 227 | uint nvram_sz); |
| 228 | |
| 229 | #endif /* _BRCMFMAC_SDIO_CHIP_H_ */ |