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iwlwifi: mvm: Re-factor enabling uAPSD logic
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / pcie / tx.c
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1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29#include <linux/etherdevice.h>
30#include <linux/slab.h>
31#include <linux/sched.h>
32
33#include "iwl-debug.h"
34#include "iwl-csr.h"
35#include "iwl-prph.h"
36#include "iwl-io.h"
37#include "iwl-op-mode.h"
38#include "internal.h"
39/* FIXME: need to abstract out TX command (once we know what it looks like) */
40#include "dvm/commands.h"
41
42#define IWL_TX_CRC_SIZE 4
43#define IWL_TX_DELIMITER_SIZE 4
44
45/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
46 * DMA services
47 *
48 * Theory of operation
49 *
50 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
51 * of buffer descriptors, each of which points to one or more data buffers for
52 * the device to read from or fill. Driver and device exchange status of each
53 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
54 * entries in each circular buffer, to protect against confusing empty and full
55 * queue states.
56 *
57 * The device reads or writes the data in the queues via the device's several
58 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
59 *
60 * For Tx queue, there are low mark and high mark limits. If, after queuing
61 * the packet for Tx, free space become < low mark, Tx queue stopped. When
62 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
63 * Tx queue resumed.
64 *
65 ***************************************************/
66static int iwl_queue_space(const struct iwl_queue *q)
67{
68 unsigned int max;
69 unsigned int used;
70
71 /*
72 * To avoid ambiguity between empty and completely full queues, there
73 * should always be less than q->n_bd elements in the queue.
74 * If q->n_window is smaller than q->n_bd, there is no need to reserve
75 * any queue entries for this purpose.
76 */
77 if (q->n_window < q->n_bd)
78 max = q->n_window;
79 else
80 max = q->n_bd - 1;
81
82 /*
83 * q->n_bd is a power of 2, so the following is equivalent to modulo by
84 * q->n_bd and is well defined for negative dividends.
85 */
86 used = (q->write_ptr - q->read_ptr) & (q->n_bd - 1);
87
88 if (WARN_ON(used > max))
89 return 0;
90
91 return max - used;
92}
93
94/*
95 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
96 */
97static int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id)
98{
99 q->n_bd = count;
100 q->n_window = slots_num;
101 q->id = id;
102
103 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
104 * and iwl_queue_dec_wrap are broken. */
105 if (WARN_ON(!is_power_of_2(count)))
106 return -EINVAL;
107
108 /* slots_num must be power-of-two size, otherwise
109 * get_cmd_index is broken. */
110 if (WARN_ON(!is_power_of_2(slots_num)))
111 return -EINVAL;
112
113 q->low_mark = q->n_window / 4;
114 if (q->low_mark < 4)
115 q->low_mark = 4;
116
117 q->high_mark = q->n_window / 8;
118 if (q->high_mark < 2)
119 q->high_mark = 2;
120
121 q->write_ptr = 0;
122 q->read_ptr = 0;
123
124 return 0;
125}
126
127static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
128 struct iwl_dma_ptr *ptr, size_t size)
129{
130 if (WARN_ON(ptr->addr))
131 return -EINVAL;
132
133 ptr->addr = dma_alloc_coherent(trans->dev, size,
134 &ptr->dma, GFP_KERNEL);
135 if (!ptr->addr)
136 return -ENOMEM;
137 ptr->size = size;
138 return 0;
139}
140
141static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans,
142 struct iwl_dma_ptr *ptr)
143{
144 if (unlikely(!ptr->addr))
145 return;
146
147 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
148 memset(ptr, 0, sizeof(*ptr));
149}
150
151static void iwl_pcie_txq_stuck_timer(unsigned long data)
152{
153 struct iwl_txq *txq = (void *)data;
154 struct iwl_queue *q = &txq->q;
155 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
156 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
157 u32 scd_sram_addr = trans_pcie->scd_base_addr +
158 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
159 u8 buf[16];
160 int i;
161
162 spin_lock(&txq->lock);
163 /* check if triggered erroneously */
164 if (txq->q.read_ptr == txq->q.write_ptr) {
165 spin_unlock(&txq->lock);
166 return;
167 }
168 spin_unlock(&txq->lock);
169
170 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
171 jiffies_to_msecs(trans_pcie->wd_timeout));
172 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
173 txq->q.read_ptr, txq->q.write_ptr);
174
175 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
176
177 iwl_print_hex_error(trans, buf, sizeof(buf));
178
179 for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
180 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
181 iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
182
183 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
184 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
185 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
186 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
187 u32 tbl_dw =
188 iwl_trans_read_mem32(trans,
189 trans_pcie->scd_base_addr +
190 SCD_TRANS_TBL_OFFSET_QUEUE(i));
191
192 if (i & 0x1)
193 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
194 else
195 tbl_dw = tbl_dw & 0x0000FFFF;
196
197 IWL_ERR(trans,
198 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
199 i, active ? "" : "in", fifo, tbl_dw,
200 iwl_read_prph(trans,
201 SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1),
202 iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
203 }
204
205 for (i = q->read_ptr; i != q->write_ptr;
206 i = iwl_queue_inc_wrap(i, q->n_bd))
207 IWL_ERR(trans, "scratch %d = 0x%08x\n", i,
208 le32_to_cpu(txq->scratchbufs[i].scratch));
209
210 iwl_write_prph(trans, DEVICE_SET_NMI_REG, 1);
211}
212
213/*
214 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
215 */
216static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
217 struct iwl_txq *txq, u16 byte_cnt)
218{
219 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
220 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
221 int write_ptr = txq->q.write_ptr;
222 int txq_id = txq->q.id;
223 u8 sec_ctl = 0;
224 u8 sta_id = 0;
225 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
226 __le16 bc_ent;
227 struct iwl_tx_cmd *tx_cmd =
228 (void *) txq->entries[txq->q.write_ptr].cmd->payload;
229
230 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
231
232 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
233
234 sta_id = tx_cmd->sta_id;
235 sec_ctl = tx_cmd->sec_ctl;
236
237 switch (sec_ctl & TX_CMD_SEC_MSK) {
238 case TX_CMD_SEC_CCM:
239 len += IEEE80211_CCMP_MIC_LEN;
240 break;
241 case TX_CMD_SEC_TKIP:
242 len += IEEE80211_TKIP_ICV_LEN;
243 break;
244 case TX_CMD_SEC_WEP:
245 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
246 break;
247 }
248
249 if (trans_pcie->bc_table_dword)
250 len = DIV_ROUND_UP(len, 4);
251
252 bc_ent = cpu_to_le16(len | (sta_id << 12));
253
254 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
255
256 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
257 scd_bc_tbl[txq_id].
258 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
259}
260
261static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
262 struct iwl_txq *txq)
263{
264 struct iwl_trans_pcie *trans_pcie =
265 IWL_TRANS_GET_PCIE_TRANS(trans);
266 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
267 int txq_id = txq->q.id;
268 int read_ptr = txq->q.read_ptr;
269 u8 sta_id = 0;
270 __le16 bc_ent;
271 struct iwl_tx_cmd *tx_cmd =
272 (void *)txq->entries[txq->q.read_ptr].cmd->payload;
273
274 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
275
276 if (txq_id != trans_pcie->cmd_queue)
277 sta_id = tx_cmd->sta_id;
278
279 bc_ent = cpu_to_le16(1 | (sta_id << 12));
280 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
281
282 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
283 scd_bc_tbl[txq_id].
284 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
285}
286
287/*
288 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
289 */
290static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
291 struct iwl_txq *txq)
292{
293 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
294 u32 reg = 0;
295 int txq_id = txq->q.id;
296
297 lockdep_assert_held(&txq->lock);
298
299 /*
300 * explicitly wake up the NIC if:
301 * 1. shadow registers aren't enabled
302 * 2. NIC is woken up for CMD regardless of shadow outside this function
303 * 3. there is a chance that the NIC is asleep
304 */
305 if (!trans->cfg->base_params->shadow_reg_enable &&
306 txq_id != trans_pcie->cmd_queue &&
307 test_bit(STATUS_TPOWER_PMI, &trans->status)) {
308 /*
309 * wake up nic if it's powered down ...
310 * uCode will wake up, and interrupt us again, so next
311 * time we'll skip this part.
312 */
313 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
314
315 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
316 IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
317 txq_id, reg);
318 iwl_set_bit(trans, CSR_GP_CNTRL,
319 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
320 txq->need_update = true;
321 return;
322 }
323 }
324
325 /*
326 * if not in power-save mode, uCode will never sleep when we're
327 * trying to tx (during RFKILL, we're not trying to tx).
328 */
329 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr);
330 iwl_write32(trans, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
331}
332
333void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
334{
335 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
336 int i;
337
338 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
339 struct iwl_txq *txq = &trans_pcie->txq[i];
340
341 spin_lock(&txq->lock);
342 if (trans_pcie->txq[i].need_update) {
343 iwl_pcie_txq_inc_wr_ptr(trans, txq);
344 trans_pcie->txq[i].need_update = false;
345 }
346 spin_unlock(&txq->lock);
347 }
348}
349
350static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
351{
352 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
353
354 dma_addr_t addr = get_unaligned_le32(&tb->lo);
355 if (sizeof(dma_addr_t) > sizeof(u32))
356 addr |=
357 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
358
359 return addr;
360}
361
362static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
363{
364 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
365
366 return le16_to_cpu(tb->hi_n_len) >> 4;
367}
368
369static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
370 dma_addr_t addr, u16 len)
371{
372 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
373 u16 hi_n_len = len << 4;
374
375 put_unaligned_le32(addr, &tb->lo);
376 if (sizeof(dma_addr_t) > sizeof(u32))
377 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
378
379 tb->hi_n_len = cpu_to_le16(hi_n_len);
380
381 tfd->num_tbs = idx + 1;
382}
383
384static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd)
385{
386 return tfd->num_tbs & 0x1f;
387}
388
389static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
390 struct iwl_cmd_meta *meta,
391 struct iwl_tfd *tfd)
392{
393 int i;
394 int num_tbs;
395
396 /* Sanity check on number of chunks */
397 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
398
399 if (num_tbs >= IWL_NUM_OF_TBS) {
400 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
401 /* @todo issue fatal error, it is quite serious situation */
402 return;
403 }
404
405 /* first TB is never freed - it's the scratchbuf data */
406
407 for (i = 1; i < num_tbs; i++)
408 dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i),
409 iwl_pcie_tfd_tb_get_len(tfd, i),
410 DMA_TO_DEVICE);
411
412 tfd->num_tbs = 0;
413}
414
415/*
416 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
417 * @trans - transport private data
418 * @txq - tx queue
419 * @dma_dir - the direction of the DMA mapping
420 *
421 * Does NOT advance any TFD circular buffer read/write indexes
422 * Does NOT free the TFD itself (which is within circular buffer)
423 */
424static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
425{
426 struct iwl_tfd *tfd_tmp = txq->tfds;
427
428 /* rd_ptr is bounded by n_bd and idx is bounded by n_window */
429 int rd_ptr = txq->q.read_ptr;
430 int idx = get_cmd_index(&txq->q, rd_ptr);
431
432 lockdep_assert_held(&txq->lock);
433
434 /* We have only q->n_window txq->entries, but we use q->n_bd tfds */
435 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]);
436
437 /* free SKB */
438 if (txq->entries) {
439 struct sk_buff *skb;
440
441 skb = txq->entries[idx].skb;
442
443 /* Can be called from irqs-disabled context
444 * If skb is not NULL, it means that the whole queue is being
445 * freed and that the queue is not empty - free the skb
446 */
447 if (skb) {
448 iwl_op_mode_free_skb(trans->op_mode, skb);
449 txq->entries[idx].skb = NULL;
450 }
451 }
452}
453
454static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
455 dma_addr_t addr, u16 len, u8 reset)
456{
457 struct iwl_queue *q;
458 struct iwl_tfd *tfd, *tfd_tmp;
459 u32 num_tbs;
460
461 q = &txq->q;
462 tfd_tmp = txq->tfds;
463 tfd = &tfd_tmp[q->write_ptr];
464
465 if (reset)
466 memset(tfd, 0, sizeof(*tfd));
467
468 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
469
470 /* Each TFD can point to a maximum 20 Tx buffers */
471 if (num_tbs >= IWL_NUM_OF_TBS) {
472 IWL_ERR(trans, "Error can not send more than %d chunks\n",
473 IWL_NUM_OF_TBS);
474 return -EINVAL;
475 }
476
477 if (WARN(addr & ~IWL_TX_DMA_MASK,
478 "Unaligned address = %llx\n", (unsigned long long)addr))
479 return -EINVAL;
480
481 iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len);
482
483 return 0;
484}
485
486static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
487 struct iwl_txq *txq, int slots_num,
488 u32 txq_id)
489{
490 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
491 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
492 size_t scratchbuf_sz;
493 int i;
494
495 if (WARN_ON(txq->entries || txq->tfds))
496 return -EINVAL;
497
498 setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer,
499 (unsigned long)txq);
500 txq->trans_pcie = trans_pcie;
501
502 txq->q.n_window = slots_num;
503
504 txq->entries = kcalloc(slots_num,
505 sizeof(struct iwl_pcie_txq_entry),
506 GFP_KERNEL);
507
508 if (!txq->entries)
509 goto error;
510
511 if (txq_id == trans_pcie->cmd_queue)
512 for (i = 0; i < slots_num; i++) {
513 txq->entries[i].cmd =
514 kmalloc(sizeof(struct iwl_device_cmd),
515 GFP_KERNEL);
516 if (!txq->entries[i].cmd)
517 goto error;
518 }
519
520 /* Circular buffer of transmit frame descriptors (TFDs),
521 * shared with device */
522 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
523 &txq->q.dma_addr, GFP_KERNEL);
524 if (!txq->tfds)
525 goto error;
526
527 BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs));
528 BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) !=
529 sizeof(struct iwl_cmd_header) +
530 offsetof(struct iwl_tx_cmd, scratch));
531
532 scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num;
533
534 txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz,
535 &txq->scratchbufs_dma,
536 GFP_KERNEL);
537 if (!txq->scratchbufs)
538 goto err_free_tfds;
539
540 txq->q.id = txq_id;
541
542 return 0;
543err_free_tfds:
544 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr);
545error:
546 if (txq->entries && txq_id == trans_pcie->cmd_queue)
547 for (i = 0; i < slots_num; i++)
548 kfree(txq->entries[i].cmd);
549 kfree(txq->entries);
550 txq->entries = NULL;
551
552 return -ENOMEM;
553
554}
555
556static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
557 int slots_num, u32 txq_id)
558{
559 int ret;
560
561 txq->need_update = false;
562
563 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
564 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
565 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
566
567 /* Initialize queue's high/low-water marks, and head/tail indexes */
568 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
569 txq_id);
570 if (ret)
571 return ret;
572
573 spin_lock_init(&txq->lock);
574
575 /*
576 * Tell nic where to find circular buffer of Tx Frame Descriptors for
577 * given Tx queue, and enable the DMA channel used for that queue.
578 * Circular buffer (TFD queue in DRAM) physical base address */
579 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
580 txq->q.dma_addr >> 8);
581
582 return 0;
583}
584
585/*
586 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
587 */
588static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
589{
590 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
591 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
592 struct iwl_queue *q = &txq->q;
593
594 if (!q->n_bd)
595 return;
596
597 spin_lock_bh(&txq->lock);
598 while (q->write_ptr != q->read_ptr) {
599 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
600 txq_id, q->read_ptr);
601 iwl_pcie_txq_free_tfd(trans, txq);
602 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
603 }
604 txq->active = false;
605 spin_unlock_bh(&txq->lock);
606
607 /* just in case - this queue may have been stopped */
608 iwl_wake_queue(trans, txq);
609}
610
611/*
612 * iwl_pcie_txq_free - Deallocate DMA queue.
613 * @txq: Transmit queue to deallocate.
614 *
615 * Empty queue by removing and destroying all BD's.
616 * Free all buffers.
617 * 0-fill, but do not free "txq" descriptor structure.
618 */
619static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
620{
621 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
622 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
623 struct device *dev = trans->dev;
624 int i;
625
626 if (WARN_ON(!txq))
627 return;
628
629 iwl_pcie_txq_unmap(trans, txq_id);
630
631 /* De-alloc array of command/tx buffers */
632 if (txq_id == trans_pcie->cmd_queue)
633 for (i = 0; i < txq->q.n_window; i++) {
634 kfree(txq->entries[i].cmd);
635 kfree(txq->entries[i].free_buf);
636 }
637
638 /* De-alloc circular buffer of TFDs */
639 if (txq->q.n_bd) {
640 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
641 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
642 txq->q.dma_addr = 0;
643
644 dma_free_coherent(dev,
645 sizeof(*txq->scratchbufs) * txq->q.n_window,
646 txq->scratchbufs, txq->scratchbufs_dma);
647 }
648
649 kfree(txq->entries);
650 txq->entries = NULL;
651
652 del_timer_sync(&txq->stuck_timer);
653
654 /* 0-fill queue descriptor structure */
655 memset(txq, 0, sizeof(*txq));
656}
657
658/*
659 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
660 */
661static void iwl_pcie_txq_set_sched(struct iwl_trans *trans, u32 mask)
662{
663 struct iwl_trans_pcie __maybe_unused *trans_pcie =
664 IWL_TRANS_GET_PCIE_TRANS(trans);
665
666 iwl_write_prph(trans, SCD_TXFACT, mask);
667}
668
669void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
670{
671 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
672 int nq = trans->cfg->base_params->num_of_queues;
673 int chan;
674 u32 reg_val;
675 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
676 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
677
678 /* make sure all queue are not stopped/used */
679 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
680 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
681
682 trans_pcie->scd_base_addr =
683 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
684
685 WARN_ON(scd_base_addr != 0 &&
686 scd_base_addr != trans_pcie->scd_base_addr);
687
688 /* reset context data, TX status and translation data */
689 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
690 SCD_CONTEXT_MEM_LOWER_BOUND,
691 NULL, clear_dwords);
692
693 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
694 trans_pcie->scd_bc_tbls.dma >> 10);
695
696 /* The chain extension of the SCD doesn't work well. This feature is
697 * enabled by default by the HW, so we need to disable it manually.
698 */
699 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
700
701 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
702 trans_pcie->cmd_fifo);
703
704 /* Activate all Tx DMA/FIFO channels */
705 iwl_pcie_txq_set_sched(trans, IWL_MASK(0, 7));
706
707 /* Enable DMA channel */
708 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
709 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
710 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
711 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
712
713 /* Update FH chicken bits */
714 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
715 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
716 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
717
718 /* Enable L1-Active */
719 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
720 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
721 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
722}
723
724void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
725{
726 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
727 int txq_id;
728
729 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
730 txq_id++) {
731 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
732
733 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
734 txq->q.dma_addr >> 8);
735 iwl_pcie_txq_unmap(trans, txq_id);
736 txq->q.read_ptr = 0;
737 txq->q.write_ptr = 0;
738 }
739
740 /* Tell NIC where to find the "keep warm" buffer */
741 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
742 trans_pcie->kw.dma >> 4);
743
744 iwl_pcie_tx_start(trans, trans_pcie->scd_base_addr);
745}
746
747/*
748 * iwl_pcie_tx_stop - Stop all Tx DMA channels
749 */
750int iwl_pcie_tx_stop(struct iwl_trans *trans)
751{
752 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
753 int ch, txq_id, ret;
754
755 /* Turn off all Tx DMA fifos */
756 spin_lock(&trans_pcie->irq_lock);
757
758 iwl_pcie_txq_set_sched(trans, 0);
759
760 /* Stop each Tx DMA channel, and wait for it to be idle */
761 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
762 iwl_write_direct32(trans,
763 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
764 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
765 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000);
766 if (ret < 0)
767 IWL_ERR(trans,
768 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
769 ch,
770 iwl_read_direct32(trans,
771 FH_TSSR_TX_STATUS_REG));
772 }
773 spin_unlock(&trans_pcie->irq_lock);
774
775 /*
776 * This function can be called before the op_mode disabled the
777 * queues. This happens when we have an rfkill interrupt.
778 * Since we stop Tx altogether - mark the queues as stopped.
779 */
780 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
781 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
782
783 /* This can happen: start_hw, stop_device */
784 if (!trans_pcie->txq)
785 return 0;
786
787 /* Unmap DMA from host system and free skb's */
788 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
789 txq_id++)
790 iwl_pcie_txq_unmap(trans, txq_id);
791
792 return 0;
793}
794
795/*
796 * iwl_trans_tx_free - Free TXQ Context
797 *
798 * Destroy all TX DMA queues and structures
799 */
800void iwl_pcie_tx_free(struct iwl_trans *trans)
801{
802 int txq_id;
803 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
804
805 /* Tx queues */
806 if (trans_pcie->txq) {
807 for (txq_id = 0;
808 txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
809 iwl_pcie_txq_free(trans, txq_id);
810 }
811
812 kfree(trans_pcie->txq);
813 trans_pcie->txq = NULL;
814
815 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
816
817 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
818}
819
820/*
821 * iwl_pcie_tx_alloc - allocate TX context
822 * Allocate all Tx DMA structures and initialize them
823 */
824static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
825{
826 int ret;
827 int txq_id, slots_num;
828 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
829
830 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
831 sizeof(struct iwlagn_scd_bc_tbl);
832
833 /*It is not allowed to alloc twice, so warn when this happens.
834 * We cannot rely on the previous allocation, so free and fail */
835 if (WARN_ON(trans_pcie->txq)) {
836 ret = -EINVAL;
837 goto error;
838 }
839
840 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
841 scd_bc_tbls_size);
842 if (ret) {
843 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
844 goto error;
845 }
846
847 /* Alloc keep-warm buffer */
848 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
849 if (ret) {
850 IWL_ERR(trans, "Keep Warm allocation failed\n");
851 goto error;
852 }
853
854 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
855 sizeof(struct iwl_txq), GFP_KERNEL);
856 if (!trans_pcie->txq) {
857 IWL_ERR(trans, "Not enough memory for txq\n");
858 ret = -ENOMEM;
859 goto error;
860 }
861
862 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
863 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
864 txq_id++) {
865 slots_num = (txq_id == trans_pcie->cmd_queue) ?
866 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
867 ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id],
868 slots_num, txq_id);
869 if (ret) {
870 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
871 goto error;
872 }
873 }
874
875 return 0;
876
877error:
878 iwl_pcie_tx_free(trans);
879
880 return ret;
881}
882int iwl_pcie_tx_init(struct iwl_trans *trans)
883{
884 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
885 int ret;
886 int txq_id, slots_num;
887 bool alloc = false;
888
889 if (!trans_pcie->txq) {
890 ret = iwl_pcie_tx_alloc(trans);
891 if (ret)
892 goto error;
893 alloc = true;
894 }
895
896 spin_lock(&trans_pcie->irq_lock);
897
898 /* Turn off all Tx DMA fifos */
899 iwl_write_prph(trans, SCD_TXFACT, 0);
900
901 /* Tell NIC where to find the "keep warm" buffer */
902 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
903 trans_pcie->kw.dma >> 4);
904
905 spin_unlock(&trans_pcie->irq_lock);
906
907 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
908 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
909 txq_id++) {
910 slots_num = (txq_id == trans_pcie->cmd_queue) ?
911 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
912 ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id],
913 slots_num, txq_id);
914 if (ret) {
915 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
916 goto error;
917 }
918 }
919
920 return 0;
921error:
922 /*Upon error, free only if we allocated something */
923 if (alloc)
924 iwl_pcie_tx_free(trans);
925 return ret;
926}
927
928static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie *trans_pcie,
929 struct iwl_txq *txq)
930{
931 if (!trans_pcie->wd_timeout)
932 return;
933
934 /*
935 * if empty delete timer, otherwise move timer forward
936 * since we're making progress on this queue
937 */
938 if (txq->q.read_ptr == txq->q.write_ptr)
939 del_timer(&txq->stuck_timer);
940 else
941 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
942}
943
944/* Frees buffers until index _not_ inclusive */
945void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
946 struct sk_buff_head *skbs)
947{
948 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
949 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
950 /* n_bd is usually 256 => n_bd - 1 = 0xff */
951 int tfd_num = ssn & (txq->q.n_bd - 1);
952 struct iwl_queue *q = &txq->q;
953 int last_to_free;
954
955 /* This function is not meant to release cmd queue*/
956 if (WARN_ON(txq_id == trans_pcie->cmd_queue))
957 return;
958
959 spin_lock_bh(&txq->lock);
960
961 if (!txq->active) {
962 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
963 txq_id, ssn);
964 goto out;
965 }
966
967 if (txq->q.read_ptr == tfd_num)
968 goto out;
969
970 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
971 txq_id, txq->q.read_ptr, tfd_num, ssn);
972
973 /*Since we free until index _not_ inclusive, the one before index is
974 * the last we will free. This one must be used */
975 last_to_free = iwl_queue_dec_wrap(tfd_num, q->n_bd);
976
977 if (!iwl_queue_used(q, last_to_free)) {
978 IWL_ERR(trans,
979 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
980 __func__, txq_id, last_to_free, q->n_bd,
981 q->write_ptr, q->read_ptr);
982 goto out;
983 }
984
985 if (WARN_ON(!skb_queue_empty(skbs)))
986 goto out;
987
988 for (;
989 q->read_ptr != tfd_num;
990 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
991
992 if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL))
993 continue;
994
995 __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb);
996
997 txq->entries[txq->q.read_ptr].skb = NULL;
998
999 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
1000
1001 iwl_pcie_txq_free_tfd(trans, txq);
1002 }
1003
1004 iwl_pcie_txq_progress(trans_pcie, txq);
1005
1006 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1007 iwl_wake_queue(trans, txq);
1008out:
1009 spin_unlock_bh(&txq->lock);
1010}
1011
1012/*
1013 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1014 *
1015 * When FW advances 'R' index, all entries between old and new 'R' index
1016 * need to be reclaimed. As result, some free space forms. If there is
1017 * enough free space (> low mark), wake the stack that feeds us.
1018 */
1019static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1020{
1021 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1022 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1023 struct iwl_queue *q = &txq->q;
1024 unsigned long flags;
1025 int nfreed = 0;
1026
1027 lockdep_assert_held(&txq->lock);
1028
1029 if ((idx >= q->n_bd) || (!iwl_queue_used(q, idx))) {
1030 IWL_ERR(trans,
1031 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1032 __func__, txq_id, idx, q->n_bd,
1033 q->write_ptr, q->read_ptr);
1034 return;
1035 }
1036
1037 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
1038 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1039
1040 if (nfreed++ > 0) {
1041 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1042 idx, q->write_ptr, q->read_ptr);
1043 iwl_write_prph(trans, DEVICE_SET_NMI_REG, 1);
1044 }
1045 }
1046
1047 if (trans->cfg->base_params->apmg_wake_up_wa &&
1048 q->read_ptr == q->write_ptr) {
1049 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1050 WARN_ON(!trans_pcie->cmd_in_flight);
1051 trans_pcie->cmd_in_flight = false;
1052 __iwl_trans_pcie_clear_bit(trans,
1053 CSR_GP_CNTRL,
1054 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1055 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1056 }
1057
1058 iwl_pcie_txq_progress(trans_pcie, txq);
1059}
1060
1061static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1062 u16 txq_id)
1063{
1064 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1065 u32 tbl_dw_addr;
1066 u32 tbl_dw;
1067 u16 scd_q2ratid;
1068
1069 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1070
1071 tbl_dw_addr = trans_pcie->scd_base_addr +
1072 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1073
1074 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1075
1076 if (txq_id & 0x1)
1077 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1078 else
1079 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1080
1081 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1082
1083 return 0;
1084}
1085
1086static inline void iwl_pcie_txq_set_inactive(struct iwl_trans *trans,
1087 u16 txq_id)
1088{
1089 /* Simply stop the queue, but don't change any configuration;
1090 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1091 iwl_write_prph(trans,
1092 SCD_QUEUE_STATUS_BITS(txq_id),
1093 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1094 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1095}
1096
1097/* Receiver address (actually, Rx station's index into station table),
1098 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1099#define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1100
1101void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo,
1102 int sta_id, int tid, int frame_limit, u16 ssn)
1103{
1104 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1105
1106 if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1107 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1108
1109 /* Stop this Tx queue before configuring it */
1110 iwl_pcie_txq_set_inactive(trans, txq_id);
1111
1112 /* Set this queue as a chain-building queue unless it is CMD queue */
1113 if (txq_id != trans_pcie->cmd_queue)
1114 iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id));
1115
1116 /* If this queue is mapped to a certain station: it is an AGG queue */
1117 if (sta_id >= 0) {
1118 u16 ra_tid = BUILD_RAxTID(sta_id, tid);
1119
1120 /* Map receiver-address / traffic-ID to this queue */
1121 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1122
1123 /* enable aggregations for the queue */
1124 iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
1125 trans_pcie->txq[txq_id].ampdu = true;
1126 } else {
1127 /*
1128 * disable aggregations for the queue, this will also make the
1129 * ra_tid mapping configuration irrelevant since it is now a
1130 * non-AGG queue.
1131 */
1132 iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
1133
1134 ssn = trans_pcie->txq[txq_id].q.read_ptr;
1135 }
1136
1137 /* Place first TFD at index corresponding to start sequence number.
1138 * Assumes that ssn_idx is valid (!= 0xFFF) */
1139 trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff);
1140 trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff);
1141
1142 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1143 (ssn & 0xff) | (txq_id << 8));
1144 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1145
1146 /* Set up Tx window size and frame limit for this queue */
1147 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1148 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1149 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1150 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1151 ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1152 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1153 ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1154 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1155
1156 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1157 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1158 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1159 (fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1160 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1161 SCD_QUEUE_STTS_REG_MSK);
1162 trans_pcie->txq[txq_id].active = true;
1163 IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d WrPtr: %d\n",
1164 txq_id, fifo, ssn & 0xff);
1165}
1166
1167void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id)
1168{
1169 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1170 u32 stts_addr = trans_pcie->scd_base_addr +
1171 SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1172 static const u32 zero_val[4] = {};
1173
1174 /*
1175 * Upon HW Rfkill - we stop the device, and then stop the queues
1176 * in the op_mode. Just for the sake of the simplicity of the op_mode,
1177 * allow the op_mode to call txq_disable after it already called
1178 * stop_device.
1179 */
1180 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1181 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1182 "queue %d not used", txq_id);
1183 return;
1184 }
1185
1186 iwl_pcie_txq_set_inactive(trans, txq_id);
1187
1188 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1189 ARRAY_SIZE(zero_val));
1190
1191 iwl_pcie_txq_unmap(trans, txq_id);
1192 trans_pcie->txq[txq_id].ampdu = false;
1193
1194 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1195}
1196
1197/*************** HOST COMMAND QUEUE FUNCTIONS *****/
1198
1199/*
1200 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1201 * @priv: device private data point
1202 * @cmd: a pointer to the ucode command structure
1203 *
1204 * The function returns < 0 values to indicate the operation
1205 * failed. On success, it returns the index (>= 0) of command in the
1206 * command queue.
1207 */
1208static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1209 struct iwl_host_cmd *cmd)
1210{
1211 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1212 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1213 struct iwl_queue *q = &txq->q;
1214 struct iwl_device_cmd *out_cmd;
1215 struct iwl_cmd_meta *out_meta;
1216 unsigned long flags;
1217 void *dup_buf = NULL;
1218 dma_addr_t phys_addr;
1219 int idx;
1220 u16 copy_size, cmd_size, scratch_size;
1221 bool had_nocopy = false;
1222 int i, ret;
1223 u32 cmd_pos;
1224 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1225 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1226
1227 copy_size = sizeof(out_cmd->hdr);
1228 cmd_size = sizeof(out_cmd->hdr);
1229
1230 /* need one for the header if the first is NOCOPY */
1231 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1232
1233 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1234 cmddata[i] = cmd->data[i];
1235 cmdlen[i] = cmd->len[i];
1236
1237 if (!cmd->len[i])
1238 continue;
1239
1240 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1241 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1242 int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1243
1244 if (copy > cmdlen[i])
1245 copy = cmdlen[i];
1246 cmdlen[i] -= copy;
1247 cmddata[i] += copy;
1248 copy_size += copy;
1249 }
1250
1251 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1252 had_nocopy = true;
1253 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1254 idx = -EINVAL;
1255 goto free_dup_buf;
1256 }
1257 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1258 /*
1259 * This is also a chunk that isn't copied
1260 * to the static buffer so set had_nocopy.
1261 */
1262 had_nocopy = true;
1263
1264 /* only allowed once */
1265 if (WARN_ON(dup_buf)) {
1266 idx = -EINVAL;
1267 goto free_dup_buf;
1268 }
1269
1270 dup_buf = kmemdup(cmddata[i], cmdlen[i],
1271 GFP_ATOMIC);
1272 if (!dup_buf)
1273 return -ENOMEM;
1274 } else {
1275 /* NOCOPY must not be followed by normal! */
1276 if (WARN_ON(had_nocopy)) {
1277 idx = -EINVAL;
1278 goto free_dup_buf;
1279 }
1280 copy_size += cmdlen[i];
1281 }
1282 cmd_size += cmd->len[i];
1283 }
1284
1285 /*
1286 * If any of the command structures end up being larger than
1287 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1288 * allocated into separate TFDs, then we will need to
1289 * increase the size of the buffers.
1290 */
1291 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1292 "Command %s (%#x) is too large (%d bytes)\n",
1293 get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) {
1294 idx = -EINVAL;
1295 goto free_dup_buf;
1296 }
1297
1298 spin_lock_bh(&txq->lock);
1299
1300 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1301 spin_unlock_bh(&txq->lock);
1302
1303 IWL_ERR(trans, "No space in command queue\n");
1304 iwl_op_mode_cmd_queue_full(trans->op_mode);
1305 idx = -ENOSPC;
1306 goto free_dup_buf;
1307 }
1308
1309 idx = get_cmd_index(q, q->write_ptr);
1310 out_cmd = txq->entries[idx].cmd;
1311 out_meta = &txq->entries[idx].meta;
1312
1313 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1314 if (cmd->flags & CMD_WANT_SKB)
1315 out_meta->source = cmd;
1316
1317 /* set up the header */
1318
1319 out_cmd->hdr.cmd = cmd->id;
1320 out_cmd->hdr.flags = 0;
1321 out_cmd->hdr.sequence =
1322 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1323 INDEX_TO_SEQ(q->write_ptr));
1324
1325 /* and copy the data that needs to be copied */
1326 cmd_pos = offsetof(struct iwl_device_cmd, payload);
1327 copy_size = sizeof(out_cmd->hdr);
1328 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1329 int copy = 0;
1330
1331 if (!cmd->len[i])
1332 continue;
1333
1334 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1335 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1336 copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1337
1338 if (copy > cmd->len[i])
1339 copy = cmd->len[i];
1340 }
1341
1342 /* copy everything if not nocopy/dup */
1343 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1344 IWL_HCMD_DFL_DUP)))
1345 copy = cmd->len[i];
1346
1347 if (copy) {
1348 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1349 cmd_pos += copy;
1350 copy_size += copy;
1351 }
1352 }
1353
1354 IWL_DEBUG_HC(trans,
1355 "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1356 get_cmd_string(trans_pcie, out_cmd->hdr.cmd),
1357 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
1358 cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue);
1359
1360 /* start the TFD with the scratchbuf */
1361 scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE);
1362 memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size);
1363 iwl_pcie_txq_build_tfd(trans, txq,
1364 iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr),
1365 scratch_size, 1);
1366
1367 /* map first command fragment, if any remains */
1368 if (copy_size > scratch_size) {
1369 phys_addr = dma_map_single(trans->dev,
1370 ((u8 *)&out_cmd->hdr) + scratch_size,
1371 copy_size - scratch_size,
1372 DMA_TO_DEVICE);
1373 if (dma_mapping_error(trans->dev, phys_addr)) {
1374 iwl_pcie_tfd_unmap(trans, out_meta,
1375 &txq->tfds[q->write_ptr]);
1376 idx = -ENOMEM;
1377 goto out;
1378 }
1379
1380 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1381 copy_size - scratch_size, 0);
1382 }
1383
1384 /* map the remaining (adjusted) nocopy/dup fragments */
1385 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1386 const void *data = cmddata[i];
1387
1388 if (!cmdlen[i])
1389 continue;
1390 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1391 IWL_HCMD_DFL_DUP)))
1392 continue;
1393 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1394 data = dup_buf;
1395 phys_addr = dma_map_single(trans->dev, (void *)data,
1396 cmdlen[i], DMA_TO_DEVICE);
1397 if (dma_mapping_error(trans->dev, phys_addr)) {
1398 iwl_pcie_tfd_unmap(trans, out_meta,
1399 &txq->tfds[q->write_ptr]);
1400 idx = -ENOMEM;
1401 goto out;
1402 }
1403
1404 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], 0);
1405 }
1406
1407 out_meta->flags = cmd->flags;
1408 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1409 kfree(txq->entries[idx].free_buf);
1410 txq->entries[idx].free_buf = dup_buf;
1411
1412 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr);
1413
1414 /* start timer if queue currently empty */
1415 if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout)
1416 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1417
1418 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1419
1420 /*
1421 * wake up the NIC to make sure that the firmware will see the host
1422 * command - we will let the NIC sleep once all the host commands
1423 * returned. This needs to be done only on NICs that have
1424 * apmg_wake_up_wa set.
1425 */
1426 if (trans->cfg->base_params->apmg_wake_up_wa &&
1427 !trans_pcie->cmd_in_flight) {
1428 trans_pcie->cmd_in_flight = true;
1429 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1430 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1431 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1432 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1433 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1434 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1435 15000);
1436 if (ret < 0) {
1437 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1438 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1439 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1440 trans_pcie->cmd_in_flight = false;
1441 idx = -EIO;
1442 goto out;
1443 }
1444 }
1445
1446 /* Increment and update queue's write index */
1447 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1448 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1449
1450 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1451
1452 out:
1453 spin_unlock_bh(&txq->lock);
1454 free_dup_buf:
1455 if (idx < 0)
1456 kfree(dup_buf);
1457 return idx;
1458}
1459
1460/*
1461 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1462 * @rxb: Rx buffer to reclaim
1463 * @handler_status: return value of the handler of the command
1464 * (put in setup_rx_handlers)
1465 *
1466 * If an Rx buffer has an async callback associated with it the callback
1467 * will be executed. The attached skb (if present) will only be freed
1468 * if the callback returns 1
1469 */
1470void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1471 struct iwl_rx_cmd_buffer *rxb, int handler_status)
1472{
1473 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1474 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1475 int txq_id = SEQ_TO_QUEUE(sequence);
1476 int index = SEQ_TO_INDEX(sequence);
1477 int cmd_index;
1478 struct iwl_device_cmd *cmd;
1479 struct iwl_cmd_meta *meta;
1480 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1481 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1482
1483 /* If a Tx command is being handled and it isn't in the actual
1484 * command queue then there a command routing bug has been introduced
1485 * in the queue management code. */
1486 if (WARN(txq_id != trans_pcie->cmd_queue,
1487 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1488 txq_id, trans_pcie->cmd_queue, sequence,
1489 trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
1490 trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
1491 iwl_print_hex_error(trans, pkt, 32);
1492 return;
1493 }
1494
1495 spin_lock_bh(&txq->lock);
1496
1497 cmd_index = get_cmd_index(&txq->q, index);
1498 cmd = txq->entries[cmd_index].cmd;
1499 meta = &txq->entries[cmd_index].meta;
1500
1501 iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]);
1502
1503 /* Input error checking is done when commands are added to queue. */
1504 if (meta->flags & CMD_WANT_SKB) {
1505 struct page *p = rxb_steal_page(rxb);
1506
1507 meta->source->resp_pkt = pkt;
1508 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1509 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1510 meta->source->handler_status = handler_status;
1511 }
1512
1513 iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1514
1515 if (!(meta->flags & CMD_ASYNC)) {
1516 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1517 IWL_WARN(trans,
1518 "HCMD_ACTIVE already clear for command %s\n",
1519 get_cmd_string(trans_pcie, cmd->hdr.cmd));
1520 }
1521 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1522 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1523 get_cmd_string(trans_pcie, cmd->hdr.cmd));
1524 wake_up(&trans_pcie->wait_command_queue);
1525 }
1526
1527 meta->flags = 0;
1528
1529 spin_unlock_bh(&txq->lock);
1530}
1531
1532#define HOST_COMPLETE_TIMEOUT (2 * HZ)
1533
1534static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1535 struct iwl_host_cmd *cmd)
1536{
1537 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1538 int ret;
1539
1540 /* An asynchronous command can not expect an SKB to be set. */
1541 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1542 return -EINVAL;
1543
1544 ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1545 if (ret < 0) {
1546 IWL_ERR(trans,
1547 "Error sending %s: enqueue_hcmd failed: %d\n",
1548 get_cmd_string(trans_pcie, cmd->id), ret);
1549 return ret;
1550 }
1551 return 0;
1552}
1553
1554static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1555 struct iwl_host_cmd *cmd)
1556{
1557 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1558 int cmd_idx;
1559 int ret;
1560
1561 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1562 get_cmd_string(trans_pcie, cmd->id));
1563
1564 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1565 &trans->status),
1566 "Command %s: a command is already active!\n",
1567 get_cmd_string(trans_pcie, cmd->id)))
1568 return -EIO;
1569
1570 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1571 get_cmd_string(trans_pcie, cmd->id));
1572
1573 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1574 if (cmd_idx < 0) {
1575 ret = cmd_idx;
1576 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1577 IWL_ERR(trans,
1578 "Error sending %s: enqueue_hcmd failed: %d\n",
1579 get_cmd_string(trans_pcie, cmd->id), ret);
1580 return ret;
1581 }
1582
1583 ret = wait_event_timeout(trans_pcie->wait_command_queue,
1584 !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1585 &trans->status),
1586 HOST_COMPLETE_TIMEOUT);
1587 if (!ret) {
1588 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1589 struct iwl_queue *q = &txq->q;
1590
1591 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1592 get_cmd_string(trans_pcie, cmd->id),
1593 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1594
1595 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1596 q->read_ptr, q->write_ptr);
1597
1598 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1599 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1600 get_cmd_string(trans_pcie, cmd->id));
1601 ret = -ETIMEDOUT;
1602
1603 iwl_write_prph(trans, DEVICE_SET_NMI_REG, 1);
1604 iwl_trans_fw_error(trans);
1605
1606 goto cancel;
1607 }
1608
1609 if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1610 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1611 get_cmd_string(trans_pcie, cmd->id));
1612 dump_stack();
1613 ret = -EIO;
1614 goto cancel;
1615 }
1616
1617 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1618 test_bit(STATUS_RFKILL, &trans->status)) {
1619 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1620 ret = -ERFKILL;
1621 goto cancel;
1622 }
1623
1624 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1625 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1626 get_cmd_string(trans_pcie, cmd->id));
1627 ret = -EIO;
1628 goto cancel;
1629 }
1630
1631 return 0;
1632
1633cancel:
1634 if (cmd->flags & CMD_WANT_SKB) {
1635 /*
1636 * Cancel the CMD_WANT_SKB flag for the cmd in the
1637 * TX cmd queue. Otherwise in case the cmd comes
1638 * in later, it will possibly set an invalid
1639 * address (cmd->meta.source).
1640 */
1641 trans_pcie->txq[trans_pcie->cmd_queue].
1642 entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1643 }
1644
1645 if (cmd->resp_pkt) {
1646 iwl_free_resp(cmd);
1647 cmd->resp_pkt = NULL;
1648 }
1649
1650 return ret;
1651}
1652
1653int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1654{
1655 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1656 test_bit(STATUS_RFKILL, &trans->status)) {
1657 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1658 cmd->id);
1659 return -ERFKILL;
1660 }
1661
1662 if (cmd->flags & CMD_ASYNC)
1663 return iwl_pcie_send_hcmd_async(trans, cmd);
1664
1665 /* We still can fail on RFKILL that can be asserted while we wait */
1666 return iwl_pcie_send_hcmd_sync(trans, cmd);
1667}
1668
1669int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1670 struct iwl_device_cmd *dev_cmd, int txq_id)
1671{
1672 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1673 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1674 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
1675 struct iwl_cmd_meta *out_meta;
1676 struct iwl_txq *txq;
1677 struct iwl_queue *q;
1678 dma_addr_t tb0_phys, tb1_phys, scratch_phys;
1679 void *tb1_addr;
1680 u16 len, tb1_len, tb2_len;
1681 bool wait_write_ptr;
1682 __le16 fc = hdr->frame_control;
1683 u8 hdr_len = ieee80211_hdrlen(fc);
1684 u16 wifi_seq;
1685
1686 txq = &trans_pcie->txq[txq_id];
1687 q = &txq->q;
1688
1689 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
1690 "TX on unused queue %d\n", txq_id))
1691 return -EINVAL;
1692
1693 spin_lock(&txq->lock);
1694
1695 /* In AGG mode, the index in the ring must correspond to the WiFi
1696 * sequence number. This is a HW requirements to help the SCD to parse
1697 * the BA.
1698 * Check here that the packets are in the right place on the ring.
1699 */
1700 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1701 WARN_ONCE(txq->ampdu &&
1702 (wifi_seq & 0xff) != q->write_ptr,
1703 "Q: %d WiFi Seq %d tfdNum %d",
1704 txq_id, wifi_seq, q->write_ptr);
1705
1706 /* Set up driver data for this TFD */
1707 txq->entries[q->write_ptr].skb = skb;
1708 txq->entries[q->write_ptr].cmd = dev_cmd;
1709
1710 dev_cmd->hdr.sequence =
1711 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1712 INDEX_TO_SEQ(q->write_ptr)));
1713
1714 tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr);
1715 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
1716 offsetof(struct iwl_tx_cmd, scratch);
1717
1718 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1719 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1720
1721 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1722 out_meta = &txq->entries[q->write_ptr].meta;
1723
1724 /*
1725 * The second TB (tb1) points to the remainder of the TX command
1726 * and the 802.11 header - dword aligned size
1727 * (This calculation modifies the TX command, so do it before the
1728 * setup of the first TB)
1729 */
1730 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
1731 hdr_len - IWL_HCMD_SCRATCHBUF_SIZE;
1732 tb1_len = ALIGN(len, 4);
1733
1734 /* Tell NIC about any 2-byte padding after MAC header */
1735 if (tb1_len != len)
1736 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1737
1738 /* The first TB points to the scratchbuf data - min_copy bytes */
1739 memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr,
1740 IWL_HCMD_SCRATCHBUF_SIZE);
1741 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
1742 IWL_HCMD_SCRATCHBUF_SIZE, 1);
1743
1744 /* there must be data left over for TB1 or this code must be changed */
1745 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE);
1746
1747 /* map the data for TB1 */
1748 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE;
1749 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
1750 if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
1751 goto out_err;
1752 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, 0);
1753
1754 /*
1755 * Set up TFD's third entry to point directly to remainder
1756 * of skb, if any (802.11 null frames have no payload).
1757 */
1758 tb2_len = skb->len - hdr_len;
1759 if (tb2_len > 0) {
1760 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1761 skb->data + hdr_len,
1762 tb2_len, DMA_TO_DEVICE);
1763 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
1764 iwl_pcie_tfd_unmap(trans, out_meta,
1765 &txq->tfds[q->write_ptr]);
1766 goto out_err;
1767 }
1768 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, 0);
1769 }
1770
1771 /* Set up entry for this TFD in Tx byte-count array */
1772 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1773
1774 trace_iwlwifi_dev_tx(trans->dev, skb,
1775 &txq->tfds[txq->q.write_ptr],
1776 sizeof(struct iwl_tfd),
1777 &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
1778 skb->data + hdr_len, tb2_len);
1779 trace_iwlwifi_dev_tx_data(trans->dev, skb,
1780 skb->data + hdr_len, tb2_len);
1781
1782 wait_write_ptr = ieee80211_has_morefrags(fc);
1783
1784 /* start timer if queue currently empty */
1785 if (txq->need_update && q->read_ptr == q->write_ptr &&
1786 trans_pcie->wd_timeout)
1787 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1788
1789 /* Tell device the write index *just past* this latest filled TFD */
1790 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1791 if (!wait_write_ptr)
1792 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1793
1794 /*
1795 * At this point the frame is "transmitted" successfully
1796 * and we will get a TX status notification eventually.
1797 */
1798 if (iwl_queue_space(q) < q->high_mark) {
1799 if (wait_write_ptr)
1800 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1801 else
1802 iwl_stop_queue(trans, txq);
1803 }
1804 spin_unlock(&txq->lock);
1805 return 0;
1806out_err:
1807 spin_unlock(&txq->lock);
1808 return -1;
1809}
Linux kernel - Deliverables
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