| 1 | /* @file mwifiex_pcie.h |
| 2 | * |
| 3 | * @brief This file contains definitions for PCI-E interface. |
| 4 | * driver. |
| 5 | * |
| 6 | * Copyright (C) 2011-2014, Marvell International Ltd. |
| 7 | * |
| 8 | * This software file (the "File") is distributed by Marvell International |
| 9 | * Ltd. under the terms of the GNU General Public License Version 2, June 1991 |
| 10 | * (the "License"). You may use, redistribute and/or modify this File in |
| 11 | * accordance with the terms and conditions of the License, a copy of which |
| 12 | * is available by writing to the Free Software Foundation, Inc., |
| 13 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the |
| 14 | * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. |
| 15 | * |
| 16 | * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE |
| 17 | * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE |
| 18 | * ARE EXPRESSLY DISCLAIMED. The License provides additional details about |
| 19 | * this warranty disclaimer. |
| 20 | */ |
| 21 | |
| 22 | #ifndef _MWIFIEX_PCIE_H |
| 23 | #define _MWIFIEX_PCIE_H |
| 24 | |
| 25 | #include <linux/pci.h> |
| 26 | #include <linux/interrupt.h> |
| 27 | |
| 28 | #include "decl.h" |
| 29 | #include "main.h" |
| 30 | |
| 31 | #define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin" |
| 32 | #define PCIE8897_DEFAULT_FW_NAME "mrvl/pcie8897_uapsta.bin" |
| 33 | #define PCIE8897_A0_FW_NAME "mrvl/pcie8897_uapsta_a0.bin" |
| 34 | #define PCIE8897_B0_FW_NAME "mrvl/pcie8897_uapsta.bin" |
| 35 | #define PCIE8997_DEFAULT_FW_NAME "mrvl/pcieusb8997_combo_v2.bin" |
| 36 | #define PCIEUART8997_FW_NAME_Z "mrvl/pcieuart8997_combo.bin" |
| 37 | #define PCIEUART8997_FW_NAME_V2 "mrvl/pcieuart8997_combo_v2.bin" |
| 38 | #define PCIEUSB8997_FW_NAME_Z "mrvl/pcieusb8997_combo.bin" |
| 39 | #define PCIEUSB8997_FW_NAME_V2 "mrvl/pcieusb8997_combo_v2.bin" |
| 40 | #define PCIE8997_DEFAULT_WIFIFW_NAME "mrvl/pcie8997_wlan.bin" |
| 41 | |
| 42 | #define PCIE_VENDOR_ID_MARVELL (0x11ab) |
| 43 | #define PCIE_VENDOR_ID_V2_MARVELL (0x1b4b) |
| 44 | #define PCIE_DEVICE_ID_MARVELL_88W8766P (0x2b30) |
| 45 | #define PCIE_DEVICE_ID_MARVELL_88W8897 (0x2b38) |
| 46 | #define PCIE_DEVICE_ID_MARVELL_88W8997 (0x2b42) |
| 47 | |
| 48 | #define PCIE8897_A0 0x1100 |
| 49 | #define PCIE8897_B0 0x1200 |
| 50 | #define PCIE8997_Z 0x0 |
| 51 | #define PCIE8997_V2 0x471 |
| 52 | #define CHIP_VER_PCIEUART 0x3 |
| 53 | |
| 54 | /* Constants for Buffer Descriptor (BD) rings */ |
| 55 | #define MWIFIEX_MAX_TXRX_BD 0x20 |
| 56 | #define MWIFIEX_TXBD_MASK 0x3F |
| 57 | #define MWIFIEX_RXBD_MASK 0x3F |
| 58 | |
| 59 | #define MWIFIEX_MAX_EVT_BD 0x08 |
| 60 | #define MWIFIEX_EVTBD_MASK 0x0f |
| 61 | |
| 62 | /* PCIE INTERNAL REGISTERS */ |
| 63 | #define PCIE_SCRATCH_0_REG 0xC10 |
| 64 | #define PCIE_SCRATCH_1_REG 0xC14 |
| 65 | #define PCIE_CPU_INT_EVENT 0xC18 |
| 66 | #define PCIE_CPU_INT_STATUS 0xC1C |
| 67 | #define PCIE_HOST_INT_STATUS 0xC30 |
| 68 | #define PCIE_HOST_INT_MASK 0xC34 |
| 69 | #define PCIE_HOST_INT_STATUS_MASK 0xC3C |
| 70 | #define PCIE_SCRATCH_2_REG 0xC40 |
| 71 | #define PCIE_SCRATCH_3_REG 0xC44 |
| 72 | #define PCIE_SCRATCH_4_REG 0xCD0 |
| 73 | #define PCIE_SCRATCH_5_REG 0xCD4 |
| 74 | #define PCIE_SCRATCH_6_REG 0xCD8 |
| 75 | #define PCIE_SCRATCH_7_REG 0xCDC |
| 76 | #define PCIE_SCRATCH_8_REG 0xCE0 |
| 77 | #define PCIE_SCRATCH_9_REG 0xCE4 |
| 78 | #define PCIE_SCRATCH_10_REG 0xCE8 |
| 79 | #define PCIE_SCRATCH_11_REG 0xCEC |
| 80 | #define PCIE_SCRATCH_12_REG 0xCF0 |
| 81 | #define PCIE_SCRATCH_13_REG 0xCF8 |
| 82 | #define PCIE_SCRATCH_14_REG 0xCFC |
| 83 | #define PCIE_RD_DATA_PTR_Q0_Q1 0xC08C |
| 84 | #define PCIE_WR_DATA_PTR_Q0_Q1 0xC05C |
| 85 | |
| 86 | #define CPU_INTR_DNLD_RDY BIT(0) |
| 87 | #define CPU_INTR_DOOR_BELL BIT(1) |
| 88 | #define CPU_INTR_SLEEP_CFM_DONE BIT(2) |
| 89 | #define CPU_INTR_RESET BIT(3) |
| 90 | #define CPU_INTR_EVENT_DONE BIT(5) |
| 91 | |
| 92 | #define HOST_INTR_DNLD_DONE BIT(0) |
| 93 | #define HOST_INTR_UPLD_RDY BIT(1) |
| 94 | #define HOST_INTR_CMD_DONE BIT(2) |
| 95 | #define HOST_INTR_EVENT_RDY BIT(3) |
| 96 | #define HOST_INTR_MASK (HOST_INTR_DNLD_DONE | \ |
| 97 | HOST_INTR_UPLD_RDY | \ |
| 98 | HOST_INTR_CMD_DONE | \ |
| 99 | HOST_INTR_EVENT_RDY) |
| 100 | |
| 101 | #define MWIFIEX_BD_FLAG_ROLLOVER_IND BIT(7) |
| 102 | #define MWIFIEX_BD_FLAG_FIRST_DESC BIT(0) |
| 103 | #define MWIFIEX_BD_FLAG_LAST_DESC BIT(1) |
| 104 | #define MWIFIEX_BD_FLAG_SOP BIT(0) |
| 105 | #define MWIFIEX_BD_FLAG_EOP BIT(1) |
| 106 | #define MWIFIEX_BD_FLAG_XS_SOP BIT(2) |
| 107 | #define MWIFIEX_BD_FLAG_XS_EOP BIT(3) |
| 108 | #define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND BIT(7) |
| 109 | #define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND BIT(10) |
| 110 | #define MWIFIEX_BD_FLAG_TX_START_PTR BIT(16) |
| 111 | #define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND BIT(26) |
| 112 | |
| 113 | /* Max retry number of command write */ |
| 114 | #define MAX_WRITE_IOMEM_RETRY 2 |
| 115 | /* Define PCIE block size for firmware download */ |
| 116 | #define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD 256 |
| 117 | /* FW awake cookie after FW ready */ |
| 118 | #define FW_AWAKE_COOKIE (0xAA55AA55) |
| 119 | #define MWIFIEX_DEF_SLEEP_COOKIE 0xBEEFBEEF |
| 120 | #define MWIFIEX_MAX_DELAY_COUNT 100 |
| 121 | |
| 122 | struct mwifiex_pcie_card_reg { |
| 123 | u16 cmd_addr_lo; |
| 124 | u16 cmd_addr_hi; |
| 125 | u16 fw_status; |
| 126 | u16 cmd_size; |
| 127 | u16 cmdrsp_addr_lo; |
| 128 | u16 cmdrsp_addr_hi; |
| 129 | u16 tx_rdptr; |
| 130 | u16 tx_wrptr; |
| 131 | u16 rx_rdptr; |
| 132 | u16 rx_wrptr; |
| 133 | u16 evt_rdptr; |
| 134 | u16 evt_wrptr; |
| 135 | u16 drv_rdy; |
| 136 | u16 tx_start_ptr; |
| 137 | u32 tx_mask; |
| 138 | u32 tx_wrap_mask; |
| 139 | u32 rx_mask; |
| 140 | u32 rx_wrap_mask; |
| 141 | u32 tx_rollover_ind; |
| 142 | u32 rx_rollover_ind; |
| 143 | u32 evt_rollover_ind; |
| 144 | u8 ring_flag_sop; |
| 145 | u8 ring_flag_eop; |
| 146 | u8 ring_flag_xs_sop; |
| 147 | u8 ring_flag_xs_eop; |
| 148 | u32 ring_tx_start_ptr; |
| 149 | u8 pfu_enabled; |
| 150 | u8 sleep_cookie; |
| 151 | u16 fw_dump_ctrl; |
| 152 | u16 fw_dump_start; |
| 153 | u16 fw_dump_end; |
| 154 | u8 fw_dump_host_ready; |
| 155 | u8 fw_dump_read_done; |
| 156 | u8 msix_support; |
| 157 | }; |
| 158 | |
| 159 | static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = { |
| 160 | .cmd_addr_lo = PCIE_SCRATCH_0_REG, |
| 161 | .cmd_addr_hi = PCIE_SCRATCH_1_REG, |
| 162 | .cmd_size = PCIE_SCRATCH_2_REG, |
| 163 | .fw_status = PCIE_SCRATCH_3_REG, |
| 164 | .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, |
| 165 | .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, |
| 166 | .tx_rdptr = PCIE_SCRATCH_6_REG, |
| 167 | .tx_wrptr = PCIE_SCRATCH_7_REG, |
| 168 | .rx_rdptr = PCIE_SCRATCH_8_REG, |
| 169 | .rx_wrptr = PCIE_SCRATCH_9_REG, |
| 170 | .evt_rdptr = PCIE_SCRATCH_10_REG, |
| 171 | .evt_wrptr = PCIE_SCRATCH_11_REG, |
| 172 | .drv_rdy = PCIE_SCRATCH_12_REG, |
| 173 | .tx_start_ptr = 0, |
| 174 | .tx_mask = MWIFIEX_TXBD_MASK, |
| 175 | .tx_wrap_mask = 0, |
| 176 | .rx_mask = MWIFIEX_RXBD_MASK, |
| 177 | .rx_wrap_mask = 0, |
| 178 | .tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, |
| 179 | .rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, |
| 180 | .evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, |
| 181 | .ring_flag_sop = 0, |
| 182 | .ring_flag_eop = 0, |
| 183 | .ring_flag_xs_sop = 0, |
| 184 | .ring_flag_xs_eop = 0, |
| 185 | .ring_tx_start_ptr = 0, |
| 186 | .pfu_enabled = 0, |
| 187 | .sleep_cookie = 1, |
| 188 | .msix_support = 0, |
| 189 | }; |
| 190 | |
| 191 | static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = { |
| 192 | .cmd_addr_lo = PCIE_SCRATCH_0_REG, |
| 193 | .cmd_addr_hi = PCIE_SCRATCH_1_REG, |
| 194 | .cmd_size = PCIE_SCRATCH_2_REG, |
| 195 | .fw_status = PCIE_SCRATCH_3_REG, |
| 196 | .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, |
| 197 | .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, |
| 198 | .tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1, |
| 199 | .tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1, |
| 200 | .rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1, |
| 201 | .rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1, |
| 202 | .evt_rdptr = PCIE_SCRATCH_10_REG, |
| 203 | .evt_wrptr = PCIE_SCRATCH_11_REG, |
| 204 | .drv_rdy = PCIE_SCRATCH_12_REG, |
| 205 | .tx_start_ptr = 16, |
| 206 | .tx_mask = 0x03FF0000, |
| 207 | .tx_wrap_mask = 0x07FF0000, |
| 208 | .rx_mask = 0x000003FF, |
| 209 | .rx_wrap_mask = 0x000007FF, |
| 210 | .tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND, |
| 211 | .rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND, |
| 212 | .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND, |
| 213 | .ring_flag_sop = MWIFIEX_BD_FLAG_SOP, |
| 214 | .ring_flag_eop = MWIFIEX_BD_FLAG_EOP, |
| 215 | .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP, |
| 216 | .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP, |
| 217 | .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR, |
| 218 | .pfu_enabled = 1, |
| 219 | .sleep_cookie = 0, |
| 220 | .fw_dump_ctrl = 0xcf4, |
| 221 | .fw_dump_start = 0xcf8, |
| 222 | .fw_dump_end = 0xcff, |
| 223 | .fw_dump_host_ready = 0xee, |
| 224 | .fw_dump_read_done = 0xfe, |
| 225 | .msix_support = 0, |
| 226 | }; |
| 227 | |
| 228 | static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = { |
| 229 | .cmd_addr_lo = PCIE_SCRATCH_0_REG, |
| 230 | .cmd_addr_hi = PCIE_SCRATCH_1_REG, |
| 231 | .cmd_size = PCIE_SCRATCH_2_REG, |
| 232 | .fw_status = PCIE_SCRATCH_3_REG, |
| 233 | .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, |
| 234 | .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, |
| 235 | .tx_rdptr = 0xC1A4, |
| 236 | .tx_wrptr = 0xC174, |
| 237 | .rx_rdptr = 0xC174, |
| 238 | .rx_wrptr = 0xC1A4, |
| 239 | .evt_rdptr = PCIE_SCRATCH_10_REG, |
| 240 | .evt_wrptr = PCIE_SCRATCH_11_REG, |
| 241 | .drv_rdy = PCIE_SCRATCH_12_REG, |
| 242 | .tx_start_ptr = 16, |
| 243 | .tx_mask = 0x0FFF0000, |
| 244 | .tx_wrap_mask = 0x1FFF0000, |
| 245 | .rx_mask = 0x00000FFF, |
| 246 | .rx_wrap_mask = 0x00001FFF, |
| 247 | .tx_rollover_ind = BIT(28), |
| 248 | .rx_rollover_ind = BIT(12), |
| 249 | .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND, |
| 250 | .ring_flag_sop = MWIFIEX_BD_FLAG_SOP, |
| 251 | .ring_flag_eop = MWIFIEX_BD_FLAG_EOP, |
| 252 | .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP, |
| 253 | .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP, |
| 254 | .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR, |
| 255 | .pfu_enabled = 1, |
| 256 | .sleep_cookie = 0, |
| 257 | .fw_dump_ctrl = 0xcf4, |
| 258 | .fw_dump_start = 0xcf8, |
| 259 | .fw_dump_end = 0xcff, |
| 260 | .fw_dump_host_ready = 0xcc, |
| 261 | .fw_dump_read_done = 0xdd, |
| 262 | .msix_support = 0, |
| 263 | }; |
| 264 | |
| 265 | static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = { |
| 266 | {"ITCM", NULL, 0, 0xF0}, |
| 267 | {"DTCM", NULL, 0, 0xF1}, |
| 268 | {"SQRAM", NULL, 0, 0xF2}, |
| 269 | {"IRAM", NULL, 0, 0xF3}, |
| 270 | {"APU", NULL, 0, 0xF4}, |
| 271 | {"CIU", NULL, 0, 0xF5}, |
| 272 | {"ICU", NULL, 0, 0xF6}, |
| 273 | {"MAC", NULL, 0, 0xF7}, |
| 274 | }; |
| 275 | |
| 276 | static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = { |
| 277 | {"DUMP", NULL, 0, 0xDD}, |
| 278 | }; |
| 279 | |
| 280 | struct mwifiex_pcie_device { |
| 281 | const struct mwifiex_pcie_card_reg *reg; |
| 282 | u16 blksz_fw_dl; |
| 283 | u16 tx_buf_size; |
| 284 | bool can_dump_fw; |
| 285 | struct memory_type_mapping *mem_type_mapping_tbl; |
| 286 | u8 num_mem_types; |
| 287 | bool can_ext_scan; |
| 288 | }; |
| 289 | |
| 290 | static const struct mwifiex_pcie_device mwifiex_pcie8766 = { |
| 291 | .reg = &mwifiex_reg_8766, |
| 292 | .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, |
| 293 | .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, |
| 294 | .can_dump_fw = false, |
| 295 | .can_ext_scan = true, |
| 296 | }; |
| 297 | |
| 298 | static const struct mwifiex_pcie_device mwifiex_pcie8897 = { |
| 299 | .reg = &mwifiex_reg_8897, |
| 300 | .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, |
| 301 | .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, |
| 302 | .can_dump_fw = true, |
| 303 | .mem_type_mapping_tbl = mem_type_mapping_tbl_w8897, |
| 304 | .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897), |
| 305 | .can_ext_scan = true, |
| 306 | }; |
| 307 | |
| 308 | static const struct mwifiex_pcie_device mwifiex_pcie8997 = { |
| 309 | .reg = &mwifiex_reg_8997, |
| 310 | .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, |
| 311 | .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, |
| 312 | .can_dump_fw = true, |
| 313 | .mem_type_mapping_tbl = mem_type_mapping_tbl_w8997, |
| 314 | .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997), |
| 315 | .can_ext_scan = true, |
| 316 | }; |
| 317 | |
| 318 | struct mwifiex_evt_buf_desc { |
| 319 | u64 paddr; |
| 320 | u16 len; |
| 321 | u16 flags; |
| 322 | } __packed; |
| 323 | |
| 324 | struct mwifiex_pcie_buf_desc { |
| 325 | u64 paddr; |
| 326 | u16 len; |
| 327 | u16 flags; |
| 328 | } __packed; |
| 329 | |
| 330 | struct mwifiex_pfu_buf_desc { |
| 331 | u16 flags; |
| 332 | u16 offset; |
| 333 | u16 frag_len; |
| 334 | u16 len; |
| 335 | u64 paddr; |
| 336 | u32 reserved; |
| 337 | } __packed; |
| 338 | |
| 339 | #define MWIFIEX_NUM_MSIX_VECTORS 4 |
| 340 | |
| 341 | struct mwifiex_msix_context { |
| 342 | struct pci_dev *dev; |
| 343 | u16 msg_id; |
| 344 | }; |
| 345 | |
| 346 | struct pcie_service_card { |
| 347 | struct pci_dev *dev; |
| 348 | struct mwifiex_adapter *adapter; |
| 349 | struct mwifiex_pcie_device pcie; |
| 350 | |
| 351 | u8 txbd_flush; |
| 352 | u32 txbd_wrptr; |
| 353 | u32 txbd_rdptr; |
| 354 | u32 txbd_ring_size; |
| 355 | u8 *txbd_ring_vbase; |
| 356 | dma_addr_t txbd_ring_pbase; |
| 357 | void *txbd_ring[MWIFIEX_MAX_TXRX_BD]; |
| 358 | struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD]; |
| 359 | |
| 360 | u32 rxbd_wrptr; |
| 361 | u32 rxbd_rdptr; |
| 362 | u32 rxbd_ring_size; |
| 363 | u8 *rxbd_ring_vbase; |
| 364 | dma_addr_t rxbd_ring_pbase; |
| 365 | void *rxbd_ring[MWIFIEX_MAX_TXRX_BD]; |
| 366 | struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD]; |
| 367 | |
| 368 | u32 evtbd_wrptr; |
| 369 | u32 evtbd_rdptr; |
| 370 | u32 evtbd_ring_size; |
| 371 | u8 *evtbd_ring_vbase; |
| 372 | dma_addr_t evtbd_ring_pbase; |
| 373 | void *evtbd_ring[MWIFIEX_MAX_EVT_BD]; |
| 374 | struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD]; |
| 375 | |
| 376 | struct sk_buff *cmd_buf; |
| 377 | struct sk_buff *cmdrsp_buf; |
| 378 | u8 *sleep_cookie_vbase; |
| 379 | dma_addr_t sleep_cookie_pbase; |
| 380 | void __iomem *pci_mmap; |
| 381 | void __iomem *pci_mmap1; |
| 382 | int msi_enable; |
| 383 | int msix_enable; |
| 384 | #ifdef CONFIG_PCI |
| 385 | struct msix_entry msix_entries[MWIFIEX_NUM_MSIX_VECTORS]; |
| 386 | #endif |
| 387 | struct mwifiex_msix_context msix_ctx[MWIFIEX_NUM_MSIX_VECTORS]; |
| 388 | struct mwifiex_msix_context share_irq_ctx; |
| 389 | }; |
| 390 | |
| 391 | static inline int |
| 392 | mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr) |
| 393 | { |
| 394 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
| 395 | |
| 396 | switch (card->dev->device) { |
| 397 | case PCIE_DEVICE_ID_MARVELL_88W8766P: |
| 398 | if (((card->txbd_wrptr & reg->tx_mask) == |
| 399 | (rdptr & reg->tx_mask)) && |
| 400 | ((card->txbd_wrptr & reg->tx_rollover_ind) != |
| 401 | (rdptr & reg->tx_rollover_ind))) |
| 402 | return 1; |
| 403 | break; |
| 404 | case PCIE_DEVICE_ID_MARVELL_88W8897: |
| 405 | case PCIE_DEVICE_ID_MARVELL_88W8997: |
| 406 | if (((card->txbd_wrptr & reg->tx_mask) == |
| 407 | (rdptr & reg->tx_mask)) && |
| 408 | ((card->txbd_wrptr & reg->tx_rollover_ind) == |
| 409 | (rdptr & reg->tx_rollover_ind))) |
| 410 | return 1; |
| 411 | break; |
| 412 | } |
| 413 | |
| 414 | return 0; |
| 415 | } |
| 416 | |
| 417 | static inline int |
| 418 | mwifiex_pcie_txbd_not_full(struct pcie_service_card *card) |
| 419 | { |
| 420 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
| 421 | |
| 422 | switch (card->dev->device) { |
| 423 | case PCIE_DEVICE_ID_MARVELL_88W8766P: |
| 424 | if (((card->txbd_wrptr & reg->tx_mask) != |
| 425 | (card->txbd_rdptr & reg->tx_mask)) || |
| 426 | ((card->txbd_wrptr & reg->tx_rollover_ind) != |
| 427 | (card->txbd_rdptr & reg->tx_rollover_ind))) |
| 428 | return 1; |
| 429 | break; |
| 430 | case PCIE_DEVICE_ID_MARVELL_88W8897: |
| 431 | case PCIE_DEVICE_ID_MARVELL_88W8997: |
| 432 | if (((card->txbd_wrptr & reg->tx_mask) != |
| 433 | (card->txbd_rdptr & reg->tx_mask)) || |
| 434 | ((card->txbd_wrptr & reg->tx_rollover_ind) == |
| 435 | (card->txbd_rdptr & reg->tx_rollover_ind))) |
| 436 | return 1; |
| 437 | break; |
| 438 | } |
| 439 | |
| 440 | return 0; |
| 441 | } |
| 442 | |
| 443 | #endif /* _MWIFIEX_PCIE_H */ |