| 1 | /* |
| 2 | Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com> |
| 3 | Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> |
| 4 | Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> |
| 5 | Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> |
| 6 | Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> |
| 7 | Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> |
| 8 | Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> |
| 9 | Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com> |
| 10 | <http://rt2x00.serialmonkey.com> |
| 11 | |
| 12 | This program is free software; you can redistribute it and/or modify |
| 13 | it under the terms of the GNU General Public License as published by |
| 14 | the Free Software Foundation; either version 2 of the License, or |
| 15 | (at your option) any later version. |
| 16 | |
| 17 | This program is distributed in the hope that it will be useful, |
| 18 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | GNU General Public License for more details. |
| 21 | |
| 22 | You should have received a copy of the GNU General Public License |
| 23 | along with this program; if not, write to the |
| 24 | Free Software Foundation, Inc., |
| 25 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 26 | */ |
| 27 | |
| 28 | /* |
| 29 | Module: rt2800pci |
| 30 | Abstract: rt2800pci device specific routines. |
| 31 | Supported chipsets: RT2800E & RT2800ED. |
| 32 | */ |
| 33 | |
| 34 | #include <linux/delay.h> |
| 35 | #include <linux/etherdevice.h> |
| 36 | #include <linux/init.h> |
| 37 | #include <linux/kernel.h> |
| 38 | #include <linux/module.h> |
| 39 | #include <linux/pci.h> |
| 40 | #include <linux/platform_device.h> |
| 41 | #include <linux/eeprom_93cx6.h> |
| 42 | |
| 43 | #include "rt2x00.h" |
| 44 | #include "rt2x00mmio.h" |
| 45 | #include "rt2x00pci.h" |
| 46 | #include "rt2x00soc.h" |
| 47 | #include "rt2800lib.h" |
| 48 | #include "rt2800mmio.h" |
| 49 | #include "rt2800.h" |
| 50 | #include "rt2800pci.h" |
| 51 | |
| 52 | /* |
| 53 | * Allow hardware encryption to be disabled. |
| 54 | */ |
| 55 | static bool modparam_nohwcrypt = false; |
| 56 | module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); |
| 57 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); |
| 58 | |
| 59 | static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev) |
| 60 | { |
| 61 | return modparam_nohwcrypt; |
| 62 | } |
| 63 | |
| 64 | static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token) |
| 65 | { |
| 66 | unsigned int i; |
| 67 | u32 reg; |
| 68 | |
| 69 | /* |
| 70 | * SOC devices don't support MCU requests. |
| 71 | */ |
| 72 | if (rt2x00_is_soc(rt2x00dev)) |
| 73 | return; |
| 74 | |
| 75 | for (i = 0; i < 200; i++) { |
| 76 | rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID, ®); |
| 77 | |
| 78 | if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) || |
| 79 | (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) || |
| 80 | (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) || |
| 81 | (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token)) |
| 82 | break; |
| 83 | |
| 84 | udelay(REGISTER_BUSY_DELAY); |
| 85 | } |
| 86 | |
| 87 | if (i == 200) |
| 88 | rt2x00_err(rt2x00dev, "MCU request failed, no response from hardware\n"); |
| 89 | |
| 90 | rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); |
| 91 | rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); |
| 92 | } |
| 93 | |
| 94 | #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X) |
| 95 | static int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev) |
| 96 | { |
| 97 | void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE); |
| 98 | |
| 99 | if (!base_addr) |
| 100 | return -ENOMEM; |
| 101 | |
| 102 | memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE); |
| 103 | |
| 104 | iounmap(base_addr); |
| 105 | return 0; |
| 106 | } |
| 107 | #else |
| 108 | static inline int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev) |
| 109 | { |
| 110 | return -ENOMEM; |
| 111 | } |
| 112 | #endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */ |
| 113 | |
| 114 | #ifdef CONFIG_PCI |
| 115 | static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom) |
| 116 | { |
| 117 | struct rt2x00_dev *rt2x00dev = eeprom->data; |
| 118 | u32 reg; |
| 119 | |
| 120 | rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, ®); |
| 121 | |
| 122 | eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); |
| 123 | eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); |
| 124 | eeprom->reg_data_clock = |
| 125 | !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK); |
| 126 | eeprom->reg_chip_select = |
| 127 | !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT); |
| 128 | } |
| 129 | |
| 130 | static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom) |
| 131 | { |
| 132 | struct rt2x00_dev *rt2x00dev = eeprom->data; |
| 133 | u32 reg = 0; |
| 134 | |
| 135 | rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in); |
| 136 | rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out); |
| 137 | rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, |
| 138 | !!eeprom->reg_data_clock); |
| 139 | rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT, |
| 140 | !!eeprom->reg_chip_select); |
| 141 | |
| 142 | rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg); |
| 143 | } |
| 144 | |
| 145 | static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev) |
| 146 | { |
| 147 | struct eeprom_93cx6 eeprom; |
| 148 | u32 reg; |
| 149 | |
| 150 | rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, ®); |
| 151 | |
| 152 | eeprom.data = rt2x00dev; |
| 153 | eeprom.register_read = rt2800pci_eepromregister_read; |
| 154 | eeprom.register_write = rt2800pci_eepromregister_write; |
| 155 | switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE)) |
| 156 | { |
| 157 | case 0: |
| 158 | eeprom.width = PCI_EEPROM_WIDTH_93C46; |
| 159 | break; |
| 160 | case 1: |
| 161 | eeprom.width = PCI_EEPROM_WIDTH_93C66; |
| 162 | break; |
| 163 | default: |
| 164 | eeprom.width = PCI_EEPROM_WIDTH_93C86; |
| 165 | break; |
| 166 | } |
| 167 | eeprom.reg_data_in = 0; |
| 168 | eeprom.reg_data_out = 0; |
| 169 | eeprom.reg_data_clock = 0; |
| 170 | eeprom.reg_chip_select = 0; |
| 171 | |
| 172 | eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, |
| 173 | EEPROM_SIZE / sizeof(u16)); |
| 174 | |
| 175 | return 0; |
| 176 | } |
| 177 | |
| 178 | static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev) |
| 179 | { |
| 180 | return rt2800_efuse_detect(rt2x00dev); |
| 181 | } |
| 182 | |
| 183 | static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) |
| 184 | { |
| 185 | return rt2800_read_eeprom_efuse(rt2x00dev); |
| 186 | } |
| 187 | #else |
| 188 | static inline int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev) |
| 189 | { |
| 190 | return -EOPNOTSUPP; |
| 191 | } |
| 192 | |
| 193 | static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev) |
| 194 | { |
| 195 | return 0; |
| 196 | } |
| 197 | |
| 198 | static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) |
| 199 | { |
| 200 | return -EOPNOTSUPP; |
| 201 | } |
| 202 | #endif /* CONFIG_PCI */ |
| 203 | |
| 204 | /* |
| 205 | * Firmware functions |
| 206 | */ |
| 207 | static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev) |
| 208 | { |
| 209 | /* |
| 210 | * Chip rt3290 use specific 4KB firmware named rt3290.bin. |
| 211 | */ |
| 212 | if (rt2x00_rt(rt2x00dev, RT3290)) |
| 213 | return FIRMWARE_RT3290; |
| 214 | else |
| 215 | return FIRMWARE_RT2860; |
| 216 | } |
| 217 | |
| 218 | static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev, |
| 219 | const u8 *data, const size_t len) |
| 220 | { |
| 221 | u32 reg; |
| 222 | |
| 223 | /* |
| 224 | * enable Host program ram write selection |
| 225 | */ |
| 226 | reg = 0; |
| 227 | rt2x00_set_field32(®, PBF_SYS_CTRL_HOST_RAM_WRITE, 1); |
| 228 | rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, reg); |
| 229 | |
| 230 | /* |
| 231 | * Write firmware to device. |
| 232 | */ |
| 233 | rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, |
| 234 | data, len); |
| 235 | |
| 236 | rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000); |
| 237 | rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001); |
| 238 | |
| 239 | rt2x00mmio_register_write(rt2x00dev, H2M_BBP_AGENT, 0); |
| 240 | rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); |
| 241 | |
| 242 | return 0; |
| 243 | } |
| 244 | |
| 245 | /* |
| 246 | * Initialization functions. |
| 247 | */ |
| 248 | static bool rt2800pci_get_entry_state(struct queue_entry *entry) |
| 249 | { |
| 250 | struct queue_entry_priv_mmio *entry_priv = entry->priv_data; |
| 251 | u32 word; |
| 252 | |
| 253 | if (entry->queue->qid == QID_RX) { |
| 254 | rt2x00_desc_read(entry_priv->desc, 1, &word); |
| 255 | |
| 256 | return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE)); |
| 257 | } else { |
| 258 | rt2x00_desc_read(entry_priv->desc, 1, &word); |
| 259 | |
| 260 | return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE)); |
| 261 | } |
| 262 | } |
| 263 | |
| 264 | static void rt2800pci_clear_entry(struct queue_entry *entry) |
| 265 | { |
| 266 | struct queue_entry_priv_mmio *entry_priv = entry->priv_data; |
| 267 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
| 268 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
| 269 | u32 word; |
| 270 | |
| 271 | if (entry->queue->qid == QID_RX) { |
| 272 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
| 273 | rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma); |
| 274 | rt2x00_desc_write(entry_priv->desc, 0, word); |
| 275 | |
| 276 | rt2x00_desc_read(entry_priv->desc, 1, &word); |
| 277 | rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0); |
| 278 | rt2x00_desc_write(entry_priv->desc, 1, word); |
| 279 | |
| 280 | /* |
| 281 | * Set RX IDX in register to inform hardware that we have |
| 282 | * handled this entry and it is available for reuse again. |
| 283 | */ |
| 284 | rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX, |
| 285 | entry->entry_idx); |
| 286 | } else { |
| 287 | rt2x00_desc_read(entry_priv->desc, 1, &word); |
| 288 | rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1); |
| 289 | rt2x00_desc_write(entry_priv->desc, 1, word); |
| 290 | } |
| 291 | } |
| 292 | |
| 293 | static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev) |
| 294 | { |
| 295 | struct queue_entry_priv_mmio *entry_priv; |
| 296 | |
| 297 | /* |
| 298 | * Initialize registers. |
| 299 | */ |
| 300 | entry_priv = rt2x00dev->tx[0].entries[0].priv_data; |
| 301 | rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR0, |
| 302 | entry_priv->desc_dma); |
| 303 | rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT0, |
| 304 | rt2x00dev->tx[0].limit); |
| 305 | rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX0, 0); |
| 306 | rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX0, 0); |
| 307 | |
| 308 | entry_priv = rt2x00dev->tx[1].entries[0].priv_data; |
| 309 | rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR1, |
| 310 | entry_priv->desc_dma); |
| 311 | rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT1, |
| 312 | rt2x00dev->tx[1].limit); |
| 313 | rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX1, 0); |
| 314 | rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX1, 0); |
| 315 | |
| 316 | entry_priv = rt2x00dev->tx[2].entries[0].priv_data; |
| 317 | rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR2, |
| 318 | entry_priv->desc_dma); |
| 319 | rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT2, |
| 320 | rt2x00dev->tx[2].limit); |
| 321 | rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX2, 0); |
| 322 | rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX2, 0); |
| 323 | |
| 324 | entry_priv = rt2x00dev->tx[3].entries[0].priv_data; |
| 325 | rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR3, |
| 326 | entry_priv->desc_dma); |
| 327 | rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT3, |
| 328 | rt2x00dev->tx[3].limit); |
| 329 | rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX3, 0); |
| 330 | rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX3, 0); |
| 331 | |
| 332 | rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR4, 0); |
| 333 | rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT4, 0); |
| 334 | rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX4, 0); |
| 335 | rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX4, 0); |
| 336 | |
| 337 | rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR5, 0); |
| 338 | rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT5, 0); |
| 339 | rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX5, 0); |
| 340 | rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX5, 0); |
| 341 | |
| 342 | entry_priv = rt2x00dev->rx->entries[0].priv_data; |
| 343 | rt2x00mmio_register_write(rt2x00dev, RX_BASE_PTR, |
| 344 | entry_priv->desc_dma); |
| 345 | rt2x00mmio_register_write(rt2x00dev, RX_MAX_CNT, |
| 346 | rt2x00dev->rx[0].limit); |
| 347 | rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX, |
| 348 | rt2x00dev->rx[0].limit - 1); |
| 349 | rt2x00mmio_register_write(rt2x00dev, RX_DRX_IDX, 0); |
| 350 | |
| 351 | rt2800_disable_wpdma(rt2x00dev); |
| 352 | |
| 353 | rt2x00mmio_register_write(rt2x00dev, DELAY_INT_CFG, 0); |
| 354 | |
| 355 | return 0; |
| 356 | } |
| 357 | |
| 358 | /* |
| 359 | * Device state switch handlers. |
| 360 | */ |
| 361 | static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev) |
| 362 | { |
| 363 | u32 reg; |
| 364 | |
| 365 | /* |
| 366 | * Reset DMA indexes |
| 367 | */ |
| 368 | rt2x00mmio_register_read(rt2x00dev, WPDMA_RST_IDX, ®); |
| 369 | rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1); |
| 370 | rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1); |
| 371 | rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1); |
| 372 | rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, 1); |
| 373 | rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1); |
| 374 | rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1); |
| 375 | rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1); |
| 376 | rt2x00mmio_register_write(rt2x00dev, WPDMA_RST_IDX, reg); |
| 377 | |
| 378 | rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f); |
| 379 | rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00); |
| 380 | |
| 381 | if (rt2x00_is_pcie(rt2x00dev) && |
| 382 | (rt2x00_rt(rt2x00dev, RT3090) || |
| 383 | rt2x00_rt(rt2x00dev, RT3390) || |
| 384 | rt2x00_rt(rt2x00dev, RT3572) || |
| 385 | rt2x00_rt(rt2x00dev, RT3593) || |
| 386 | rt2x00_rt(rt2x00dev, RT5390) || |
| 387 | rt2x00_rt(rt2x00dev, RT5392) || |
| 388 | rt2x00_rt(rt2x00dev, RT5592))) { |
| 389 | rt2x00mmio_register_read(rt2x00dev, AUX_CTRL, ®); |
| 390 | rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); |
| 391 | rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); |
| 392 | rt2x00mmio_register_write(rt2x00dev, AUX_CTRL, reg); |
| 393 | } |
| 394 | |
| 395 | rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); |
| 396 | |
| 397 | reg = 0; |
| 398 | rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1); |
| 399 | rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1); |
| 400 | rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg); |
| 401 | |
| 402 | rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); |
| 403 | |
| 404 | return 0; |
| 405 | } |
| 406 | |
| 407 | static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev) |
| 408 | { |
| 409 | int retval; |
| 410 | |
| 411 | /* Wait for DMA, ignore error until we initialize queues. */ |
| 412 | rt2800_wait_wpdma_ready(rt2x00dev); |
| 413 | |
| 414 | if (unlikely(rt2800pci_init_queues(rt2x00dev))) |
| 415 | return -EIO; |
| 416 | |
| 417 | retval = rt2800_enable_radio(rt2x00dev); |
| 418 | if (retval) |
| 419 | return retval; |
| 420 | |
| 421 | /* After resume MCU_BOOT_SIGNAL will trash these. */ |
| 422 | rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); |
| 423 | rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); |
| 424 | |
| 425 | rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02); |
| 426 | rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF); |
| 427 | |
| 428 | rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0); |
| 429 | rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP); |
| 430 | |
| 431 | return retval; |
| 432 | } |
| 433 | |
| 434 | static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev) |
| 435 | { |
| 436 | if (rt2x00_is_soc(rt2x00dev)) { |
| 437 | rt2800_disable_radio(rt2x00dev); |
| 438 | rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0); |
| 439 | rt2x00mmio_register_write(rt2x00dev, TX_PIN_CFG, 0); |
| 440 | } |
| 441 | } |
| 442 | |
| 443 | static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev, |
| 444 | enum dev_state state) |
| 445 | { |
| 446 | if (state == STATE_AWAKE) { |
| 447 | rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, |
| 448 | 0, 0x02); |
| 449 | rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP); |
| 450 | } else if (state == STATE_SLEEP) { |
| 451 | rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, |
| 452 | 0xffffffff); |
| 453 | rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, |
| 454 | 0xffffffff); |
| 455 | rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP, |
| 456 | 0xff, 0x01); |
| 457 | } |
| 458 | |
| 459 | return 0; |
| 460 | } |
| 461 | |
| 462 | static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev, |
| 463 | enum dev_state state) |
| 464 | { |
| 465 | int retval = 0; |
| 466 | |
| 467 | switch (state) { |
| 468 | case STATE_RADIO_ON: |
| 469 | retval = rt2800pci_enable_radio(rt2x00dev); |
| 470 | break; |
| 471 | case STATE_RADIO_OFF: |
| 472 | /* |
| 473 | * After the radio has been disabled, the device should |
| 474 | * be put to sleep for powersaving. |
| 475 | */ |
| 476 | rt2800pci_disable_radio(rt2x00dev); |
| 477 | rt2800pci_set_state(rt2x00dev, STATE_SLEEP); |
| 478 | break; |
| 479 | case STATE_RADIO_IRQ_ON: |
| 480 | case STATE_RADIO_IRQ_OFF: |
| 481 | rt2800mmio_toggle_irq(rt2x00dev, state); |
| 482 | break; |
| 483 | case STATE_DEEP_SLEEP: |
| 484 | case STATE_SLEEP: |
| 485 | case STATE_STANDBY: |
| 486 | case STATE_AWAKE: |
| 487 | retval = rt2800pci_set_state(rt2x00dev, state); |
| 488 | break; |
| 489 | default: |
| 490 | retval = -ENOTSUPP; |
| 491 | break; |
| 492 | } |
| 493 | |
| 494 | if (unlikely(retval)) |
| 495 | rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n", |
| 496 | state, retval); |
| 497 | |
| 498 | return retval; |
| 499 | } |
| 500 | |
| 501 | /* |
| 502 | * Device probe functions. |
| 503 | */ |
| 504 | static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev) |
| 505 | { |
| 506 | int retval; |
| 507 | |
| 508 | if (rt2x00_is_soc(rt2x00dev)) |
| 509 | retval = rt2800pci_read_eeprom_soc(rt2x00dev); |
| 510 | else if (rt2800pci_efuse_detect(rt2x00dev)) |
| 511 | retval = rt2800pci_read_eeprom_efuse(rt2x00dev); |
| 512 | else |
| 513 | retval = rt2800pci_read_eeprom_pci(rt2x00dev); |
| 514 | |
| 515 | return retval; |
| 516 | } |
| 517 | |
| 518 | static const struct ieee80211_ops rt2800pci_mac80211_ops = { |
| 519 | .tx = rt2x00mac_tx, |
| 520 | .start = rt2x00mac_start, |
| 521 | .stop = rt2x00mac_stop, |
| 522 | .add_interface = rt2x00mac_add_interface, |
| 523 | .remove_interface = rt2x00mac_remove_interface, |
| 524 | .config = rt2x00mac_config, |
| 525 | .configure_filter = rt2x00mac_configure_filter, |
| 526 | .set_key = rt2x00mac_set_key, |
| 527 | .sw_scan_start = rt2x00mac_sw_scan_start, |
| 528 | .sw_scan_complete = rt2x00mac_sw_scan_complete, |
| 529 | .get_stats = rt2x00mac_get_stats, |
| 530 | .get_tkip_seq = rt2800_get_tkip_seq, |
| 531 | .set_rts_threshold = rt2800_set_rts_threshold, |
| 532 | .sta_add = rt2x00mac_sta_add, |
| 533 | .sta_remove = rt2x00mac_sta_remove, |
| 534 | .bss_info_changed = rt2x00mac_bss_info_changed, |
| 535 | .conf_tx = rt2800_conf_tx, |
| 536 | .get_tsf = rt2800_get_tsf, |
| 537 | .rfkill_poll = rt2x00mac_rfkill_poll, |
| 538 | .ampdu_action = rt2800_ampdu_action, |
| 539 | .flush = rt2x00mac_flush, |
| 540 | .get_survey = rt2800_get_survey, |
| 541 | .get_ringparam = rt2x00mac_get_ringparam, |
| 542 | .tx_frames_pending = rt2x00mac_tx_frames_pending, |
| 543 | }; |
| 544 | |
| 545 | static const struct rt2800_ops rt2800pci_rt2800_ops = { |
| 546 | .register_read = rt2x00mmio_register_read, |
| 547 | .register_read_lock = rt2x00mmio_register_read, /* same for PCI */ |
| 548 | .register_write = rt2x00mmio_register_write, |
| 549 | .register_write_lock = rt2x00mmio_register_write, /* same for PCI */ |
| 550 | .register_multiread = rt2x00mmio_register_multiread, |
| 551 | .register_multiwrite = rt2x00mmio_register_multiwrite, |
| 552 | .regbusy_read = rt2x00mmio_regbusy_read, |
| 553 | .read_eeprom = rt2800pci_read_eeprom, |
| 554 | .hwcrypt_disabled = rt2800pci_hwcrypt_disabled, |
| 555 | .drv_write_firmware = rt2800pci_write_firmware, |
| 556 | .drv_init_registers = rt2800pci_init_registers, |
| 557 | .drv_get_txwi = rt2800mmio_get_txwi, |
| 558 | }; |
| 559 | |
| 560 | static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = { |
| 561 | .irq_handler = rt2800mmio_interrupt, |
| 562 | .txstatus_tasklet = rt2800mmio_txstatus_tasklet, |
| 563 | .pretbtt_tasklet = rt2800mmio_pretbtt_tasklet, |
| 564 | .tbtt_tasklet = rt2800mmio_tbtt_tasklet, |
| 565 | .rxdone_tasklet = rt2800mmio_rxdone_tasklet, |
| 566 | .autowake_tasklet = rt2800mmio_autowake_tasklet, |
| 567 | .probe_hw = rt2800_probe_hw, |
| 568 | .get_firmware_name = rt2800pci_get_firmware_name, |
| 569 | .check_firmware = rt2800_check_firmware, |
| 570 | .load_firmware = rt2800_load_firmware, |
| 571 | .initialize = rt2x00mmio_initialize, |
| 572 | .uninitialize = rt2x00mmio_uninitialize, |
| 573 | .get_entry_state = rt2800pci_get_entry_state, |
| 574 | .clear_entry = rt2800pci_clear_entry, |
| 575 | .set_device_state = rt2800pci_set_device_state, |
| 576 | .rfkill_poll = rt2800_rfkill_poll, |
| 577 | .link_stats = rt2800_link_stats, |
| 578 | .reset_tuner = rt2800_reset_tuner, |
| 579 | .link_tuner = rt2800_link_tuner, |
| 580 | .gain_calibration = rt2800_gain_calibration, |
| 581 | .vco_calibration = rt2800_vco_calibration, |
| 582 | .start_queue = rt2800mmio_start_queue, |
| 583 | .kick_queue = rt2800mmio_kick_queue, |
| 584 | .stop_queue = rt2800mmio_stop_queue, |
| 585 | .flush_queue = rt2x00mmio_flush_queue, |
| 586 | .write_tx_desc = rt2800mmio_write_tx_desc, |
| 587 | .write_tx_data = rt2800_write_tx_data, |
| 588 | .write_beacon = rt2800_write_beacon, |
| 589 | .clear_beacon = rt2800_clear_beacon, |
| 590 | .fill_rxdone = rt2800mmio_fill_rxdone, |
| 591 | .config_shared_key = rt2800_config_shared_key, |
| 592 | .config_pairwise_key = rt2800_config_pairwise_key, |
| 593 | .config_filter = rt2800_config_filter, |
| 594 | .config_intf = rt2800_config_intf, |
| 595 | .config_erp = rt2800_config_erp, |
| 596 | .config_ant = rt2800_config_ant, |
| 597 | .config = rt2800_config, |
| 598 | .sta_add = rt2800_sta_add, |
| 599 | .sta_remove = rt2800_sta_remove, |
| 600 | }; |
| 601 | |
| 602 | static const struct rt2x00_ops rt2800pci_ops = { |
| 603 | .name = KBUILD_MODNAME, |
| 604 | .drv_data_size = sizeof(struct rt2800_drv_data), |
| 605 | .max_ap_intf = 8, |
| 606 | .eeprom_size = EEPROM_SIZE, |
| 607 | .rf_size = RF_SIZE, |
| 608 | .tx_queues = NUM_TX_QUEUES, |
| 609 | .queue_init = rt2800mmio_queue_init, |
| 610 | .lib = &rt2800pci_rt2x00_ops, |
| 611 | .drv = &rt2800pci_rt2800_ops, |
| 612 | .hw = &rt2800pci_mac80211_ops, |
| 613 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |
| 614 | .debugfs = &rt2800_rt2x00debug, |
| 615 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ |
| 616 | }; |
| 617 | |
| 618 | /* |
| 619 | * RT2800pci module information. |
| 620 | */ |
| 621 | #ifdef CONFIG_PCI |
| 622 | static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = { |
| 623 | { PCI_DEVICE(0x1814, 0x0601) }, |
| 624 | { PCI_DEVICE(0x1814, 0x0681) }, |
| 625 | { PCI_DEVICE(0x1814, 0x0701) }, |
| 626 | { PCI_DEVICE(0x1814, 0x0781) }, |
| 627 | { PCI_DEVICE(0x1814, 0x3090) }, |
| 628 | { PCI_DEVICE(0x1814, 0x3091) }, |
| 629 | { PCI_DEVICE(0x1814, 0x3092) }, |
| 630 | { PCI_DEVICE(0x1432, 0x7708) }, |
| 631 | { PCI_DEVICE(0x1432, 0x7727) }, |
| 632 | { PCI_DEVICE(0x1432, 0x7728) }, |
| 633 | { PCI_DEVICE(0x1432, 0x7738) }, |
| 634 | { PCI_DEVICE(0x1432, 0x7748) }, |
| 635 | { PCI_DEVICE(0x1432, 0x7758) }, |
| 636 | { PCI_DEVICE(0x1432, 0x7768) }, |
| 637 | { PCI_DEVICE(0x1462, 0x891a) }, |
| 638 | { PCI_DEVICE(0x1a3b, 0x1059) }, |
| 639 | #ifdef CONFIG_RT2800PCI_RT3290 |
| 640 | { PCI_DEVICE(0x1814, 0x3290) }, |
| 641 | #endif |
| 642 | #ifdef CONFIG_RT2800PCI_RT33XX |
| 643 | { PCI_DEVICE(0x1814, 0x3390) }, |
| 644 | #endif |
| 645 | #ifdef CONFIG_RT2800PCI_RT35XX |
| 646 | { PCI_DEVICE(0x1432, 0x7711) }, |
| 647 | { PCI_DEVICE(0x1432, 0x7722) }, |
| 648 | { PCI_DEVICE(0x1814, 0x3060) }, |
| 649 | { PCI_DEVICE(0x1814, 0x3062) }, |
| 650 | { PCI_DEVICE(0x1814, 0x3562) }, |
| 651 | { PCI_DEVICE(0x1814, 0x3592) }, |
| 652 | { PCI_DEVICE(0x1814, 0x3593) }, |
| 653 | { PCI_DEVICE(0x1814, 0x359f) }, |
| 654 | #endif |
| 655 | #ifdef CONFIG_RT2800PCI_RT53XX |
| 656 | { PCI_DEVICE(0x1814, 0x5360) }, |
| 657 | { PCI_DEVICE(0x1814, 0x5362) }, |
| 658 | { PCI_DEVICE(0x1814, 0x5390) }, |
| 659 | { PCI_DEVICE(0x1814, 0x5392) }, |
| 660 | { PCI_DEVICE(0x1814, 0x539a) }, |
| 661 | { PCI_DEVICE(0x1814, 0x539b) }, |
| 662 | { PCI_DEVICE(0x1814, 0x539f) }, |
| 663 | #endif |
| 664 | { 0, } |
| 665 | }; |
| 666 | #endif /* CONFIG_PCI */ |
| 667 | |
| 668 | MODULE_AUTHOR(DRV_PROJECT); |
| 669 | MODULE_VERSION(DRV_VERSION); |
| 670 | MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver."); |
| 671 | MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards"); |
| 672 | #ifdef CONFIG_PCI |
| 673 | MODULE_FIRMWARE(FIRMWARE_RT2860); |
| 674 | MODULE_DEVICE_TABLE(pci, rt2800pci_device_table); |
| 675 | #endif /* CONFIG_PCI */ |
| 676 | MODULE_LICENSE("GPL"); |
| 677 | |
| 678 | #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X) |
| 679 | static int rt2800soc_probe(struct platform_device *pdev) |
| 680 | { |
| 681 | return rt2x00soc_probe(pdev, &rt2800pci_ops); |
| 682 | } |
| 683 | |
| 684 | static struct platform_driver rt2800soc_driver = { |
| 685 | .driver = { |
| 686 | .name = "rt2800_wmac", |
| 687 | .owner = THIS_MODULE, |
| 688 | .mod_name = KBUILD_MODNAME, |
| 689 | }, |
| 690 | .probe = rt2800soc_probe, |
| 691 | .remove = rt2x00soc_remove, |
| 692 | .suspend = rt2x00soc_suspend, |
| 693 | .resume = rt2x00soc_resume, |
| 694 | }; |
| 695 | #endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */ |
| 696 | |
| 697 | #ifdef CONFIG_PCI |
| 698 | static int rt2800pci_probe(struct pci_dev *pci_dev, |
| 699 | const struct pci_device_id *id) |
| 700 | { |
| 701 | return rt2x00pci_probe(pci_dev, &rt2800pci_ops); |
| 702 | } |
| 703 | |
| 704 | static struct pci_driver rt2800pci_driver = { |
| 705 | .name = KBUILD_MODNAME, |
| 706 | .id_table = rt2800pci_device_table, |
| 707 | .probe = rt2800pci_probe, |
| 708 | .remove = rt2x00pci_remove, |
| 709 | .suspend = rt2x00pci_suspend, |
| 710 | .resume = rt2x00pci_resume, |
| 711 | }; |
| 712 | #endif /* CONFIG_PCI */ |
| 713 | |
| 714 | static int __init rt2800pci_init(void) |
| 715 | { |
| 716 | int ret = 0; |
| 717 | |
| 718 | #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X) |
| 719 | ret = platform_driver_register(&rt2800soc_driver); |
| 720 | if (ret) |
| 721 | return ret; |
| 722 | #endif |
| 723 | #ifdef CONFIG_PCI |
| 724 | ret = pci_register_driver(&rt2800pci_driver); |
| 725 | if (ret) { |
| 726 | #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X) |
| 727 | platform_driver_unregister(&rt2800soc_driver); |
| 728 | #endif |
| 729 | return ret; |
| 730 | } |
| 731 | #endif |
| 732 | |
| 733 | return ret; |
| 734 | } |
| 735 | |
| 736 | static void __exit rt2800pci_exit(void) |
| 737 | { |
| 738 | #ifdef CONFIG_PCI |
| 739 | pci_unregister_driver(&rt2800pci_driver); |
| 740 | #endif |
| 741 | #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X) |
| 742 | platform_driver_unregister(&rt2800soc_driver); |
| 743 | #endif |
| 744 | } |
| 745 | |
| 746 | module_init(rt2800pci_init); |
| 747 | module_exit(rt2800pci_exit); |