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nvme: move nvme_cancel_request() to common code
[deliverable/linux.git] / drivers / nvme / host / pci.c
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CommitLineData
1/*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/aer.h>
16#include <linux/bitops.h>
17#include <linux/blkdev.h>
18#include <linux/blk-mq.h>
19#include <linux/cpu.h>
20#include <linux/delay.h>
21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
24#include <linux/hdreg.h>
25#include <linux/idr.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
30#include <linux/kernel.h>
31#include <linux/mm.h>
32#include <linux/module.h>
33#include <linux/moduleparam.h>
34#include <linux/mutex.h>
35#include <linux/pci.h>
36#include <linux/poison.h>
37#include <linux/ptrace.h>
38#include <linux/sched.h>
39#include <linux/slab.h>
40#include <linux/t10-pi.h>
41#include <linux/timer.h>
42#include <linux/types.h>
43#include <linux/io-64-nonatomic-lo-hi.h>
44#include <asm/unaligned.h>
45
46#include "nvme.h"
47
48#define NVME_Q_DEPTH 1024
49#define NVME_AQ_DEPTH 256
50#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
51#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
52
53/*
54 * We handle AEN commands ourselves and don't even let the
55 * block layer know about them.
56 */
57#define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS)
58
59static int use_threaded_interrupts;
60module_param(use_threaded_interrupts, int, 0);
61
62static bool use_cmb_sqes = true;
63module_param(use_cmb_sqes, bool, 0644);
64MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
65
66static struct workqueue_struct *nvme_workq;
67
68struct nvme_dev;
69struct nvme_queue;
70
71static int nvme_reset(struct nvme_dev *dev);
72static void nvme_process_cq(struct nvme_queue *nvmeq);
73static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
74
75/*
76 * Represents an NVM Express device. Each nvme_dev is a PCI function.
77 */
78struct nvme_dev {
79 struct nvme_queue **queues;
80 struct blk_mq_tag_set tagset;
81 struct blk_mq_tag_set admin_tagset;
82 u32 __iomem *dbs;
83 struct device *dev;
84 struct dma_pool *prp_page_pool;
85 struct dma_pool *prp_small_pool;
86 unsigned queue_count;
87 unsigned online_queues;
88 unsigned max_qid;
89 int q_depth;
90 u32 db_stride;
91 struct msix_entry *entry;
92 void __iomem *bar;
93 struct work_struct reset_work;
94 struct work_struct remove_work;
95 struct timer_list watchdog_timer;
96 struct mutex shutdown_lock;
97 bool subsystem;
98 void __iomem *cmb;
99 dma_addr_t cmb_dma_addr;
100 u64 cmb_size;
101 u32 cmbsz;
102 struct nvme_ctrl ctrl;
103 struct completion ioq_wait;
104};
105
106static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
107{
108 return container_of(ctrl, struct nvme_dev, ctrl);
109}
110
111/*
112 * An NVM Express queue. Each device has at least two (one for admin
113 * commands and one for I/O commands).
114 */
115struct nvme_queue {
116 struct device *q_dmadev;
117 struct nvme_dev *dev;
118 char irqname[24]; /* nvme4294967295-65535\0 */
119 spinlock_t q_lock;
120 struct nvme_command *sq_cmds;
121 struct nvme_command __iomem *sq_cmds_io;
122 volatile struct nvme_completion *cqes;
123 struct blk_mq_tags **tags;
124 dma_addr_t sq_dma_addr;
125 dma_addr_t cq_dma_addr;
126 u32 __iomem *q_db;
127 u16 q_depth;
128 s16 cq_vector;
129 u16 sq_tail;
130 u16 cq_head;
131 u16 qid;
132 u8 cq_phase;
133 u8 cqe_seen;
134};
135
136/*
137 * The nvme_iod describes the data in an I/O, including the list of PRP
138 * entries. You can't see it in this data structure because C doesn't let
139 * me express that. Use nvme_init_iod to ensure there's enough space
140 * allocated to store the PRP list.
141 */
142struct nvme_iod {
143 struct nvme_queue *nvmeq;
144 int aborted;
145 int npages; /* In the PRP list. 0 means small pool in use */
146 int nents; /* Used in scatterlist */
147 int length; /* Of data, in bytes */
148 dma_addr_t first_dma;
149 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
150 struct scatterlist *sg;
151 struct scatterlist inline_sg[0];
152};
153
154/*
155 * Check we didin't inadvertently grow the command struct
156 */
157static inline void _nvme_check_size(void)
158{
159 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
160 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
161 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
162 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
163 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
164 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
165 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
166 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
167 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
168 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
169 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
170 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
171}
172
173/*
174 * Max size of iod being embedded in the request payload
175 */
176#define NVME_INT_PAGES 2
177#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
178
179/*
180 * Will slightly overestimate the number of pages needed. This is OK
181 * as it only leads to a small amount of wasted memory for the lifetime of
182 * the I/O.
183 */
184static int nvme_npages(unsigned size, struct nvme_dev *dev)
185{
186 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
187 dev->ctrl.page_size);
188 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
189}
190
191static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
192 unsigned int size, unsigned int nseg)
193{
194 return sizeof(__le64 *) * nvme_npages(size, dev) +
195 sizeof(struct scatterlist) * nseg;
196}
197
198static unsigned int nvme_cmd_size(struct nvme_dev *dev)
199{
200 return sizeof(struct nvme_iod) +
201 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
202}
203
204static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
205 unsigned int hctx_idx)
206{
207 struct nvme_dev *dev = data;
208 struct nvme_queue *nvmeq = dev->queues[0];
209
210 WARN_ON(hctx_idx != 0);
211 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
212 WARN_ON(nvmeq->tags);
213
214 hctx->driver_data = nvmeq;
215 nvmeq->tags = &dev->admin_tagset.tags[0];
216 return 0;
217}
218
219static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
220{
221 struct nvme_queue *nvmeq = hctx->driver_data;
222
223 nvmeq->tags = NULL;
224}
225
226static int nvme_admin_init_request(void *data, struct request *req,
227 unsigned int hctx_idx, unsigned int rq_idx,
228 unsigned int numa_node)
229{
230 struct nvme_dev *dev = data;
231 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
232 struct nvme_queue *nvmeq = dev->queues[0];
233
234 BUG_ON(!nvmeq);
235 iod->nvmeq = nvmeq;
236 return 0;
237}
238
239static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
240 unsigned int hctx_idx)
241{
242 struct nvme_dev *dev = data;
243 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
244
245 if (!nvmeq->tags)
246 nvmeq->tags = &dev->tagset.tags[hctx_idx];
247
248 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
249 hctx->driver_data = nvmeq;
250 return 0;
251}
252
253static int nvme_init_request(void *data, struct request *req,
254 unsigned int hctx_idx, unsigned int rq_idx,
255 unsigned int numa_node)
256{
257 struct nvme_dev *dev = data;
258 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
259 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
260
261 BUG_ON(!nvmeq);
262 iod->nvmeq = nvmeq;
263 return 0;
264}
265
266/**
267 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
268 * @nvmeq: The queue to use
269 * @cmd: The command to send
270 *
271 * Safe to use from interrupt context
272 */
273static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
274 struct nvme_command *cmd)
275{
276 u16 tail = nvmeq->sq_tail;
277
278 if (nvmeq->sq_cmds_io)
279 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
280 else
281 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
282
283 if (++tail == nvmeq->q_depth)
284 tail = 0;
285 writel(tail, nvmeq->q_db);
286 nvmeq->sq_tail = tail;
287}
288
289static __le64 **iod_list(struct request *req)
290{
291 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
292 return (__le64 **)(iod->sg + req->nr_phys_segments);
293}
294
295static int nvme_init_iod(struct request *rq, unsigned size,
296 struct nvme_dev *dev)
297{
298 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
299 int nseg = rq->nr_phys_segments;
300
301 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
302 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
303 if (!iod->sg)
304 return BLK_MQ_RQ_QUEUE_BUSY;
305 } else {
306 iod->sg = iod->inline_sg;
307 }
308
309 iod->aborted = 0;
310 iod->npages = -1;
311 iod->nents = 0;
312 iod->length = size;
313 return 0;
314}
315
316static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
317{
318 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
319 const int last_prp = dev->ctrl.page_size / 8 - 1;
320 int i;
321 __le64 **list = iod_list(req);
322 dma_addr_t prp_dma = iod->first_dma;
323
324 nvme_cleanup_cmd(req);
325
326 if (iod->npages == 0)
327 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
328 for (i = 0; i < iod->npages; i++) {
329 __le64 *prp_list = list[i];
330 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
331 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
332 prp_dma = next_prp_dma;
333 }
334
335 if (iod->sg != iod->inline_sg)
336 kfree(iod->sg);
337}
338
339#ifdef CONFIG_BLK_DEV_INTEGRITY
340static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
341{
342 if (be32_to_cpu(pi->ref_tag) == v)
343 pi->ref_tag = cpu_to_be32(p);
344}
345
346static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
347{
348 if (be32_to_cpu(pi->ref_tag) == p)
349 pi->ref_tag = cpu_to_be32(v);
350}
351
352/**
353 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
354 *
355 * The virtual start sector is the one that was originally submitted by the
356 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
357 * start sector may be different. Remap protection information to match the
358 * physical LBA on writes, and back to the original seed on reads.
359 *
360 * Type 0 and 3 do not have a ref tag, so no remapping required.
361 */
362static void nvme_dif_remap(struct request *req,
363 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
364{
365 struct nvme_ns *ns = req->rq_disk->private_data;
366 struct bio_integrity_payload *bip;
367 struct t10_pi_tuple *pi;
368 void *p, *pmap;
369 u32 i, nlb, ts, phys, virt;
370
371 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
372 return;
373
374 bip = bio_integrity(req->bio);
375 if (!bip)
376 return;
377
378 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
379
380 p = pmap;
381 virt = bip_get_seed(bip);
382 phys = nvme_block_nr(ns, blk_rq_pos(req));
383 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
384 ts = ns->disk->queue->integrity.tuple_size;
385
386 for (i = 0; i < nlb; i++, virt++, phys++) {
387 pi = (struct t10_pi_tuple *)p;
388 dif_swap(phys, virt, pi);
389 p += ts;
390 }
391 kunmap_atomic(pmap);
392}
393#else /* CONFIG_BLK_DEV_INTEGRITY */
394static void nvme_dif_remap(struct request *req,
395 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
396{
397}
398static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
399{
400}
401static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
402{
403}
404#endif
405
406static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req,
407 int total_len)
408{
409 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
410 struct dma_pool *pool;
411 int length = total_len;
412 struct scatterlist *sg = iod->sg;
413 int dma_len = sg_dma_len(sg);
414 u64 dma_addr = sg_dma_address(sg);
415 u32 page_size = dev->ctrl.page_size;
416 int offset = dma_addr & (page_size - 1);
417 __le64 *prp_list;
418 __le64 **list = iod_list(req);
419 dma_addr_t prp_dma;
420 int nprps, i;
421
422 length -= (page_size - offset);
423 if (length <= 0)
424 return true;
425
426 dma_len -= (page_size - offset);
427 if (dma_len) {
428 dma_addr += (page_size - offset);
429 } else {
430 sg = sg_next(sg);
431 dma_addr = sg_dma_address(sg);
432 dma_len = sg_dma_len(sg);
433 }
434
435 if (length <= page_size) {
436 iod->first_dma = dma_addr;
437 return true;
438 }
439
440 nprps = DIV_ROUND_UP(length, page_size);
441 if (nprps <= (256 / 8)) {
442 pool = dev->prp_small_pool;
443 iod->npages = 0;
444 } else {
445 pool = dev->prp_page_pool;
446 iod->npages = 1;
447 }
448
449 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
450 if (!prp_list) {
451 iod->first_dma = dma_addr;
452 iod->npages = -1;
453 return false;
454 }
455 list[0] = prp_list;
456 iod->first_dma = prp_dma;
457 i = 0;
458 for (;;) {
459 if (i == page_size >> 3) {
460 __le64 *old_prp_list = prp_list;
461 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
462 if (!prp_list)
463 return false;
464 list[iod->npages++] = prp_list;
465 prp_list[0] = old_prp_list[i - 1];
466 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
467 i = 1;
468 }
469 prp_list[i++] = cpu_to_le64(dma_addr);
470 dma_len -= page_size;
471 dma_addr += page_size;
472 length -= page_size;
473 if (length <= 0)
474 break;
475 if (dma_len > 0)
476 continue;
477 BUG_ON(dma_len < 0);
478 sg = sg_next(sg);
479 dma_addr = sg_dma_address(sg);
480 dma_len = sg_dma_len(sg);
481 }
482
483 return true;
484}
485
486static int nvme_map_data(struct nvme_dev *dev, struct request *req,
487 unsigned size, struct nvme_command *cmnd)
488{
489 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
490 struct request_queue *q = req->q;
491 enum dma_data_direction dma_dir = rq_data_dir(req) ?
492 DMA_TO_DEVICE : DMA_FROM_DEVICE;
493 int ret = BLK_MQ_RQ_QUEUE_ERROR;
494
495 sg_init_table(iod->sg, req->nr_phys_segments);
496 iod->nents = blk_rq_map_sg(q, req, iod->sg);
497 if (!iod->nents)
498 goto out;
499
500 ret = BLK_MQ_RQ_QUEUE_BUSY;
501 if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir))
502 goto out;
503
504 if (!nvme_setup_prps(dev, req, size))
505 goto out_unmap;
506
507 ret = BLK_MQ_RQ_QUEUE_ERROR;
508 if (blk_integrity_rq(req)) {
509 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
510 goto out_unmap;
511
512 sg_init_table(&iod->meta_sg, 1);
513 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
514 goto out_unmap;
515
516 if (rq_data_dir(req))
517 nvme_dif_remap(req, nvme_dif_prep);
518
519 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
520 goto out_unmap;
521 }
522
523 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
524 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
525 if (blk_integrity_rq(req))
526 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
527 return BLK_MQ_RQ_QUEUE_OK;
528
529out_unmap:
530 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
531out:
532 return ret;
533}
534
535static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
536{
537 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
538 enum dma_data_direction dma_dir = rq_data_dir(req) ?
539 DMA_TO_DEVICE : DMA_FROM_DEVICE;
540
541 if (iod->nents) {
542 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
543 if (blk_integrity_rq(req)) {
544 if (!rq_data_dir(req))
545 nvme_dif_remap(req, nvme_dif_complete);
546 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
547 }
548 }
549
550 nvme_free_iod(dev, req);
551}
552
553/*
554 * NOTE: ns is NULL when called on the admin queue.
555 */
556static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
557 const struct blk_mq_queue_data *bd)
558{
559 struct nvme_ns *ns = hctx->queue->queuedata;
560 struct nvme_queue *nvmeq = hctx->driver_data;
561 struct nvme_dev *dev = nvmeq->dev;
562 struct request *req = bd->rq;
563 struct nvme_command cmnd;
564 unsigned map_len;
565 int ret = BLK_MQ_RQ_QUEUE_OK;
566
567 /*
568 * If formated with metadata, require the block layer provide a buffer
569 * unless this namespace is formated such that the metadata can be
570 * stripped/generated by the controller with PRACT=1.
571 */
572 if (ns && ns->ms && !blk_integrity_rq(req)) {
573 if (!(ns->pi_type && ns->ms == 8) &&
574 req->cmd_type != REQ_TYPE_DRV_PRIV) {
575 blk_mq_end_request(req, -EFAULT);
576 return BLK_MQ_RQ_QUEUE_OK;
577 }
578 }
579
580 map_len = nvme_map_len(req);
581 ret = nvme_init_iod(req, map_len, dev);
582 if (ret)
583 return ret;
584
585 ret = nvme_setup_cmd(ns, req, &cmnd);
586 if (ret)
587 goto out;
588
589 if (req->nr_phys_segments)
590 ret = nvme_map_data(dev, req, map_len, &cmnd);
591
592 if (ret)
593 goto out;
594
595 cmnd.common.command_id = req->tag;
596 blk_mq_start_request(req);
597
598 spin_lock_irq(&nvmeq->q_lock);
599 if (unlikely(nvmeq->cq_vector < 0)) {
600 if (ns && !test_bit(NVME_NS_DEAD, &ns->flags))
601 ret = BLK_MQ_RQ_QUEUE_BUSY;
602 else
603 ret = BLK_MQ_RQ_QUEUE_ERROR;
604 spin_unlock_irq(&nvmeq->q_lock);
605 goto out;
606 }
607 __nvme_submit_cmd(nvmeq, &cmnd);
608 nvme_process_cq(nvmeq);
609 spin_unlock_irq(&nvmeq->q_lock);
610 return BLK_MQ_RQ_QUEUE_OK;
611out:
612 nvme_free_iod(dev, req);
613 return ret;
614}
615
616static void nvme_complete_rq(struct request *req)
617{
618 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
619 struct nvme_dev *dev = iod->nvmeq->dev;
620 int error = 0;
621
622 nvme_unmap_data(dev, req);
623
624 if (unlikely(req->errors)) {
625 if (nvme_req_needs_retry(req, req->errors)) {
626 nvme_requeue_req(req);
627 return;
628 }
629
630 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
631 error = req->errors;
632 else
633 error = nvme_error_status(req->errors);
634 }
635
636 if (unlikely(iod->aborted)) {
637 dev_warn(dev->ctrl.device,
638 "completing aborted command with status: %04x\n",
639 req->errors);
640 }
641
642 blk_mq_end_request(req, error);
643}
644
645/* We read the CQE phase first to check if the rest of the entry is valid */
646static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
647 u16 phase)
648{
649 return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
650}
651
652static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
653{
654 u16 head, phase;
655
656 head = nvmeq->cq_head;
657 phase = nvmeq->cq_phase;
658
659 while (nvme_cqe_valid(nvmeq, head, phase)) {
660 struct nvme_completion cqe = nvmeq->cqes[head];
661 struct request *req;
662
663 if (++head == nvmeq->q_depth) {
664 head = 0;
665 phase = !phase;
666 }
667
668 if (tag && *tag == cqe.command_id)
669 *tag = -1;
670
671 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
672 dev_warn(nvmeq->dev->ctrl.device,
673 "invalid id %d completed on queue %d\n",
674 cqe.command_id, le16_to_cpu(cqe.sq_id));
675 continue;
676 }
677
678 /*
679 * AEN requests are special as they don't time out and can
680 * survive any kind of queue freeze and often don't respond to
681 * aborts. We don't even bother to allocate a struct request
682 * for them but rather special case them here.
683 */
684 if (unlikely(nvmeq->qid == 0 &&
685 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
686 nvme_complete_async_event(&nvmeq->dev->ctrl, &cqe);
687 continue;
688 }
689
690 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
691 if (req->cmd_type == REQ_TYPE_DRV_PRIV && req->special)
692 memcpy(req->special, &cqe, sizeof(cqe));
693 blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1);
694
695 }
696
697 /* If the controller ignores the cq head doorbell and continuously
698 * writes to the queue, it is theoretically possible to wrap around
699 * the queue twice and mistakenly return IRQ_NONE. Linux only
700 * requires that 0.1% of your interrupts are handled, so this isn't
701 * a big problem.
702 */
703 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
704 return;
705
706 if (likely(nvmeq->cq_vector >= 0))
707 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
708 nvmeq->cq_head = head;
709 nvmeq->cq_phase = phase;
710
711 nvmeq->cqe_seen = 1;
712}
713
714static void nvme_process_cq(struct nvme_queue *nvmeq)
715{
716 __nvme_process_cq(nvmeq, NULL);
717}
718
719static irqreturn_t nvme_irq(int irq, void *data)
720{
721 irqreturn_t result;
722 struct nvme_queue *nvmeq = data;
723 spin_lock(&nvmeq->q_lock);
724 nvme_process_cq(nvmeq);
725 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
726 nvmeq->cqe_seen = 0;
727 spin_unlock(&nvmeq->q_lock);
728 return result;
729}
730
731static irqreturn_t nvme_irq_check(int irq, void *data)
732{
733 struct nvme_queue *nvmeq = data;
734 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
735 return IRQ_WAKE_THREAD;
736 return IRQ_NONE;
737}
738
739static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
740{
741 struct nvme_queue *nvmeq = hctx->driver_data;
742
743 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
744 spin_lock_irq(&nvmeq->q_lock);
745 __nvme_process_cq(nvmeq, &tag);
746 spin_unlock_irq(&nvmeq->q_lock);
747
748 if (tag == -1)
749 return 1;
750 }
751
752 return 0;
753}
754
755static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
756{
757 struct nvme_dev *dev = to_nvme_dev(ctrl);
758 struct nvme_queue *nvmeq = dev->queues[0];
759 struct nvme_command c;
760
761 memset(&c, 0, sizeof(c));
762 c.common.opcode = nvme_admin_async_event;
763 c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
764
765 spin_lock_irq(&nvmeq->q_lock);
766 __nvme_submit_cmd(nvmeq, &c);
767 spin_unlock_irq(&nvmeq->q_lock);
768}
769
770static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
771{
772 struct nvme_command c;
773
774 memset(&c, 0, sizeof(c));
775 c.delete_queue.opcode = opcode;
776 c.delete_queue.qid = cpu_to_le16(id);
777
778 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
779}
780
781static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
782 struct nvme_queue *nvmeq)
783{
784 struct nvme_command c;
785 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
786
787 /*
788 * Note: we (ab)use the fact the the prp fields survive if no data
789 * is attached to the request.
790 */
791 memset(&c, 0, sizeof(c));
792 c.create_cq.opcode = nvme_admin_create_cq;
793 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
794 c.create_cq.cqid = cpu_to_le16(qid);
795 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
796 c.create_cq.cq_flags = cpu_to_le16(flags);
797 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
798
799 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
800}
801
802static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
803 struct nvme_queue *nvmeq)
804{
805 struct nvme_command c;
806 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
807
808 /*
809 * Note: we (ab)use the fact the the prp fields survive if no data
810 * is attached to the request.
811 */
812 memset(&c, 0, sizeof(c));
813 c.create_sq.opcode = nvme_admin_create_sq;
814 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
815 c.create_sq.sqid = cpu_to_le16(qid);
816 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
817 c.create_sq.sq_flags = cpu_to_le16(flags);
818 c.create_sq.cqid = cpu_to_le16(qid);
819
820 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
821}
822
823static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
824{
825 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
826}
827
828static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
829{
830 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
831}
832
833static void abort_endio(struct request *req, int error)
834{
835 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
836 struct nvme_queue *nvmeq = iod->nvmeq;
837 u16 status = req->errors;
838
839 dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status);
840 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
841 blk_mq_free_request(req);
842}
843
844static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
845{
846 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
847 struct nvme_queue *nvmeq = iod->nvmeq;
848 struct nvme_dev *dev = nvmeq->dev;
849 struct request *abort_req;
850 struct nvme_command cmd;
851
852 /*
853 * Shutdown immediately if controller times out while starting. The
854 * reset work will see the pci device disabled when it gets the forced
855 * cancellation error. All outstanding requests are completed on
856 * shutdown, so we return BLK_EH_HANDLED.
857 */
858 if (dev->ctrl.state == NVME_CTRL_RESETTING) {
859 dev_warn(dev->ctrl.device,
860 "I/O %d QID %d timeout, disable controller\n",
861 req->tag, nvmeq->qid);
862 nvme_dev_disable(dev, false);
863 req->errors = NVME_SC_CANCELLED;
864 return BLK_EH_HANDLED;
865 }
866
867 /*
868 * Shutdown the controller immediately and schedule a reset if the
869 * command was already aborted once before and still hasn't been
870 * returned to the driver, or if this is the admin queue.
871 */
872 if (!nvmeq->qid || iod->aborted) {
873 dev_warn(dev->ctrl.device,
874 "I/O %d QID %d timeout, reset controller\n",
875 req->tag, nvmeq->qid);
876 nvme_dev_disable(dev, false);
877 queue_work(nvme_workq, &dev->reset_work);
878
879 /*
880 * Mark the request as handled, since the inline shutdown
881 * forces all outstanding requests to complete.
882 */
883 req->errors = NVME_SC_CANCELLED;
884 return BLK_EH_HANDLED;
885 }
886
887 iod->aborted = 1;
888
889 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
890 atomic_inc(&dev->ctrl.abort_limit);
891 return BLK_EH_RESET_TIMER;
892 }
893
894 memset(&cmd, 0, sizeof(cmd));
895 cmd.abort.opcode = nvme_admin_abort_cmd;
896 cmd.abort.cid = req->tag;
897 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
898
899 dev_warn(nvmeq->dev->ctrl.device,
900 "I/O %d QID %d timeout, aborting\n",
901 req->tag, nvmeq->qid);
902
903 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
904 BLK_MQ_REQ_NOWAIT);
905 if (IS_ERR(abort_req)) {
906 atomic_inc(&dev->ctrl.abort_limit);
907 return BLK_EH_RESET_TIMER;
908 }
909
910 abort_req->timeout = ADMIN_TIMEOUT;
911 abort_req->end_io_data = NULL;
912 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
913
914 /*
915 * The aborted req will be completed on receiving the abort req.
916 * We enable the timer again. If hit twice, it'll cause a device reset,
917 * as the device then is in a faulty state.
918 */
919 return BLK_EH_RESET_TIMER;
920}
921
922static void nvme_free_queue(struct nvme_queue *nvmeq)
923{
924 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
925 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
926 if (nvmeq->sq_cmds)
927 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
928 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
929 kfree(nvmeq);
930}
931
932static void nvme_free_queues(struct nvme_dev *dev, int lowest)
933{
934 int i;
935
936 for (i = dev->queue_count - 1; i >= lowest; i--) {
937 struct nvme_queue *nvmeq = dev->queues[i];
938 dev->queue_count--;
939 dev->queues[i] = NULL;
940 nvme_free_queue(nvmeq);
941 }
942}
943
944/**
945 * nvme_suspend_queue - put queue into suspended state
946 * @nvmeq - queue to suspend
947 */
948static int nvme_suspend_queue(struct nvme_queue *nvmeq)
949{
950 int vector;
951
952 spin_lock_irq(&nvmeq->q_lock);
953 if (nvmeq->cq_vector == -1) {
954 spin_unlock_irq(&nvmeq->q_lock);
955 return 1;
956 }
957 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
958 nvmeq->dev->online_queues--;
959 nvmeq->cq_vector = -1;
960 spin_unlock_irq(&nvmeq->q_lock);
961
962 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
963 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
964
965 irq_set_affinity_hint(vector, NULL);
966 free_irq(vector, nvmeq);
967
968 return 0;
969}
970
971static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
972{
973 struct nvme_queue *nvmeq = dev->queues[0];
974
975 if (!nvmeq)
976 return;
977 if (nvme_suspend_queue(nvmeq))
978 return;
979
980 if (shutdown)
981 nvme_shutdown_ctrl(&dev->ctrl);
982 else
983 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
984 dev->bar + NVME_REG_CAP));
985
986 spin_lock_irq(&nvmeq->q_lock);
987 nvme_process_cq(nvmeq);
988 spin_unlock_irq(&nvmeq->q_lock);
989}
990
991static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
992 int entry_size)
993{
994 int q_depth = dev->q_depth;
995 unsigned q_size_aligned = roundup(q_depth * entry_size,
996 dev->ctrl.page_size);
997
998 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
999 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1000 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1001 q_depth = div_u64(mem_per_q, entry_size);
1002
1003 /*
1004 * Ensure the reduced q_depth is above some threshold where it
1005 * would be better to map queues in system memory with the
1006 * original depth
1007 */
1008 if (q_depth < 64)
1009 return -ENOMEM;
1010 }
1011
1012 return q_depth;
1013}
1014
1015static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1016 int qid, int depth)
1017{
1018 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1019 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1020 dev->ctrl.page_size);
1021 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1022 nvmeq->sq_cmds_io = dev->cmb + offset;
1023 } else {
1024 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1025 &nvmeq->sq_dma_addr, GFP_KERNEL);
1026 if (!nvmeq->sq_cmds)
1027 return -ENOMEM;
1028 }
1029
1030 return 0;
1031}
1032
1033static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1034 int depth)
1035{
1036 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1037 if (!nvmeq)
1038 return NULL;
1039
1040 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1041 &nvmeq->cq_dma_addr, GFP_KERNEL);
1042 if (!nvmeq->cqes)
1043 goto free_nvmeq;
1044
1045 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1046 goto free_cqdma;
1047
1048 nvmeq->q_dmadev = dev->dev;
1049 nvmeq->dev = dev;
1050 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1051 dev->ctrl.instance, qid);
1052 spin_lock_init(&nvmeq->q_lock);
1053 nvmeq->cq_head = 0;
1054 nvmeq->cq_phase = 1;
1055 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1056 nvmeq->q_depth = depth;
1057 nvmeq->qid = qid;
1058 nvmeq->cq_vector = -1;
1059 dev->queues[qid] = nvmeq;
1060 dev->queue_count++;
1061
1062 return nvmeq;
1063
1064 free_cqdma:
1065 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1066 nvmeq->cq_dma_addr);
1067 free_nvmeq:
1068 kfree(nvmeq);
1069 return NULL;
1070}
1071
1072static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1073 const char *name)
1074{
1075 if (use_threaded_interrupts)
1076 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1077 nvme_irq_check, nvme_irq, IRQF_SHARED,
1078 name, nvmeq);
1079 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1080 IRQF_SHARED, name, nvmeq);
1081}
1082
1083static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1084{
1085 struct nvme_dev *dev = nvmeq->dev;
1086
1087 spin_lock_irq(&nvmeq->q_lock);
1088 nvmeq->sq_tail = 0;
1089 nvmeq->cq_head = 0;
1090 nvmeq->cq_phase = 1;
1091 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1092 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1093 dev->online_queues++;
1094 spin_unlock_irq(&nvmeq->q_lock);
1095}
1096
1097static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1098{
1099 struct nvme_dev *dev = nvmeq->dev;
1100 int result;
1101
1102 nvmeq->cq_vector = qid - 1;
1103 result = adapter_alloc_cq(dev, qid, nvmeq);
1104 if (result < 0)
1105 return result;
1106
1107 result = adapter_alloc_sq(dev, qid, nvmeq);
1108 if (result < 0)
1109 goto release_cq;
1110
1111 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1112 if (result < 0)
1113 goto release_sq;
1114
1115 nvme_init_queue(nvmeq, qid);
1116 return result;
1117
1118 release_sq:
1119 adapter_delete_sq(dev, qid);
1120 release_cq:
1121 adapter_delete_cq(dev, qid);
1122 return result;
1123}
1124
1125static struct blk_mq_ops nvme_mq_admin_ops = {
1126 .queue_rq = nvme_queue_rq,
1127 .complete = nvme_complete_rq,
1128 .map_queue = blk_mq_map_queue,
1129 .init_hctx = nvme_admin_init_hctx,
1130 .exit_hctx = nvme_admin_exit_hctx,
1131 .init_request = nvme_admin_init_request,
1132 .timeout = nvme_timeout,
1133};
1134
1135static struct blk_mq_ops nvme_mq_ops = {
1136 .queue_rq = nvme_queue_rq,
1137 .complete = nvme_complete_rq,
1138 .map_queue = blk_mq_map_queue,
1139 .init_hctx = nvme_init_hctx,
1140 .init_request = nvme_init_request,
1141 .timeout = nvme_timeout,
1142 .poll = nvme_poll,
1143};
1144
1145static void nvme_dev_remove_admin(struct nvme_dev *dev)
1146{
1147 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1148 /*
1149 * If the controller was reset during removal, it's possible
1150 * user requests may be waiting on a stopped queue. Start the
1151 * queue to flush these to completion.
1152 */
1153 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1154 blk_cleanup_queue(dev->ctrl.admin_q);
1155 blk_mq_free_tag_set(&dev->admin_tagset);
1156 }
1157}
1158
1159static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1160{
1161 if (!dev->ctrl.admin_q) {
1162 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1163 dev->admin_tagset.nr_hw_queues = 1;
1164
1165 /*
1166 * Subtract one to leave an empty queue entry for 'Full Queue'
1167 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1168 */
1169 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1170 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1171 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1172 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1173 dev->admin_tagset.driver_data = dev;
1174
1175 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1176 return -ENOMEM;
1177
1178 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1179 if (IS_ERR(dev->ctrl.admin_q)) {
1180 blk_mq_free_tag_set(&dev->admin_tagset);
1181 return -ENOMEM;
1182 }
1183 if (!blk_get_queue(dev->ctrl.admin_q)) {
1184 nvme_dev_remove_admin(dev);
1185 dev->ctrl.admin_q = NULL;
1186 return -ENODEV;
1187 }
1188 } else
1189 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1190
1191 return 0;
1192}
1193
1194static int nvme_configure_admin_queue(struct nvme_dev *dev)
1195{
1196 int result;
1197 u32 aqa;
1198 u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1199 struct nvme_queue *nvmeq;
1200
1201 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ?
1202 NVME_CAP_NSSRC(cap) : 0;
1203
1204 if (dev->subsystem &&
1205 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1206 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1207
1208 result = nvme_disable_ctrl(&dev->ctrl, cap);
1209 if (result < 0)
1210 return result;
1211
1212 nvmeq = dev->queues[0];
1213 if (!nvmeq) {
1214 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1215 if (!nvmeq)
1216 return -ENOMEM;
1217 }
1218
1219 aqa = nvmeq->q_depth - 1;
1220 aqa |= aqa << 16;
1221
1222 writel(aqa, dev->bar + NVME_REG_AQA);
1223 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1224 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1225
1226 result = nvme_enable_ctrl(&dev->ctrl, cap);
1227 if (result)
1228 goto free_nvmeq;
1229
1230 nvmeq->cq_vector = 0;
1231 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1232 if (result) {
1233 nvmeq->cq_vector = -1;
1234 goto free_nvmeq;
1235 }
1236
1237 return result;
1238
1239 free_nvmeq:
1240 nvme_free_queues(dev, 0);
1241 return result;
1242}
1243
1244static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1245{
1246
1247 /* If true, indicates loss of adapter communication, possibly by a
1248 * NVMe Subsystem reset.
1249 */
1250 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1251
1252 /* If there is a reset ongoing, we shouldn't reset again. */
1253 if (work_busy(&dev->reset_work))
1254 return false;
1255
1256 /* We shouldn't reset unless the controller is on fatal error state
1257 * _or_ if we lost the communication with it.
1258 */
1259 if (!(csts & NVME_CSTS_CFS) && !nssro)
1260 return false;
1261
1262 /* If PCI error recovery process is happening, we cannot reset or
1263 * the recovery mechanism will surely fail.
1264 */
1265 if (pci_channel_offline(to_pci_dev(dev->dev)))
1266 return false;
1267
1268 return true;
1269}
1270
1271static void nvme_watchdog_timer(unsigned long data)
1272{
1273 struct nvme_dev *dev = (struct nvme_dev *)data;
1274 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1275
1276 /* Skip controllers under certain specific conditions. */
1277 if (nvme_should_reset(dev, csts)) {
1278 if (queue_work(nvme_workq, &dev->reset_work))
1279 dev_warn(dev->dev,
1280 "Failed status: 0x%x, reset controller.\n",
1281 csts);
1282 return;
1283 }
1284
1285 mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1286}
1287
1288static int nvme_create_io_queues(struct nvme_dev *dev)
1289{
1290 unsigned i, max;
1291 int ret = 0;
1292
1293 for (i = dev->queue_count; i <= dev->max_qid; i++) {
1294 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1295 ret = -ENOMEM;
1296 break;
1297 }
1298 }
1299
1300 max = min(dev->max_qid, dev->queue_count - 1);
1301 for (i = dev->online_queues; i <= max; i++) {
1302 ret = nvme_create_queue(dev->queues[i], i);
1303 if (ret) {
1304 nvme_free_queues(dev, i);
1305 break;
1306 }
1307 }
1308
1309 /*
1310 * Ignore failing Create SQ/CQ commands, we can continue with less
1311 * than the desired aount of queues, and even a controller without
1312 * I/O queues an still be used to issue admin commands. This might
1313 * be useful to upgrade a buggy firmware for example.
1314 */
1315 return ret >= 0 ? 0 : ret;
1316}
1317
1318static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1319{
1320 u64 szu, size, offset;
1321 u32 cmbloc;
1322 resource_size_t bar_size;
1323 struct pci_dev *pdev = to_pci_dev(dev->dev);
1324 void __iomem *cmb;
1325 dma_addr_t dma_addr;
1326
1327 if (!use_cmb_sqes)
1328 return NULL;
1329
1330 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1331 if (!(NVME_CMB_SZ(dev->cmbsz)))
1332 return NULL;
1333
1334 cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1335
1336 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1337 size = szu * NVME_CMB_SZ(dev->cmbsz);
1338 offset = szu * NVME_CMB_OFST(cmbloc);
1339 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
1340
1341 if (offset > bar_size)
1342 return NULL;
1343
1344 /*
1345 * Controllers may support a CMB size larger than their BAR,
1346 * for example, due to being behind a bridge. Reduce the CMB to
1347 * the reported size of the BAR
1348 */
1349 if (size > bar_size - offset)
1350 size = bar_size - offset;
1351
1352 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
1353 cmb = ioremap_wc(dma_addr, size);
1354 if (!cmb)
1355 return NULL;
1356
1357 dev->cmb_dma_addr = dma_addr;
1358 dev->cmb_size = size;
1359 return cmb;
1360}
1361
1362static inline void nvme_release_cmb(struct nvme_dev *dev)
1363{
1364 if (dev->cmb) {
1365 iounmap(dev->cmb);
1366 dev->cmb = NULL;
1367 }
1368}
1369
1370static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1371{
1372 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1373}
1374
1375static int nvme_setup_io_queues(struct nvme_dev *dev)
1376{
1377 struct nvme_queue *adminq = dev->queues[0];
1378 struct pci_dev *pdev = to_pci_dev(dev->dev);
1379 int result, i, vecs, nr_io_queues, size;
1380
1381 nr_io_queues = num_online_cpus();
1382 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1383 if (result < 0)
1384 return result;
1385
1386 /*
1387 * Degraded controllers might return an error when setting the queue
1388 * count. We still want to be able to bring them online and offer
1389 * access to the admin queue, as that might be only way to fix them up.
1390 */
1391 if (result > 0) {
1392 dev_err(dev->ctrl.device,
1393 "Could not set queue count (%d)\n", result);
1394 return 0;
1395 }
1396
1397 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1398 result = nvme_cmb_qdepth(dev, nr_io_queues,
1399 sizeof(struct nvme_command));
1400 if (result > 0)
1401 dev->q_depth = result;
1402 else
1403 nvme_release_cmb(dev);
1404 }
1405
1406 size = db_bar_size(dev, nr_io_queues);
1407 if (size > 8192) {
1408 iounmap(dev->bar);
1409 do {
1410 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1411 if (dev->bar)
1412 break;
1413 if (!--nr_io_queues)
1414 return -ENOMEM;
1415 size = db_bar_size(dev, nr_io_queues);
1416 } while (1);
1417 dev->dbs = dev->bar + 4096;
1418 adminq->q_db = dev->dbs;
1419 }
1420
1421 /* Deregister the admin queue's interrupt */
1422 free_irq(dev->entry[0].vector, adminq);
1423
1424 /*
1425 * If we enable msix early due to not intx, disable it again before
1426 * setting up the full range we need.
1427 */
1428 if (pdev->msi_enabled)
1429 pci_disable_msi(pdev);
1430 else if (pdev->msix_enabled)
1431 pci_disable_msix(pdev);
1432
1433 for (i = 0; i < nr_io_queues; i++)
1434 dev->entry[i].entry = i;
1435 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
1436 if (vecs < 0) {
1437 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
1438 if (vecs < 0) {
1439 vecs = 1;
1440 } else {
1441 for (i = 0; i < vecs; i++)
1442 dev->entry[i].vector = i + pdev->irq;
1443 }
1444 }
1445
1446 /*
1447 * Should investigate if there's a performance win from allocating
1448 * more queues than interrupt vectors; it might allow the submission
1449 * path to scale better, even if the receive path is limited by the
1450 * number of interrupts.
1451 */
1452 nr_io_queues = vecs;
1453 dev->max_qid = nr_io_queues;
1454
1455 result = queue_request_irq(dev, adminq, adminq->irqname);
1456 if (result) {
1457 adminq->cq_vector = -1;
1458 goto free_queues;
1459 }
1460 return nvme_create_io_queues(dev);
1461
1462 free_queues:
1463 nvme_free_queues(dev, 1);
1464 return result;
1465}
1466
1467static void nvme_pci_post_scan(struct nvme_ctrl *ctrl)
1468{
1469 struct nvme_dev *dev = to_nvme_dev(ctrl);
1470 struct nvme_queue *nvmeq;
1471 int i;
1472
1473 for (i = 0; i < dev->online_queues; i++) {
1474 nvmeq = dev->queues[i];
1475
1476 if (!nvmeq->tags || !(*nvmeq->tags))
1477 continue;
1478
1479 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
1480 blk_mq_tags_cpumask(*nvmeq->tags));
1481 }
1482}
1483
1484static void nvme_del_queue_end(struct request *req, int error)
1485{
1486 struct nvme_queue *nvmeq = req->end_io_data;
1487
1488 blk_mq_free_request(req);
1489 complete(&nvmeq->dev->ioq_wait);
1490}
1491
1492static void nvme_del_cq_end(struct request *req, int error)
1493{
1494 struct nvme_queue *nvmeq = req->end_io_data;
1495
1496 if (!error) {
1497 unsigned long flags;
1498
1499 /*
1500 * We might be called with the AQ q_lock held
1501 * and the I/O queue q_lock should always
1502 * nest inside the AQ one.
1503 */
1504 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1505 SINGLE_DEPTH_NESTING);
1506 nvme_process_cq(nvmeq);
1507 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1508 }
1509
1510 nvme_del_queue_end(req, error);
1511}
1512
1513static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1514{
1515 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1516 struct request *req;
1517 struct nvme_command cmd;
1518
1519 memset(&cmd, 0, sizeof(cmd));
1520 cmd.delete_queue.opcode = opcode;
1521 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1522
1523 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
1524 if (IS_ERR(req))
1525 return PTR_ERR(req);
1526
1527 req->timeout = ADMIN_TIMEOUT;
1528 req->end_io_data = nvmeq;
1529
1530 blk_execute_rq_nowait(q, NULL, req, false,
1531 opcode == nvme_admin_delete_cq ?
1532 nvme_del_cq_end : nvme_del_queue_end);
1533 return 0;
1534}
1535
1536static void nvme_disable_io_queues(struct nvme_dev *dev)
1537{
1538 int pass, queues = dev->online_queues - 1;
1539 unsigned long timeout;
1540 u8 opcode = nvme_admin_delete_sq;
1541
1542 for (pass = 0; pass < 2; pass++) {
1543 int sent = 0, i = queues;
1544
1545 reinit_completion(&dev->ioq_wait);
1546 retry:
1547 timeout = ADMIN_TIMEOUT;
1548 for (; i > 0; i--) {
1549 struct nvme_queue *nvmeq = dev->queues[i];
1550
1551 if (!pass)
1552 nvme_suspend_queue(nvmeq);
1553 if (nvme_delete_queue(nvmeq, opcode))
1554 break;
1555 ++sent;
1556 }
1557 while (sent--) {
1558 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1559 if (timeout == 0)
1560 return;
1561 if (i)
1562 goto retry;
1563 }
1564 opcode = nvme_admin_delete_cq;
1565 }
1566}
1567
1568/*
1569 * Return: error value if an error occurred setting up the queues or calling
1570 * Identify Device. 0 if these succeeded, even if adding some of the
1571 * namespaces failed. At the moment, these failures are silent. TBD which
1572 * failures should be reported.
1573 */
1574static int nvme_dev_add(struct nvme_dev *dev)
1575{
1576 if (!dev->ctrl.tagset) {
1577 dev->tagset.ops = &nvme_mq_ops;
1578 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1579 dev->tagset.timeout = NVME_IO_TIMEOUT;
1580 dev->tagset.numa_node = dev_to_node(dev->dev);
1581 dev->tagset.queue_depth =
1582 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1583 dev->tagset.cmd_size = nvme_cmd_size(dev);
1584 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1585 dev->tagset.driver_data = dev;
1586
1587 if (blk_mq_alloc_tag_set(&dev->tagset))
1588 return 0;
1589 dev->ctrl.tagset = &dev->tagset;
1590 } else {
1591 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1592
1593 /* Free previously allocated queues that are no longer usable */
1594 nvme_free_queues(dev, dev->online_queues);
1595 }
1596
1597 return 0;
1598}
1599
1600static int nvme_pci_enable(struct nvme_dev *dev)
1601{
1602 u64 cap;
1603 int result = -ENOMEM;
1604 struct pci_dev *pdev = to_pci_dev(dev->dev);
1605
1606 if (pci_enable_device_mem(pdev))
1607 return result;
1608
1609 pci_set_master(pdev);
1610
1611 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1612 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1613 goto disable;
1614
1615 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1616 result = -ENODEV;
1617 goto disable;
1618 }
1619
1620 /*
1621 * Some devices and/or platforms don't advertise or work with INTx
1622 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1623 * adjust this later.
1624 */
1625 if (pci_enable_msix(pdev, dev->entry, 1)) {
1626 pci_enable_msi(pdev);
1627 dev->entry[0].vector = pdev->irq;
1628 }
1629
1630 if (!dev->entry[0].vector) {
1631 result = -ENODEV;
1632 goto disable;
1633 }
1634
1635 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1636
1637 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1638 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1639 dev->dbs = dev->bar + 4096;
1640
1641 /*
1642 * Temporary fix for the Apple controller found in the MacBook8,1 and
1643 * some MacBook7,1 to avoid controller resets and data loss.
1644 */
1645 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1646 dev->q_depth = 2;
1647 dev_warn(dev->dev, "detected Apple NVMe controller, set "
1648 "queue depth=%u to work around controller resets\n",
1649 dev->q_depth);
1650 }
1651
1652 if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2))
1653 dev->cmb = nvme_map_cmb(dev);
1654
1655 pci_enable_pcie_error_reporting(pdev);
1656 pci_save_state(pdev);
1657 return 0;
1658
1659 disable:
1660 pci_disable_device(pdev);
1661 return result;
1662}
1663
1664static void nvme_dev_unmap(struct nvme_dev *dev)
1665{
1666 if (dev->bar)
1667 iounmap(dev->bar);
1668 pci_release_regions(to_pci_dev(dev->dev));
1669}
1670
1671static void nvme_pci_disable(struct nvme_dev *dev)
1672{
1673 struct pci_dev *pdev = to_pci_dev(dev->dev);
1674
1675 if (pdev->msi_enabled)
1676 pci_disable_msi(pdev);
1677 else if (pdev->msix_enabled)
1678 pci_disable_msix(pdev);
1679
1680 if (pci_is_enabled(pdev)) {
1681 pci_disable_pcie_error_reporting(pdev);
1682 pci_disable_device(pdev);
1683 }
1684}
1685
1686static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1687{
1688 int i;
1689 u32 csts = -1;
1690
1691 del_timer_sync(&dev->watchdog_timer);
1692
1693 mutex_lock(&dev->shutdown_lock);
1694 if (pci_is_enabled(to_pci_dev(dev->dev))) {
1695 nvme_stop_queues(&dev->ctrl);
1696 csts = readl(dev->bar + NVME_REG_CSTS);
1697 }
1698 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
1699 for (i = dev->queue_count - 1; i >= 0; i--) {
1700 struct nvme_queue *nvmeq = dev->queues[i];
1701 nvme_suspend_queue(nvmeq);
1702 }
1703 } else {
1704 nvme_disable_io_queues(dev);
1705 nvme_disable_admin_queue(dev, shutdown);
1706 }
1707 nvme_pci_disable(dev);
1708
1709 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
1710 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
1711 mutex_unlock(&dev->shutdown_lock);
1712}
1713
1714static int nvme_setup_prp_pools(struct nvme_dev *dev)
1715{
1716 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1717 PAGE_SIZE, PAGE_SIZE, 0);
1718 if (!dev->prp_page_pool)
1719 return -ENOMEM;
1720
1721 /* Optimisation for I/Os between 4k and 128k */
1722 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1723 256, 256, 0);
1724 if (!dev->prp_small_pool) {
1725 dma_pool_destroy(dev->prp_page_pool);
1726 return -ENOMEM;
1727 }
1728 return 0;
1729}
1730
1731static void nvme_release_prp_pools(struct nvme_dev *dev)
1732{
1733 dma_pool_destroy(dev->prp_page_pool);
1734 dma_pool_destroy(dev->prp_small_pool);
1735}
1736
1737static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1738{
1739 struct nvme_dev *dev = to_nvme_dev(ctrl);
1740
1741 put_device(dev->dev);
1742 if (dev->tagset.tags)
1743 blk_mq_free_tag_set(&dev->tagset);
1744 if (dev->ctrl.admin_q)
1745 blk_put_queue(dev->ctrl.admin_q);
1746 kfree(dev->queues);
1747 kfree(dev->entry);
1748 kfree(dev);
1749}
1750
1751static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
1752{
1753 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
1754
1755 kref_get(&dev->ctrl.kref);
1756 nvme_dev_disable(dev, false);
1757 if (!schedule_work(&dev->remove_work))
1758 nvme_put_ctrl(&dev->ctrl);
1759}
1760
1761static void nvme_reset_work(struct work_struct *work)
1762{
1763 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1764 int result = -ENODEV;
1765
1766 if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING))
1767 goto out;
1768
1769 /*
1770 * If we're called to reset a live controller first shut it down before
1771 * moving on.
1772 */
1773 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
1774 nvme_dev_disable(dev, false);
1775
1776 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
1777 goto out;
1778
1779 result = nvme_pci_enable(dev);
1780 if (result)
1781 goto out;
1782
1783 result = nvme_configure_admin_queue(dev);
1784 if (result)
1785 goto out;
1786
1787 nvme_init_queue(dev->queues[0], 0);
1788 result = nvme_alloc_admin_tags(dev);
1789 if (result)
1790 goto out;
1791
1792 result = nvme_init_identify(&dev->ctrl);
1793 if (result)
1794 goto out;
1795
1796 result = nvme_setup_io_queues(dev);
1797 if (result)
1798 goto out;
1799
1800 /*
1801 * A controller that can not execute IO typically requires user
1802 * intervention to correct. For such degraded controllers, the driver
1803 * should not submit commands the user did not request, so skip
1804 * registering for asynchronous event notification on this condition.
1805 */
1806 if (dev->online_queues > 1)
1807 nvme_queue_async_events(&dev->ctrl);
1808
1809 mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1810
1811 /*
1812 * Keep the controller around but remove all namespaces if we don't have
1813 * any working I/O queue.
1814 */
1815 if (dev->online_queues < 2) {
1816 dev_warn(dev->ctrl.device, "IO queues not created\n");
1817 nvme_kill_queues(&dev->ctrl);
1818 nvme_remove_namespaces(&dev->ctrl);
1819 } else {
1820 nvme_start_queues(&dev->ctrl);
1821 nvme_dev_add(dev);
1822 }
1823
1824 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
1825 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
1826 goto out;
1827 }
1828
1829 if (dev->online_queues > 1)
1830 nvme_queue_scan(&dev->ctrl);
1831 return;
1832
1833 out:
1834 nvme_remove_dead_ctrl(dev, result);
1835}
1836
1837static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1838{
1839 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1840 struct pci_dev *pdev = to_pci_dev(dev->dev);
1841
1842 nvme_kill_queues(&dev->ctrl);
1843 if (pci_get_drvdata(pdev))
1844 device_release_driver(&pdev->dev);
1845 nvme_put_ctrl(&dev->ctrl);
1846}
1847
1848static int nvme_reset(struct nvme_dev *dev)
1849{
1850 if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1851 return -ENODEV;
1852
1853 if (!queue_work(nvme_workq, &dev->reset_work))
1854 return -EBUSY;
1855
1856 flush_work(&dev->reset_work);
1857 return 0;
1858}
1859
1860static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
1861{
1862 *val = readl(to_nvme_dev(ctrl)->bar + off);
1863 return 0;
1864}
1865
1866static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
1867{
1868 writel(val, to_nvme_dev(ctrl)->bar + off);
1869 return 0;
1870}
1871
1872static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
1873{
1874 *val = readq(to_nvme_dev(ctrl)->bar + off);
1875 return 0;
1876}
1877
1878static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
1879{
1880 return nvme_reset(to_nvme_dev(ctrl));
1881}
1882
1883static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1884 .module = THIS_MODULE,
1885 .reg_read32 = nvme_pci_reg_read32,
1886 .reg_write32 = nvme_pci_reg_write32,
1887 .reg_read64 = nvme_pci_reg_read64,
1888 .reset_ctrl = nvme_pci_reset_ctrl,
1889 .free_ctrl = nvme_pci_free_ctrl,
1890 .post_scan = nvme_pci_post_scan,
1891 .submit_async_event = nvme_pci_submit_async_event,
1892};
1893
1894static int nvme_dev_map(struct nvme_dev *dev)
1895{
1896 int bars;
1897 struct pci_dev *pdev = to_pci_dev(dev->dev);
1898
1899 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1900 if (!bars)
1901 return -ENODEV;
1902 if (pci_request_selected_regions(pdev, bars, "nvme"))
1903 return -ENODEV;
1904
1905 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1906 if (!dev->bar)
1907 goto release;
1908
1909 return 0;
1910 release:
1911 pci_release_regions(pdev);
1912 return -ENODEV;
1913}
1914
1915static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1916{
1917 int node, result = -ENOMEM;
1918 struct nvme_dev *dev;
1919
1920 node = dev_to_node(&pdev->dev);
1921 if (node == NUMA_NO_NODE)
1922 set_dev_node(&pdev->dev, 0);
1923
1924 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
1925 if (!dev)
1926 return -ENOMEM;
1927 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
1928 GFP_KERNEL, node);
1929 if (!dev->entry)
1930 goto free;
1931 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1932 GFP_KERNEL, node);
1933 if (!dev->queues)
1934 goto free;
1935
1936 dev->dev = get_device(&pdev->dev);
1937 pci_set_drvdata(pdev, dev);
1938
1939 result = nvme_dev_map(dev);
1940 if (result)
1941 goto free;
1942
1943 INIT_WORK(&dev->reset_work, nvme_reset_work);
1944 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
1945 setup_timer(&dev->watchdog_timer, nvme_watchdog_timer,
1946 (unsigned long)dev);
1947 mutex_init(&dev->shutdown_lock);
1948 init_completion(&dev->ioq_wait);
1949
1950 result = nvme_setup_prp_pools(dev);
1951 if (result)
1952 goto put_pci;
1953
1954 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
1955 id->driver_data);
1956 if (result)
1957 goto release_pools;
1958
1959 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
1960
1961 queue_work(nvme_workq, &dev->reset_work);
1962 return 0;
1963
1964 release_pools:
1965 nvme_release_prp_pools(dev);
1966 put_pci:
1967 put_device(dev->dev);
1968 nvme_dev_unmap(dev);
1969 free:
1970 kfree(dev->queues);
1971 kfree(dev->entry);
1972 kfree(dev);
1973 return result;
1974}
1975
1976static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
1977{
1978 struct nvme_dev *dev = pci_get_drvdata(pdev);
1979
1980 if (prepare)
1981 nvme_dev_disable(dev, false);
1982 else
1983 queue_work(nvme_workq, &dev->reset_work);
1984}
1985
1986static void nvme_shutdown(struct pci_dev *pdev)
1987{
1988 struct nvme_dev *dev = pci_get_drvdata(pdev);
1989 nvme_dev_disable(dev, true);
1990}
1991
1992/*
1993 * The driver's remove may be called on a device in a partially initialized
1994 * state. This function must not have any dependencies on the device state in
1995 * order to proceed.
1996 */
1997static void nvme_remove(struct pci_dev *pdev)
1998{
1999 struct nvme_dev *dev = pci_get_drvdata(pdev);
2000
2001 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2002
2003 pci_set_drvdata(pdev, NULL);
2004
2005 if (!pci_device_is_present(pdev))
2006 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2007
2008 flush_work(&dev->reset_work);
2009 nvme_uninit_ctrl(&dev->ctrl);
2010 nvme_dev_disable(dev, true);
2011 nvme_dev_remove_admin(dev);
2012 nvme_free_queues(dev, 0);
2013 nvme_release_cmb(dev);
2014 nvme_release_prp_pools(dev);
2015 nvme_dev_unmap(dev);
2016 nvme_put_ctrl(&dev->ctrl);
2017}
2018
2019#ifdef CONFIG_PM_SLEEP
2020static int nvme_suspend(struct device *dev)
2021{
2022 struct pci_dev *pdev = to_pci_dev(dev);
2023 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2024
2025 nvme_dev_disable(ndev, true);
2026 return 0;
2027}
2028
2029static int nvme_resume(struct device *dev)
2030{
2031 struct pci_dev *pdev = to_pci_dev(dev);
2032 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2033
2034 queue_work(nvme_workq, &ndev->reset_work);
2035 return 0;
2036}
2037#endif
2038
2039static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2040
2041static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2042 pci_channel_state_t state)
2043{
2044 struct nvme_dev *dev = pci_get_drvdata(pdev);
2045
2046 /*
2047 * A frozen channel requires a reset. When detected, this method will
2048 * shutdown the controller to quiesce. The controller will be restarted
2049 * after the slot reset through driver's slot_reset callback.
2050 */
2051 switch (state) {
2052 case pci_channel_io_normal:
2053 return PCI_ERS_RESULT_CAN_RECOVER;
2054 case pci_channel_io_frozen:
2055 dev_warn(dev->ctrl.device,
2056 "frozen state error detected, reset controller\n");
2057 nvme_dev_disable(dev, false);
2058 return PCI_ERS_RESULT_NEED_RESET;
2059 case pci_channel_io_perm_failure:
2060 dev_warn(dev->ctrl.device,
2061 "failure state error detected, request disconnect\n");
2062 return PCI_ERS_RESULT_DISCONNECT;
2063 }
2064 return PCI_ERS_RESULT_NEED_RESET;
2065}
2066
2067static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2068{
2069 struct nvme_dev *dev = pci_get_drvdata(pdev);
2070
2071 dev_info(dev->ctrl.device, "restart after slot reset\n");
2072 pci_restore_state(pdev);
2073 queue_work(nvme_workq, &dev->reset_work);
2074 return PCI_ERS_RESULT_RECOVERED;
2075}
2076
2077static void nvme_error_resume(struct pci_dev *pdev)
2078{
2079 pci_cleanup_aer_uncorrect_error_status(pdev);
2080}
2081
2082static const struct pci_error_handlers nvme_err_handler = {
2083 .error_detected = nvme_error_detected,
2084 .slot_reset = nvme_slot_reset,
2085 .resume = nvme_error_resume,
2086 .reset_notify = nvme_reset_notify,
2087};
2088
2089/* Move to pci_ids.h later */
2090#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2091
2092static const struct pci_device_id nvme_id_table[] = {
2093 { PCI_VDEVICE(INTEL, 0x0953),
2094 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2095 NVME_QUIRK_DISCARD_ZEROES, },
2096 { PCI_VDEVICE(INTEL, 0x0a53),
2097 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2098 NVME_QUIRK_DISCARD_ZEROES, },
2099 { PCI_VDEVICE(INTEL, 0x0a54),
2100 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2101 NVME_QUIRK_DISCARD_ZEROES, },
2102 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2103 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2104 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2105 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2106 { 0, }
2107};
2108MODULE_DEVICE_TABLE(pci, nvme_id_table);
2109
2110static struct pci_driver nvme_driver = {
2111 .name = "nvme",
2112 .id_table = nvme_id_table,
2113 .probe = nvme_probe,
2114 .remove = nvme_remove,
2115 .shutdown = nvme_shutdown,
2116 .driver = {
2117 .pm = &nvme_dev_pm_ops,
2118 },
2119 .err_handler = &nvme_err_handler,
2120};
2121
2122static int __init nvme_init(void)
2123{
2124 int result;
2125
2126 nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2127 if (!nvme_workq)
2128 return -ENOMEM;
2129
2130 result = pci_register_driver(&nvme_driver);
2131 if (result)
2132 destroy_workqueue(nvme_workq);
2133 return result;
2134}
2135
2136static void __exit nvme_exit(void)
2137{
2138 pci_unregister_driver(&nvme_driver);
2139 destroy_workqueue(nvme_workq);
2140 _nvme_check_size();
2141}
2142
2143MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2144MODULE_LICENSE("GPL");
2145MODULE_VERSION("1.0");
2146module_init(nvme_init);
2147module_exit(nvme_exit);
Linux kernel - Deliverables
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