| 1 | /* |
| 2 | * File: msi.c |
| 3 | * Purpose: PCI Message Signaled Interrupt (MSI) |
| 4 | * |
| 5 | * Copyright (C) 2003-2004 Intel |
| 6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) |
| 7 | */ |
| 8 | |
| 9 | #include <linux/err.h> |
| 10 | #include <linux/mm.h> |
| 11 | #include <linux/irq.h> |
| 12 | #include <linux/interrupt.h> |
| 13 | #include <linux/export.h> |
| 14 | #include <linux/ioport.h> |
| 15 | #include <linux/pci.h> |
| 16 | #include <linux/proc_fs.h> |
| 17 | #include <linux/msi.h> |
| 18 | #include <linux/smp.h> |
| 19 | #include <linux/errno.h> |
| 20 | #include <linux/io.h> |
| 21 | #include <linux/slab.h> |
| 22 | #include <linux/irqdomain.h> |
| 23 | |
| 24 | #include "pci.h" |
| 25 | |
| 26 | static int pci_msi_enable = 1; |
| 27 | int pci_msi_ignore_mask; |
| 28 | |
| 29 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
| 30 | |
| 31 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
| 32 | static struct irq_domain *pci_msi_default_domain; |
| 33 | static DEFINE_MUTEX(pci_msi_domain_lock); |
| 34 | |
| 35 | struct irq_domain * __weak arch_get_pci_msi_domain(struct pci_dev *dev) |
| 36 | { |
| 37 | return pci_msi_default_domain; |
| 38 | } |
| 39 | |
| 40 | static struct irq_domain *pci_msi_get_domain(struct pci_dev *dev) |
| 41 | { |
| 42 | struct irq_domain *domain = NULL; |
| 43 | |
| 44 | if (dev->bus->msi) |
| 45 | domain = dev->bus->msi->domain; |
| 46 | if (!domain) |
| 47 | domain = arch_get_pci_msi_domain(dev); |
| 48 | |
| 49 | return domain; |
| 50 | } |
| 51 | |
| 52 | static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
| 53 | { |
| 54 | struct irq_domain *domain; |
| 55 | |
| 56 | domain = pci_msi_get_domain(dev); |
| 57 | if (domain) |
| 58 | return pci_msi_domain_alloc_irqs(domain, dev, nvec, type); |
| 59 | |
| 60 | return arch_setup_msi_irqs(dev, nvec, type); |
| 61 | } |
| 62 | |
| 63 | static void pci_msi_teardown_msi_irqs(struct pci_dev *dev) |
| 64 | { |
| 65 | struct irq_domain *domain; |
| 66 | |
| 67 | domain = pci_msi_get_domain(dev); |
| 68 | if (domain) |
| 69 | pci_msi_domain_free_irqs(domain, dev); |
| 70 | else |
| 71 | arch_teardown_msi_irqs(dev); |
| 72 | } |
| 73 | #else |
| 74 | #define pci_msi_setup_msi_irqs arch_setup_msi_irqs |
| 75 | #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs |
| 76 | #endif |
| 77 | |
| 78 | /* Arch hooks */ |
| 79 | |
| 80 | struct msi_controller * __weak pcibios_msi_controller(struct pci_dev *dev) |
| 81 | { |
| 82 | return NULL; |
| 83 | } |
| 84 | |
| 85 | static struct msi_controller *pci_msi_controller(struct pci_dev *dev) |
| 86 | { |
| 87 | struct msi_controller *msi_ctrl = dev->bus->msi; |
| 88 | |
| 89 | if (msi_ctrl) |
| 90 | return msi_ctrl; |
| 91 | |
| 92 | return pcibios_msi_controller(dev); |
| 93 | } |
| 94 | |
| 95 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
| 96 | { |
| 97 | struct msi_controller *chip = pci_msi_controller(dev); |
| 98 | int err; |
| 99 | |
| 100 | if (!chip || !chip->setup_irq) |
| 101 | return -EINVAL; |
| 102 | |
| 103 | err = chip->setup_irq(chip, dev, desc); |
| 104 | if (err < 0) |
| 105 | return err; |
| 106 | |
| 107 | irq_set_chip_data(desc->irq, chip); |
| 108 | |
| 109 | return 0; |
| 110 | } |
| 111 | |
| 112 | void __weak arch_teardown_msi_irq(unsigned int irq) |
| 113 | { |
| 114 | struct msi_controller *chip = irq_get_chip_data(irq); |
| 115 | |
| 116 | if (!chip || !chip->teardown_irq) |
| 117 | return; |
| 118 | |
| 119 | chip->teardown_irq(chip, irq); |
| 120 | } |
| 121 | |
| 122 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
| 123 | { |
| 124 | struct msi_desc *entry; |
| 125 | int ret; |
| 126 | |
| 127 | /* |
| 128 | * If an architecture wants to support multiple MSI, it needs to |
| 129 | * override arch_setup_msi_irqs() |
| 130 | */ |
| 131 | if (type == PCI_CAP_ID_MSI && nvec > 1) |
| 132 | return 1; |
| 133 | |
| 134 | list_for_each_entry(entry, &dev->msi_list, list) { |
| 135 | ret = arch_setup_msi_irq(dev, entry); |
| 136 | if (ret < 0) |
| 137 | return ret; |
| 138 | if (ret > 0) |
| 139 | return -ENOSPC; |
| 140 | } |
| 141 | |
| 142 | return 0; |
| 143 | } |
| 144 | |
| 145 | /* |
| 146 | * We have a default implementation available as a separate non-weak |
| 147 | * function, as it is used by the Xen x86 PCI code |
| 148 | */ |
| 149 | void default_teardown_msi_irqs(struct pci_dev *dev) |
| 150 | { |
| 151 | int i; |
| 152 | struct msi_desc *entry; |
| 153 | |
| 154 | list_for_each_entry(entry, &dev->msi_list, list) |
| 155 | if (entry->irq) |
| 156 | for (i = 0; i < entry->nvec_used; i++) |
| 157 | arch_teardown_msi_irq(entry->irq + i); |
| 158 | } |
| 159 | |
| 160 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
| 161 | { |
| 162 | return default_teardown_msi_irqs(dev); |
| 163 | } |
| 164 | |
| 165 | static void default_restore_msi_irq(struct pci_dev *dev, int irq) |
| 166 | { |
| 167 | struct msi_desc *entry; |
| 168 | |
| 169 | entry = NULL; |
| 170 | if (dev->msix_enabled) { |
| 171 | list_for_each_entry(entry, &dev->msi_list, list) { |
| 172 | if (irq == entry->irq) |
| 173 | break; |
| 174 | } |
| 175 | } else if (dev->msi_enabled) { |
| 176 | entry = irq_get_msi_desc(irq); |
| 177 | } |
| 178 | |
| 179 | if (entry) |
| 180 | __pci_write_msi_msg(entry, &entry->msg); |
| 181 | } |
| 182 | |
| 183 | void __weak arch_restore_msi_irqs(struct pci_dev *dev) |
| 184 | { |
| 185 | return default_restore_msi_irqs(dev); |
| 186 | } |
| 187 | |
| 188 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
| 189 | { |
| 190 | /* Don't shift by >= width of type */ |
| 191 | if (x >= 5) |
| 192 | return 0xffffffff; |
| 193 | return (1 << (1 << x)) - 1; |
| 194 | } |
| 195 | |
| 196 | /* |
| 197 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to |
| 198 | * mask all MSI interrupts by clearing the MSI enable bit does not work |
| 199 | * reliably as devices without an INTx disable bit will then generate a |
| 200 | * level IRQ which will never be cleared. |
| 201 | */ |
| 202 | u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
| 203 | { |
| 204 | u32 mask_bits = desc->masked; |
| 205 | |
| 206 | if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit) |
| 207 | return 0; |
| 208 | |
| 209 | mask_bits &= ~mask; |
| 210 | mask_bits |= flag; |
| 211 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); |
| 212 | |
| 213 | return mask_bits; |
| 214 | } |
| 215 | |
| 216 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
| 217 | { |
| 218 | desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag); |
| 219 | } |
| 220 | |
| 221 | /* |
| 222 | * This internal function does not flush PCI writes to the device. |
| 223 | * All users must ensure that they read from the device before either |
| 224 | * assuming that the device state is up to date, or returning out of this |
| 225 | * file. This saves a few milliseconds when initialising devices with lots |
| 226 | * of MSI-X interrupts. |
| 227 | */ |
| 228 | u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag) |
| 229 | { |
| 230 | u32 mask_bits = desc->masked; |
| 231 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + |
| 232 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
| 233 | |
| 234 | if (pci_msi_ignore_mask) |
| 235 | return 0; |
| 236 | |
| 237 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
| 238 | if (flag) |
| 239 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; |
| 240 | writel(mask_bits, desc->mask_base + offset); |
| 241 | |
| 242 | return mask_bits; |
| 243 | } |
| 244 | |
| 245 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) |
| 246 | { |
| 247 | desc->masked = __pci_msix_desc_mask_irq(desc, flag); |
| 248 | } |
| 249 | |
| 250 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
| 251 | { |
| 252 | struct msi_desc *desc = irq_data_get_msi(data); |
| 253 | |
| 254 | if (desc->msi_attrib.is_msix) { |
| 255 | msix_mask_irq(desc, flag); |
| 256 | readl(desc->mask_base); /* Flush write to device */ |
| 257 | } else { |
| 258 | unsigned offset = data->irq - desc->irq; |
| 259 | msi_mask_irq(desc, 1 << offset, flag << offset); |
| 260 | } |
| 261 | } |
| 262 | |
| 263 | /** |
| 264 | * pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts |
| 265 | * @data: pointer to irqdata associated to that interrupt |
| 266 | */ |
| 267 | void pci_msi_mask_irq(struct irq_data *data) |
| 268 | { |
| 269 | msi_set_mask_bit(data, 1); |
| 270 | } |
| 271 | |
| 272 | /** |
| 273 | * pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts |
| 274 | * @data: pointer to irqdata associated to that interrupt |
| 275 | */ |
| 276 | void pci_msi_unmask_irq(struct irq_data *data) |
| 277 | { |
| 278 | msi_set_mask_bit(data, 0); |
| 279 | } |
| 280 | |
| 281 | void default_restore_msi_irqs(struct pci_dev *dev) |
| 282 | { |
| 283 | struct msi_desc *entry; |
| 284 | |
| 285 | list_for_each_entry(entry, &dev->msi_list, list) |
| 286 | default_restore_msi_irq(dev, entry->irq); |
| 287 | } |
| 288 | |
| 289 | void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
| 290 | { |
| 291 | BUG_ON(entry->dev->current_state != PCI_D0); |
| 292 | |
| 293 | if (entry->msi_attrib.is_msix) { |
| 294 | void __iomem *base = entry->mask_base + |
| 295 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; |
| 296 | |
| 297 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); |
| 298 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); |
| 299 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); |
| 300 | } else { |
| 301 | struct pci_dev *dev = entry->dev; |
| 302 | int pos = dev->msi_cap; |
| 303 | u16 data; |
| 304 | |
| 305 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
| 306 | &msg->address_lo); |
| 307 | if (entry->msi_attrib.is_64) { |
| 308 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
| 309 | &msg->address_hi); |
| 310 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
| 311 | } else { |
| 312 | msg->address_hi = 0; |
| 313 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
| 314 | } |
| 315 | msg->data = data; |
| 316 | } |
| 317 | } |
| 318 | |
| 319 | void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
| 320 | { |
| 321 | if (entry->dev->current_state != PCI_D0) { |
| 322 | /* Don't touch the hardware now */ |
| 323 | } else if (entry->msi_attrib.is_msix) { |
| 324 | void __iomem *base; |
| 325 | base = entry->mask_base + |
| 326 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; |
| 327 | |
| 328 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
| 329 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); |
| 330 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); |
| 331 | } else { |
| 332 | struct pci_dev *dev = entry->dev; |
| 333 | int pos = dev->msi_cap; |
| 334 | u16 msgctl; |
| 335 | |
| 336 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
| 337 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
| 338 | msgctl |= entry->msi_attrib.multiple << 4; |
| 339 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
| 340 | |
| 341 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
| 342 | msg->address_lo); |
| 343 | if (entry->msi_attrib.is_64) { |
| 344 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
| 345 | msg->address_hi); |
| 346 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
| 347 | msg->data); |
| 348 | } else { |
| 349 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
| 350 | msg->data); |
| 351 | } |
| 352 | } |
| 353 | entry->msg = *msg; |
| 354 | } |
| 355 | |
| 356 | void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg) |
| 357 | { |
| 358 | struct msi_desc *entry = irq_get_msi_desc(irq); |
| 359 | |
| 360 | __pci_write_msi_msg(entry, msg); |
| 361 | } |
| 362 | EXPORT_SYMBOL_GPL(pci_write_msi_msg); |
| 363 | |
| 364 | static void free_msi_irqs(struct pci_dev *dev) |
| 365 | { |
| 366 | struct msi_desc *entry, *tmp; |
| 367 | struct attribute **msi_attrs; |
| 368 | struct device_attribute *dev_attr; |
| 369 | int i, count = 0; |
| 370 | |
| 371 | list_for_each_entry(entry, &dev->msi_list, list) |
| 372 | if (entry->irq) |
| 373 | for (i = 0; i < entry->nvec_used; i++) |
| 374 | BUG_ON(irq_has_action(entry->irq + i)); |
| 375 | |
| 376 | pci_msi_teardown_msi_irqs(dev); |
| 377 | |
| 378 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { |
| 379 | if (entry->msi_attrib.is_msix) { |
| 380 | if (list_is_last(&entry->list, &dev->msi_list)) |
| 381 | iounmap(entry->mask_base); |
| 382 | } |
| 383 | |
| 384 | list_del(&entry->list); |
| 385 | kfree(entry); |
| 386 | } |
| 387 | |
| 388 | if (dev->msi_irq_groups) { |
| 389 | sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups); |
| 390 | msi_attrs = dev->msi_irq_groups[0]->attrs; |
| 391 | while (msi_attrs[count]) { |
| 392 | dev_attr = container_of(msi_attrs[count], |
| 393 | struct device_attribute, attr); |
| 394 | kfree(dev_attr->attr.name); |
| 395 | kfree(dev_attr); |
| 396 | ++count; |
| 397 | } |
| 398 | kfree(msi_attrs); |
| 399 | kfree(dev->msi_irq_groups[0]); |
| 400 | kfree(dev->msi_irq_groups); |
| 401 | dev->msi_irq_groups = NULL; |
| 402 | } |
| 403 | } |
| 404 | |
| 405 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
| 406 | { |
| 407 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
| 408 | if (!desc) |
| 409 | return NULL; |
| 410 | |
| 411 | INIT_LIST_HEAD(&desc->list); |
| 412 | desc->dev = dev; |
| 413 | |
| 414 | return desc; |
| 415 | } |
| 416 | |
| 417 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
| 418 | { |
| 419 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) |
| 420 | pci_intx(dev, enable); |
| 421 | } |
| 422 | |
| 423 | static void __pci_restore_msi_state(struct pci_dev *dev) |
| 424 | { |
| 425 | u16 control; |
| 426 | struct msi_desc *entry; |
| 427 | |
| 428 | if (!dev->msi_enabled) |
| 429 | return; |
| 430 | |
| 431 | entry = irq_get_msi_desc(dev->irq); |
| 432 | |
| 433 | pci_intx_for_msi(dev, 0); |
| 434 | pci_msi_set_enable(dev, 0); |
| 435 | arch_restore_msi_irqs(dev); |
| 436 | |
| 437 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
| 438 | msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap), |
| 439 | entry->masked); |
| 440 | control &= ~PCI_MSI_FLAGS_QSIZE; |
| 441 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
| 442 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
| 443 | } |
| 444 | |
| 445 | static void __pci_restore_msix_state(struct pci_dev *dev) |
| 446 | { |
| 447 | struct msi_desc *entry; |
| 448 | |
| 449 | if (!dev->msix_enabled) |
| 450 | return; |
| 451 | BUG_ON(list_empty(&dev->msi_list)); |
| 452 | |
| 453 | /* route the table */ |
| 454 | pci_intx_for_msi(dev, 0); |
| 455 | pci_msix_clear_and_set_ctrl(dev, 0, |
| 456 | PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL); |
| 457 | |
| 458 | arch_restore_msi_irqs(dev); |
| 459 | list_for_each_entry(entry, &dev->msi_list, list) |
| 460 | msix_mask_irq(entry, entry->masked); |
| 461 | |
| 462 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
| 463 | } |
| 464 | |
| 465 | void pci_restore_msi_state(struct pci_dev *dev) |
| 466 | { |
| 467 | __pci_restore_msi_state(dev); |
| 468 | __pci_restore_msix_state(dev); |
| 469 | } |
| 470 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
| 471 | |
| 472 | static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr, |
| 473 | char *buf) |
| 474 | { |
| 475 | struct msi_desc *entry; |
| 476 | unsigned long irq; |
| 477 | int retval; |
| 478 | |
| 479 | retval = kstrtoul(attr->attr.name, 10, &irq); |
| 480 | if (retval) |
| 481 | return retval; |
| 482 | |
| 483 | entry = irq_get_msi_desc(irq); |
| 484 | if (entry) |
| 485 | return sprintf(buf, "%s\n", |
| 486 | entry->msi_attrib.is_msix ? "msix" : "msi"); |
| 487 | |
| 488 | return -ENODEV; |
| 489 | } |
| 490 | |
| 491 | static int populate_msi_sysfs(struct pci_dev *pdev) |
| 492 | { |
| 493 | struct attribute **msi_attrs; |
| 494 | struct attribute *msi_attr; |
| 495 | struct device_attribute *msi_dev_attr; |
| 496 | struct attribute_group *msi_irq_group; |
| 497 | const struct attribute_group **msi_irq_groups; |
| 498 | struct msi_desc *entry; |
| 499 | int ret = -ENOMEM; |
| 500 | int num_msi = 0; |
| 501 | int count = 0; |
| 502 | |
| 503 | /* Determine how many msi entries we have */ |
| 504 | list_for_each_entry(entry, &pdev->msi_list, list) |
| 505 | ++num_msi; |
| 506 | if (!num_msi) |
| 507 | return 0; |
| 508 | |
| 509 | /* Dynamically create the MSI attributes for the PCI device */ |
| 510 | msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL); |
| 511 | if (!msi_attrs) |
| 512 | return -ENOMEM; |
| 513 | list_for_each_entry(entry, &pdev->msi_list, list) { |
| 514 | msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL); |
| 515 | if (!msi_dev_attr) |
| 516 | goto error_attrs; |
| 517 | msi_attrs[count] = &msi_dev_attr->attr; |
| 518 | |
| 519 | sysfs_attr_init(&msi_dev_attr->attr); |
| 520 | msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d", |
| 521 | entry->irq); |
| 522 | if (!msi_dev_attr->attr.name) |
| 523 | goto error_attrs; |
| 524 | msi_dev_attr->attr.mode = S_IRUGO; |
| 525 | msi_dev_attr->show = msi_mode_show; |
| 526 | ++count; |
| 527 | } |
| 528 | |
| 529 | msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL); |
| 530 | if (!msi_irq_group) |
| 531 | goto error_attrs; |
| 532 | msi_irq_group->name = "msi_irqs"; |
| 533 | msi_irq_group->attrs = msi_attrs; |
| 534 | |
| 535 | msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL); |
| 536 | if (!msi_irq_groups) |
| 537 | goto error_irq_group; |
| 538 | msi_irq_groups[0] = msi_irq_group; |
| 539 | |
| 540 | ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups); |
| 541 | if (ret) |
| 542 | goto error_irq_groups; |
| 543 | pdev->msi_irq_groups = msi_irq_groups; |
| 544 | |
| 545 | return 0; |
| 546 | |
| 547 | error_irq_groups: |
| 548 | kfree(msi_irq_groups); |
| 549 | error_irq_group: |
| 550 | kfree(msi_irq_group); |
| 551 | error_attrs: |
| 552 | count = 0; |
| 553 | msi_attr = msi_attrs[count]; |
| 554 | while (msi_attr) { |
| 555 | msi_dev_attr = container_of(msi_attr, struct device_attribute, attr); |
| 556 | kfree(msi_attr->name); |
| 557 | kfree(msi_dev_attr); |
| 558 | ++count; |
| 559 | msi_attr = msi_attrs[count]; |
| 560 | } |
| 561 | kfree(msi_attrs); |
| 562 | return ret; |
| 563 | } |
| 564 | |
| 565 | static struct msi_desc *msi_setup_entry(struct pci_dev *dev, int nvec) |
| 566 | { |
| 567 | u16 control; |
| 568 | struct msi_desc *entry; |
| 569 | |
| 570 | /* MSI Entry Initialization */ |
| 571 | entry = alloc_msi_entry(dev); |
| 572 | if (!entry) |
| 573 | return NULL; |
| 574 | |
| 575 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
| 576 | |
| 577 | entry->msi_attrib.is_msix = 0; |
| 578 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); |
| 579 | entry->msi_attrib.entry_nr = 0; |
| 580 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); |
| 581 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
| 582 | entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1; |
| 583 | entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec)); |
| 584 | entry->nvec_used = nvec; |
| 585 | |
| 586 | if (control & PCI_MSI_FLAGS_64BIT) |
| 587 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; |
| 588 | else |
| 589 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; |
| 590 | |
| 591 | /* Save the initial mask status */ |
| 592 | if (entry->msi_attrib.maskbit) |
| 593 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); |
| 594 | |
| 595 | return entry; |
| 596 | } |
| 597 | |
| 598 | static int msi_verify_entries(struct pci_dev *dev) |
| 599 | { |
| 600 | struct msi_desc *entry; |
| 601 | |
| 602 | list_for_each_entry(entry, &dev->msi_list, list) { |
| 603 | if (!dev->no_64bit_msi || !entry->msg.address_hi) |
| 604 | continue; |
| 605 | dev_err(&dev->dev, "Device has broken 64-bit MSI but arch" |
| 606 | " tried to assign one above 4G\n"); |
| 607 | return -EIO; |
| 608 | } |
| 609 | return 0; |
| 610 | } |
| 611 | |
| 612 | /** |
| 613 | * msi_capability_init - configure device's MSI capability structure |
| 614 | * @dev: pointer to the pci_dev data structure of MSI device function |
| 615 | * @nvec: number of interrupts to allocate |
| 616 | * |
| 617 | * Setup the MSI capability structure of the device with the requested |
| 618 | * number of interrupts. A return value of zero indicates the successful |
| 619 | * setup of an entry with the new MSI irq. A negative return value indicates |
| 620 | * an error, and a positive return value indicates the number of interrupts |
| 621 | * which could have been allocated. |
| 622 | */ |
| 623 | static int msi_capability_init(struct pci_dev *dev, int nvec) |
| 624 | { |
| 625 | struct msi_desc *entry; |
| 626 | int ret; |
| 627 | unsigned mask; |
| 628 | |
| 629 | pci_msi_set_enable(dev, 0); /* Disable MSI during set up */ |
| 630 | |
| 631 | entry = msi_setup_entry(dev, nvec); |
| 632 | if (!entry) |
| 633 | return -ENOMEM; |
| 634 | |
| 635 | /* All MSIs are unmasked by default, Mask them all */ |
| 636 | mask = msi_mask(entry->msi_attrib.multi_cap); |
| 637 | msi_mask_irq(entry, mask, mask); |
| 638 | |
| 639 | list_add_tail(&entry->list, &dev->msi_list); |
| 640 | |
| 641 | /* Configure MSI capability structure */ |
| 642 | ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
| 643 | if (ret) { |
| 644 | msi_mask_irq(entry, mask, ~mask); |
| 645 | free_msi_irqs(dev); |
| 646 | return ret; |
| 647 | } |
| 648 | |
| 649 | ret = msi_verify_entries(dev); |
| 650 | if (ret) { |
| 651 | msi_mask_irq(entry, mask, ~mask); |
| 652 | free_msi_irqs(dev); |
| 653 | return ret; |
| 654 | } |
| 655 | |
| 656 | ret = populate_msi_sysfs(dev); |
| 657 | if (ret) { |
| 658 | msi_mask_irq(entry, mask, ~mask); |
| 659 | free_msi_irqs(dev); |
| 660 | return ret; |
| 661 | } |
| 662 | |
| 663 | /* Set MSI enabled bits */ |
| 664 | pci_intx_for_msi(dev, 0); |
| 665 | pci_msi_set_enable(dev, 1); |
| 666 | dev->msi_enabled = 1; |
| 667 | |
| 668 | dev->irq = entry->irq; |
| 669 | return 0; |
| 670 | } |
| 671 | |
| 672 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
| 673 | { |
| 674 | resource_size_t phys_addr; |
| 675 | u32 table_offset; |
| 676 | unsigned long flags; |
| 677 | u8 bir; |
| 678 | |
| 679 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
| 680 | &table_offset); |
| 681 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
| 682 | flags = pci_resource_flags(dev, bir); |
| 683 | if (!flags || (flags & IORESOURCE_UNSET)) |
| 684 | return NULL; |
| 685 | |
| 686 | table_offset &= PCI_MSIX_TABLE_OFFSET; |
| 687 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
| 688 | |
| 689 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
| 690 | } |
| 691 | |
| 692 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
| 693 | struct msix_entry *entries, int nvec) |
| 694 | { |
| 695 | struct msi_desc *entry; |
| 696 | int i; |
| 697 | |
| 698 | for (i = 0; i < nvec; i++) { |
| 699 | entry = alloc_msi_entry(dev); |
| 700 | if (!entry) { |
| 701 | if (!i) |
| 702 | iounmap(base); |
| 703 | else |
| 704 | free_msi_irqs(dev); |
| 705 | /* No enough memory. Don't try again */ |
| 706 | return -ENOMEM; |
| 707 | } |
| 708 | |
| 709 | entry->msi_attrib.is_msix = 1; |
| 710 | entry->msi_attrib.is_64 = 1; |
| 711 | entry->msi_attrib.entry_nr = entries[i].entry; |
| 712 | entry->msi_attrib.default_irq = dev->irq; |
| 713 | entry->mask_base = base; |
| 714 | entry->nvec_used = 1; |
| 715 | |
| 716 | list_add_tail(&entry->list, &dev->msi_list); |
| 717 | } |
| 718 | |
| 719 | return 0; |
| 720 | } |
| 721 | |
| 722 | static void msix_program_entries(struct pci_dev *dev, |
| 723 | struct msix_entry *entries) |
| 724 | { |
| 725 | struct msi_desc *entry; |
| 726 | int i = 0; |
| 727 | |
| 728 | list_for_each_entry(entry, &dev->msi_list, list) { |
| 729 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + |
| 730 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
| 731 | |
| 732 | entries[i].vector = entry->irq; |
| 733 | entry->masked = readl(entry->mask_base + offset); |
| 734 | msix_mask_irq(entry, 1); |
| 735 | i++; |
| 736 | } |
| 737 | } |
| 738 | |
| 739 | /** |
| 740 | * msix_capability_init - configure device's MSI-X capability |
| 741 | * @dev: pointer to the pci_dev data structure of MSI-X device function |
| 742 | * @entries: pointer to an array of struct msix_entry entries |
| 743 | * @nvec: number of @entries |
| 744 | * |
| 745 | * Setup the MSI-X capability structure of device function with a |
| 746 | * single MSI-X irq. A return of zero indicates the successful setup of |
| 747 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. |
| 748 | **/ |
| 749 | static int msix_capability_init(struct pci_dev *dev, |
| 750 | struct msix_entry *entries, int nvec) |
| 751 | { |
| 752 | int ret; |
| 753 | u16 control; |
| 754 | void __iomem *base; |
| 755 | |
| 756 | /* Ensure MSI-X is disabled while it is set up */ |
| 757 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
| 758 | |
| 759 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
| 760 | /* Request & Map MSI-X table region */ |
| 761 | base = msix_map_region(dev, msix_table_size(control)); |
| 762 | if (!base) |
| 763 | return -ENOMEM; |
| 764 | |
| 765 | ret = msix_setup_entries(dev, base, entries, nvec); |
| 766 | if (ret) |
| 767 | return ret; |
| 768 | |
| 769 | ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); |
| 770 | if (ret) |
| 771 | goto out_avail; |
| 772 | |
| 773 | /* Check if all MSI entries honor device restrictions */ |
| 774 | ret = msi_verify_entries(dev); |
| 775 | if (ret) |
| 776 | goto out_free; |
| 777 | |
| 778 | /* |
| 779 | * Some devices require MSI-X to be enabled before we can touch the |
| 780 | * MSI-X registers. We need to mask all the vectors to prevent |
| 781 | * interrupts coming in before they're fully set up. |
| 782 | */ |
| 783 | pci_msix_clear_and_set_ctrl(dev, 0, |
| 784 | PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE); |
| 785 | |
| 786 | msix_program_entries(dev, entries); |
| 787 | |
| 788 | ret = populate_msi_sysfs(dev); |
| 789 | if (ret) |
| 790 | goto out_free; |
| 791 | |
| 792 | /* Set MSI-X enabled bits and unmask the function */ |
| 793 | pci_intx_for_msi(dev, 0); |
| 794 | dev->msix_enabled = 1; |
| 795 | |
| 796 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
| 797 | |
| 798 | return 0; |
| 799 | |
| 800 | out_avail: |
| 801 | if (ret < 0) { |
| 802 | /* |
| 803 | * If we had some success, report the number of irqs |
| 804 | * we succeeded in setting up. |
| 805 | */ |
| 806 | struct msi_desc *entry; |
| 807 | int avail = 0; |
| 808 | |
| 809 | list_for_each_entry(entry, &dev->msi_list, list) { |
| 810 | if (entry->irq != 0) |
| 811 | avail++; |
| 812 | } |
| 813 | if (avail != 0) |
| 814 | ret = avail; |
| 815 | } |
| 816 | |
| 817 | out_free: |
| 818 | free_msi_irqs(dev); |
| 819 | |
| 820 | return ret; |
| 821 | } |
| 822 | |
| 823 | /** |
| 824 | * pci_msi_supported - check whether MSI may be enabled on a device |
| 825 | * @dev: pointer to the pci_dev data structure of MSI device function |
| 826 | * @nvec: how many MSIs have been requested ? |
| 827 | * |
| 828 | * Look at global flags, the device itself, and its parent buses |
| 829 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
| 830 | * supported return 1, else return 0. |
| 831 | **/ |
| 832 | static int pci_msi_supported(struct pci_dev *dev, int nvec) |
| 833 | { |
| 834 | struct pci_bus *bus; |
| 835 | |
| 836 | /* MSI must be globally enabled and supported by the device */ |
| 837 | if (!pci_msi_enable) |
| 838 | return 0; |
| 839 | |
| 840 | if (!dev || dev->no_msi || dev->current_state != PCI_D0) |
| 841 | return 0; |
| 842 | |
| 843 | /* |
| 844 | * You can't ask to have 0 or less MSIs configured. |
| 845 | * a) it's stupid .. |
| 846 | * b) the list manipulation code assumes nvec >= 1. |
| 847 | */ |
| 848 | if (nvec < 1) |
| 849 | return 0; |
| 850 | |
| 851 | /* |
| 852 | * Any bridge which does NOT route MSI transactions from its |
| 853 | * secondary bus to its primary bus must set NO_MSI flag on |
| 854 | * the secondary pci_bus. |
| 855 | * We expect only arch-specific PCI host bus controller driver |
| 856 | * or quirks for specific PCI bridges to be setting NO_MSI. |
| 857 | */ |
| 858 | for (bus = dev->bus; bus; bus = bus->parent) |
| 859 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) |
| 860 | return 0; |
| 861 | |
| 862 | return 1; |
| 863 | } |
| 864 | |
| 865 | /** |
| 866 | * pci_msi_vec_count - Return the number of MSI vectors a device can send |
| 867 | * @dev: device to report about |
| 868 | * |
| 869 | * This function returns the number of MSI vectors a device requested via |
| 870 | * Multiple Message Capable register. It returns a negative errno if the |
| 871 | * device is not capable sending MSI interrupts. Otherwise, the call succeeds |
| 872 | * and returns a power of two, up to a maximum of 2^5 (32), according to the |
| 873 | * MSI specification. |
| 874 | **/ |
| 875 | int pci_msi_vec_count(struct pci_dev *dev) |
| 876 | { |
| 877 | int ret; |
| 878 | u16 msgctl; |
| 879 | |
| 880 | if (!dev->msi_cap) |
| 881 | return -EINVAL; |
| 882 | |
| 883 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); |
| 884 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); |
| 885 | |
| 886 | return ret; |
| 887 | } |
| 888 | EXPORT_SYMBOL(pci_msi_vec_count); |
| 889 | |
| 890 | void pci_msi_shutdown(struct pci_dev *dev) |
| 891 | { |
| 892 | struct msi_desc *desc; |
| 893 | u32 mask; |
| 894 | |
| 895 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
| 896 | return; |
| 897 | |
| 898 | BUG_ON(list_empty(&dev->msi_list)); |
| 899 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); |
| 900 | |
| 901 | pci_msi_set_enable(dev, 0); |
| 902 | pci_intx_for_msi(dev, 1); |
| 903 | dev->msi_enabled = 0; |
| 904 | |
| 905 | /* Return the device with MSI unmasked as initial states */ |
| 906 | mask = msi_mask(desc->msi_attrib.multi_cap); |
| 907 | /* Keep cached state to be restored */ |
| 908 | __pci_msi_desc_mask_irq(desc, mask, ~mask); |
| 909 | |
| 910 | /* Restore dev->irq to its default pin-assertion irq */ |
| 911 | dev->irq = desc->msi_attrib.default_irq; |
| 912 | } |
| 913 | |
| 914 | void pci_disable_msi(struct pci_dev *dev) |
| 915 | { |
| 916 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
| 917 | return; |
| 918 | |
| 919 | pci_msi_shutdown(dev); |
| 920 | free_msi_irqs(dev); |
| 921 | } |
| 922 | EXPORT_SYMBOL(pci_disable_msi); |
| 923 | |
| 924 | /** |
| 925 | * pci_msix_vec_count - return the number of device's MSI-X table entries |
| 926 | * @dev: pointer to the pci_dev data structure of MSI-X device function |
| 927 | * This function returns the number of device's MSI-X table entries and |
| 928 | * therefore the number of MSI-X vectors device is capable of sending. |
| 929 | * It returns a negative errno if the device is not capable of sending MSI-X |
| 930 | * interrupts. |
| 931 | **/ |
| 932 | int pci_msix_vec_count(struct pci_dev *dev) |
| 933 | { |
| 934 | u16 control; |
| 935 | |
| 936 | if (!dev->msix_cap) |
| 937 | return -EINVAL; |
| 938 | |
| 939 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
| 940 | return msix_table_size(control); |
| 941 | } |
| 942 | EXPORT_SYMBOL(pci_msix_vec_count); |
| 943 | |
| 944 | /** |
| 945 | * pci_enable_msix - configure device's MSI-X capability structure |
| 946 | * @dev: pointer to the pci_dev data structure of MSI-X device function |
| 947 | * @entries: pointer to an array of MSI-X entries |
| 948 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
| 949 | * |
| 950 | * Setup the MSI-X capability structure of device function with the number |
| 951 | * of requested irqs upon its software driver call to request for |
| 952 | * MSI-X mode enabled on its hardware device function. A return of zero |
| 953 | * indicates the successful configuration of MSI-X capability structure |
| 954 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
| 955 | * Or a return of > 0 indicates that driver request is exceeding the number |
| 956 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
| 957 | * re-send its request. |
| 958 | **/ |
| 959 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
| 960 | { |
| 961 | int nr_entries; |
| 962 | int i, j; |
| 963 | |
| 964 | if (!pci_msi_supported(dev, nvec)) |
| 965 | return -EINVAL; |
| 966 | |
| 967 | if (!entries) |
| 968 | return -EINVAL; |
| 969 | |
| 970 | nr_entries = pci_msix_vec_count(dev); |
| 971 | if (nr_entries < 0) |
| 972 | return nr_entries; |
| 973 | if (nvec > nr_entries) |
| 974 | return nr_entries; |
| 975 | |
| 976 | /* Check for any invalid entries */ |
| 977 | for (i = 0; i < nvec; i++) { |
| 978 | if (entries[i].entry >= nr_entries) |
| 979 | return -EINVAL; /* invalid entry */ |
| 980 | for (j = i + 1; j < nvec; j++) { |
| 981 | if (entries[i].entry == entries[j].entry) |
| 982 | return -EINVAL; /* duplicate entry */ |
| 983 | } |
| 984 | } |
| 985 | WARN_ON(!!dev->msix_enabled); |
| 986 | |
| 987 | /* Check whether driver already requested for MSI irq */ |
| 988 | if (dev->msi_enabled) { |
| 989 | dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n"); |
| 990 | return -EINVAL; |
| 991 | } |
| 992 | return msix_capability_init(dev, entries, nvec); |
| 993 | } |
| 994 | EXPORT_SYMBOL(pci_enable_msix); |
| 995 | |
| 996 | void pci_msix_shutdown(struct pci_dev *dev) |
| 997 | { |
| 998 | struct msi_desc *entry; |
| 999 | |
| 1000 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
| 1001 | return; |
| 1002 | |
| 1003 | /* Return the device with MSI-X masked as initial states */ |
| 1004 | list_for_each_entry(entry, &dev->msi_list, list) { |
| 1005 | /* Keep cached states to be restored */ |
| 1006 | __pci_msix_desc_mask_irq(entry, 1); |
| 1007 | } |
| 1008 | |
| 1009 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
| 1010 | pci_intx_for_msi(dev, 1); |
| 1011 | dev->msix_enabled = 0; |
| 1012 | } |
| 1013 | |
| 1014 | void pci_disable_msix(struct pci_dev *dev) |
| 1015 | { |
| 1016 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
| 1017 | return; |
| 1018 | |
| 1019 | pci_msix_shutdown(dev); |
| 1020 | free_msi_irqs(dev); |
| 1021 | } |
| 1022 | EXPORT_SYMBOL(pci_disable_msix); |
| 1023 | |
| 1024 | void pci_no_msi(void) |
| 1025 | { |
| 1026 | pci_msi_enable = 0; |
| 1027 | } |
| 1028 | |
| 1029 | /** |
| 1030 | * pci_msi_enabled - is MSI enabled? |
| 1031 | * |
| 1032 | * Returns true if MSI has not been disabled by the command-line option |
| 1033 | * pci=nomsi. |
| 1034 | **/ |
| 1035 | int pci_msi_enabled(void) |
| 1036 | { |
| 1037 | return pci_msi_enable; |
| 1038 | } |
| 1039 | EXPORT_SYMBOL(pci_msi_enabled); |
| 1040 | |
| 1041 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
| 1042 | { |
| 1043 | INIT_LIST_HEAD(&dev->msi_list); |
| 1044 | } |
| 1045 | |
| 1046 | /** |
| 1047 | * pci_enable_msi_range - configure device's MSI capability structure |
| 1048 | * @dev: device to configure |
| 1049 | * @minvec: minimal number of interrupts to configure |
| 1050 | * @maxvec: maximum number of interrupts to configure |
| 1051 | * |
| 1052 | * This function tries to allocate a maximum possible number of interrupts in a |
| 1053 | * range between @minvec and @maxvec. It returns a negative errno if an error |
| 1054 | * occurs. If it succeeds, it returns the actual number of interrupts allocated |
| 1055 | * and updates the @dev's irq member to the lowest new interrupt number; |
| 1056 | * the other interrupt numbers allocated to this device are consecutive. |
| 1057 | **/ |
| 1058 | int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec) |
| 1059 | { |
| 1060 | int nvec; |
| 1061 | int rc; |
| 1062 | |
| 1063 | if (!pci_msi_supported(dev, minvec)) |
| 1064 | return -EINVAL; |
| 1065 | |
| 1066 | WARN_ON(!!dev->msi_enabled); |
| 1067 | |
| 1068 | /* Check whether driver already requested MSI-X irqs */ |
| 1069 | if (dev->msix_enabled) { |
| 1070 | dev_info(&dev->dev, |
| 1071 | "can't enable MSI (MSI-X already enabled)\n"); |
| 1072 | return -EINVAL; |
| 1073 | } |
| 1074 | |
| 1075 | if (maxvec < minvec) |
| 1076 | return -ERANGE; |
| 1077 | |
| 1078 | nvec = pci_msi_vec_count(dev); |
| 1079 | if (nvec < 0) |
| 1080 | return nvec; |
| 1081 | else if (nvec < minvec) |
| 1082 | return -EINVAL; |
| 1083 | else if (nvec > maxvec) |
| 1084 | nvec = maxvec; |
| 1085 | |
| 1086 | do { |
| 1087 | rc = msi_capability_init(dev, nvec); |
| 1088 | if (rc < 0) { |
| 1089 | return rc; |
| 1090 | } else if (rc > 0) { |
| 1091 | if (rc < minvec) |
| 1092 | return -ENOSPC; |
| 1093 | nvec = rc; |
| 1094 | } |
| 1095 | } while (rc); |
| 1096 | |
| 1097 | return nvec; |
| 1098 | } |
| 1099 | EXPORT_SYMBOL(pci_enable_msi_range); |
| 1100 | |
| 1101 | /** |
| 1102 | * pci_enable_msix_range - configure device's MSI-X capability structure |
| 1103 | * @dev: pointer to the pci_dev data structure of MSI-X device function |
| 1104 | * @entries: pointer to an array of MSI-X entries |
| 1105 | * @minvec: minimum number of MSI-X irqs requested |
| 1106 | * @maxvec: maximum number of MSI-X irqs requested |
| 1107 | * |
| 1108 | * Setup the MSI-X capability structure of device function with a maximum |
| 1109 | * possible number of interrupts in the range between @minvec and @maxvec |
| 1110 | * upon its software driver call to request for MSI-X mode enabled on its |
| 1111 | * hardware device function. It returns a negative errno if an error occurs. |
| 1112 | * If it succeeds, it returns the actual number of interrupts allocated and |
| 1113 | * indicates the successful configuration of MSI-X capability structure |
| 1114 | * with new allocated MSI-X interrupts. |
| 1115 | **/ |
| 1116 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, |
| 1117 | int minvec, int maxvec) |
| 1118 | { |
| 1119 | int nvec = maxvec; |
| 1120 | int rc; |
| 1121 | |
| 1122 | if (maxvec < minvec) |
| 1123 | return -ERANGE; |
| 1124 | |
| 1125 | do { |
| 1126 | rc = pci_enable_msix(dev, entries, nvec); |
| 1127 | if (rc < 0) { |
| 1128 | return rc; |
| 1129 | } else if (rc > 0) { |
| 1130 | if (rc < minvec) |
| 1131 | return -ENOSPC; |
| 1132 | nvec = rc; |
| 1133 | } |
| 1134 | } while (rc); |
| 1135 | |
| 1136 | return nvec; |
| 1137 | } |
| 1138 | EXPORT_SYMBOL(pci_enable_msix_range); |
| 1139 | |
| 1140 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
| 1141 | /** |
| 1142 | * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space |
| 1143 | * @irq_data: Pointer to interrupt data of the MSI interrupt |
| 1144 | * @msg: Pointer to the message |
| 1145 | */ |
| 1146 | void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg) |
| 1147 | { |
| 1148 | struct msi_desc *desc = irq_data->msi_desc; |
| 1149 | |
| 1150 | /* |
| 1151 | * For MSI-X desc->irq is always equal to irq_data->irq. For |
| 1152 | * MSI only the first interrupt of MULTI MSI passes the test. |
| 1153 | */ |
| 1154 | if (desc->irq == irq_data->irq) |
| 1155 | __pci_write_msi_msg(desc, msg); |
| 1156 | } |
| 1157 | |
| 1158 | /** |
| 1159 | * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source |
| 1160 | * @dev: Pointer to the PCI device |
| 1161 | * @desc: Pointer to the msi descriptor |
| 1162 | * |
| 1163 | * The ID number is only used within the irqdomain. |
| 1164 | */ |
| 1165 | irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev, |
| 1166 | struct msi_desc *desc) |
| 1167 | { |
| 1168 | return (irq_hw_number_t)desc->msi_attrib.entry_nr | |
| 1169 | PCI_DEVID(dev->bus->number, dev->devfn) << 11 | |
| 1170 | (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27; |
| 1171 | } |
| 1172 | |
| 1173 | static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc) |
| 1174 | { |
| 1175 | return !desc->msi_attrib.is_msix && desc->nvec_used > 1; |
| 1176 | } |
| 1177 | |
| 1178 | /** |
| 1179 | * pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev |
| 1180 | * @domain: The interrupt domain to check |
| 1181 | * @info: The domain info for verification |
| 1182 | * @dev: The device to check |
| 1183 | * |
| 1184 | * Returns: |
| 1185 | * 0 if the functionality is supported |
| 1186 | * 1 if Multi MSI is requested, but the domain does not support it |
| 1187 | * -ENOTSUPP otherwise |
| 1188 | */ |
| 1189 | int pci_msi_domain_check_cap(struct irq_domain *domain, |
| 1190 | struct msi_domain_info *info, struct device *dev) |
| 1191 | { |
| 1192 | struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev)); |
| 1193 | |
| 1194 | /* Special handling to support pci_enable_msi_range() */ |
| 1195 | if (pci_msi_desc_is_multi_msi(desc) && |
| 1196 | !(info->flags & MSI_FLAG_MULTI_PCI_MSI)) |
| 1197 | return 1; |
| 1198 | else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX)) |
| 1199 | return -ENOTSUPP; |
| 1200 | |
| 1201 | return 0; |
| 1202 | } |
| 1203 | |
| 1204 | static int pci_msi_domain_handle_error(struct irq_domain *domain, |
| 1205 | struct msi_desc *desc, int error) |
| 1206 | { |
| 1207 | /* Special handling to support pci_enable_msi_range() */ |
| 1208 | if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC) |
| 1209 | return 1; |
| 1210 | |
| 1211 | return error; |
| 1212 | } |
| 1213 | |
| 1214 | #ifdef GENERIC_MSI_DOMAIN_OPS |
| 1215 | static void pci_msi_domain_set_desc(msi_alloc_info_t *arg, |
| 1216 | struct msi_desc *desc) |
| 1217 | { |
| 1218 | arg->desc = desc; |
| 1219 | arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc), |
| 1220 | desc); |
| 1221 | } |
| 1222 | #else |
| 1223 | #define pci_msi_domain_set_desc NULL |
| 1224 | #endif |
| 1225 | |
| 1226 | static struct msi_domain_ops pci_msi_domain_ops_default = { |
| 1227 | .set_desc = pci_msi_domain_set_desc, |
| 1228 | .msi_check = pci_msi_domain_check_cap, |
| 1229 | .handle_error = pci_msi_domain_handle_error, |
| 1230 | }; |
| 1231 | |
| 1232 | static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info) |
| 1233 | { |
| 1234 | struct msi_domain_ops *ops = info->ops; |
| 1235 | |
| 1236 | if (ops == NULL) { |
| 1237 | info->ops = &pci_msi_domain_ops_default; |
| 1238 | } else { |
| 1239 | if (ops->set_desc == NULL) |
| 1240 | ops->set_desc = pci_msi_domain_set_desc; |
| 1241 | if (ops->msi_check == NULL) |
| 1242 | ops->msi_check = pci_msi_domain_check_cap; |
| 1243 | if (ops->handle_error == NULL) |
| 1244 | ops->handle_error = pci_msi_domain_handle_error; |
| 1245 | } |
| 1246 | } |
| 1247 | |
| 1248 | static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info) |
| 1249 | { |
| 1250 | struct irq_chip *chip = info->chip; |
| 1251 | |
| 1252 | BUG_ON(!chip); |
| 1253 | if (!chip->irq_write_msi_msg) |
| 1254 | chip->irq_write_msi_msg = pci_msi_domain_write_msg; |
| 1255 | } |
| 1256 | |
| 1257 | /** |
| 1258 | * pci_msi_create_irq_domain - Creat a MSI interrupt domain |
| 1259 | * @node: Optional device-tree node of the interrupt controller |
| 1260 | * @info: MSI domain info |
| 1261 | * @parent: Parent irq domain |
| 1262 | * |
| 1263 | * Updates the domain and chip ops and creates a MSI interrupt domain. |
| 1264 | * |
| 1265 | * Returns: |
| 1266 | * A domain pointer or NULL in case of failure. |
| 1267 | */ |
| 1268 | struct irq_domain *pci_msi_create_irq_domain(struct device_node *node, |
| 1269 | struct msi_domain_info *info, |
| 1270 | struct irq_domain *parent) |
| 1271 | { |
| 1272 | if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS) |
| 1273 | pci_msi_domain_update_dom_ops(info); |
| 1274 | if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS) |
| 1275 | pci_msi_domain_update_chip_ops(info); |
| 1276 | |
| 1277 | return msi_create_irq_domain(node, info, parent); |
| 1278 | } |
| 1279 | |
| 1280 | /** |
| 1281 | * pci_msi_domain_alloc_irqs - Allocate interrupts for @dev in @domain |
| 1282 | * @domain: The interrupt domain to allocate from |
| 1283 | * @dev: The device for which to allocate |
| 1284 | * @nvec: The number of interrupts to allocate |
| 1285 | * @type: Unused to allow simpler migration from the arch_XXX interfaces |
| 1286 | * |
| 1287 | * Returns: |
| 1288 | * A virtual interrupt number or an error code in case of failure |
| 1289 | */ |
| 1290 | int pci_msi_domain_alloc_irqs(struct irq_domain *domain, struct pci_dev *dev, |
| 1291 | int nvec, int type) |
| 1292 | { |
| 1293 | return msi_domain_alloc_irqs(domain, &dev->dev, nvec); |
| 1294 | } |
| 1295 | |
| 1296 | /** |
| 1297 | * pci_msi_domain_free_irqs - Free interrupts for @dev in @domain |
| 1298 | * @domain: The interrupt domain |
| 1299 | * @dev: The device for which to free interrupts |
| 1300 | */ |
| 1301 | void pci_msi_domain_free_irqs(struct irq_domain *domain, struct pci_dev *dev) |
| 1302 | { |
| 1303 | msi_domain_free_irqs(domain, &dev->dev); |
| 1304 | } |
| 1305 | |
| 1306 | /** |
| 1307 | * pci_msi_create_default_irq_domain - Create a default MSI interrupt domain |
| 1308 | * @node: Optional device-tree node of the interrupt controller |
| 1309 | * @info: MSI domain info |
| 1310 | * @parent: Parent irq domain |
| 1311 | * |
| 1312 | * Returns: A domain pointer or NULL in case of failure. If successful |
| 1313 | * the default PCI/MSI irqdomain pointer is updated. |
| 1314 | */ |
| 1315 | struct irq_domain *pci_msi_create_default_irq_domain(struct device_node *node, |
| 1316 | struct msi_domain_info *info, struct irq_domain *parent) |
| 1317 | { |
| 1318 | struct irq_domain *domain; |
| 1319 | |
| 1320 | mutex_lock(&pci_msi_domain_lock); |
| 1321 | if (pci_msi_default_domain) { |
| 1322 | pr_err("PCI: default irq domain for PCI MSI has already been created.\n"); |
| 1323 | domain = NULL; |
| 1324 | } else { |
| 1325 | domain = pci_msi_create_irq_domain(node, info, parent); |
| 1326 | pci_msi_default_domain = domain; |
| 1327 | } |
| 1328 | mutex_unlock(&pci_msi_domain_lock); |
| 1329 | |
| 1330 | return domain; |
| 1331 | } |
| 1332 | #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */ |