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cpufreq: governor: Always schedule work on the CPU running update
[deliverable/linux.git] / drivers / pci / pci.h
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1#ifndef DRIVERS_PCI_H
2#define DRIVERS_PCI_H
3
4#define PCI_CFG_SPACE_SIZE 256
5#define PCI_CFG_SPACE_EXP_SIZE 4096
6
7#define PCI_FIND_CAP_TTL 48
8
9extern const unsigned char pcie_link_speed[];
10
11bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
12
13/* Functions internal to the PCI core code */
14
15int pci_create_sysfs_dev_files(struct pci_dev *pdev);
16void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
17#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
18static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
19{ return; }
20static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
21{ return; }
22#else
23void pci_create_firmware_label_files(struct pci_dev *pdev);
24void pci_remove_firmware_label_files(struct pci_dev *pdev);
25#endif
26void pci_cleanup_rom(struct pci_dev *dev);
27#ifdef HAVE_PCI_MMAP
28enum pci_mmap_api {
29 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
30 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
31};
32int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
33 enum pci_mmap_api mmap_api);
34#endif
35int pci_probe_reset_function(struct pci_dev *dev);
36
37/**
38 * struct pci_platform_pm_ops - Firmware PM callbacks
39 *
40 * @is_manageable: returns 'true' if given device is power manageable by the
41 * platform firmware
42 *
43 * @set_state: invokes the platform firmware to set the device's power state
44 *
45 * @choose_state: returns PCI power state of given device preferred by the
46 * platform; to be used during system-wide transitions from a
47 * sleeping state to the working state and vice versa
48 *
49 * @sleep_wake: enables/disables the system wake up capability of given device
50 *
51 * @run_wake: enables/disables the platform to generate run-time wake-up events
52 * for given device (the device's wake-up capability has to be
53 * enabled by @sleep_wake for this feature to work)
54 *
55 * @need_resume: returns 'true' if the given device (which is currently
56 * suspended) needs to be resumed to be configured for system
57 * wakeup.
58 *
59 * If given platform is generally capable of power managing PCI devices, all of
60 * these callbacks are mandatory.
61 */
62struct pci_platform_pm_ops {
63 bool (*is_manageable)(struct pci_dev *dev);
64 int (*set_state)(struct pci_dev *dev, pci_power_t state);
65 pci_power_t (*choose_state)(struct pci_dev *dev);
66 int (*sleep_wake)(struct pci_dev *dev, bool enable);
67 int (*run_wake)(struct pci_dev *dev, bool enable);
68 bool (*need_resume)(struct pci_dev *dev);
69};
70
71int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
72void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
73void pci_power_up(struct pci_dev *dev);
74void pci_disable_enabled_device(struct pci_dev *dev);
75int pci_finish_runtime_suspend(struct pci_dev *dev);
76int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
77bool pci_dev_keep_suspended(struct pci_dev *dev);
78void pci_dev_complete_resume(struct pci_dev *pci_dev);
79void pci_config_pm_runtime_get(struct pci_dev *dev);
80void pci_config_pm_runtime_put(struct pci_dev *dev);
81void pci_pm_init(struct pci_dev *dev);
82void pci_ea_init(struct pci_dev *dev);
83void pci_allocate_cap_save_buffers(struct pci_dev *dev);
84void pci_free_cap_save_buffers(struct pci_dev *dev);
85
86static inline void pci_wakeup_event(struct pci_dev *dev)
87{
88 /* Wait 100 ms before the system can be put into a sleep state. */
89 pm_wakeup_event(&dev->dev, 100);
90}
91
92static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
93{
94 return !!(pci_dev->subordinate);
95}
96
97struct pci_vpd_ops {
98 ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
99 ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
100 void (*release)(struct pci_dev *dev);
101};
102
103struct pci_vpd {
104 unsigned int len;
105 const struct pci_vpd_ops *ops;
106 struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
107};
108
109int pci_vpd_pci22_init(struct pci_dev *dev);
110static inline void pci_vpd_release(struct pci_dev *dev)
111{
112 if (dev->vpd)
113 dev->vpd->ops->release(dev);
114}
115
116/* PCI /proc functions */
117#ifdef CONFIG_PROC_FS
118int pci_proc_attach_device(struct pci_dev *dev);
119int pci_proc_detach_device(struct pci_dev *dev);
120int pci_proc_detach_bus(struct pci_bus *bus);
121#else
122static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
123static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
124static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
125#endif
126
127/* Functions for PCI Hotplug drivers to use */
128int pci_hp_add_bridge(struct pci_dev *dev);
129
130#ifdef HAVE_PCI_LEGACY
131void pci_create_legacy_files(struct pci_bus *bus);
132void pci_remove_legacy_files(struct pci_bus *bus);
133#else
134static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
135static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
136#endif
137
138/* Lock for read/write access to pci device and bus lists */
139extern struct rw_semaphore pci_bus_sem;
140
141extern raw_spinlock_t pci_lock;
142
143extern unsigned int pci_pm_d3_delay;
144
145#ifdef CONFIG_PCI_MSI
146void pci_no_msi(void);
147#else
148static inline void pci_no_msi(void) { }
149#endif
150
151static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
152{
153 u16 control;
154
155 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
156 control &= ~PCI_MSI_FLAGS_ENABLE;
157 if (enable)
158 control |= PCI_MSI_FLAGS_ENABLE;
159 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
160}
161
162static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
163{
164 u16 ctrl;
165
166 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
167 ctrl &= ~clear;
168 ctrl |= set;
169 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
170}
171
172void pci_realloc_get_opt(char *);
173
174static inline int pci_no_d1d2(struct pci_dev *dev)
175{
176 unsigned int parent_dstates = 0;
177
178 if (dev->bus->self)
179 parent_dstates = dev->bus->self->no_d1d2;
180 return (dev->no_d1d2 || parent_dstates);
181
182}
183extern const struct attribute_group *pci_dev_groups[];
184extern const struct attribute_group *pcibus_groups[];
185extern struct device_type pci_dev_type;
186extern const struct attribute_group *pci_bus_groups[];
187
188
189/**
190 * pci_match_one_device - Tell if a PCI device structure has a matching
191 * PCI device id structure
192 * @id: single PCI device id structure to match
193 * @dev: the PCI device structure to match against
194 *
195 * Returns the matching pci_device_id structure or %NULL if there is no match.
196 */
197static inline const struct pci_device_id *
198pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
199{
200 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
201 (id->device == PCI_ANY_ID || id->device == dev->device) &&
202 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
203 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
204 !((id->class ^ dev->class) & id->class_mask))
205 return id;
206 return NULL;
207}
208
209/* PCI slot sysfs helper code */
210#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
211
212extern struct kset *pci_slots_kset;
213
214struct pci_slot_attribute {
215 struct attribute attr;
216 ssize_t (*show)(struct pci_slot *, char *);
217 ssize_t (*store)(struct pci_slot *, const char *, size_t);
218};
219#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
220
221enum pci_bar_type {
222 pci_bar_unknown, /* Standard PCI BAR probe */
223 pci_bar_io, /* An io port BAR */
224 pci_bar_mem32, /* A 32-bit memory BAR */
225 pci_bar_mem64, /* A 64-bit memory BAR */
226};
227
228bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
229 int crs_timeout);
230int pci_setup_device(struct pci_dev *dev);
231int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
232 struct resource *res, unsigned int reg);
233int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type);
234void pci_configure_ari(struct pci_dev *dev);
235void __pci_bus_size_bridges(struct pci_bus *bus,
236 struct list_head *realloc_head);
237void __pci_bus_assign_resources(const struct pci_bus *bus,
238 struct list_head *realloc_head,
239 struct list_head *fail_head);
240bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
241
242void pci_reassigndev_resource_alignment(struct pci_dev *dev);
243void pci_disable_bridge_window(struct pci_dev *dev);
244
245/* Single Root I/O Virtualization */
246struct pci_sriov {
247 int pos; /* capability position */
248 int nres; /* number of resources */
249 u32 cap; /* SR-IOV Capabilities */
250 u16 ctrl; /* SR-IOV Control */
251 u16 total_VFs; /* total VFs associated with the PF */
252 u16 initial_VFs; /* initial VFs associated with the PF */
253 u16 num_VFs; /* number of VFs available */
254 u16 offset; /* first VF Routing ID offset */
255 u16 stride; /* following VF stride */
256 u32 pgsz; /* page size for BAR alignment */
257 u8 link; /* Function Dependency Link */
258 u8 max_VF_buses; /* max buses consumed by VFs */
259 u16 driver_max_VFs; /* max num VFs driver supports */
260 struct pci_dev *dev; /* lowest numbered PF */
261 struct pci_dev *self; /* this PF */
262 struct mutex lock; /* lock for VF bus */
263 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
264};
265
266#ifdef CONFIG_PCI_ATS
267void pci_restore_ats_state(struct pci_dev *dev);
268#else
269static inline void pci_restore_ats_state(struct pci_dev *dev)
270{
271}
272#endif /* CONFIG_PCI_ATS */
273
274#ifdef CONFIG_PCI_IOV
275int pci_iov_init(struct pci_dev *dev);
276void pci_iov_release(struct pci_dev *dev);
277int pci_iov_resource_bar(struct pci_dev *dev, int resno);
278resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
279void pci_restore_iov_state(struct pci_dev *dev);
280int pci_iov_bus_range(struct pci_bus *bus);
281
282#else
283static inline int pci_iov_init(struct pci_dev *dev)
284{
285 return -ENODEV;
286}
287static inline void pci_iov_release(struct pci_dev *dev)
288
289{
290}
291static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno)
292{
293 return 0;
294}
295static inline void pci_restore_iov_state(struct pci_dev *dev)
296{
297}
298static inline int pci_iov_bus_range(struct pci_bus *bus)
299{
300 return 0;
301}
302
303#endif /* CONFIG_PCI_IOV */
304
305unsigned long pci_cardbus_resource_alignment(struct resource *);
306
307static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
308 struct resource *res)
309{
310#ifdef CONFIG_PCI_IOV
311 int resno = res - dev->resource;
312
313 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
314 return pci_sriov_resource_alignment(dev, resno);
315#endif
316 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
317 return pci_cardbus_resource_alignment(res);
318 return resource_alignment(res);
319}
320
321void pci_enable_acs(struct pci_dev *dev);
322
323struct pci_dev_reset_methods {
324 u16 vendor;
325 u16 device;
326 int (*reset)(struct pci_dev *dev, int probe);
327};
328
329#ifdef CONFIG_PCI_QUIRKS
330int pci_dev_specific_reset(struct pci_dev *dev, int probe);
331#else
332static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
333{
334 return -ENOTTY;
335}
336#endif
337
338#endif /* DRIVERS_PCI_H */
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