| 1 | /* |
| 2 | * SuperH Pin Function Controller Support |
| 3 | * |
| 4 | * Copyright (c) 2008 Magnus Damm |
| 5 | * |
| 6 | * This file is subject to the terms and conditions of the GNU General Public |
| 7 | * License. See the file "COPYING" in the main directory of this archive |
| 8 | * for more details. |
| 9 | */ |
| 10 | |
| 11 | #ifndef __SH_PFC_H |
| 12 | #define __SH_PFC_H |
| 13 | |
| 14 | #include <linux/bug.h> |
| 15 | #include <linux/stringify.h> |
| 16 | |
| 17 | enum { |
| 18 | PINMUX_TYPE_NONE, |
| 19 | PINMUX_TYPE_FUNCTION, |
| 20 | PINMUX_TYPE_GPIO, |
| 21 | PINMUX_TYPE_OUTPUT, |
| 22 | PINMUX_TYPE_INPUT, |
| 23 | }; |
| 24 | |
| 25 | #define SH_PFC_PIN_CFG_INPUT (1 << 0) |
| 26 | #define SH_PFC_PIN_CFG_OUTPUT (1 << 1) |
| 27 | #define SH_PFC_PIN_CFG_PULL_UP (1 << 2) |
| 28 | #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) |
| 29 | |
| 30 | struct sh_pfc_pin { |
| 31 | u16 pin; |
| 32 | u16 enum_id; |
| 33 | const char *name; |
| 34 | unsigned int configs; |
| 35 | }; |
| 36 | |
| 37 | #define SH_PFC_PIN_GROUP(n) \ |
| 38 | { \ |
| 39 | .name = #n, \ |
| 40 | .pins = n##_pins, \ |
| 41 | .mux = n##_mux, \ |
| 42 | .nr_pins = ARRAY_SIZE(n##_pins), \ |
| 43 | } |
| 44 | |
| 45 | struct sh_pfc_pin_group { |
| 46 | const char *name; |
| 47 | const unsigned int *pins; |
| 48 | const unsigned int *mux; |
| 49 | unsigned int nr_pins; |
| 50 | }; |
| 51 | |
| 52 | #define SH_PFC_FUNCTION(n) \ |
| 53 | { \ |
| 54 | .name = #n, \ |
| 55 | .groups = n##_groups, \ |
| 56 | .nr_groups = ARRAY_SIZE(n##_groups), \ |
| 57 | } |
| 58 | |
| 59 | struct sh_pfc_function { |
| 60 | const char *name; |
| 61 | const char * const *groups; |
| 62 | unsigned int nr_groups; |
| 63 | }; |
| 64 | |
| 65 | struct pinmux_func { |
| 66 | u16 enum_id; |
| 67 | const char *name; |
| 68 | }; |
| 69 | |
| 70 | struct pinmux_cfg_reg { |
| 71 | unsigned long reg, reg_width, field_width; |
| 72 | const u16 *enum_ids; |
| 73 | const unsigned long *var_field_width; |
| 74 | }; |
| 75 | |
| 76 | #define PINMUX_CFG_REG(name, r, r_width, f_width) \ |
| 77 | .reg = r, .reg_width = r_width, .field_width = f_width, \ |
| 78 | .enum_ids = (u16 [(r_width / f_width) * (1 << f_width)]) |
| 79 | |
| 80 | #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ |
| 81 | .reg = r, .reg_width = r_width, \ |
| 82 | .var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \ |
| 83 | .enum_ids = (u16 []) |
| 84 | |
| 85 | struct pinmux_data_reg { |
| 86 | unsigned long reg, reg_width; |
| 87 | const u16 *enum_ids; |
| 88 | }; |
| 89 | |
| 90 | #define PINMUX_DATA_REG(name, r, r_width) \ |
| 91 | .reg = r, .reg_width = r_width, \ |
| 92 | .enum_ids = (u16 [r_width]) \ |
| 93 | |
| 94 | struct pinmux_irq { |
| 95 | int irq; |
| 96 | unsigned short *gpios; |
| 97 | }; |
| 98 | |
| 99 | #define PINMUX_IRQ(irq_nr, ids...) \ |
| 100 | { .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } } \ |
| 101 | |
| 102 | struct pinmux_range { |
| 103 | u16 begin; |
| 104 | u16 end; |
| 105 | u16 force; |
| 106 | }; |
| 107 | |
| 108 | struct sh_pfc; |
| 109 | |
| 110 | struct sh_pfc_soc_operations { |
| 111 | int (*init)(struct sh_pfc *pfc); |
| 112 | void (*exit)(struct sh_pfc *pfc); |
| 113 | unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); |
| 114 | void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, |
| 115 | unsigned int bias); |
| 116 | }; |
| 117 | |
| 118 | struct sh_pfc_soc_info { |
| 119 | const char *name; |
| 120 | const struct sh_pfc_soc_operations *ops; |
| 121 | |
| 122 | struct pinmux_range input; |
| 123 | struct pinmux_range output; |
| 124 | struct pinmux_range function; |
| 125 | |
| 126 | const struct sh_pfc_pin *pins; |
| 127 | unsigned int nr_pins; |
| 128 | const struct sh_pfc_pin_group *groups; |
| 129 | unsigned int nr_groups; |
| 130 | const struct sh_pfc_function *functions; |
| 131 | unsigned int nr_functions; |
| 132 | |
| 133 | const struct pinmux_func *func_gpios; |
| 134 | unsigned int nr_func_gpios; |
| 135 | |
| 136 | const struct pinmux_cfg_reg *cfg_regs; |
| 137 | const struct pinmux_data_reg *data_regs; |
| 138 | |
| 139 | const u16 *gpio_data; |
| 140 | unsigned int gpio_data_size; |
| 141 | |
| 142 | const struct pinmux_irq *gpio_irq; |
| 143 | unsigned int gpio_irq_size; |
| 144 | |
| 145 | unsigned long unlock_reg; |
| 146 | }; |
| 147 | |
| 148 | /* ----------------------------------------------------------------------------- |
| 149 | * Helper macros to create pin and port lists |
| 150 | */ |
| 151 | |
| 152 | /* |
| 153 | * sh_pfc_soc_info gpio_data array macros |
| 154 | */ |
| 155 | |
| 156 | #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 |
| 157 | |
| 158 | #define PINMUX_IPSR_NOGP(ispr, fn) \ |
| 159 | PINMUX_DATA(fn##_MARK, FN_##fn) |
| 160 | #define PINMUX_IPSR_DATA(ipsr, fn) \ |
| 161 | PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr) |
| 162 | #define PINMUX_IPSR_NOGM(ispr, fn, ms) \ |
| 163 | PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms) |
| 164 | #define PINMUX_IPSR_MSEL(ipsr, fn, ms) \ |
| 165 | PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms) |
| 166 | #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) \ |
| 167 | PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn) |
| 168 | |
| 169 | /* |
| 170 | * GP port style (32 ports banks) |
| 171 | */ |
| 172 | |
| 173 | #define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx) |
| 174 | |
| 175 | #define PORT_GP_32(bank, fn, sfx) \ |
| 176 | PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ |
| 177 | PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ |
| 178 | PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ |
| 179 | PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ |
| 180 | PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ |
| 181 | PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ |
| 182 | PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ |
| 183 | PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ |
| 184 | PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ |
| 185 | PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ |
| 186 | PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ |
| 187 | PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ |
| 188 | PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ |
| 189 | PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \ |
| 190 | PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \ |
| 191 | PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx) |
| 192 | |
| 193 | #define PORT_GP_32_REV(bank, fn, sfx) \ |
| 194 | PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \ |
| 195 | PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \ |
| 196 | PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \ |
| 197 | PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \ |
| 198 | PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \ |
| 199 | PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \ |
| 200 | PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \ |
| 201 | PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \ |
| 202 | PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \ |
| 203 | PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \ |
| 204 | PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \ |
| 205 | PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \ |
| 206 | PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \ |
| 207 | PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \ |
| 208 | PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \ |
| 209 | PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx) |
| 210 | |
| 211 | /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */ |
| 212 | #define _GP_ALL(bank, pin, name, sfx) name##_##sfx |
| 213 | #define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str) |
| 214 | |
| 215 | /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ |
| 216 | #define _GP_GPIO(bank, _pin, _name, sfx) \ |
| 217 | [(bank * 32) + _pin] = { \ |
| 218 | .pin = (bank * 32) + _pin, \ |
| 219 | .name = __stringify(_name), \ |
| 220 | .enum_id = _name##_DATA, \ |
| 221 | } |
| 222 | #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) |
| 223 | |
| 224 | /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */ |
| 225 | #define _GP_DATA(bank, pin, name, sfx) PINMUX_DATA(name##_DATA, name##_FN) |
| 226 | #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) |
| 227 | |
| 228 | /* |
| 229 | * PORT style (linear pin space) |
| 230 | */ |
| 231 | |
| 232 | #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx) |
| 233 | |
| 234 | #define PORT_10(pn, fn, pfx, sfx) \ |
| 235 | PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \ |
| 236 | PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \ |
| 237 | PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \ |
| 238 | PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \ |
| 239 | PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx) |
| 240 | |
| 241 | #define PORT_90(pn, fn, pfx, sfx) \ |
| 242 | PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \ |
| 243 | PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \ |
| 244 | PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \ |
| 245 | PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \ |
| 246 | PORT_10(pn+90, fn, pfx##9, sfx) |
| 247 | |
| 248 | /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */ |
| 249 | #define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx |
| 250 | #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) |
| 251 | |
| 252 | /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */ |
| 253 | #define PINMUX_GPIO(_pin) \ |
| 254 | [GPIO_##_pin] = { \ |
| 255 | .pin = (u16)-1, \ |
| 256 | .name = __stringify(name), \ |
| 257 | .enum_id = _pin##_DATA, \ |
| 258 | } |
| 259 | |
| 260 | /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */ |
| 261 | #define SH_PFC_PIN_CFG(_pin, cfgs) \ |
| 262 | { \ |
| 263 | .pin = _pin, \ |
| 264 | .name = __stringify(PORT##_pin), \ |
| 265 | .enum_id = PORT##_pin##_DATA, \ |
| 266 | .configs = cfgs, \ |
| 267 | } |
| 268 | |
| 269 | /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0, |
| 270 | * PORT_name_OUT, PORT_name_IN marks |
| 271 | */ |
| 272 | #define _PORT_DATA(pn, pfx, sfx) \ |
| 273 | PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \ |
| 274 | PORT##pfx##_OUT, PORT##pfx##_IN) |
| 275 | #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) |
| 276 | |
| 277 | /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */ |
| 278 | #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ |
| 279 | [gpio - (base)] = { \ |
| 280 | .name = __stringify(gpio), \ |
| 281 | .enum_id = data_or_mark, \ |
| 282 | } |
| 283 | #define GPIO_FN(str) \ |
| 284 | PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) |
| 285 | |
| 286 | /* |
| 287 | * PORTnCR macro |
| 288 | */ |
| 289 | #define _PCRH(in, in_pd, in_pu, out) \ |
| 290 | 0, (out), (in), 0, \ |
| 291 | 0, 0, 0, 0, \ |
| 292 | 0, 0, (in_pd), 0, \ |
| 293 | 0, 0, (in_pu), 0 |
| 294 | |
| 295 | #define PORTCR(nr, reg) \ |
| 296 | { \ |
| 297 | PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ |
| 298 | _PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \ |
| 299 | PORT##nr##_IN_PU, PORT##nr##_OUT), \ |
| 300 | PORT##nr##_FN0, PORT##nr##_FN1, \ |
| 301 | PORT##nr##_FN2, PORT##nr##_FN3, \ |
| 302 | PORT##nr##_FN4, PORT##nr##_FN5, \ |
| 303 | PORT##nr##_FN6, PORT##nr##_FN7 } \ |
| 304 | } |
| 305 | |
| 306 | #endif /* __SH_PFC_H */ |