| 1 | /* |
| 2 | * Disk Array driver for HP Smart Array SAS controllers |
| 3 | * Copyright 2016 Microsemi Corporation |
| 4 | * Copyright 2014-2015 PMC-Sierra, Inc. |
| 5 | * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or |
| 14 | * NON INFRINGEMENT. See the GNU General Public License for more details. |
| 15 | * |
| 16 | * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com |
| 17 | * |
| 18 | */ |
| 19 | #ifndef HPSA_H |
| 20 | #define HPSA_H |
| 21 | |
| 22 | #include <scsi/scsicam.h> |
| 23 | |
| 24 | #define IO_OK 0 |
| 25 | #define IO_ERROR 1 |
| 26 | |
| 27 | struct ctlr_info; |
| 28 | |
| 29 | struct access_method { |
| 30 | void (*submit_command)(struct ctlr_info *h, |
| 31 | struct CommandList *c); |
| 32 | void (*set_intr_mask)(struct ctlr_info *h, unsigned long val); |
| 33 | bool (*intr_pending)(struct ctlr_info *h); |
| 34 | unsigned long (*command_completed)(struct ctlr_info *h, u8 q); |
| 35 | }; |
| 36 | |
| 37 | /* for SAS hosts and SAS expanders */ |
| 38 | struct hpsa_sas_node { |
| 39 | struct device *parent_dev; |
| 40 | struct list_head port_list_head; |
| 41 | }; |
| 42 | |
| 43 | struct hpsa_sas_port { |
| 44 | struct list_head port_list_entry; |
| 45 | u64 sas_address; |
| 46 | struct sas_port *port; |
| 47 | int next_phy_index; |
| 48 | struct list_head phy_list_head; |
| 49 | struct hpsa_sas_node *parent_node; |
| 50 | struct sas_rphy *rphy; |
| 51 | }; |
| 52 | |
| 53 | struct hpsa_sas_phy { |
| 54 | struct list_head phy_list_entry; |
| 55 | struct sas_phy *phy; |
| 56 | struct hpsa_sas_port *parent_port; |
| 57 | bool added_to_port; |
| 58 | }; |
| 59 | |
| 60 | struct hpsa_scsi_dev_t { |
| 61 | unsigned int devtype; |
| 62 | int bus, target, lun; /* as presented to the OS */ |
| 63 | unsigned char scsi3addr[8]; /* as presented to the HW */ |
| 64 | u8 physical_device : 1; |
| 65 | u8 expose_device; |
| 66 | u8 removed : 1; /* device is marked for death */ |
| 67 | #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" |
| 68 | unsigned char device_id[16]; /* from inquiry pg. 0x83 */ |
| 69 | u64 sas_address; |
| 70 | unsigned char vendor[8]; /* bytes 8-15 of inquiry data */ |
| 71 | unsigned char model[16]; /* bytes 16-31 of inquiry data */ |
| 72 | unsigned char raid_level; /* from inquiry page 0xC1 */ |
| 73 | unsigned char volume_offline; /* discovered via TUR or VPD */ |
| 74 | u16 queue_depth; /* max queue_depth for this device */ |
| 75 | atomic_t reset_cmds_out; /* Count of commands to-be affected */ |
| 76 | atomic_t ioaccel_cmds_out; /* Only used for physical devices |
| 77 | * counts commands sent to physical |
| 78 | * device via "ioaccel" path. |
| 79 | */ |
| 80 | u32 ioaccel_handle; |
| 81 | u8 active_path_index; |
| 82 | u8 path_map; |
| 83 | u8 bay; |
| 84 | u8 box[8]; |
| 85 | u16 phys_connector[8]; |
| 86 | int offload_config; /* I/O accel RAID offload configured */ |
| 87 | int offload_enabled; /* I/O accel RAID offload enabled */ |
| 88 | int offload_to_be_enabled; |
| 89 | int hba_ioaccel_enabled; |
| 90 | int offload_to_mirror; /* Send next I/O accelerator RAID |
| 91 | * offload request to mirror drive |
| 92 | */ |
| 93 | struct raid_map_data raid_map; /* I/O accelerator RAID map */ |
| 94 | |
| 95 | /* |
| 96 | * Pointers from logical drive map indices to the phys drives that |
| 97 | * make those logical drives. Note, multiple logical drives may |
| 98 | * share physical drives. You can have for instance 5 physical |
| 99 | * drives with 3 logical drives each using those same 5 physical |
| 100 | * disks. We need these pointers for counting i/o's out to physical |
| 101 | * devices in order to honor physical device queue depth limits. |
| 102 | */ |
| 103 | struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES]; |
| 104 | int nphysical_disks; |
| 105 | int supports_aborts; |
| 106 | struct hpsa_sas_port *sas_port; |
| 107 | int external; /* 1-from external array 0-not <0-unknown */ |
| 108 | }; |
| 109 | |
| 110 | struct reply_queue_buffer { |
| 111 | u64 *head; |
| 112 | size_t size; |
| 113 | u8 wraparound; |
| 114 | u32 current_entry; |
| 115 | dma_addr_t busaddr; |
| 116 | }; |
| 117 | |
| 118 | #pragma pack(1) |
| 119 | struct bmic_controller_parameters { |
| 120 | u8 led_flags; |
| 121 | u8 enable_command_list_verification; |
| 122 | u8 backed_out_write_drives; |
| 123 | u16 stripes_for_parity; |
| 124 | u8 parity_distribution_mode_flags; |
| 125 | u16 max_driver_requests; |
| 126 | u16 elevator_trend_count; |
| 127 | u8 disable_elevator; |
| 128 | u8 force_scan_complete; |
| 129 | u8 scsi_transfer_mode; |
| 130 | u8 force_narrow; |
| 131 | u8 rebuild_priority; |
| 132 | u8 expand_priority; |
| 133 | u8 host_sdb_asic_fix; |
| 134 | u8 pdpi_burst_from_host_disabled; |
| 135 | char software_name[64]; |
| 136 | char hardware_name[32]; |
| 137 | u8 bridge_revision; |
| 138 | u8 snapshot_priority; |
| 139 | u32 os_specific; |
| 140 | u8 post_prompt_timeout; |
| 141 | u8 automatic_drive_slamming; |
| 142 | u8 reserved1; |
| 143 | u8 nvram_flags; |
| 144 | u8 cache_nvram_flags; |
| 145 | u8 drive_config_flags; |
| 146 | u16 reserved2; |
| 147 | u8 temp_warning_level; |
| 148 | u8 temp_shutdown_level; |
| 149 | u8 temp_condition_reset; |
| 150 | u8 max_coalesce_commands; |
| 151 | u32 max_coalesce_delay; |
| 152 | u8 orca_password[4]; |
| 153 | u8 access_id[16]; |
| 154 | u8 reserved[356]; |
| 155 | }; |
| 156 | #pragma pack() |
| 157 | |
| 158 | struct ctlr_info { |
| 159 | int ctlr; |
| 160 | char devname[8]; |
| 161 | char *product_name; |
| 162 | struct pci_dev *pdev; |
| 163 | u32 board_id; |
| 164 | u64 sas_address; |
| 165 | void __iomem *vaddr; |
| 166 | unsigned long paddr; |
| 167 | int nr_cmds; /* Number of commands allowed on this controller */ |
| 168 | #define HPSA_CMDS_RESERVED_FOR_ABORTS 2 |
| 169 | #define HPSA_CMDS_RESERVED_FOR_DRIVER 1 |
| 170 | struct CfgTable __iomem *cfgtable; |
| 171 | int interrupts_enabled; |
| 172 | int max_commands; |
| 173 | atomic_t commands_outstanding; |
| 174 | # define PERF_MODE_INT 0 |
| 175 | # define DOORBELL_INT 1 |
| 176 | # define SIMPLE_MODE_INT 2 |
| 177 | # define MEMQ_MODE_INT 3 |
| 178 | unsigned int intr[MAX_REPLY_QUEUES]; |
| 179 | unsigned int msix_vector; |
| 180 | unsigned int msi_vector; |
| 181 | int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */ |
| 182 | struct access_method access; |
| 183 | |
| 184 | /* queue and queue Info */ |
| 185 | unsigned int Qdepth; |
| 186 | unsigned int maxSG; |
| 187 | spinlock_t lock; |
| 188 | int maxsgentries; |
| 189 | u8 max_cmd_sg_entries; |
| 190 | int chainsize; |
| 191 | struct SGDescriptor **cmd_sg_list; |
| 192 | struct ioaccel2_sg_element **ioaccel2_cmd_sg_list; |
| 193 | |
| 194 | /* pointers to command and error info pool */ |
| 195 | struct CommandList *cmd_pool; |
| 196 | dma_addr_t cmd_pool_dhandle; |
| 197 | struct io_accel1_cmd *ioaccel_cmd_pool; |
| 198 | dma_addr_t ioaccel_cmd_pool_dhandle; |
| 199 | struct io_accel2_cmd *ioaccel2_cmd_pool; |
| 200 | dma_addr_t ioaccel2_cmd_pool_dhandle; |
| 201 | struct ErrorInfo *errinfo_pool; |
| 202 | dma_addr_t errinfo_pool_dhandle; |
| 203 | unsigned long *cmd_pool_bits; |
| 204 | int scan_finished; |
| 205 | spinlock_t scan_lock; |
| 206 | wait_queue_head_t scan_wait_queue; |
| 207 | |
| 208 | struct Scsi_Host *scsi_host; |
| 209 | spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */ |
| 210 | int ndevices; /* number of used elements in .dev[] array. */ |
| 211 | struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES]; |
| 212 | /* |
| 213 | * Performant mode tables. |
| 214 | */ |
| 215 | u32 trans_support; |
| 216 | u32 trans_offset; |
| 217 | struct TransTable_struct __iomem *transtable; |
| 218 | unsigned long transMethod; |
| 219 | |
| 220 | /* cap concurrent passthrus at some reasonable maximum */ |
| 221 | #define HPSA_MAX_CONCURRENT_PASSTHRUS (10) |
| 222 | atomic_t passthru_cmds_avail; |
| 223 | |
| 224 | /* |
| 225 | * Performant mode completion buffers |
| 226 | */ |
| 227 | size_t reply_queue_size; |
| 228 | struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES]; |
| 229 | u8 nreply_queues; |
| 230 | u32 *blockFetchTable; |
| 231 | u32 *ioaccel1_blockFetchTable; |
| 232 | u32 *ioaccel2_blockFetchTable; |
| 233 | u32 __iomem *ioaccel2_bft2_regs; |
| 234 | unsigned char *hba_inquiry_data; |
| 235 | u32 driver_support; |
| 236 | u32 fw_support; |
| 237 | int ioaccel_support; |
| 238 | int ioaccel_maxsg; |
| 239 | u64 last_intr_timestamp; |
| 240 | u32 last_heartbeat; |
| 241 | u64 last_heartbeat_timestamp; |
| 242 | u32 heartbeat_sample_interval; |
| 243 | atomic_t firmware_flash_in_progress; |
| 244 | u32 __percpu *lockup_detected; |
| 245 | struct delayed_work monitor_ctlr_work; |
| 246 | struct delayed_work rescan_ctlr_work; |
| 247 | int remove_in_progress; |
| 248 | /* Address of h->q[x] is passed to intr handler to know which queue */ |
| 249 | u8 q[MAX_REPLY_QUEUES]; |
| 250 | char intrname[MAX_REPLY_QUEUES][16]; /* "hpsa0-msix00" names */ |
| 251 | u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */ |
| 252 | #define HPSATMF_BITS_SUPPORTED (1 << 0) |
| 253 | #define HPSATMF_PHYS_LUN_RESET (1 << 1) |
| 254 | #define HPSATMF_PHYS_NEX_RESET (1 << 2) |
| 255 | #define HPSATMF_PHYS_TASK_ABORT (1 << 3) |
| 256 | #define HPSATMF_PHYS_TSET_ABORT (1 << 4) |
| 257 | #define HPSATMF_PHYS_CLEAR_ACA (1 << 5) |
| 258 | #define HPSATMF_PHYS_CLEAR_TSET (1 << 6) |
| 259 | #define HPSATMF_PHYS_QRY_TASK (1 << 7) |
| 260 | #define HPSATMF_PHYS_QRY_TSET (1 << 8) |
| 261 | #define HPSATMF_PHYS_QRY_ASYNC (1 << 9) |
| 262 | #define HPSATMF_IOACCEL_ENABLED (1 << 15) |
| 263 | #define HPSATMF_MASK_SUPPORTED (1 << 16) |
| 264 | #define HPSATMF_LOG_LUN_RESET (1 << 17) |
| 265 | #define HPSATMF_LOG_NEX_RESET (1 << 18) |
| 266 | #define HPSATMF_LOG_TASK_ABORT (1 << 19) |
| 267 | #define HPSATMF_LOG_TSET_ABORT (1 << 20) |
| 268 | #define HPSATMF_LOG_CLEAR_ACA (1 << 21) |
| 269 | #define HPSATMF_LOG_CLEAR_TSET (1 << 22) |
| 270 | #define HPSATMF_LOG_QRY_TASK (1 << 23) |
| 271 | #define HPSATMF_LOG_QRY_TSET (1 << 24) |
| 272 | #define HPSATMF_LOG_QRY_ASYNC (1 << 25) |
| 273 | u32 events; |
| 274 | #define CTLR_STATE_CHANGE_EVENT (1 << 0) |
| 275 | #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1) |
| 276 | #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4) |
| 277 | #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5) |
| 278 | #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6) |
| 279 | #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30) |
| 280 | #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31) |
| 281 | |
| 282 | #define RESCAN_REQUIRED_EVENT_BITS \ |
| 283 | (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \ |
| 284 | CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \ |
| 285 | CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \ |
| 286 | CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \ |
| 287 | CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE) |
| 288 | spinlock_t offline_device_lock; |
| 289 | struct list_head offline_device_list; |
| 290 | int acciopath_status; |
| 291 | int drv_req_rescan; |
| 292 | int raid_offload_debug; |
| 293 | int discovery_polling; |
| 294 | struct ReportLUNdata *lastlogicals; |
| 295 | int needs_abort_tags_swizzled; |
| 296 | struct workqueue_struct *resubmit_wq; |
| 297 | struct workqueue_struct *rescan_ctlr_wq; |
| 298 | atomic_t abort_cmds_available; |
| 299 | wait_queue_head_t abort_cmd_wait_queue; |
| 300 | wait_queue_head_t event_sync_wait_queue; |
| 301 | struct mutex reset_mutex; |
| 302 | u8 reset_in_progress; |
| 303 | struct hpsa_sas_node *sas_host; |
| 304 | }; |
| 305 | |
| 306 | struct offline_device_entry { |
| 307 | unsigned char scsi3addr[8]; |
| 308 | struct list_head offline_list; |
| 309 | }; |
| 310 | |
| 311 | #define HPSA_ABORT_MSG 0 |
| 312 | #define HPSA_DEVICE_RESET_MSG 1 |
| 313 | #define HPSA_RESET_TYPE_CONTROLLER 0x00 |
| 314 | #define HPSA_RESET_TYPE_BUS 0x01 |
| 315 | #define HPSA_RESET_TYPE_TARGET 0x03 |
| 316 | #define HPSA_RESET_TYPE_LUN 0x04 |
| 317 | #define HPSA_PHYS_TARGET_RESET 0x99 /* not defined by cciss spec */ |
| 318 | #define HPSA_MSG_SEND_RETRY_LIMIT 10 |
| 319 | #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000) |
| 320 | |
| 321 | /* Maximum time in seconds driver will wait for command completions |
| 322 | * when polling before giving up. |
| 323 | */ |
| 324 | #define HPSA_MAX_POLL_TIME_SECS (20) |
| 325 | |
| 326 | /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines |
| 327 | * how many times to retry TEST UNIT READY on a device |
| 328 | * while waiting for it to become ready before giving up. |
| 329 | * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval |
| 330 | * between sending TURs while waiting for a device |
| 331 | * to become ready. |
| 332 | */ |
| 333 | #define HPSA_TUR_RETRY_LIMIT (20) |
| 334 | #define HPSA_MAX_WAIT_INTERVAL_SECS (30) |
| 335 | |
| 336 | /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board |
| 337 | * to become ready, in seconds, before giving up on it. |
| 338 | * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait |
| 339 | * between polling the board to see if it is ready, in |
| 340 | * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and |
| 341 | * HPSA_BOARD_READY_ITERATIONS are derived from those. |
| 342 | */ |
| 343 | #define HPSA_BOARD_READY_WAIT_SECS (120) |
| 344 | #define HPSA_BOARD_NOT_READY_WAIT_SECS (100) |
| 345 | #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100) |
| 346 | #define HPSA_BOARD_READY_POLL_INTERVAL \ |
| 347 | ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000) |
| 348 | #define HPSA_BOARD_READY_ITERATIONS \ |
| 349 | ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \ |
| 350 | HPSA_BOARD_READY_POLL_INTERVAL_MSECS) |
| 351 | #define HPSA_BOARD_NOT_READY_ITERATIONS \ |
| 352 | ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \ |
| 353 | HPSA_BOARD_READY_POLL_INTERVAL_MSECS) |
| 354 | #define HPSA_POST_RESET_PAUSE_MSECS (3000) |
| 355 | #define HPSA_POST_RESET_NOOP_RETRIES (12) |
| 356 | |
| 357 | /* Defining the diffent access_menthods */ |
| 358 | /* |
| 359 | * Memory mapped FIFO interface (SMART 53xx cards) |
| 360 | */ |
| 361 | #define SA5_DOORBELL 0x20 |
| 362 | #define SA5_REQUEST_PORT_OFFSET 0x40 |
| 363 | #define SA5_REQUEST_PORT64_LO_OFFSET 0xC0 |
| 364 | #define SA5_REQUEST_PORT64_HI_OFFSET 0xC4 |
| 365 | #define SA5_REPLY_INTR_MASK_OFFSET 0x34 |
| 366 | #define SA5_REPLY_PORT_OFFSET 0x44 |
| 367 | #define SA5_INTR_STATUS 0x30 |
| 368 | #define SA5_SCRATCHPAD_OFFSET 0xB0 |
| 369 | |
| 370 | #define SA5_CTCFG_OFFSET 0xB4 |
| 371 | #define SA5_CTMEM_OFFSET 0xB8 |
| 372 | |
| 373 | #define SA5_INTR_OFF 0x08 |
| 374 | #define SA5B_INTR_OFF 0x04 |
| 375 | #define SA5_INTR_PENDING 0x08 |
| 376 | #define SA5B_INTR_PENDING 0x04 |
| 377 | #define FIFO_EMPTY 0xffffffff |
| 378 | #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ |
| 379 | |
| 380 | #define HPSA_ERROR_BIT 0x02 |
| 381 | |
| 382 | /* Performant mode flags */ |
| 383 | #define SA5_PERF_INTR_PENDING 0x04 |
| 384 | #define SA5_PERF_INTR_OFF 0x05 |
| 385 | #define SA5_OUTDB_STATUS_PERF_BIT 0x01 |
| 386 | #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 |
| 387 | #define SA5_OUTDB_CLEAR 0xA0 |
| 388 | #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 |
| 389 | #define SA5_OUTDB_STATUS 0x9C |
| 390 | |
| 391 | |
| 392 | #define HPSA_INTR_ON 1 |
| 393 | #define HPSA_INTR_OFF 0 |
| 394 | |
| 395 | /* |
| 396 | * Inbound Post Queue offsets for IO Accelerator Mode 2 |
| 397 | */ |
| 398 | #define IOACCEL2_INBOUND_POSTQ_32 0x48 |
| 399 | #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0 |
| 400 | #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4 |
| 401 | |
| 402 | #define HPSA_PHYSICAL_DEVICE_BUS 0 |
| 403 | #define HPSA_RAID_VOLUME_BUS 1 |
| 404 | #define HPSA_EXTERNAL_RAID_VOLUME_BUS 2 |
| 405 | #define HPSA_HBA_BUS 0 |
| 406 | |
| 407 | /* |
| 408 | Send the command to the hardware |
| 409 | */ |
| 410 | static void SA5_submit_command(struct ctlr_info *h, |
| 411 | struct CommandList *c) |
| 412 | { |
| 413 | writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); |
| 414 | (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); |
| 415 | } |
| 416 | |
| 417 | static void SA5_submit_command_no_read(struct ctlr_info *h, |
| 418 | struct CommandList *c) |
| 419 | { |
| 420 | writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); |
| 421 | } |
| 422 | |
| 423 | static void SA5_submit_command_ioaccel2(struct ctlr_info *h, |
| 424 | struct CommandList *c) |
| 425 | { |
| 426 | writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); |
| 427 | } |
| 428 | |
| 429 | /* |
| 430 | * This card is the opposite of the other cards. |
| 431 | * 0 turns interrupts on... |
| 432 | * 0x08 turns them off... |
| 433 | */ |
| 434 | static void SA5_intr_mask(struct ctlr_info *h, unsigned long val) |
| 435 | { |
| 436 | if (val) { /* Turn interrupts on */ |
| 437 | h->interrupts_enabled = 1; |
| 438 | writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
| 439 | (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
| 440 | } else { /* Turn them off */ |
| 441 | h->interrupts_enabled = 0; |
| 442 | writel(SA5_INTR_OFF, |
| 443 | h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
| 444 | (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
| 445 | } |
| 446 | } |
| 447 | |
| 448 | static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val) |
| 449 | { |
| 450 | if (val) { /* turn on interrupts */ |
| 451 | h->interrupts_enabled = 1; |
| 452 | writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
| 453 | (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
| 454 | } else { |
| 455 | h->interrupts_enabled = 0; |
| 456 | writel(SA5_PERF_INTR_OFF, |
| 457 | h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
| 458 | (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
| 459 | } |
| 460 | } |
| 461 | |
| 462 | static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q) |
| 463 | { |
| 464 | struct reply_queue_buffer *rq = &h->reply_queue[q]; |
| 465 | unsigned long register_value = FIFO_EMPTY; |
| 466 | |
| 467 | /* msi auto clears the interrupt pending bit. */ |
| 468 | if (unlikely(!(h->msi_vector || h->msix_vector))) { |
| 469 | /* flush the controller write of the reply queue by reading |
| 470 | * outbound doorbell status register. |
| 471 | */ |
| 472 | (void) readl(h->vaddr + SA5_OUTDB_STATUS); |
| 473 | writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); |
| 474 | /* Do a read in order to flush the write to the controller |
| 475 | * (as per spec.) |
| 476 | */ |
| 477 | (void) readl(h->vaddr + SA5_OUTDB_STATUS); |
| 478 | } |
| 479 | |
| 480 | if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) { |
| 481 | register_value = rq->head[rq->current_entry]; |
| 482 | rq->current_entry++; |
| 483 | atomic_dec(&h->commands_outstanding); |
| 484 | } else { |
| 485 | register_value = FIFO_EMPTY; |
| 486 | } |
| 487 | /* Check for wraparound */ |
| 488 | if (rq->current_entry == h->max_commands) { |
| 489 | rq->current_entry = 0; |
| 490 | rq->wraparound ^= 1; |
| 491 | } |
| 492 | return register_value; |
| 493 | } |
| 494 | |
| 495 | /* |
| 496 | * returns value read from hardware. |
| 497 | * returns FIFO_EMPTY if there is nothing to read |
| 498 | */ |
| 499 | static unsigned long SA5_completed(struct ctlr_info *h, |
| 500 | __attribute__((unused)) u8 q) |
| 501 | { |
| 502 | unsigned long register_value |
| 503 | = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); |
| 504 | |
| 505 | if (register_value != FIFO_EMPTY) |
| 506 | atomic_dec(&h->commands_outstanding); |
| 507 | |
| 508 | #ifdef HPSA_DEBUG |
| 509 | if (register_value != FIFO_EMPTY) |
| 510 | dev_dbg(&h->pdev->dev, "Read %lx back from board\n", |
| 511 | register_value); |
| 512 | else |
| 513 | dev_dbg(&h->pdev->dev, "FIFO Empty read\n"); |
| 514 | #endif |
| 515 | |
| 516 | return register_value; |
| 517 | } |
| 518 | /* |
| 519 | * Returns true if an interrupt is pending.. |
| 520 | */ |
| 521 | static bool SA5_intr_pending(struct ctlr_info *h) |
| 522 | { |
| 523 | unsigned long register_value = |
| 524 | readl(h->vaddr + SA5_INTR_STATUS); |
| 525 | return register_value & SA5_INTR_PENDING; |
| 526 | } |
| 527 | |
| 528 | static bool SA5_performant_intr_pending(struct ctlr_info *h) |
| 529 | { |
| 530 | unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); |
| 531 | |
| 532 | if (!register_value) |
| 533 | return false; |
| 534 | |
| 535 | /* Read outbound doorbell to flush */ |
| 536 | register_value = readl(h->vaddr + SA5_OUTDB_STATUS); |
| 537 | return register_value & SA5_OUTDB_STATUS_PERF_BIT; |
| 538 | } |
| 539 | |
| 540 | #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100 |
| 541 | |
| 542 | static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h) |
| 543 | { |
| 544 | unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); |
| 545 | |
| 546 | return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ? |
| 547 | true : false; |
| 548 | } |
| 549 | |
| 550 | #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0 |
| 551 | #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8 |
| 552 | #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC |
| 553 | #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL |
| 554 | |
| 555 | static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q) |
| 556 | { |
| 557 | u64 register_value; |
| 558 | struct reply_queue_buffer *rq = &h->reply_queue[q]; |
| 559 | |
| 560 | BUG_ON(q >= h->nreply_queues); |
| 561 | |
| 562 | register_value = rq->head[rq->current_entry]; |
| 563 | if (register_value != IOACCEL_MODE1_REPLY_UNUSED) { |
| 564 | rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED; |
| 565 | if (++rq->current_entry == rq->size) |
| 566 | rq->current_entry = 0; |
| 567 | /* |
| 568 | * @todo |
| 569 | * |
| 570 | * Don't really need to write the new index after each command, |
| 571 | * but with current driver design this is easiest. |
| 572 | */ |
| 573 | wmb(); |
| 574 | writel((q << 24) | rq->current_entry, h->vaddr + |
| 575 | IOACCEL_MODE1_CONSUMER_INDEX); |
| 576 | atomic_dec(&h->commands_outstanding); |
| 577 | } |
| 578 | return (unsigned long) register_value; |
| 579 | } |
| 580 | |
| 581 | static struct access_method SA5_access = { |
| 582 | SA5_submit_command, |
| 583 | SA5_intr_mask, |
| 584 | SA5_intr_pending, |
| 585 | SA5_completed, |
| 586 | }; |
| 587 | |
| 588 | static struct access_method SA5_ioaccel_mode1_access = { |
| 589 | SA5_submit_command, |
| 590 | SA5_performant_intr_mask, |
| 591 | SA5_ioaccel_mode1_intr_pending, |
| 592 | SA5_ioaccel_mode1_completed, |
| 593 | }; |
| 594 | |
| 595 | static struct access_method SA5_ioaccel_mode2_access = { |
| 596 | SA5_submit_command_ioaccel2, |
| 597 | SA5_performant_intr_mask, |
| 598 | SA5_performant_intr_pending, |
| 599 | SA5_performant_completed, |
| 600 | }; |
| 601 | |
| 602 | static struct access_method SA5_performant_access = { |
| 603 | SA5_submit_command, |
| 604 | SA5_performant_intr_mask, |
| 605 | SA5_performant_intr_pending, |
| 606 | SA5_performant_completed, |
| 607 | }; |
| 608 | |
| 609 | static struct access_method SA5_performant_access_no_read = { |
| 610 | SA5_submit_command_no_read, |
| 611 | SA5_performant_intr_mask, |
| 612 | SA5_performant_intr_pending, |
| 613 | SA5_performant_completed, |
| 614 | }; |
| 615 | |
| 616 | struct board_type { |
| 617 | u32 board_id; |
| 618 | char *product_name; |
| 619 | struct access_method *access; |
| 620 | }; |
| 621 | |
| 622 | #endif /* HPSA_H */ |
| 623 | |