| 1 | /* |
| 2 | comedi/drivers/ni_labpc.c |
| 3 | Driver for National Instruments Lab-PC series boards and compatibles |
| 4 | Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net> |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 2 of the License, or |
| 9 | (at your option) any later version. |
| 10 | |
| 11 | This program is distributed in the hope that it will be useful, |
| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | GNU General Public License for more details. |
| 15 | |
| 16 | You should have received a copy of the GNU General Public License |
| 17 | along with this program; if not, write to the Free Software |
| 18 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 19 | |
| 20 | ************************************************************************ |
| 21 | */ |
| 22 | /* |
| 23 | Driver: ni_labpc |
| 24 | Description: National Instruments Lab-PC (& compatibles) |
| 25 | Author: Frank Mori Hess <fmhess@users.sourceforge.net> |
| 26 | Devices: [National Instruments] Lab-PC-1200 (labpc-1200), |
| 27 | Lab-PC-1200AI (labpc-1200ai), Lab-PC+ (lab-pc+), PCI-1200 (ni_labpc) |
| 28 | Status: works |
| 29 | |
| 30 | Tested with lab-pc-1200. For the older Lab-PC+, not all input ranges |
| 31 | and analog references will work, the available ranges/arefs will |
| 32 | depend on how you have configured the jumpers on your board |
| 33 | (see your owner's manual). |
| 34 | |
| 35 | Kernel-level ISA plug-and-play support for the lab-pc-1200 |
| 36 | boards has not |
| 37 | yet been added to the driver, mainly due to the fact that |
| 38 | I don't know the device id numbers. If you have one |
| 39 | of these boards, |
| 40 | please file a bug report at http://comedi.org/ |
| 41 | so I can get the necessary information from you. |
| 42 | |
| 43 | The 1200 series boards have onboard calibration dacs for correcting |
| 44 | analog input/output offsets and gains. The proper settings for these |
| 45 | caldacs are stored on the board's eeprom. To read the caldac values |
| 46 | from the eeprom and store them into a file that can be then be used by |
| 47 | comedilib, use the comedi_calibrate program. |
| 48 | |
| 49 | Configuration options - ISA boards: |
| 50 | [0] - I/O port base address |
| 51 | [1] - IRQ (optional, required for timed or externally triggered conversions) |
| 52 | [2] - DMA channel (optional) |
| 53 | |
| 54 | Configuration options - PCI boards: |
| 55 | [0] - bus (optional) |
| 56 | [1] - slot (optional) |
| 57 | |
| 58 | The Lab-pc+ has quirky chanlist requirements |
| 59 | when scanning multiple channels. Multiple channel scan |
| 60 | sequence must start at highest channel, then decrement down to |
| 61 | channel 0. The rest of the cards can scan down like lab-pc+ or scan |
| 62 | up from channel zero. Chanlists consisting of all one channel |
| 63 | are also legal, and allow you to pace conversions in bursts. |
| 64 | |
| 65 | */ |
| 66 | |
| 67 | /* |
| 68 | |
| 69 | NI manuals: |
| 70 | 341309a (labpc-1200 register manual) |
| 71 | 340914a (pci-1200) |
| 72 | 320502b (lab-pc+) |
| 73 | |
| 74 | */ |
| 75 | |
| 76 | #include <linux/interrupt.h> |
| 77 | #include <linux/slab.h> |
| 78 | #include <linux/io.h> |
| 79 | #include "../comedidev.h" |
| 80 | |
| 81 | #include <linux/delay.h> |
| 82 | #include <asm/dma.h> |
| 83 | |
| 84 | #include "8253.h" |
| 85 | #include "8255.h" |
| 86 | #include "mite.h" |
| 87 | #include "comedi_fc.h" |
| 88 | #include "ni_labpc.h" |
| 89 | |
| 90 | #define DRV_NAME "ni_labpc" |
| 91 | |
| 92 | /* size of io region used by board */ |
| 93 | #define LABPC_SIZE 32 |
| 94 | /* 2 MHz master clock */ |
| 95 | #define LABPC_TIMER_BASE 500 |
| 96 | |
| 97 | /* Registers for the lab-pc+ */ |
| 98 | |
| 99 | /* write-only registers */ |
| 100 | #define COMMAND1_REG 0x0 |
| 101 | #define ADC_GAIN_MASK (0x7 << 4) |
| 102 | #define ADC_CHAN_BITS(x) ((x) & 0x7) |
| 103 | /* enables multi channel scans */ |
| 104 | #define ADC_SCAN_EN_BIT 0x80 |
| 105 | #define COMMAND2_REG 0x1 |
| 106 | /* enable pretriggering (used in conjunction with SWTRIG) */ |
| 107 | #define PRETRIG_BIT 0x1 |
| 108 | /* enable paced conversions on external trigger */ |
| 109 | #define HWTRIG_BIT 0x2 |
| 110 | /* enable paced conversions */ |
| 111 | #define SWTRIG_BIT 0x4 |
| 112 | /* use two cascaded counters for pacing */ |
| 113 | #define CASCADE_BIT 0x8 |
| 114 | #define DAC_PACED_BIT(channel) (0x40 << ((channel) & 0x1)) |
| 115 | #define COMMAND3_REG 0x2 |
| 116 | /* enable dma transfers */ |
| 117 | #define DMA_EN_BIT 0x1 |
| 118 | /* enable interrupts for 8255 */ |
| 119 | #define DIO_INTR_EN_BIT 0x2 |
| 120 | /* enable dma terminal count interrupt */ |
| 121 | #define DMATC_INTR_EN_BIT 0x4 |
| 122 | /* enable timer interrupt */ |
| 123 | #define TIMER_INTR_EN_BIT 0x8 |
| 124 | /* enable error interrupt */ |
| 125 | #define ERR_INTR_EN_BIT 0x10 |
| 126 | /* enable fifo not empty interrupt */ |
| 127 | #define ADC_FNE_INTR_EN_BIT 0x20 |
| 128 | #define ADC_CONVERT_REG 0x3 |
| 129 | #define DAC_LSB_REG(channel) (0x4 + 2 * ((channel) & 0x1)) |
| 130 | #define DAC_MSB_REG(channel) (0x5 + 2 * ((channel) & 0x1)) |
| 131 | #define ADC_CLEAR_REG 0x8 |
| 132 | #define DMATC_CLEAR_REG 0xa |
| 133 | #define TIMER_CLEAR_REG 0xc |
| 134 | /* 1200 boards only */ |
| 135 | #define COMMAND6_REG 0xe |
| 136 | /* select ground or common-mode reference */ |
| 137 | #define ADC_COMMON_BIT 0x1 |
| 138 | /* adc unipolar */ |
| 139 | #define ADC_UNIP_BIT 0x2 |
| 140 | /* dac unipolar */ |
| 141 | #define DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1)) |
| 142 | /* enable fifo half full interrupt */ |
| 143 | #define ADC_FHF_INTR_EN_BIT 0x20 |
| 144 | /* enable interrupt on end of hardware count */ |
| 145 | #define A1_INTR_EN_BIT 0x40 |
| 146 | /* scan up from channel zero instead of down to zero */ |
| 147 | #define ADC_SCAN_UP_BIT 0x80 |
| 148 | #define COMMAND4_REG 0xf |
| 149 | /* enables 'interval' scanning */ |
| 150 | #define INTERVAL_SCAN_EN_BIT 0x1 |
| 151 | /* enables external signal on counter b1 output to trigger scan */ |
| 152 | #define EXT_SCAN_EN_BIT 0x2 |
| 153 | /* chooses direction (output or input) for EXTCONV* line */ |
| 154 | #define EXT_CONVERT_OUT_BIT 0x4 |
| 155 | /* chooses differential inputs for adc (in conjunction with board jumper) */ |
| 156 | #define ADC_DIFF_BIT 0x8 |
| 157 | #define EXT_CONVERT_DISABLE_BIT 0x10 |
| 158 | /* 1200 boards only, calibration stuff */ |
| 159 | #define COMMAND5_REG 0x1c |
| 160 | /* enable eeprom for write */ |
| 161 | #define EEPROM_WRITE_UNPROTECT_BIT 0x4 |
| 162 | /* enable dithering */ |
| 163 | #define DITHER_EN_BIT 0x8 |
| 164 | /* load calibration dac */ |
| 165 | #define CALDAC_LOAD_BIT 0x10 |
| 166 | /* serial clock - rising edge writes, falling edge reads */ |
| 167 | #define SCLOCK_BIT 0x20 |
| 168 | /* serial data bit for writing to eeprom or calibration dacs */ |
| 169 | #define SDATA_BIT 0x40 |
| 170 | /* enable eeprom for read/write */ |
| 171 | #define EEPROM_EN_BIT 0x80 |
| 172 | #define INTERVAL_COUNT_REG 0x1e |
| 173 | #define INTERVAL_LOAD_REG 0x1f |
| 174 | #define INTERVAL_LOAD_BITS 0x1 |
| 175 | |
| 176 | /* read-only registers */ |
| 177 | #define STATUS1_REG 0x0 |
| 178 | /* data is available in fifo */ |
| 179 | #define DATA_AVAIL_BIT 0x1 |
| 180 | /* overrun has occurred */ |
| 181 | #define OVERRUN_BIT 0x2 |
| 182 | /* fifo overflow */ |
| 183 | #define OVERFLOW_BIT 0x4 |
| 184 | /* timer interrupt has occurred */ |
| 185 | #define TIMER_BIT 0x8 |
| 186 | /* dma terminal count has occurred */ |
| 187 | #define DMATC_BIT 0x10 |
| 188 | /* external trigger has occurred */ |
| 189 | #define EXT_TRIG_BIT 0x40 |
| 190 | /* 1200 boards only */ |
| 191 | #define STATUS2_REG 0x1d |
| 192 | /* programmable eeprom serial output */ |
| 193 | #define EEPROM_OUT_BIT 0x1 |
| 194 | /* counter A1 terminal count */ |
| 195 | #define A1_TC_BIT 0x2 |
| 196 | /* fifo not half full */ |
| 197 | #define FNHF_BIT 0x4 |
| 198 | #define ADC_FIFO_REG 0xa |
| 199 | |
| 200 | #define DIO_BASE_REG 0x10 |
| 201 | #define COUNTER_A_BASE_REG 0x14 |
| 202 | #define COUNTER_A_CONTROL_REG (COUNTER_A_BASE_REG + 0x3) |
| 203 | /* check modes put conversion pacer output in harmless state (a0 mode 2) */ |
| 204 | #define INIT_A0_BITS 0x14 |
| 205 | /* put hardware conversion counter output in harmless state (a1 mode 0) */ |
| 206 | #define INIT_A1_BITS 0x70 |
| 207 | #define COUNTER_B_BASE_REG 0x18 |
| 208 | |
| 209 | enum scan_mode { |
| 210 | MODE_SINGLE_CHAN, |
| 211 | MODE_SINGLE_CHAN_INTERVAL, |
| 212 | MODE_MULT_CHAN_UP, |
| 213 | MODE_MULT_CHAN_DOWN, |
| 214 | }; |
| 215 | |
| 216 | static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s); |
| 217 | static irqreturn_t labpc_interrupt(int irq, void *d); |
| 218 | static int labpc_drain_fifo(struct comedi_device *dev); |
| 219 | #ifdef CONFIG_ISA_DMA_API |
| 220 | static void labpc_drain_dma(struct comedi_device *dev); |
| 221 | static void handle_isa_dma(struct comedi_device *dev); |
| 222 | #endif |
| 223 | static void labpc_drain_dregs(struct comedi_device *dev); |
| 224 | static int labpc_ai_cmdtest(struct comedi_device *dev, |
| 225 | struct comedi_subdevice *s, struct comedi_cmd *cmd); |
| 226 | static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s); |
| 227 | static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, |
| 228 | struct comedi_insn *insn, unsigned int *data); |
| 229 | static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, |
| 230 | struct comedi_insn *insn, unsigned int *data); |
| 231 | static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, |
| 232 | struct comedi_insn *insn, unsigned int *data); |
| 233 | static int labpc_calib_read_insn(struct comedi_device *dev, |
| 234 | struct comedi_subdevice *s, |
| 235 | struct comedi_insn *insn, unsigned int *data); |
| 236 | static int labpc_calib_write_insn(struct comedi_device *dev, |
| 237 | struct comedi_subdevice *s, |
| 238 | struct comedi_insn *insn, unsigned int *data); |
| 239 | static int labpc_eeprom_read_insn(struct comedi_device *dev, |
| 240 | struct comedi_subdevice *s, |
| 241 | struct comedi_insn *insn, unsigned int *data); |
| 242 | static int labpc_eeprom_write_insn(struct comedi_device *dev, |
| 243 | struct comedi_subdevice *s, |
| 244 | struct comedi_insn *insn, |
| 245 | unsigned int *data); |
| 246 | static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd, |
| 247 | enum scan_mode scan_mode); |
| 248 | #ifdef CONFIG_ISA_DMA_API |
| 249 | static unsigned int labpc_suggest_transfer_size(const struct comedi_cmd *cmd); |
| 250 | #endif |
| 251 | static int labpc_dio_mem_callback(int dir, int port, int data, |
| 252 | unsigned long arg); |
| 253 | static void labpc_serial_out(struct comedi_device *dev, unsigned int value, |
| 254 | unsigned int num_bits); |
| 255 | static unsigned int labpc_serial_in(struct comedi_device *dev); |
| 256 | static unsigned int labpc_eeprom_read(struct comedi_device *dev, |
| 257 | unsigned int address); |
| 258 | static unsigned int labpc_eeprom_read_status(struct comedi_device *dev); |
| 259 | static int labpc_eeprom_write(struct comedi_device *dev, |
| 260 | unsigned int address, |
| 261 | unsigned int value); |
| 262 | static void write_caldac(struct comedi_device *dev, unsigned int channel, |
| 263 | unsigned int value); |
| 264 | |
| 265 | /* analog input ranges */ |
| 266 | #define NUM_LABPC_PLUS_AI_RANGES 16 |
| 267 | /* indicates unipolar ranges */ |
| 268 | static const int labpc_plus_is_unipolar[NUM_LABPC_PLUS_AI_RANGES] = { |
| 269 | 0, |
| 270 | 0, |
| 271 | 0, |
| 272 | 0, |
| 273 | 0, |
| 274 | 0, |
| 275 | 0, |
| 276 | 0, |
| 277 | 1, |
| 278 | 1, |
| 279 | 1, |
| 280 | 1, |
| 281 | 1, |
| 282 | 1, |
| 283 | 1, |
| 284 | 1, |
| 285 | }; |
| 286 | |
| 287 | /* map range index to gain bits */ |
| 288 | static const int labpc_plus_ai_gain_bits[NUM_LABPC_PLUS_AI_RANGES] = { |
| 289 | 0x00, |
| 290 | 0x10, |
| 291 | 0x20, |
| 292 | 0x30, |
| 293 | 0x40, |
| 294 | 0x50, |
| 295 | 0x60, |
| 296 | 0x70, |
| 297 | 0x00, |
| 298 | 0x10, |
| 299 | 0x20, |
| 300 | 0x30, |
| 301 | 0x40, |
| 302 | 0x50, |
| 303 | 0x60, |
| 304 | 0x70, |
| 305 | }; |
| 306 | |
| 307 | static const struct comedi_lrange range_labpc_plus_ai = { |
| 308 | NUM_LABPC_PLUS_AI_RANGES, |
| 309 | { |
| 310 | BIP_RANGE(5), |
| 311 | BIP_RANGE(4), |
| 312 | BIP_RANGE(2.5), |
| 313 | BIP_RANGE(1), |
| 314 | BIP_RANGE(0.5), |
| 315 | BIP_RANGE(0.25), |
| 316 | BIP_RANGE(0.1), |
| 317 | BIP_RANGE(0.05), |
| 318 | UNI_RANGE(10), |
| 319 | UNI_RANGE(8), |
| 320 | UNI_RANGE(5), |
| 321 | UNI_RANGE(2), |
| 322 | UNI_RANGE(1), |
| 323 | UNI_RANGE(0.5), |
| 324 | UNI_RANGE(0.2), |
| 325 | UNI_RANGE(0.1), |
| 326 | } |
| 327 | }; |
| 328 | |
| 329 | #define NUM_LABPC_1200_AI_RANGES 14 |
| 330 | /* indicates unipolar ranges */ |
| 331 | const int labpc_1200_is_unipolar[NUM_LABPC_1200_AI_RANGES] = { |
| 332 | 0, |
| 333 | 0, |
| 334 | 0, |
| 335 | 0, |
| 336 | 0, |
| 337 | 0, |
| 338 | 0, |
| 339 | 1, |
| 340 | 1, |
| 341 | 1, |
| 342 | 1, |
| 343 | 1, |
| 344 | 1, |
| 345 | 1, |
| 346 | }; |
| 347 | EXPORT_SYMBOL_GPL(labpc_1200_is_unipolar); |
| 348 | |
| 349 | /* map range index to gain bits */ |
| 350 | const int labpc_1200_ai_gain_bits[NUM_LABPC_1200_AI_RANGES] = { |
| 351 | 0x00, |
| 352 | 0x20, |
| 353 | 0x30, |
| 354 | 0x40, |
| 355 | 0x50, |
| 356 | 0x60, |
| 357 | 0x70, |
| 358 | 0x00, |
| 359 | 0x20, |
| 360 | 0x30, |
| 361 | 0x40, |
| 362 | 0x50, |
| 363 | 0x60, |
| 364 | 0x70, |
| 365 | }; |
| 366 | EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits); |
| 367 | |
| 368 | const struct comedi_lrange range_labpc_1200_ai = { |
| 369 | NUM_LABPC_1200_AI_RANGES, |
| 370 | { |
| 371 | BIP_RANGE(5), |
| 372 | BIP_RANGE(2.5), |
| 373 | BIP_RANGE(1), |
| 374 | BIP_RANGE(0.5), |
| 375 | BIP_RANGE(0.25), |
| 376 | BIP_RANGE(0.1), |
| 377 | BIP_RANGE(0.05), |
| 378 | UNI_RANGE(10), |
| 379 | UNI_RANGE(5), |
| 380 | UNI_RANGE(2), |
| 381 | UNI_RANGE(1), |
| 382 | UNI_RANGE(0.5), |
| 383 | UNI_RANGE(0.2), |
| 384 | UNI_RANGE(0.1), |
| 385 | } |
| 386 | }; |
| 387 | EXPORT_SYMBOL_GPL(range_labpc_1200_ai); |
| 388 | |
| 389 | /* analog output ranges */ |
| 390 | #define AO_RANGE_IS_UNIPOLAR 0x1 |
| 391 | static const struct comedi_lrange range_labpc_ao = { |
| 392 | 2, |
| 393 | { |
| 394 | BIP_RANGE(5), |
| 395 | UNI_RANGE(10), |
| 396 | } |
| 397 | }; |
| 398 | |
| 399 | /* functions that do inb/outb and readb/writeb so we can use |
| 400 | * function pointers to decide which to use */ |
| 401 | static inline unsigned int labpc_inb(unsigned long address) |
| 402 | { |
| 403 | return inb(address); |
| 404 | } |
| 405 | |
| 406 | static inline void labpc_outb(unsigned int byte, unsigned long address) |
| 407 | { |
| 408 | outb(byte, address); |
| 409 | } |
| 410 | |
| 411 | static inline unsigned int labpc_readb(unsigned long address) |
| 412 | { |
| 413 | return readb((void __iomem *)address); |
| 414 | } |
| 415 | |
| 416 | static inline void labpc_writeb(unsigned int byte, unsigned long address) |
| 417 | { |
| 418 | writeb(byte, (void __iomem *)address); |
| 419 | } |
| 420 | |
| 421 | static const struct labpc_board_struct labpc_boards[] = { |
| 422 | { |
| 423 | .name = "lab-pc-1200", |
| 424 | .ai_speed = 10000, |
| 425 | .bustype = isa_bustype, |
| 426 | .register_layout = labpc_1200_layout, |
| 427 | .has_ao = 1, |
| 428 | .ai_range_table = &range_labpc_1200_ai, |
| 429 | .ai_range_code = labpc_1200_ai_gain_bits, |
| 430 | .ai_range_is_unipolar = labpc_1200_is_unipolar, |
| 431 | .ai_scan_up = 1, |
| 432 | .memory_mapped_io = 0, |
| 433 | }, |
| 434 | { |
| 435 | .name = "lab-pc-1200ai", |
| 436 | .ai_speed = 10000, |
| 437 | .bustype = isa_bustype, |
| 438 | .register_layout = labpc_1200_layout, |
| 439 | .has_ao = 0, |
| 440 | .ai_range_table = &range_labpc_1200_ai, |
| 441 | .ai_range_code = labpc_1200_ai_gain_bits, |
| 442 | .ai_range_is_unipolar = labpc_1200_is_unipolar, |
| 443 | .ai_scan_up = 1, |
| 444 | .memory_mapped_io = 0, |
| 445 | }, |
| 446 | { |
| 447 | .name = "lab-pc+", |
| 448 | .ai_speed = 12000, |
| 449 | .bustype = isa_bustype, |
| 450 | .register_layout = labpc_plus_layout, |
| 451 | .has_ao = 1, |
| 452 | .ai_range_table = &range_labpc_plus_ai, |
| 453 | .ai_range_code = labpc_plus_ai_gain_bits, |
| 454 | .ai_range_is_unipolar = labpc_plus_is_unipolar, |
| 455 | .ai_scan_up = 0, |
| 456 | .memory_mapped_io = 0, |
| 457 | }, |
| 458 | #ifdef CONFIG_COMEDI_PCI_DRIVERS |
| 459 | { |
| 460 | .name = "pci-1200", |
| 461 | .device_id = 0x161, |
| 462 | .ai_speed = 10000, |
| 463 | .bustype = pci_bustype, |
| 464 | .register_layout = labpc_1200_layout, |
| 465 | .has_ao = 1, |
| 466 | .ai_range_table = &range_labpc_1200_ai, |
| 467 | .ai_range_code = labpc_1200_ai_gain_bits, |
| 468 | .ai_range_is_unipolar = labpc_1200_is_unipolar, |
| 469 | .ai_scan_up = 1, |
| 470 | .memory_mapped_io = 1, |
| 471 | }, |
| 472 | /* dummy entry so pci board works when comedi_config is passed driver name */ |
| 473 | { |
| 474 | .name = DRV_NAME, |
| 475 | .bustype = pci_bustype, |
| 476 | }, |
| 477 | #endif |
| 478 | }; |
| 479 | |
| 480 | /* |
| 481 | * Useful for shorthand access to the particular board structure |
| 482 | */ |
| 483 | #define thisboard ((struct labpc_board_struct *)dev->board_ptr) |
| 484 | |
| 485 | /* size in bytes of dma buffer */ |
| 486 | static const int dma_buffer_size = 0xff00; |
| 487 | /* 2 bytes per sample */ |
| 488 | static const int sample_size = 2; |
| 489 | |
| 490 | static inline int labpc_counter_load(struct comedi_device *dev, |
| 491 | unsigned long base_address, |
| 492 | unsigned int counter_number, |
| 493 | unsigned int count, unsigned int mode) |
| 494 | { |
| 495 | if (thisboard->memory_mapped_io) |
| 496 | return i8254_mm_load((void __iomem *)base_address, 0, |
| 497 | counter_number, count, mode); |
| 498 | else |
| 499 | return i8254_load(base_address, 0, counter_number, count, mode); |
| 500 | } |
| 501 | |
| 502 | int labpc_common_attach(struct comedi_device *dev, unsigned long iobase, |
| 503 | unsigned int irq, unsigned int dma_chan) |
| 504 | { |
| 505 | struct labpc_private *devpriv = dev->private; |
| 506 | struct comedi_subdevice *s; |
| 507 | int i; |
| 508 | unsigned long isr_flags; |
| 509 | #ifdef CONFIG_ISA_DMA_API |
| 510 | unsigned long dma_flags; |
| 511 | #endif |
| 512 | short lsb, msb; |
| 513 | int ret; |
| 514 | |
| 515 | dev_info(dev->class_dev, "ni_labpc: %s\n", thisboard->name); |
| 516 | if (iobase == 0) { |
| 517 | dev_err(dev->class_dev, "io base address is zero!\n"); |
| 518 | return -EINVAL; |
| 519 | } |
| 520 | /* request io regions for isa boards */ |
| 521 | if (thisboard->bustype == isa_bustype) { |
| 522 | /* check if io addresses are available */ |
| 523 | if (!request_region(iobase, LABPC_SIZE, DRV_NAME)) { |
| 524 | dev_err(dev->class_dev, "I/O port conflict\n"); |
| 525 | return -EIO; |
| 526 | } |
| 527 | } |
| 528 | dev->iobase = iobase; |
| 529 | |
| 530 | if (thisboard->memory_mapped_io) { |
| 531 | devpriv->read_byte = labpc_readb; |
| 532 | devpriv->write_byte = labpc_writeb; |
| 533 | } else { |
| 534 | devpriv->read_byte = labpc_inb; |
| 535 | devpriv->write_byte = labpc_outb; |
| 536 | } |
| 537 | /* initialize board's command registers */ |
| 538 | devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); |
| 539 | devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); |
| 540 | devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); |
| 541 | devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); |
| 542 | if (thisboard->register_layout == labpc_1200_layout) { |
| 543 | devpriv->write_byte(devpriv->command5_bits, |
| 544 | dev->iobase + COMMAND5_REG); |
| 545 | devpriv->write_byte(devpriv->command6_bits, |
| 546 | dev->iobase + COMMAND6_REG); |
| 547 | } |
| 548 | |
| 549 | /* grab our IRQ */ |
| 550 | if (irq) { |
| 551 | isr_flags = 0; |
| 552 | if (thisboard->bustype == pci_bustype |
| 553 | || thisboard->bustype == pcmcia_bustype) |
| 554 | isr_flags |= IRQF_SHARED; |
| 555 | if (request_irq(irq, labpc_interrupt, isr_flags, |
| 556 | DRV_NAME, dev)) { |
| 557 | dev_err(dev->class_dev, "unable to allocate irq %u\n", |
| 558 | irq); |
| 559 | return -EINVAL; |
| 560 | } |
| 561 | } |
| 562 | dev->irq = irq; |
| 563 | |
| 564 | #ifdef CONFIG_ISA_DMA_API |
| 565 | /* grab dma channel */ |
| 566 | if (dma_chan > 3) { |
| 567 | dev_err(dev->class_dev, "invalid dma channel %u\n", dma_chan); |
| 568 | return -EINVAL; |
| 569 | } else if (dma_chan) { |
| 570 | /* allocate dma buffer */ |
| 571 | devpriv->dma_buffer = |
| 572 | kmalloc(dma_buffer_size, GFP_KERNEL | GFP_DMA); |
| 573 | if (devpriv->dma_buffer == NULL) { |
| 574 | dev_err(dev->class_dev, |
| 575 | "failed to allocate dma buffer\n"); |
| 576 | return -ENOMEM; |
| 577 | } |
| 578 | if (request_dma(dma_chan, DRV_NAME)) { |
| 579 | dev_err(dev->class_dev, |
| 580 | "failed to allocate dma channel %u\n", |
| 581 | dma_chan); |
| 582 | return -EINVAL; |
| 583 | } |
| 584 | devpriv->dma_chan = dma_chan; |
| 585 | dma_flags = claim_dma_lock(); |
| 586 | disable_dma(devpriv->dma_chan); |
| 587 | set_dma_mode(devpriv->dma_chan, DMA_MODE_READ); |
| 588 | release_dma_lock(dma_flags); |
| 589 | } |
| 590 | #endif |
| 591 | |
| 592 | dev->board_name = thisboard->name; |
| 593 | |
| 594 | ret = comedi_alloc_subdevices(dev, 5); |
| 595 | if (ret) |
| 596 | return ret; |
| 597 | |
| 598 | /* analog input subdevice */ |
| 599 | s = &dev->subdevices[0]; |
| 600 | dev->read_subdev = s; |
| 601 | s->type = COMEDI_SUBD_AI; |
| 602 | s->subdev_flags = |
| 603 | SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ; |
| 604 | s->n_chan = 8; |
| 605 | s->len_chanlist = 8; |
| 606 | s->maxdata = (1 << 12) - 1; /* 12 bit resolution */ |
| 607 | s->range_table = thisboard->ai_range_table; |
| 608 | s->do_cmd = labpc_ai_cmd; |
| 609 | s->do_cmdtest = labpc_ai_cmdtest; |
| 610 | s->insn_read = labpc_ai_rinsn; |
| 611 | s->cancel = labpc_cancel; |
| 612 | |
| 613 | /* analog output */ |
| 614 | s = &dev->subdevices[1]; |
| 615 | if (thisboard->has_ao) { |
| 616 | /* |
| 617 | * Could provide command support, except it only has a |
| 618 | * one sample hardware buffer for analog output and no |
| 619 | * underrun flag. |
| 620 | */ |
| 621 | s->type = COMEDI_SUBD_AO; |
| 622 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND; |
| 623 | s->n_chan = NUM_AO_CHAN; |
| 624 | s->maxdata = (1 << 12) - 1; /* 12 bit resolution */ |
| 625 | s->range_table = &range_labpc_ao; |
| 626 | s->insn_read = labpc_ao_rinsn; |
| 627 | s->insn_write = labpc_ao_winsn; |
| 628 | /* initialize analog outputs to a known value */ |
| 629 | for (i = 0; i < s->n_chan; i++) { |
| 630 | devpriv->ao_value[i] = s->maxdata / 2; |
| 631 | lsb = devpriv->ao_value[i] & 0xff; |
| 632 | msb = (devpriv->ao_value[i] >> 8) & 0xff; |
| 633 | devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i)); |
| 634 | devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i)); |
| 635 | } |
| 636 | } else { |
| 637 | s->type = COMEDI_SUBD_UNUSED; |
| 638 | } |
| 639 | |
| 640 | /* 8255 dio */ |
| 641 | s = &dev->subdevices[2]; |
| 642 | /* if board uses io memory we have to give a custom callback |
| 643 | * function to the 8255 driver */ |
| 644 | if (thisboard->memory_mapped_io) |
| 645 | subdev_8255_init(dev, s, labpc_dio_mem_callback, |
| 646 | (unsigned long)(dev->iobase + DIO_BASE_REG)); |
| 647 | else |
| 648 | subdev_8255_init(dev, s, NULL, dev->iobase + DIO_BASE_REG); |
| 649 | |
| 650 | /* calibration subdevices for boards that have one */ |
| 651 | s = &dev->subdevices[3]; |
| 652 | if (thisboard->register_layout == labpc_1200_layout) { |
| 653 | s->type = COMEDI_SUBD_CALIB; |
| 654 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; |
| 655 | s->n_chan = 16; |
| 656 | s->maxdata = 0xff; |
| 657 | s->insn_read = labpc_calib_read_insn; |
| 658 | s->insn_write = labpc_calib_write_insn; |
| 659 | |
| 660 | for (i = 0; i < s->n_chan; i++) |
| 661 | write_caldac(dev, i, s->maxdata / 2); |
| 662 | } else |
| 663 | s->type = COMEDI_SUBD_UNUSED; |
| 664 | |
| 665 | /* EEPROM */ |
| 666 | s = &dev->subdevices[4]; |
| 667 | if (thisboard->register_layout == labpc_1200_layout) { |
| 668 | s->type = COMEDI_SUBD_MEMORY; |
| 669 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; |
| 670 | s->n_chan = EEPROM_SIZE; |
| 671 | s->maxdata = 0xff; |
| 672 | s->insn_read = labpc_eeprom_read_insn; |
| 673 | s->insn_write = labpc_eeprom_write_insn; |
| 674 | |
| 675 | for (i = 0; i < EEPROM_SIZE; i++) |
| 676 | devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i); |
| 677 | } else |
| 678 | s->type = COMEDI_SUBD_UNUSED; |
| 679 | |
| 680 | return 0; |
| 681 | } |
| 682 | EXPORT_SYMBOL_GPL(labpc_common_attach); |
| 683 | |
| 684 | static const struct labpc_board_struct * |
| 685 | labpc_pci_find_boardinfo(struct pci_dev *pcidev) |
| 686 | { |
| 687 | unsigned int device_id = pcidev->device; |
| 688 | unsigned int n; |
| 689 | |
| 690 | for (n = 0; n < ARRAY_SIZE(labpc_boards); n++) { |
| 691 | const struct labpc_board_struct *board = &labpc_boards[n]; |
| 692 | if (board->bustype == pci_bustype && |
| 693 | board->device_id == device_id) |
| 694 | return board; |
| 695 | } |
| 696 | return NULL; |
| 697 | } |
| 698 | |
| 699 | static int __devinit labpc_attach_pci(struct comedi_device *dev, |
| 700 | struct pci_dev *pcidev) |
| 701 | { |
| 702 | struct labpc_private *devpriv; |
| 703 | unsigned long iobase; |
| 704 | unsigned int irq; |
| 705 | int ret; |
| 706 | |
| 707 | if (!IS_ENABLED(CONFIG_COMEDI_PCI_DRIVERS)) |
| 708 | return -ENODEV; |
| 709 | |
| 710 | devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL); |
| 711 | if (!devpriv) |
| 712 | return -ENOMEM; |
| 713 | dev->private = devpriv; |
| 714 | |
| 715 | dev->board_ptr = labpc_pci_find_boardinfo(pcidev); |
| 716 | if (!dev->board_ptr) |
| 717 | return -ENODEV; |
| 718 | devpriv->mite = mite_alloc(pcidev); |
| 719 | if (!devpriv->mite) |
| 720 | return -ENOMEM; |
| 721 | ret = mite_setup(devpriv->mite); |
| 722 | if (ret < 0) |
| 723 | return ret; |
| 724 | iobase = (unsigned long)devpriv->mite->daq_io_addr; |
| 725 | irq = mite_irq(devpriv->mite); |
| 726 | return labpc_common_attach(dev, iobase, irq, 0); |
| 727 | } |
| 728 | |
| 729 | static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it) |
| 730 | { |
| 731 | struct labpc_private *devpriv; |
| 732 | unsigned long iobase = 0; |
| 733 | unsigned int irq = 0; |
| 734 | unsigned int dma_chan = 0; |
| 735 | |
| 736 | devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL); |
| 737 | if (!devpriv) |
| 738 | return -ENOMEM; |
| 739 | dev->private = devpriv; |
| 740 | |
| 741 | /* get base address, irq etc. based on bustype */ |
| 742 | switch (thisboard->bustype) { |
| 743 | case isa_bustype: |
| 744 | #ifdef CONFIG_ISA_DMA_API |
| 745 | iobase = it->options[0]; |
| 746 | irq = it->options[1]; |
| 747 | dma_chan = it->options[2]; |
| 748 | #else |
| 749 | dev_err(dev->class_dev, |
| 750 | "ni_labpc driver has not been built with ISA DMA support.\n"); |
| 751 | return -EINVAL; |
| 752 | #endif |
| 753 | break; |
| 754 | case pci_bustype: |
| 755 | #ifdef CONFIG_COMEDI_PCI_DRIVERS |
| 756 | dev_err(dev->class_dev, |
| 757 | "manual configuration of PCI board '%s' is not supported\n", |
| 758 | thisboard->name); |
| 759 | return -EINVAL; |
| 760 | #else |
| 761 | dev_err(dev->class_dev, |
| 762 | "ni_labpc driver has not been built with PCI support.\n"); |
| 763 | return -EINVAL; |
| 764 | #endif |
| 765 | break; |
| 766 | default: |
| 767 | dev_err(dev->class_dev, |
| 768 | "ni_labpc: bug! couldn't determine board type\n"); |
| 769 | return -EINVAL; |
| 770 | break; |
| 771 | } |
| 772 | |
| 773 | return labpc_common_attach(dev, iobase, irq, dma_chan); |
| 774 | } |
| 775 | |
| 776 | void labpc_common_detach(struct comedi_device *dev) |
| 777 | { |
| 778 | struct labpc_private *devpriv = dev->private; |
| 779 | struct comedi_subdevice *s; |
| 780 | |
| 781 | if (dev->subdevices) { |
| 782 | s = &dev->subdevices[2]; |
| 783 | subdev_8255_cleanup(dev, s); |
| 784 | } |
| 785 | #ifdef CONFIG_ISA_DMA_API |
| 786 | /* only free stuff if it has been allocated by _attach */ |
| 787 | kfree(devpriv->dma_buffer); |
| 788 | if (devpriv->dma_chan) |
| 789 | free_dma(devpriv->dma_chan); |
| 790 | #endif |
| 791 | if (dev->irq) |
| 792 | free_irq(dev->irq, dev); |
| 793 | if (thisboard->bustype == isa_bustype && dev->iobase) |
| 794 | release_region(dev->iobase, LABPC_SIZE); |
| 795 | #ifdef CONFIG_COMEDI_PCI_DRIVERS |
| 796 | if (devpriv->mite) { |
| 797 | mite_unsetup(devpriv->mite); |
| 798 | mite_free(devpriv->mite); |
| 799 | } |
| 800 | #endif |
| 801 | }; |
| 802 | EXPORT_SYMBOL_GPL(labpc_common_detach); |
| 803 | |
| 804 | static void labpc_clear_adc_fifo(const struct comedi_device *dev) |
| 805 | { |
| 806 | struct labpc_private *devpriv = dev->private; |
| 807 | |
| 808 | devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); |
| 809 | devpriv->read_byte(dev->iobase + ADC_FIFO_REG); |
| 810 | devpriv->read_byte(dev->iobase + ADC_FIFO_REG); |
| 811 | } |
| 812 | |
| 813 | static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s) |
| 814 | { |
| 815 | struct labpc_private *devpriv = dev->private; |
| 816 | unsigned long flags; |
| 817 | |
| 818 | spin_lock_irqsave(&dev->spinlock, flags); |
| 819 | devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; |
| 820 | devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); |
| 821 | spin_unlock_irqrestore(&dev->spinlock, flags); |
| 822 | |
| 823 | devpriv->command3_bits = 0; |
| 824 | devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); |
| 825 | |
| 826 | return 0; |
| 827 | } |
| 828 | |
| 829 | static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd) |
| 830 | { |
| 831 | if (cmd->chanlist_len == 1) |
| 832 | return MODE_SINGLE_CHAN; |
| 833 | |
| 834 | /* chanlist may be NULL during cmdtest. */ |
| 835 | if (cmd->chanlist == NULL) |
| 836 | return MODE_MULT_CHAN_UP; |
| 837 | |
| 838 | if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1])) |
| 839 | return MODE_SINGLE_CHAN_INTERVAL; |
| 840 | |
| 841 | if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1])) |
| 842 | return MODE_MULT_CHAN_UP; |
| 843 | |
| 844 | if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1])) |
| 845 | return MODE_MULT_CHAN_DOWN; |
| 846 | |
| 847 | pr_err("ni_labpc: bug! cannot determine AI scan mode\n"); |
| 848 | return 0; |
| 849 | } |
| 850 | |
| 851 | static int labpc_ai_chanlist_invalid(const struct comedi_device *dev, |
| 852 | const struct comedi_cmd *cmd, |
| 853 | enum scan_mode mode) |
| 854 | { |
| 855 | int channel, range, aref, i; |
| 856 | |
| 857 | if (cmd->chanlist == NULL) |
| 858 | return 0; |
| 859 | |
| 860 | if (mode == MODE_SINGLE_CHAN) |
| 861 | return 0; |
| 862 | |
| 863 | if (mode == MODE_SINGLE_CHAN_INTERVAL) { |
| 864 | if (cmd->chanlist_len > 0xff) { |
| 865 | comedi_error(dev, |
| 866 | "ni_labpc: chanlist too long for single channel interval mode\n"); |
| 867 | return 1; |
| 868 | } |
| 869 | } |
| 870 | |
| 871 | channel = CR_CHAN(cmd->chanlist[0]); |
| 872 | range = CR_RANGE(cmd->chanlist[0]); |
| 873 | aref = CR_AREF(cmd->chanlist[0]); |
| 874 | |
| 875 | for (i = 0; i < cmd->chanlist_len; i++) { |
| 876 | |
| 877 | switch (mode) { |
| 878 | case MODE_SINGLE_CHAN_INTERVAL: |
| 879 | if (CR_CHAN(cmd->chanlist[i]) != channel) { |
| 880 | comedi_error(dev, |
| 881 | "channel scanning order specified in chanlist is not supported by hardware.\n"); |
| 882 | return 1; |
| 883 | } |
| 884 | break; |
| 885 | case MODE_MULT_CHAN_UP: |
| 886 | if (CR_CHAN(cmd->chanlist[i]) != i) { |
| 887 | comedi_error(dev, |
| 888 | "channel scanning order specified in chanlist is not supported by hardware.\n"); |
| 889 | return 1; |
| 890 | } |
| 891 | break; |
| 892 | case MODE_MULT_CHAN_DOWN: |
| 893 | if (CR_CHAN(cmd->chanlist[i]) != |
| 894 | cmd->chanlist_len - i - 1) { |
| 895 | comedi_error(dev, |
| 896 | "channel scanning order specified in chanlist is not supported by hardware.\n"); |
| 897 | return 1; |
| 898 | } |
| 899 | break; |
| 900 | default: |
| 901 | dev_err(dev->class_dev, |
| 902 | "ni_labpc: bug! in chanlist check\n"); |
| 903 | return 1; |
| 904 | break; |
| 905 | } |
| 906 | |
| 907 | if (CR_RANGE(cmd->chanlist[i]) != range) { |
| 908 | comedi_error(dev, |
| 909 | "entries in chanlist must all have the same range\n"); |
| 910 | return 1; |
| 911 | } |
| 912 | |
| 913 | if (CR_AREF(cmd->chanlist[i]) != aref) { |
| 914 | comedi_error(dev, |
| 915 | "entries in chanlist must all have the same reference\n"); |
| 916 | return 1; |
| 917 | } |
| 918 | } |
| 919 | |
| 920 | return 0; |
| 921 | } |
| 922 | |
| 923 | static int labpc_use_continuous_mode(const struct comedi_cmd *cmd, |
| 924 | enum scan_mode mode) |
| 925 | { |
| 926 | if (mode == MODE_SINGLE_CHAN) |
| 927 | return 1; |
| 928 | |
| 929 | if (cmd->scan_begin_src == TRIG_FOLLOW) |
| 930 | return 1; |
| 931 | |
| 932 | return 0; |
| 933 | } |
| 934 | |
| 935 | static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd, |
| 936 | enum scan_mode mode) |
| 937 | { |
| 938 | if (cmd->convert_src != TRIG_TIMER) |
| 939 | return 0; |
| 940 | |
| 941 | if (mode == MODE_SINGLE_CHAN && cmd->scan_begin_src == TRIG_TIMER) |
| 942 | return cmd->scan_begin_arg; |
| 943 | |
| 944 | return cmd->convert_arg; |
| 945 | } |
| 946 | |
| 947 | static void labpc_set_ai_convert_period(struct comedi_cmd *cmd, |
| 948 | enum scan_mode mode, unsigned int ns) |
| 949 | { |
| 950 | if (cmd->convert_src != TRIG_TIMER) |
| 951 | return; |
| 952 | |
| 953 | if (mode == MODE_SINGLE_CHAN && |
| 954 | cmd->scan_begin_src == TRIG_TIMER) { |
| 955 | cmd->scan_begin_arg = ns; |
| 956 | if (cmd->convert_arg > cmd->scan_begin_arg) |
| 957 | cmd->convert_arg = cmd->scan_begin_arg; |
| 958 | } else |
| 959 | cmd->convert_arg = ns; |
| 960 | } |
| 961 | |
| 962 | static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd, |
| 963 | enum scan_mode mode) |
| 964 | { |
| 965 | if (cmd->scan_begin_src != TRIG_TIMER) |
| 966 | return 0; |
| 967 | |
| 968 | if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER) |
| 969 | return 0; |
| 970 | |
| 971 | return cmd->scan_begin_arg; |
| 972 | } |
| 973 | |
| 974 | static void labpc_set_ai_scan_period(struct comedi_cmd *cmd, |
| 975 | enum scan_mode mode, unsigned int ns) |
| 976 | { |
| 977 | if (cmd->scan_begin_src != TRIG_TIMER) |
| 978 | return; |
| 979 | |
| 980 | if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER) |
| 981 | return; |
| 982 | |
| 983 | cmd->scan_begin_arg = ns; |
| 984 | } |
| 985 | |
| 986 | static int labpc_ai_cmdtest(struct comedi_device *dev, |
| 987 | struct comedi_subdevice *s, struct comedi_cmd *cmd) |
| 988 | { |
| 989 | int err = 0; |
| 990 | int tmp, tmp2; |
| 991 | unsigned int stop_mask; |
| 992 | enum scan_mode mode; |
| 993 | |
| 994 | /* Step 1 : check if triggers are trivially valid */ |
| 995 | |
| 996 | err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT); |
| 997 | err |= cfc_check_trigger_src(&cmd->scan_begin_src, |
| 998 | TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT); |
| 999 | err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT); |
| 1000 | err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); |
| 1001 | |
| 1002 | stop_mask = TRIG_COUNT | TRIG_NONE; |
| 1003 | if (thisboard->register_layout == labpc_1200_layout) |
| 1004 | stop_mask |= TRIG_EXT; |
| 1005 | err |= cfc_check_trigger_src(&cmd->stop_src, stop_mask); |
| 1006 | |
| 1007 | if (err) |
| 1008 | return 1; |
| 1009 | |
| 1010 | /* Step 2a : make sure trigger sources are unique */ |
| 1011 | |
| 1012 | err |= cfc_check_trigger_is_unique(cmd->start_src); |
| 1013 | err |= cfc_check_trigger_is_unique(cmd->scan_begin_src); |
| 1014 | err |= cfc_check_trigger_is_unique(cmd->convert_src); |
| 1015 | err |= cfc_check_trigger_is_unique(cmd->stop_src); |
| 1016 | |
| 1017 | /* Step 2b : and mutually compatible */ |
| 1018 | |
| 1019 | /* can't have external stop and start triggers at once */ |
| 1020 | if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT) |
| 1021 | err++; |
| 1022 | |
| 1023 | if (err) |
| 1024 | return 2; |
| 1025 | |
| 1026 | /* step 3: make sure arguments are trivially compatible */ |
| 1027 | |
| 1028 | if (cmd->start_arg == TRIG_NOW && cmd->start_arg != 0) { |
| 1029 | cmd->start_arg = 0; |
| 1030 | err++; |
| 1031 | } |
| 1032 | |
| 1033 | if (!cmd->chanlist_len) |
| 1034 | err++; |
| 1035 | |
| 1036 | if (cmd->scan_end_arg != cmd->chanlist_len) { |
| 1037 | cmd->scan_end_arg = cmd->chanlist_len; |
| 1038 | err++; |
| 1039 | } |
| 1040 | |
| 1041 | if (cmd->convert_src == TRIG_TIMER) { |
| 1042 | if (cmd->convert_arg < thisboard->ai_speed) { |
| 1043 | cmd->convert_arg = thisboard->ai_speed; |
| 1044 | err++; |
| 1045 | } |
| 1046 | } |
| 1047 | /* make sure scan timing is not too fast */ |
| 1048 | if (cmd->scan_begin_src == TRIG_TIMER) { |
| 1049 | if (cmd->convert_src == TRIG_TIMER && |
| 1050 | cmd->scan_begin_arg < |
| 1051 | cmd->convert_arg * cmd->chanlist_len) { |
| 1052 | cmd->scan_begin_arg = |
| 1053 | cmd->convert_arg * cmd->chanlist_len; |
| 1054 | err++; |
| 1055 | } |
| 1056 | if (cmd->scan_begin_arg < |
| 1057 | thisboard->ai_speed * cmd->chanlist_len) { |
| 1058 | cmd->scan_begin_arg = |
| 1059 | thisboard->ai_speed * cmd->chanlist_len; |
| 1060 | err++; |
| 1061 | } |
| 1062 | } |
| 1063 | /* stop source */ |
| 1064 | switch (cmd->stop_src) { |
| 1065 | case TRIG_COUNT: |
| 1066 | if (!cmd->stop_arg) { |
| 1067 | cmd->stop_arg = 1; |
| 1068 | err++; |
| 1069 | } |
| 1070 | break; |
| 1071 | case TRIG_NONE: |
| 1072 | if (cmd->stop_arg != 0) { |
| 1073 | cmd->stop_arg = 0; |
| 1074 | err++; |
| 1075 | } |
| 1076 | break; |
| 1077 | /* |
| 1078 | * TRIG_EXT doesn't care since it doesn't |
| 1079 | * trigger off a numbered channel |
| 1080 | */ |
| 1081 | default: |
| 1082 | break; |
| 1083 | } |
| 1084 | |
| 1085 | if (err) |
| 1086 | return 3; |
| 1087 | |
| 1088 | /* step 4: fix up any arguments */ |
| 1089 | |
| 1090 | tmp = cmd->convert_arg; |
| 1091 | tmp2 = cmd->scan_begin_arg; |
| 1092 | mode = labpc_ai_scan_mode(cmd); |
| 1093 | labpc_adc_timing(dev, cmd, mode); |
| 1094 | if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg) |
| 1095 | err++; |
| 1096 | |
| 1097 | if (err) |
| 1098 | return 4; |
| 1099 | |
| 1100 | if (labpc_ai_chanlist_invalid(dev, cmd, mode)) |
| 1101 | return 5; |
| 1102 | |
| 1103 | return 0; |
| 1104 | } |
| 1105 | |
| 1106 | static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
| 1107 | { |
| 1108 | struct labpc_private *devpriv = dev->private; |
| 1109 | int channel, range, aref; |
| 1110 | #ifdef CONFIG_ISA_DMA_API |
| 1111 | unsigned long irq_flags; |
| 1112 | #endif |
| 1113 | int ret; |
| 1114 | struct comedi_async *async = s->async; |
| 1115 | struct comedi_cmd *cmd = &async->cmd; |
| 1116 | enum transfer_type xfer; |
| 1117 | enum scan_mode mode; |
| 1118 | unsigned long flags; |
| 1119 | |
| 1120 | if (!dev->irq) { |
| 1121 | comedi_error(dev, "no irq assigned, cannot perform command"); |
| 1122 | return -1; |
| 1123 | } |
| 1124 | |
| 1125 | range = CR_RANGE(cmd->chanlist[0]); |
| 1126 | aref = CR_AREF(cmd->chanlist[0]); |
| 1127 | |
| 1128 | /* make sure board is disabled before setting up acquisition */ |
| 1129 | spin_lock_irqsave(&dev->spinlock, flags); |
| 1130 | devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; |
| 1131 | devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); |
| 1132 | spin_unlock_irqrestore(&dev->spinlock, flags); |
| 1133 | |
| 1134 | devpriv->command3_bits = 0; |
| 1135 | devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); |
| 1136 | |
| 1137 | /* initialize software conversion count */ |
| 1138 | if (cmd->stop_src == TRIG_COUNT) |
| 1139 | devpriv->count = cmd->stop_arg * cmd->chanlist_len; |
| 1140 | |
| 1141 | /* setup hardware conversion counter */ |
| 1142 | if (cmd->stop_src == TRIG_EXT) { |
| 1143 | /* |
| 1144 | * load counter a1 with count of 3 |
| 1145 | * (pc+ manual says this is minimum allowed) using mode 0 |
| 1146 | */ |
| 1147 | ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, |
| 1148 | 1, 3, 0); |
| 1149 | if (ret < 0) { |
| 1150 | comedi_error(dev, "error loading counter a1"); |
| 1151 | return -1; |
| 1152 | } |
| 1153 | } else /* |
| 1154 | * otherwise, just put a1 in mode 0 |
| 1155 | * with no count to set its output low |
| 1156 | */ |
| 1157 | devpriv->write_byte(INIT_A1_BITS, |
| 1158 | dev->iobase + COUNTER_A_CONTROL_REG); |
| 1159 | |
| 1160 | #ifdef CONFIG_ISA_DMA_API |
| 1161 | /* figure out what method we will use to transfer data */ |
| 1162 | if (devpriv->dma_chan && /* need a dma channel allocated */ |
| 1163 | /* |
| 1164 | * dma unsafe at RT priority, |
| 1165 | * and too much setup time for TRIG_WAKE_EOS for |
| 1166 | */ |
| 1167 | (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 && |
| 1168 | /* only available on the isa boards */ |
| 1169 | thisboard->bustype == isa_bustype) { |
| 1170 | xfer = isa_dma_transfer; |
| 1171 | /* pc-plus has no fifo-half full interrupt */ |
| 1172 | } else |
| 1173 | #endif |
| 1174 | if (thisboard->register_layout == labpc_1200_layout && |
| 1175 | /* wake-end-of-scan should interrupt on fifo not empty */ |
| 1176 | (cmd->flags & TRIG_WAKE_EOS) == 0 && |
| 1177 | /* make sure we are taking more than just a few points */ |
| 1178 | (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) { |
| 1179 | xfer = fifo_half_full_transfer; |
| 1180 | } else |
| 1181 | xfer = fifo_not_empty_transfer; |
| 1182 | devpriv->current_transfer = xfer; |
| 1183 | mode = labpc_ai_scan_mode(cmd); |
| 1184 | |
| 1185 | /* setup command6 register for 1200 boards */ |
| 1186 | if (thisboard->register_layout == labpc_1200_layout) { |
| 1187 | /* reference inputs to ground or common? */ |
| 1188 | if (aref != AREF_GROUND) |
| 1189 | devpriv->command6_bits |= ADC_COMMON_BIT; |
| 1190 | else |
| 1191 | devpriv->command6_bits &= ~ADC_COMMON_BIT; |
| 1192 | /* bipolar or unipolar range? */ |
| 1193 | if (thisboard->ai_range_is_unipolar[range]) |
| 1194 | devpriv->command6_bits |= ADC_UNIP_BIT; |
| 1195 | else |
| 1196 | devpriv->command6_bits &= ~ADC_UNIP_BIT; |
| 1197 | /* interrupt on fifo half full? */ |
| 1198 | if (xfer == fifo_half_full_transfer) |
| 1199 | devpriv->command6_bits |= ADC_FHF_INTR_EN_BIT; |
| 1200 | else |
| 1201 | devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT; |
| 1202 | /* enable interrupt on counter a1 terminal count? */ |
| 1203 | if (cmd->stop_src == TRIG_EXT) |
| 1204 | devpriv->command6_bits |= A1_INTR_EN_BIT; |
| 1205 | else |
| 1206 | devpriv->command6_bits &= ~A1_INTR_EN_BIT; |
| 1207 | /* are we scanning up or down through channels? */ |
| 1208 | if (mode == MODE_MULT_CHAN_UP) |
| 1209 | devpriv->command6_bits |= ADC_SCAN_UP_BIT; |
| 1210 | else |
| 1211 | devpriv->command6_bits &= ~ADC_SCAN_UP_BIT; |
| 1212 | /* write to register */ |
| 1213 | devpriv->write_byte(devpriv->command6_bits, |
| 1214 | dev->iobase + COMMAND6_REG); |
| 1215 | } |
| 1216 | |
| 1217 | /* setup channel list, etc (command1 register) */ |
| 1218 | devpriv->command1_bits = 0; |
| 1219 | if (mode == MODE_MULT_CHAN_UP) |
| 1220 | channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]); |
| 1221 | else |
| 1222 | channel = CR_CHAN(cmd->chanlist[0]); |
| 1223 | /* munge channel bits for differential / scan disabled mode */ |
| 1224 | if (mode != MODE_SINGLE_CHAN && aref == AREF_DIFF) |
| 1225 | channel *= 2; |
| 1226 | devpriv->command1_bits |= ADC_CHAN_BITS(channel); |
| 1227 | devpriv->command1_bits |= thisboard->ai_range_code[range]; |
| 1228 | devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); |
| 1229 | /* manual says to set scan enable bit on second pass */ |
| 1230 | if (mode == MODE_MULT_CHAN_UP || mode == MODE_MULT_CHAN_DOWN) { |
| 1231 | devpriv->command1_bits |= ADC_SCAN_EN_BIT; |
| 1232 | /* need a brief delay before enabling scan, or scan |
| 1233 | * list will get screwed when you switch |
| 1234 | * between scan up to scan down mode - dunno why */ |
| 1235 | udelay(1); |
| 1236 | devpriv->write_byte(devpriv->command1_bits, |
| 1237 | dev->iobase + COMMAND1_REG); |
| 1238 | } |
| 1239 | /* setup any external triggering/pacing (command4 register) */ |
| 1240 | devpriv->command4_bits = 0; |
| 1241 | if (cmd->convert_src != TRIG_EXT) |
| 1242 | devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT; |
| 1243 | /* XXX should discard first scan when using interval scanning |
| 1244 | * since manual says it is not synced with scan clock */ |
| 1245 | if (labpc_use_continuous_mode(cmd, mode) == 0) { |
| 1246 | devpriv->command4_bits |= INTERVAL_SCAN_EN_BIT; |
| 1247 | if (cmd->scan_begin_src == TRIG_EXT) |
| 1248 | devpriv->command4_bits |= EXT_SCAN_EN_BIT; |
| 1249 | } |
| 1250 | /* single-ended/differential */ |
| 1251 | if (aref == AREF_DIFF) |
| 1252 | devpriv->command4_bits |= ADC_DIFF_BIT; |
| 1253 | devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); |
| 1254 | |
| 1255 | devpriv->write_byte(cmd->chanlist_len, |
| 1256 | dev->iobase + INTERVAL_COUNT_REG); |
| 1257 | /* load count */ |
| 1258 | devpriv->write_byte(INTERVAL_LOAD_BITS, |
| 1259 | dev->iobase + INTERVAL_LOAD_REG); |
| 1260 | |
| 1261 | if (cmd->convert_src == TRIG_TIMER || cmd->scan_begin_src == TRIG_TIMER) { |
| 1262 | /* set up pacing */ |
| 1263 | labpc_adc_timing(dev, cmd, mode); |
| 1264 | /* load counter b0 in mode 3 */ |
| 1265 | ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, |
| 1266 | 0, devpriv->divisor_b0, 3); |
| 1267 | if (ret < 0) { |
| 1268 | comedi_error(dev, "error loading counter b0"); |
| 1269 | return -1; |
| 1270 | } |
| 1271 | } |
| 1272 | /* set up conversion pacing */ |
| 1273 | if (labpc_ai_convert_period(cmd, mode)) { |
| 1274 | /* load counter a0 in mode 2 */ |
| 1275 | ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, |
| 1276 | 0, devpriv->divisor_a0, 2); |
| 1277 | if (ret < 0) { |
| 1278 | comedi_error(dev, "error loading counter a0"); |
| 1279 | return -1; |
| 1280 | } |
| 1281 | } else |
| 1282 | devpriv->write_byte(INIT_A0_BITS, |
| 1283 | dev->iobase + COUNTER_A_CONTROL_REG); |
| 1284 | |
| 1285 | /* set up scan pacing */ |
| 1286 | if (labpc_ai_scan_period(cmd, mode)) { |
| 1287 | /* load counter b1 in mode 2 */ |
| 1288 | ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, |
| 1289 | 1, devpriv->divisor_b1, 2); |
| 1290 | if (ret < 0) { |
| 1291 | comedi_error(dev, "error loading counter b1"); |
| 1292 | return -1; |
| 1293 | } |
| 1294 | } |
| 1295 | |
| 1296 | labpc_clear_adc_fifo(dev); |
| 1297 | |
| 1298 | #ifdef CONFIG_ISA_DMA_API |
| 1299 | /* set up dma transfer */ |
| 1300 | if (xfer == isa_dma_transfer) { |
| 1301 | irq_flags = claim_dma_lock(); |
| 1302 | disable_dma(devpriv->dma_chan); |
| 1303 | /* clear flip-flop to make sure 2-byte registers for |
| 1304 | * count and address get set correctly */ |
| 1305 | clear_dma_ff(devpriv->dma_chan); |
| 1306 | set_dma_addr(devpriv->dma_chan, |
| 1307 | virt_to_bus(devpriv->dma_buffer)); |
| 1308 | /* set appropriate size of transfer */ |
| 1309 | devpriv->dma_transfer_size = labpc_suggest_transfer_size(cmd); |
| 1310 | if (cmd->stop_src == TRIG_COUNT && |
| 1311 | devpriv->count * sample_size < devpriv->dma_transfer_size) { |
| 1312 | devpriv->dma_transfer_size = |
| 1313 | devpriv->count * sample_size; |
| 1314 | } |
| 1315 | set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size); |
| 1316 | enable_dma(devpriv->dma_chan); |
| 1317 | release_dma_lock(irq_flags); |
| 1318 | /* enable board's dma */ |
| 1319 | devpriv->command3_bits |= DMA_EN_BIT | DMATC_INTR_EN_BIT; |
| 1320 | } else |
| 1321 | devpriv->command3_bits &= ~DMA_EN_BIT & ~DMATC_INTR_EN_BIT; |
| 1322 | #endif |
| 1323 | |
| 1324 | /* enable error interrupts */ |
| 1325 | devpriv->command3_bits |= ERR_INTR_EN_BIT; |
| 1326 | /* enable fifo not empty interrupt? */ |
| 1327 | if (xfer == fifo_not_empty_transfer) |
| 1328 | devpriv->command3_bits |= ADC_FNE_INTR_EN_BIT; |
| 1329 | else |
| 1330 | devpriv->command3_bits &= ~ADC_FNE_INTR_EN_BIT; |
| 1331 | devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); |
| 1332 | |
| 1333 | /* startup acquisition */ |
| 1334 | |
| 1335 | /* command2 reg */ |
| 1336 | /* use 2 cascaded counters for pacing */ |
| 1337 | spin_lock_irqsave(&dev->spinlock, flags); |
| 1338 | devpriv->command2_bits |= CASCADE_BIT; |
| 1339 | switch (cmd->start_src) { |
| 1340 | case TRIG_EXT: |
| 1341 | devpriv->command2_bits |= HWTRIG_BIT; |
| 1342 | devpriv->command2_bits &= ~PRETRIG_BIT & ~SWTRIG_BIT; |
| 1343 | break; |
| 1344 | case TRIG_NOW: |
| 1345 | devpriv->command2_bits |= SWTRIG_BIT; |
| 1346 | devpriv->command2_bits &= ~PRETRIG_BIT & ~HWTRIG_BIT; |
| 1347 | break; |
| 1348 | default: |
| 1349 | comedi_error(dev, "bug with start_src"); |
| 1350 | spin_unlock_irqrestore(&dev->spinlock, flags); |
| 1351 | return -1; |
| 1352 | break; |
| 1353 | } |
| 1354 | switch (cmd->stop_src) { |
| 1355 | case TRIG_EXT: |
| 1356 | devpriv->command2_bits |= HWTRIG_BIT | PRETRIG_BIT; |
| 1357 | break; |
| 1358 | case TRIG_COUNT: |
| 1359 | case TRIG_NONE: |
| 1360 | break; |
| 1361 | default: |
| 1362 | comedi_error(dev, "bug with stop_src"); |
| 1363 | spin_unlock_irqrestore(&dev->spinlock, flags); |
| 1364 | return -1; |
| 1365 | } |
| 1366 | devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); |
| 1367 | spin_unlock_irqrestore(&dev->spinlock, flags); |
| 1368 | |
| 1369 | return 0; |
| 1370 | } |
| 1371 | |
| 1372 | /* interrupt service routine */ |
| 1373 | static irqreturn_t labpc_interrupt(int irq, void *d) |
| 1374 | { |
| 1375 | struct comedi_device *dev = d; |
| 1376 | struct labpc_private *devpriv = dev->private; |
| 1377 | struct comedi_subdevice *s = dev->read_subdev; |
| 1378 | struct comedi_async *async; |
| 1379 | struct comedi_cmd *cmd; |
| 1380 | |
| 1381 | if (dev->attached == 0) { |
| 1382 | comedi_error(dev, "premature interrupt"); |
| 1383 | return IRQ_HANDLED; |
| 1384 | } |
| 1385 | |
| 1386 | async = s->async; |
| 1387 | cmd = &async->cmd; |
| 1388 | async->events = 0; |
| 1389 | |
| 1390 | /* read board status */ |
| 1391 | devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG); |
| 1392 | if (thisboard->register_layout == labpc_1200_layout) |
| 1393 | devpriv->status2_bits = |
| 1394 | devpriv->read_byte(dev->iobase + STATUS2_REG); |
| 1395 | |
| 1396 | if ((devpriv->status1_bits & (DMATC_BIT | TIMER_BIT | OVERFLOW_BIT | |
| 1397 | OVERRUN_BIT | DATA_AVAIL_BIT)) == 0 |
| 1398 | && (devpriv->status2_bits & A1_TC_BIT) == 0 |
| 1399 | && (devpriv->status2_bits & FNHF_BIT)) { |
| 1400 | return IRQ_NONE; |
| 1401 | } |
| 1402 | |
| 1403 | if (devpriv->status1_bits & OVERRUN_BIT) { |
| 1404 | /* clear error interrupt */ |
| 1405 | devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); |
| 1406 | async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; |
| 1407 | comedi_event(dev, s); |
| 1408 | comedi_error(dev, "overrun"); |
| 1409 | return IRQ_HANDLED; |
| 1410 | } |
| 1411 | |
| 1412 | #ifdef CONFIG_ISA_DMA_API |
| 1413 | if (devpriv->current_transfer == isa_dma_transfer) { |
| 1414 | /* |
| 1415 | * if a dma terminal count of external stop trigger |
| 1416 | * has occurred |
| 1417 | */ |
| 1418 | if (devpriv->status1_bits & DMATC_BIT || |
| 1419 | (thisboard->register_layout == labpc_1200_layout |
| 1420 | && devpriv->status2_bits & A1_TC_BIT)) { |
| 1421 | handle_isa_dma(dev); |
| 1422 | } |
| 1423 | } else |
| 1424 | #endif |
| 1425 | labpc_drain_fifo(dev); |
| 1426 | |
| 1427 | if (devpriv->status1_bits & TIMER_BIT) { |
| 1428 | comedi_error(dev, "handled timer interrupt?"); |
| 1429 | /* clear it */ |
| 1430 | devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG); |
| 1431 | } |
| 1432 | |
| 1433 | if (devpriv->status1_bits & OVERFLOW_BIT) { |
| 1434 | /* clear error interrupt */ |
| 1435 | devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); |
| 1436 | async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; |
| 1437 | comedi_event(dev, s); |
| 1438 | comedi_error(dev, "overflow"); |
| 1439 | return IRQ_HANDLED; |
| 1440 | } |
| 1441 | /* handle external stop trigger */ |
| 1442 | if (cmd->stop_src == TRIG_EXT) { |
| 1443 | if (devpriv->status2_bits & A1_TC_BIT) { |
| 1444 | labpc_drain_dregs(dev); |
| 1445 | labpc_cancel(dev, s); |
| 1446 | async->events |= COMEDI_CB_EOA; |
| 1447 | } |
| 1448 | } |
| 1449 | |
| 1450 | /* TRIG_COUNT end of acquisition */ |
| 1451 | if (cmd->stop_src == TRIG_COUNT) { |
| 1452 | if (devpriv->count == 0) { |
| 1453 | labpc_cancel(dev, s); |
| 1454 | async->events |= COMEDI_CB_EOA; |
| 1455 | } |
| 1456 | } |
| 1457 | |
| 1458 | comedi_event(dev, s); |
| 1459 | return IRQ_HANDLED; |
| 1460 | } |
| 1461 | |
| 1462 | /* read all available samples from ai fifo */ |
| 1463 | static int labpc_drain_fifo(struct comedi_device *dev) |
| 1464 | { |
| 1465 | struct labpc_private *devpriv = dev->private; |
| 1466 | unsigned int lsb, msb; |
| 1467 | short data; |
| 1468 | struct comedi_async *async = dev->read_subdev->async; |
| 1469 | const int timeout = 10000; |
| 1470 | unsigned int i; |
| 1471 | |
| 1472 | devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG); |
| 1473 | |
| 1474 | for (i = 0; (devpriv->status1_bits & DATA_AVAIL_BIT) && i < timeout; |
| 1475 | i++) { |
| 1476 | /* quit if we have all the data we want */ |
| 1477 | if (async->cmd.stop_src == TRIG_COUNT) { |
| 1478 | if (devpriv->count == 0) |
| 1479 | break; |
| 1480 | devpriv->count--; |
| 1481 | } |
| 1482 | lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); |
| 1483 | msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); |
| 1484 | data = (msb << 8) | lsb; |
| 1485 | cfc_write_to_buffer(dev->read_subdev, data); |
| 1486 | devpriv->status1_bits = |
| 1487 | devpriv->read_byte(dev->iobase + STATUS1_REG); |
| 1488 | } |
| 1489 | if (i == timeout) { |
| 1490 | comedi_error(dev, "ai timeout, fifo never empties"); |
| 1491 | async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; |
| 1492 | return -1; |
| 1493 | } |
| 1494 | |
| 1495 | return 0; |
| 1496 | } |
| 1497 | |
| 1498 | #ifdef CONFIG_ISA_DMA_API |
| 1499 | static void labpc_drain_dma(struct comedi_device *dev) |
| 1500 | { |
| 1501 | struct labpc_private *devpriv = dev->private; |
| 1502 | struct comedi_subdevice *s = dev->read_subdev; |
| 1503 | struct comedi_async *async = s->async; |
| 1504 | int status; |
| 1505 | unsigned long flags; |
| 1506 | unsigned int max_points, num_points, residue, leftover; |
| 1507 | int i; |
| 1508 | |
| 1509 | status = devpriv->status1_bits; |
| 1510 | |
| 1511 | flags = claim_dma_lock(); |
| 1512 | disable_dma(devpriv->dma_chan); |
| 1513 | /* clear flip-flop to make sure 2-byte registers for |
| 1514 | * count and address get set correctly */ |
| 1515 | clear_dma_ff(devpriv->dma_chan); |
| 1516 | |
| 1517 | /* figure out how many points to read */ |
| 1518 | max_points = devpriv->dma_transfer_size / sample_size; |
| 1519 | /* residue is the number of points left to be done on the dma |
| 1520 | * transfer. It should always be zero at this point unless |
| 1521 | * the stop_src is set to external triggering. |
| 1522 | */ |
| 1523 | residue = get_dma_residue(devpriv->dma_chan) / sample_size; |
| 1524 | num_points = max_points - residue; |
| 1525 | if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT) |
| 1526 | num_points = devpriv->count; |
| 1527 | |
| 1528 | /* figure out how many points will be stored next time */ |
| 1529 | leftover = 0; |
| 1530 | if (async->cmd.stop_src != TRIG_COUNT) { |
| 1531 | leftover = devpriv->dma_transfer_size / sample_size; |
| 1532 | } else if (devpriv->count > num_points) { |
| 1533 | leftover = devpriv->count - num_points; |
| 1534 | if (leftover > max_points) |
| 1535 | leftover = max_points; |
| 1536 | } |
| 1537 | |
| 1538 | /* write data to comedi buffer */ |
| 1539 | for (i = 0; i < num_points; i++) |
| 1540 | cfc_write_to_buffer(s, devpriv->dma_buffer[i]); |
| 1541 | |
| 1542 | if (async->cmd.stop_src == TRIG_COUNT) |
| 1543 | devpriv->count -= num_points; |
| 1544 | |
| 1545 | /* set address and count for next transfer */ |
| 1546 | set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer)); |
| 1547 | set_dma_count(devpriv->dma_chan, leftover * sample_size); |
| 1548 | release_dma_lock(flags); |
| 1549 | |
| 1550 | async->events |= COMEDI_CB_BLOCK; |
| 1551 | } |
| 1552 | |
| 1553 | static void handle_isa_dma(struct comedi_device *dev) |
| 1554 | { |
| 1555 | struct labpc_private *devpriv = dev->private; |
| 1556 | |
| 1557 | labpc_drain_dma(dev); |
| 1558 | |
| 1559 | enable_dma(devpriv->dma_chan); |
| 1560 | |
| 1561 | /* clear dma tc interrupt */ |
| 1562 | devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG); |
| 1563 | } |
| 1564 | #endif |
| 1565 | |
| 1566 | /* makes sure all data acquired by board is transferred to comedi (used |
| 1567 | * when acquisition is terminated by stop_src == TRIG_EXT). */ |
| 1568 | static void labpc_drain_dregs(struct comedi_device *dev) |
| 1569 | { |
| 1570 | #ifdef CONFIG_ISA_DMA_API |
| 1571 | struct labpc_private *devpriv = dev->private; |
| 1572 | |
| 1573 | if (devpriv->current_transfer == isa_dma_transfer) |
| 1574 | labpc_drain_dma(dev); |
| 1575 | #endif |
| 1576 | |
| 1577 | labpc_drain_fifo(dev); |
| 1578 | } |
| 1579 | |
| 1580 | static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, |
| 1581 | struct comedi_insn *insn, unsigned int *data) |
| 1582 | { |
| 1583 | struct labpc_private *devpriv = dev->private; |
| 1584 | int i, n; |
| 1585 | int chan, range; |
| 1586 | int lsb, msb; |
| 1587 | int timeout = 1000; |
| 1588 | unsigned long flags; |
| 1589 | |
| 1590 | /* disable timed conversions */ |
| 1591 | spin_lock_irqsave(&dev->spinlock, flags); |
| 1592 | devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; |
| 1593 | devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); |
| 1594 | spin_unlock_irqrestore(&dev->spinlock, flags); |
| 1595 | |
| 1596 | /* disable interrupt generation and dma */ |
| 1597 | devpriv->command3_bits = 0; |
| 1598 | devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); |
| 1599 | |
| 1600 | /* set gain and channel */ |
| 1601 | devpriv->command1_bits = 0; |
| 1602 | chan = CR_CHAN(insn->chanspec); |
| 1603 | range = CR_RANGE(insn->chanspec); |
| 1604 | devpriv->command1_bits |= thisboard->ai_range_code[range]; |
| 1605 | /* munge channel bits for differential/scan disabled mode */ |
| 1606 | if (CR_AREF(insn->chanspec) == AREF_DIFF) |
| 1607 | chan *= 2; |
| 1608 | devpriv->command1_bits |= ADC_CHAN_BITS(chan); |
| 1609 | devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); |
| 1610 | |
| 1611 | /* setup command6 register for 1200 boards */ |
| 1612 | if (thisboard->register_layout == labpc_1200_layout) { |
| 1613 | /* reference inputs to ground or common? */ |
| 1614 | if (CR_AREF(insn->chanspec) != AREF_GROUND) |
| 1615 | devpriv->command6_bits |= ADC_COMMON_BIT; |
| 1616 | else |
| 1617 | devpriv->command6_bits &= ~ADC_COMMON_BIT; |
| 1618 | /* bipolar or unipolar range? */ |
| 1619 | if (thisboard->ai_range_is_unipolar[range]) |
| 1620 | devpriv->command6_bits |= ADC_UNIP_BIT; |
| 1621 | else |
| 1622 | devpriv->command6_bits &= ~ADC_UNIP_BIT; |
| 1623 | /* don't interrupt on fifo half full */ |
| 1624 | devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT; |
| 1625 | /* don't enable interrupt on counter a1 terminal count? */ |
| 1626 | devpriv->command6_bits &= ~A1_INTR_EN_BIT; |
| 1627 | /* write to register */ |
| 1628 | devpriv->write_byte(devpriv->command6_bits, |
| 1629 | dev->iobase + COMMAND6_REG); |
| 1630 | } |
| 1631 | /* setup command4 register */ |
| 1632 | devpriv->command4_bits = 0; |
| 1633 | devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT; |
| 1634 | /* single-ended/differential */ |
| 1635 | if (CR_AREF(insn->chanspec) == AREF_DIFF) |
| 1636 | devpriv->command4_bits |= ADC_DIFF_BIT; |
| 1637 | devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); |
| 1638 | |
| 1639 | /* |
| 1640 | * initialize pacer counter output to make sure it doesn't |
| 1641 | * cause any problems |
| 1642 | */ |
| 1643 | devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG); |
| 1644 | |
| 1645 | labpc_clear_adc_fifo(dev); |
| 1646 | |
| 1647 | for (n = 0; n < insn->n; n++) { |
| 1648 | /* trigger conversion */ |
| 1649 | devpriv->write_byte(0x1, dev->iobase + ADC_CONVERT_REG); |
| 1650 | |
| 1651 | for (i = 0; i < timeout; i++) { |
| 1652 | if (devpriv->read_byte(dev->iobase + |
| 1653 | STATUS1_REG) & DATA_AVAIL_BIT) |
| 1654 | break; |
| 1655 | udelay(1); |
| 1656 | } |
| 1657 | if (i == timeout) { |
| 1658 | comedi_error(dev, "timeout"); |
| 1659 | return -ETIME; |
| 1660 | } |
| 1661 | lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); |
| 1662 | msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); |
| 1663 | data[n] = (msb << 8) | lsb; |
| 1664 | } |
| 1665 | |
| 1666 | return n; |
| 1667 | } |
| 1668 | |
| 1669 | /* analog output insn */ |
| 1670 | static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, |
| 1671 | struct comedi_insn *insn, unsigned int *data) |
| 1672 | { |
| 1673 | struct labpc_private *devpriv = dev->private; |
| 1674 | int channel, range; |
| 1675 | unsigned long flags; |
| 1676 | int lsb, msb; |
| 1677 | |
| 1678 | channel = CR_CHAN(insn->chanspec); |
| 1679 | |
| 1680 | /* turn off pacing of analog output channel */ |
| 1681 | /* note: hardware bug in daqcard-1200 means pacing cannot |
| 1682 | * be independently enabled/disabled for its the two channels */ |
| 1683 | spin_lock_irqsave(&dev->spinlock, flags); |
| 1684 | devpriv->command2_bits &= ~DAC_PACED_BIT(channel); |
| 1685 | devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); |
| 1686 | spin_unlock_irqrestore(&dev->spinlock, flags); |
| 1687 | |
| 1688 | /* set range */ |
| 1689 | if (thisboard->register_layout == labpc_1200_layout) { |
| 1690 | range = CR_RANGE(insn->chanspec); |
| 1691 | if (range & AO_RANGE_IS_UNIPOLAR) |
| 1692 | devpriv->command6_bits |= DAC_UNIP_BIT(channel); |
| 1693 | else |
| 1694 | devpriv->command6_bits &= ~DAC_UNIP_BIT(channel); |
| 1695 | /* write to register */ |
| 1696 | devpriv->write_byte(devpriv->command6_bits, |
| 1697 | dev->iobase + COMMAND6_REG); |
| 1698 | } |
| 1699 | /* send data */ |
| 1700 | lsb = data[0] & 0xff; |
| 1701 | msb = (data[0] >> 8) & 0xff; |
| 1702 | devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel)); |
| 1703 | devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel)); |
| 1704 | |
| 1705 | /* remember value for readback */ |
| 1706 | devpriv->ao_value[channel] = data[0]; |
| 1707 | |
| 1708 | return 1; |
| 1709 | } |
| 1710 | |
| 1711 | /* analog output readback insn */ |
| 1712 | static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, |
| 1713 | struct comedi_insn *insn, unsigned int *data) |
| 1714 | { |
| 1715 | struct labpc_private *devpriv = dev->private; |
| 1716 | |
| 1717 | data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)]; |
| 1718 | |
| 1719 | return 1; |
| 1720 | } |
| 1721 | |
| 1722 | static int labpc_calib_read_insn(struct comedi_device *dev, |
| 1723 | struct comedi_subdevice *s, |
| 1724 | struct comedi_insn *insn, unsigned int *data) |
| 1725 | { |
| 1726 | struct labpc_private *devpriv = dev->private; |
| 1727 | |
| 1728 | data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)]; |
| 1729 | |
| 1730 | return 1; |
| 1731 | } |
| 1732 | |
| 1733 | static int labpc_calib_write_insn(struct comedi_device *dev, |
| 1734 | struct comedi_subdevice *s, |
| 1735 | struct comedi_insn *insn, unsigned int *data) |
| 1736 | { |
| 1737 | int channel = CR_CHAN(insn->chanspec); |
| 1738 | |
| 1739 | write_caldac(dev, channel, data[0]); |
| 1740 | return 1; |
| 1741 | } |
| 1742 | |
| 1743 | static int labpc_eeprom_read_insn(struct comedi_device *dev, |
| 1744 | struct comedi_subdevice *s, |
| 1745 | struct comedi_insn *insn, unsigned int *data) |
| 1746 | { |
| 1747 | struct labpc_private *devpriv = dev->private; |
| 1748 | |
| 1749 | data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)]; |
| 1750 | |
| 1751 | return 1; |
| 1752 | } |
| 1753 | |
| 1754 | static int labpc_eeprom_write_insn(struct comedi_device *dev, |
| 1755 | struct comedi_subdevice *s, |
| 1756 | struct comedi_insn *insn, unsigned int *data) |
| 1757 | { |
| 1758 | int channel = CR_CHAN(insn->chanspec); |
| 1759 | int ret; |
| 1760 | |
| 1761 | /* only allow writes to user area of eeprom */ |
| 1762 | if (channel < 16 || channel > 127) { |
| 1763 | dev_dbg(dev->class_dev, |
| 1764 | "eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)\n"); |
| 1765 | return -EINVAL; |
| 1766 | } |
| 1767 | |
| 1768 | ret = labpc_eeprom_write(dev, channel, data[0]); |
| 1769 | if (ret < 0) |
| 1770 | return ret; |
| 1771 | |
| 1772 | return 1; |
| 1773 | } |
| 1774 | |
| 1775 | #ifdef CONFIG_ISA_DMA_API |
| 1776 | /* utility function that suggests a dma transfer size in bytes */ |
| 1777 | static unsigned int labpc_suggest_transfer_size(const struct comedi_cmd *cmd) |
| 1778 | { |
| 1779 | unsigned int size; |
| 1780 | unsigned int freq; |
| 1781 | |
| 1782 | if (cmd->convert_src == TRIG_TIMER) |
| 1783 | freq = 1000000000 / cmd->convert_arg; |
| 1784 | /* return some default value */ |
| 1785 | else |
| 1786 | freq = 0xffffffff; |
| 1787 | |
| 1788 | /* make buffer fill in no more than 1/3 second */ |
| 1789 | size = (freq / 3) * sample_size; |
| 1790 | |
| 1791 | /* set a minimum and maximum size allowed */ |
| 1792 | if (size > dma_buffer_size) |
| 1793 | size = dma_buffer_size - dma_buffer_size % sample_size; |
| 1794 | else if (size < sample_size) |
| 1795 | size = sample_size; |
| 1796 | |
| 1797 | return size; |
| 1798 | } |
| 1799 | #endif |
| 1800 | |
| 1801 | /* figures out what counter values to use based on command */ |
| 1802 | static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd, |
| 1803 | enum scan_mode mode) |
| 1804 | { |
| 1805 | struct labpc_private *devpriv = dev->private; |
| 1806 | /* max value for 16 bit counter in mode 2 */ |
| 1807 | const int max_counter_value = 0x10000; |
| 1808 | /* min value for 16 bit counter in mode 2 */ |
| 1809 | const int min_counter_value = 2; |
| 1810 | unsigned int base_period; |
| 1811 | unsigned int scan_period; |
| 1812 | unsigned int convert_period; |
| 1813 | |
| 1814 | /* |
| 1815 | * if both convert and scan triggers are TRIG_TIMER, then they |
| 1816 | * both rely on counter b0 |
| 1817 | */ |
| 1818 | convert_period = labpc_ai_convert_period(cmd, mode); |
| 1819 | scan_period = labpc_ai_scan_period(cmd, mode); |
| 1820 | if (convert_period && scan_period) { |
| 1821 | /* |
| 1822 | * pick the lowest b0 divisor value we can (for maximum input |
| 1823 | * clock speed on convert and scan counters) |
| 1824 | */ |
| 1825 | devpriv->divisor_b0 = (scan_period - 1) / |
| 1826 | (LABPC_TIMER_BASE * max_counter_value) + 1; |
| 1827 | if (devpriv->divisor_b0 < min_counter_value) |
| 1828 | devpriv->divisor_b0 = min_counter_value; |
| 1829 | if (devpriv->divisor_b0 > max_counter_value) |
| 1830 | devpriv->divisor_b0 = max_counter_value; |
| 1831 | |
| 1832 | base_period = LABPC_TIMER_BASE * devpriv->divisor_b0; |
| 1833 | |
| 1834 | /* set a0 for conversion frequency and b1 for scan frequency */ |
| 1835 | switch (cmd->flags & TRIG_ROUND_MASK) { |
| 1836 | default: |
| 1837 | case TRIG_ROUND_NEAREST: |
| 1838 | devpriv->divisor_a0 = |
| 1839 | (convert_period + (base_period / 2)) / base_period; |
| 1840 | devpriv->divisor_b1 = |
| 1841 | (scan_period + (base_period / 2)) / base_period; |
| 1842 | break; |
| 1843 | case TRIG_ROUND_UP: |
| 1844 | devpriv->divisor_a0 = |
| 1845 | (convert_period + (base_period - 1)) / base_period; |
| 1846 | devpriv->divisor_b1 = |
| 1847 | (scan_period + (base_period - 1)) / base_period; |
| 1848 | break; |
| 1849 | case TRIG_ROUND_DOWN: |
| 1850 | devpriv->divisor_a0 = convert_period / base_period; |
| 1851 | devpriv->divisor_b1 = scan_period / base_period; |
| 1852 | break; |
| 1853 | } |
| 1854 | /* make sure a0 and b1 values are acceptable */ |
| 1855 | if (devpriv->divisor_a0 < min_counter_value) |
| 1856 | devpriv->divisor_a0 = min_counter_value; |
| 1857 | if (devpriv->divisor_a0 > max_counter_value) |
| 1858 | devpriv->divisor_a0 = max_counter_value; |
| 1859 | if (devpriv->divisor_b1 < min_counter_value) |
| 1860 | devpriv->divisor_b1 = min_counter_value; |
| 1861 | if (devpriv->divisor_b1 > max_counter_value) |
| 1862 | devpriv->divisor_b1 = max_counter_value; |
| 1863 | /* write corrected timings to command */ |
| 1864 | labpc_set_ai_convert_period(cmd, mode, |
| 1865 | base_period * devpriv->divisor_a0); |
| 1866 | labpc_set_ai_scan_period(cmd, mode, |
| 1867 | base_period * devpriv->divisor_b1); |
| 1868 | /* |
| 1869 | * if only one TRIG_TIMER is used, we can employ the generic |
| 1870 | * cascaded timing functions |
| 1871 | */ |
| 1872 | } else if (scan_period) { |
| 1873 | /* |
| 1874 | * calculate cascaded counter values |
| 1875 | * that give desired scan timing |
| 1876 | */ |
| 1877 | i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, |
| 1878 | &(devpriv->divisor_b1), |
| 1879 | &(devpriv->divisor_b0), |
| 1880 | &scan_period, |
| 1881 | cmd->flags & TRIG_ROUND_MASK); |
| 1882 | labpc_set_ai_scan_period(cmd, mode, scan_period); |
| 1883 | } else if (convert_period) { |
| 1884 | /* |
| 1885 | * calculate cascaded counter values |
| 1886 | * that give desired conversion timing |
| 1887 | */ |
| 1888 | i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, |
| 1889 | &(devpriv->divisor_a0), |
| 1890 | &(devpriv->divisor_b0), |
| 1891 | &convert_period, |
| 1892 | cmd->flags & TRIG_ROUND_MASK); |
| 1893 | labpc_set_ai_convert_period(cmd, mode, convert_period); |
| 1894 | } |
| 1895 | } |
| 1896 | |
| 1897 | static int labpc_dio_mem_callback(int dir, int port, int data, |
| 1898 | unsigned long iobase) |
| 1899 | { |
| 1900 | if (dir) { |
| 1901 | writeb(data, (void __iomem *)(iobase + port)); |
| 1902 | return 0; |
| 1903 | } else { |
| 1904 | return readb((void __iomem *)(iobase + port)); |
| 1905 | } |
| 1906 | } |
| 1907 | |
| 1908 | /* lowlevel write to eeprom/dac */ |
| 1909 | static void labpc_serial_out(struct comedi_device *dev, unsigned int value, |
| 1910 | unsigned int value_width) |
| 1911 | { |
| 1912 | struct labpc_private *devpriv = dev->private; |
| 1913 | int i; |
| 1914 | |
| 1915 | for (i = 1; i <= value_width; i++) { |
| 1916 | /* clear serial clock */ |
| 1917 | devpriv->command5_bits &= ~SCLOCK_BIT; |
| 1918 | /* send bits most significant bit first */ |
| 1919 | if (value & (1 << (value_width - i))) |
| 1920 | devpriv->command5_bits |= SDATA_BIT; |
| 1921 | else |
| 1922 | devpriv->command5_bits &= ~SDATA_BIT; |
| 1923 | udelay(1); |
| 1924 | devpriv->write_byte(devpriv->command5_bits, |
| 1925 | dev->iobase + COMMAND5_REG); |
| 1926 | /* set clock to load bit */ |
| 1927 | devpriv->command5_bits |= SCLOCK_BIT; |
| 1928 | udelay(1); |
| 1929 | devpriv->write_byte(devpriv->command5_bits, |
| 1930 | dev->iobase + COMMAND5_REG); |
| 1931 | } |
| 1932 | } |
| 1933 | |
| 1934 | /* lowlevel read from eeprom */ |
| 1935 | static unsigned int labpc_serial_in(struct comedi_device *dev) |
| 1936 | { |
| 1937 | struct labpc_private *devpriv = dev->private; |
| 1938 | unsigned int value = 0; |
| 1939 | int i; |
| 1940 | const int value_width = 8; /* number of bits wide values are */ |
| 1941 | |
| 1942 | for (i = 1; i <= value_width; i++) { |
| 1943 | /* set serial clock */ |
| 1944 | devpriv->command5_bits |= SCLOCK_BIT; |
| 1945 | udelay(1); |
| 1946 | devpriv->write_byte(devpriv->command5_bits, |
| 1947 | dev->iobase + COMMAND5_REG); |
| 1948 | /* clear clock bit */ |
| 1949 | devpriv->command5_bits &= ~SCLOCK_BIT; |
| 1950 | udelay(1); |
| 1951 | devpriv->write_byte(devpriv->command5_bits, |
| 1952 | dev->iobase + COMMAND5_REG); |
| 1953 | /* read bits most significant bit first */ |
| 1954 | udelay(1); |
| 1955 | devpriv->status2_bits = |
| 1956 | devpriv->read_byte(dev->iobase + STATUS2_REG); |
| 1957 | if (devpriv->status2_bits & EEPROM_OUT_BIT) |
| 1958 | value |= 1 << (value_width - i); |
| 1959 | } |
| 1960 | |
| 1961 | return value; |
| 1962 | } |
| 1963 | |
| 1964 | static unsigned int labpc_eeprom_read(struct comedi_device *dev, |
| 1965 | unsigned int address) |
| 1966 | { |
| 1967 | struct labpc_private *devpriv = dev->private; |
| 1968 | unsigned int value; |
| 1969 | /* bits to tell eeprom to expect a read */ |
| 1970 | const int read_instruction = 0x3; |
| 1971 | /* 8 bit write lengths to eeprom */ |
| 1972 | const int write_length = 8; |
| 1973 | |
| 1974 | /* enable read/write to eeprom */ |
| 1975 | devpriv->command5_bits &= ~EEPROM_EN_BIT; |
| 1976 | udelay(1); |
| 1977 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
| 1978 | devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; |
| 1979 | udelay(1); |
| 1980 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
| 1981 | |
| 1982 | /* send read instruction */ |
| 1983 | labpc_serial_out(dev, read_instruction, write_length); |
| 1984 | /* send 8 bit address to read from */ |
| 1985 | labpc_serial_out(dev, address, write_length); |
| 1986 | /* read result */ |
| 1987 | value = labpc_serial_in(dev); |
| 1988 | |
| 1989 | /* disable read/write to eeprom */ |
| 1990 | devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; |
| 1991 | udelay(1); |
| 1992 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
| 1993 | |
| 1994 | return value; |
| 1995 | } |
| 1996 | |
| 1997 | static int labpc_eeprom_write(struct comedi_device *dev, |
| 1998 | unsigned int address, unsigned int value) |
| 1999 | { |
| 2000 | struct labpc_private *devpriv = dev->private; |
| 2001 | const int write_enable_instruction = 0x6; |
| 2002 | const int write_instruction = 0x2; |
| 2003 | const int write_length = 8; /* 8 bit write lengths to eeprom */ |
| 2004 | const int write_in_progress_bit = 0x1; |
| 2005 | const int timeout = 10000; |
| 2006 | int i; |
| 2007 | |
| 2008 | /* make sure there isn't already a write in progress */ |
| 2009 | for (i = 0; i < timeout; i++) { |
| 2010 | if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) == |
| 2011 | 0) |
| 2012 | break; |
| 2013 | } |
| 2014 | if (i == timeout) { |
| 2015 | comedi_error(dev, "eeprom write timed out"); |
| 2016 | return -ETIME; |
| 2017 | } |
| 2018 | /* update software copy of eeprom */ |
| 2019 | devpriv->eeprom_data[address] = value; |
| 2020 | |
| 2021 | /* enable read/write to eeprom */ |
| 2022 | devpriv->command5_bits &= ~EEPROM_EN_BIT; |
| 2023 | udelay(1); |
| 2024 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
| 2025 | devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; |
| 2026 | udelay(1); |
| 2027 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
| 2028 | |
| 2029 | /* send write_enable instruction */ |
| 2030 | labpc_serial_out(dev, write_enable_instruction, write_length); |
| 2031 | devpriv->command5_bits &= ~EEPROM_EN_BIT; |
| 2032 | udelay(1); |
| 2033 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
| 2034 | |
| 2035 | /* send write instruction */ |
| 2036 | devpriv->command5_bits |= EEPROM_EN_BIT; |
| 2037 | udelay(1); |
| 2038 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
| 2039 | labpc_serial_out(dev, write_instruction, write_length); |
| 2040 | /* send 8 bit address to write to */ |
| 2041 | labpc_serial_out(dev, address, write_length); |
| 2042 | /* write value */ |
| 2043 | labpc_serial_out(dev, value, write_length); |
| 2044 | devpriv->command5_bits &= ~EEPROM_EN_BIT; |
| 2045 | udelay(1); |
| 2046 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
| 2047 | |
| 2048 | /* disable read/write to eeprom */ |
| 2049 | devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; |
| 2050 | udelay(1); |
| 2051 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
| 2052 | |
| 2053 | return 0; |
| 2054 | } |
| 2055 | |
| 2056 | static unsigned int labpc_eeprom_read_status(struct comedi_device *dev) |
| 2057 | { |
| 2058 | struct labpc_private *devpriv = dev->private; |
| 2059 | unsigned int value; |
| 2060 | const int read_status_instruction = 0x5; |
| 2061 | const int write_length = 8; /* 8 bit write lengths to eeprom */ |
| 2062 | |
| 2063 | /* enable read/write to eeprom */ |
| 2064 | devpriv->command5_bits &= ~EEPROM_EN_BIT; |
| 2065 | udelay(1); |
| 2066 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
| 2067 | devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; |
| 2068 | udelay(1); |
| 2069 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
| 2070 | |
| 2071 | /* send read status instruction */ |
| 2072 | labpc_serial_out(dev, read_status_instruction, write_length); |
| 2073 | /* read result */ |
| 2074 | value = labpc_serial_in(dev); |
| 2075 | |
| 2076 | /* disable read/write to eeprom */ |
| 2077 | devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; |
| 2078 | udelay(1); |
| 2079 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
| 2080 | |
| 2081 | return value; |
| 2082 | } |
| 2083 | |
| 2084 | /* writes to 8 bit calibration dacs */ |
| 2085 | static void write_caldac(struct comedi_device *dev, unsigned int channel, |
| 2086 | unsigned int value) |
| 2087 | { |
| 2088 | struct labpc_private *devpriv = dev->private; |
| 2089 | |
| 2090 | if (value == devpriv->caldac[channel]) |
| 2091 | return; |
| 2092 | devpriv->caldac[channel] = value; |
| 2093 | |
| 2094 | /* clear caldac load bit and make sure we don't write to eeprom */ |
| 2095 | devpriv->command5_bits &= |
| 2096 | ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; |
| 2097 | udelay(1); |
| 2098 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
| 2099 | |
| 2100 | /* write 4 bit channel */ |
| 2101 | labpc_serial_out(dev, channel, 4); |
| 2102 | /* write 8 bit caldac value */ |
| 2103 | labpc_serial_out(dev, value, 8); |
| 2104 | |
| 2105 | /* set and clear caldac bit to load caldac value */ |
| 2106 | devpriv->command5_bits |= CALDAC_LOAD_BIT; |
| 2107 | udelay(1); |
| 2108 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
| 2109 | devpriv->command5_bits &= ~CALDAC_LOAD_BIT; |
| 2110 | udelay(1); |
| 2111 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
| 2112 | } |
| 2113 | |
| 2114 | static struct comedi_driver labpc_driver = { |
| 2115 | .driver_name = DRV_NAME, |
| 2116 | .module = THIS_MODULE, |
| 2117 | .attach = labpc_attach, |
| 2118 | .attach_pci = labpc_attach_pci, |
| 2119 | .detach = labpc_common_detach, |
| 2120 | .num_names = ARRAY_SIZE(labpc_boards), |
| 2121 | .board_name = &labpc_boards[0].name, |
| 2122 | .offset = sizeof(struct labpc_board_struct), |
| 2123 | }; |
| 2124 | |
| 2125 | #ifdef CONFIG_COMEDI_PCI_DRIVERS |
| 2126 | static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = { |
| 2127 | {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x161)}, |
| 2128 | {0} |
| 2129 | }; |
| 2130 | MODULE_DEVICE_TABLE(pci, labpc_pci_table); |
| 2131 | |
| 2132 | static int __devinit labpc_pci_probe(struct pci_dev *dev, |
| 2133 | const struct pci_device_id *ent) |
| 2134 | { |
| 2135 | return comedi_pci_auto_config(dev, &labpc_driver); |
| 2136 | } |
| 2137 | |
| 2138 | static void __devexit labpc_pci_remove(struct pci_dev *dev) |
| 2139 | { |
| 2140 | comedi_pci_auto_unconfig(dev); |
| 2141 | } |
| 2142 | |
| 2143 | static struct pci_driver labpc_pci_driver = { |
| 2144 | .name = DRV_NAME, |
| 2145 | .id_table = labpc_pci_table, |
| 2146 | .probe = labpc_pci_probe, |
| 2147 | .remove = __devexit_p(labpc_pci_remove) |
| 2148 | }; |
| 2149 | module_comedi_pci_driver(labpc_driver, labpc_pci_driver); |
| 2150 | #else |
| 2151 | module_comedi_driver(labpc_driver); |
| 2152 | #endif |
| 2153 | |
| 2154 | |
| 2155 | MODULE_AUTHOR("Comedi http://www.comedi.org"); |
| 2156 | MODULE_DESCRIPTION("Comedi low-level driver"); |
| 2157 | MODULE_LICENSE("GPL"); |