| 1 | /*************************************************************************** |
| 2 | * Copyright (C) 2006-2010 by Marin Mitov * |
| 3 | * mitov@issp.bas.bg * |
| 4 | * * |
| 5 | * This program is free software; you can redistribute it and/or modify * |
| 6 | * it under the terms of the GNU General Public License as published by * |
| 7 | * the Free Software Foundation; either version 2 of the License, or * |
| 8 | * (at your option) any later version. * |
| 9 | * * |
| 10 | * This program is distributed in the hope that it will be useful, * |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
| 13 | * GNU General Public License for more details. * |
| 14 | * * |
| 15 | * You should have received a copy of the GNU General Public License * |
| 16 | * along with this program; if not, write to the * |
| 17 | * Free Software Foundation, Inc., * |
| 18 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * |
| 19 | ***************************************************************************/ |
| 20 | |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/version.h> |
| 23 | #include <linux/stringify.h> |
| 24 | #include <linux/delay.h> |
| 25 | #include <linux/kthread.h> |
| 26 | #include <linux/slab.h> |
| 27 | #include <media/v4l2-dev.h> |
| 28 | #include <media/v4l2-ioctl.h> |
| 29 | #include <media/videobuf2-dma-contig.h> |
| 30 | |
| 31 | #include "dt3155v4l.h" |
| 32 | |
| 33 | #define DT3155_VENDOR_ID 0x8086 |
| 34 | #define DT3155_DEVICE_ID 0x1223 |
| 35 | |
| 36 | /* DT3155_CHUNK_SIZE is 4M (2^22) 8 full size buffers */ |
| 37 | #define DT3155_CHUNK_SIZE (1U << 22) |
| 38 | |
| 39 | #define DT3155_COH_FLAGS (GFP_KERNEL | GFP_DMA32 | __GFP_COLD | __GFP_NOWARN) |
| 40 | |
| 41 | #define DT3155_BUF_SIZE (768 * 576) |
| 42 | |
| 43 | #ifdef CONFIG_DT3155_STREAMING |
| 44 | #define DT3155_CAPTURE_METHOD V4L2_CAP_STREAMING |
| 45 | #else |
| 46 | #define DT3155_CAPTURE_METHOD V4L2_CAP_READWRITE |
| 47 | #endif |
| 48 | |
| 49 | /* global initializers (for all boards) */ |
| 50 | #ifdef CONFIG_DT3155_CCIR |
| 51 | static const u8 csr2_init = VT_50HZ; |
| 52 | #define DT3155_CURRENT_NORM V4L2_STD_625_50 |
| 53 | static const unsigned int img_width = 768; |
| 54 | static const unsigned int img_height = 576; |
| 55 | static const unsigned int frames_per_sec = 25; |
| 56 | static const struct v4l2_fmtdesc frame_std[] = { |
| 57 | { |
| 58 | .index = 0, |
| 59 | .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, |
| 60 | .flags = 0, |
| 61 | .description = "CCIR/50Hz 8 bits gray", |
| 62 | .pixelformat = V4L2_PIX_FMT_GREY, |
| 63 | }, |
| 64 | }; |
| 65 | #else |
| 66 | static const u8 csr2_init = VT_60HZ; |
| 67 | #define DT3155_CURRENT_NORM V4L2_STD_525_60 |
| 68 | static const unsigned int img_width = 640; |
| 69 | static const unsigned int img_height = 480; |
| 70 | static const unsigned int frames_per_sec = 30; |
| 71 | static const struct v4l2_fmtdesc frame_std[] = { |
| 72 | { |
| 73 | .index = 0, |
| 74 | .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, |
| 75 | .flags = 0, |
| 76 | .description = "RS-170/60Hz 8 bits gray", |
| 77 | .pixelformat = V4L2_PIX_FMT_GREY, |
| 78 | }, |
| 79 | }; |
| 80 | #endif |
| 81 | |
| 82 | #define NUM_OF_FORMATS ARRAY_SIZE(frame_std) |
| 83 | |
| 84 | static u8 config_init = ACQ_MODE_EVEN; |
| 85 | |
| 86 | /** |
| 87 | * read_i2c_reg - reads an internal i2c register |
| 88 | * |
| 89 | * @addr: dt3155 mmio base address |
| 90 | * @index: index (internal address) of register to read |
| 91 | * @data: pointer to byte the read data will be placed in |
| 92 | * |
| 93 | * returns: zero on success or error code |
| 94 | * |
| 95 | * This function starts reading the specified (by index) register |
| 96 | * and busy waits for the process to finish. The result is placed |
| 97 | * in a byte pointed by data. |
| 98 | */ |
| 99 | static int |
| 100 | read_i2c_reg(void __iomem *addr, u8 index, u8 *data) |
| 101 | { |
| 102 | u32 tmp = index; |
| 103 | |
| 104 | iowrite32((tmp<<17) | IIC_READ, addr + IIC_CSR2); |
| 105 | mmiowb(); |
| 106 | udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */ |
| 107 | if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) |
| 108 | return -EIO; /* error: NEW_CYCLE not cleared */ |
| 109 | tmp = ioread32(addr + IIC_CSR1); |
| 110 | if (tmp & DIRECT_ABORT) { |
| 111 | /* reset DIRECT_ABORT bit */ |
| 112 | iowrite32(DIRECT_ABORT, addr + IIC_CSR1); |
| 113 | return -EIO; /* error: DIRECT_ABORT set */ |
| 114 | } |
| 115 | *data = tmp>>24; |
| 116 | return 0; |
| 117 | } |
| 118 | |
| 119 | /** |
| 120 | * write_i2c_reg - writes to an internal i2c register |
| 121 | * |
| 122 | * @addr: dt3155 mmio base address |
| 123 | * @index: index (internal address) of register to read |
| 124 | * @data: data to be written |
| 125 | * |
| 126 | * returns: zero on success or error code |
| 127 | * |
| 128 | * This function starts writting the specified (by index) register |
| 129 | * and busy waits for the process to finish. |
| 130 | */ |
| 131 | static int |
| 132 | write_i2c_reg(void __iomem *addr, u8 index, u8 data) |
| 133 | { |
| 134 | u32 tmp = index; |
| 135 | |
| 136 | iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2); |
| 137 | mmiowb(); |
| 138 | udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */ |
| 139 | if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) |
| 140 | return -EIO; /* error: NEW_CYCLE not cleared */ |
| 141 | if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) { |
| 142 | /* reset DIRECT_ABORT bit */ |
| 143 | iowrite32(DIRECT_ABORT, addr + IIC_CSR1); |
| 144 | return -EIO; /* error: DIRECT_ABORT set */ |
| 145 | } |
| 146 | return 0; |
| 147 | } |
| 148 | |
| 149 | /** |
| 150 | * write_i2c_reg_nowait - writes to an internal i2c register |
| 151 | * |
| 152 | * @addr: dt3155 mmio base address |
| 153 | * @index: index (internal address) of register to read |
| 154 | * @data: data to be written |
| 155 | * |
| 156 | * This function starts writting the specified (by index) register |
| 157 | * and then returns. |
| 158 | */ |
| 159 | static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data) |
| 160 | { |
| 161 | u32 tmp = index; |
| 162 | |
| 163 | iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2); |
| 164 | mmiowb(); |
| 165 | } |
| 166 | |
| 167 | /** |
| 168 | * wait_i2c_reg - waits the read/write to finish |
| 169 | * |
| 170 | * @addr: dt3155 mmio base address |
| 171 | * |
| 172 | * returns: zero on success or error code |
| 173 | * |
| 174 | * This function waits reading/writting to finish. |
| 175 | */ |
| 176 | static int wait_i2c_reg(void __iomem *addr) |
| 177 | { |
| 178 | if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) |
| 179 | udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */ |
| 180 | if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) |
| 181 | return -EIO; /* error: NEW_CYCLE not cleared */ |
| 182 | if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) { |
| 183 | /* reset DIRECT_ABORT bit */ |
| 184 | iowrite32(DIRECT_ABORT, addr + IIC_CSR1); |
| 185 | return -EIO; /* error: DIRECT_ABORT set */ |
| 186 | } |
| 187 | return 0; |
| 188 | } |
| 189 | |
| 190 | static int |
| 191 | dt3155_start_acq(struct dt3155_priv *pd) |
| 192 | { |
| 193 | struct vb2_buffer *vb = pd->curr_buf; |
| 194 | dma_addr_t dma_addr; |
| 195 | |
| 196 | dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0); |
| 197 | iowrite32(dma_addr, pd->regs + EVEN_DMA_START); |
| 198 | iowrite32(dma_addr + img_width, pd->regs + ODD_DMA_START); |
| 199 | iowrite32(img_width, pd->regs + EVEN_DMA_STRIDE); |
| 200 | iowrite32(img_width, pd->regs + ODD_DMA_STRIDE); |
| 201 | /* enable interrupts, clear all irq flags */ |
| 202 | iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START | |
| 203 | FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR); |
| 204 | iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | |
| 205 | FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD, |
| 206 | pd->regs + CSR1); |
| 207 | wait_i2c_reg(pd->regs); |
| 208 | write_i2c_reg(pd->regs, CONFIG, pd->config); |
| 209 | write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE); |
| 210 | write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE); |
| 211 | |
| 212 | /* start the board */ |
| 213 | write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD); |
| 214 | return 0; /* success */ |
| 215 | } |
| 216 | |
| 217 | /* |
| 218 | * driver-specific callbacks (vb2_ops) |
| 219 | */ |
| 220 | static int |
| 221 | dt3155_queue_setup(struct vb2_queue *q, const struct v4l2_format *fmt, |
| 222 | unsigned int *num_buffers, unsigned int *num_planes, |
| 223 | unsigned int sizes[], void *alloc_ctxs[]) |
| 224 | |
| 225 | { |
| 226 | struct dt3155_priv *pd = vb2_get_drv_priv(q); |
| 227 | void *ret; |
| 228 | |
| 229 | if (*num_buffers == 0) |
| 230 | *num_buffers = 1; |
| 231 | *num_planes = 1; |
| 232 | sizes[0] = img_width * img_height; |
| 233 | if (pd->q->alloc_ctx[0]) |
| 234 | return 0; |
| 235 | ret = vb2_dma_contig_init_ctx(&pd->pdev->dev); |
| 236 | if (IS_ERR(ret)) |
| 237 | return PTR_ERR(ret); |
| 238 | pd->q->alloc_ctx[0] = ret; |
| 239 | return 0; |
| 240 | } |
| 241 | |
| 242 | static void |
| 243 | dt3155_wait_prepare(struct vb2_queue *q) |
| 244 | { |
| 245 | struct dt3155_priv *pd = vb2_get_drv_priv(q); |
| 246 | |
| 247 | mutex_unlock(pd->vdev->lock); |
| 248 | } |
| 249 | |
| 250 | static void |
| 251 | dt3155_wait_finish(struct vb2_queue *q) |
| 252 | { |
| 253 | struct dt3155_priv *pd = vb2_get_drv_priv(q); |
| 254 | |
| 255 | mutex_lock(pd->vdev->lock); |
| 256 | } |
| 257 | |
| 258 | static int |
| 259 | dt3155_buf_prepare(struct vb2_buffer *vb) |
| 260 | { |
| 261 | vb2_set_plane_payload(vb, 0, img_width * img_height); |
| 262 | return 0; |
| 263 | } |
| 264 | |
| 265 | static int |
| 266 | dt3155_stop_streaming(struct vb2_queue *q) |
| 267 | { |
| 268 | struct dt3155_priv *pd = vb2_get_drv_priv(q); |
| 269 | struct vb2_buffer *vb; |
| 270 | |
| 271 | spin_lock_irq(&pd->lock); |
| 272 | while (!list_empty(&pd->dmaq)) { |
| 273 | vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry); |
| 274 | list_del(&vb->done_entry); |
| 275 | vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); |
| 276 | } |
| 277 | spin_unlock_irq(&pd->lock); |
| 278 | msleep(45); /* irq hendler will stop the hardware */ |
| 279 | return 0; |
| 280 | } |
| 281 | |
| 282 | static void |
| 283 | dt3155_buf_queue(struct vb2_buffer *vb) |
| 284 | { |
| 285 | struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue); |
| 286 | |
| 287 | /* pd->q->streaming = 1 when dt3155_buf_queue() is invoked */ |
| 288 | spin_lock_irq(&pd->lock); |
| 289 | if (pd->curr_buf) |
| 290 | list_add_tail(&vb->done_entry, &pd->dmaq); |
| 291 | else { |
| 292 | pd->curr_buf = vb; |
| 293 | dt3155_start_acq(pd); |
| 294 | } |
| 295 | spin_unlock_irq(&pd->lock); |
| 296 | } |
| 297 | /* |
| 298 | * end driver-specific callbacks |
| 299 | */ |
| 300 | |
| 301 | const struct vb2_ops q_ops = { |
| 302 | .queue_setup = dt3155_queue_setup, |
| 303 | .wait_prepare = dt3155_wait_prepare, |
| 304 | .wait_finish = dt3155_wait_finish, |
| 305 | .buf_prepare = dt3155_buf_prepare, |
| 306 | .stop_streaming = dt3155_stop_streaming, |
| 307 | .buf_queue = dt3155_buf_queue, |
| 308 | }; |
| 309 | |
| 310 | static irqreturn_t |
| 311 | dt3155_irq_handler_even(int irq, void *dev_id) |
| 312 | { |
| 313 | struct dt3155_priv *ipd = dev_id; |
| 314 | struct vb2_buffer *ivb; |
| 315 | dma_addr_t dma_addr; |
| 316 | u32 tmp; |
| 317 | |
| 318 | tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD); |
| 319 | if (!tmp) |
| 320 | return IRQ_NONE; /* not our irq */ |
| 321 | if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) { |
| 322 | iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START, |
| 323 | ipd->regs + INT_CSR); |
| 324 | ipd->field_count++; |
| 325 | return IRQ_HANDLED; /* start of field irq */ |
| 326 | } |
| 327 | if ((tmp & FLD_START) && (tmp & FLD_END_ODD)) |
| 328 | ipd->stats.start_before_end++; |
| 329 | /* check for corrupted fields */ |
| 330 | /* write_i2c_reg(ipd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE); */ |
| 331 | /* write_i2c_reg(ipd->regs, ODD_CSR, CSR_ERROR | CSR_DONE); */ |
| 332 | tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD); |
| 333 | if (tmp) { |
| 334 | ipd->stats.corrupted_fields++; |
| 335 | iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | |
| 336 | FLD_DN_ODD | FLD_DN_EVEN | |
| 337 | CAP_CONT_EVEN | CAP_CONT_ODD, |
| 338 | ipd->regs + CSR1); |
| 339 | mmiowb(); |
| 340 | } |
| 341 | |
| 342 | spin_lock(&ipd->lock); |
| 343 | if (ipd->curr_buf) { |
| 344 | do_gettimeofday(&ipd->curr_buf->v4l2_buf.timestamp); |
| 345 | ipd->curr_buf->v4l2_buf.sequence = (ipd->field_count) >> 1; |
| 346 | vb2_buffer_done(ipd->curr_buf, VB2_BUF_STATE_DONE); |
| 347 | } |
| 348 | |
| 349 | if (!ipd->q->streaming || list_empty(&ipd->dmaq)) |
| 350 | goto stop_dma; |
| 351 | ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry); |
| 352 | list_del(&ivb->done_entry); |
| 353 | ipd->curr_buf = ivb; |
| 354 | dma_addr = vb2_dma_contig_plane_dma_addr(ivb, 0); |
| 355 | iowrite32(dma_addr, ipd->regs + EVEN_DMA_START); |
| 356 | iowrite32(dma_addr + img_width, ipd->regs + ODD_DMA_START); |
| 357 | iowrite32(img_width, ipd->regs + EVEN_DMA_STRIDE); |
| 358 | iowrite32(img_width, ipd->regs + ODD_DMA_STRIDE); |
| 359 | mmiowb(); |
| 360 | /* enable interrupts, clear all irq flags */ |
| 361 | iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START | |
| 362 | FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR); |
| 363 | spin_unlock(&ipd->lock); |
| 364 | return IRQ_HANDLED; |
| 365 | |
| 366 | stop_dma: |
| 367 | ipd->curr_buf = NULL; |
| 368 | /* stop the board */ |
| 369 | write_i2c_reg_nowait(ipd->regs, CSR2, ipd->csr2); |
| 370 | iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | |
| 371 | FLD_DN_ODD | FLD_DN_EVEN, ipd->regs + CSR1); |
| 372 | /* disable interrupts, clear all irq flags */ |
| 373 | iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR); |
| 374 | spin_unlock(&ipd->lock); |
| 375 | return IRQ_HANDLED; |
| 376 | } |
| 377 | |
| 378 | static int |
| 379 | dt3155_open(struct file *filp) |
| 380 | { |
| 381 | int ret = 0; |
| 382 | struct dt3155_priv *pd = video_drvdata(filp); |
| 383 | |
| 384 | if (mutex_lock_interruptible(&pd->mux)) |
| 385 | return -ERESTARTSYS; |
| 386 | if (!pd->users) { |
| 387 | pd->q = kzalloc(sizeof(*pd->q), GFP_KERNEL); |
| 388 | if (!pd->q) { |
| 389 | ret = -ENOMEM; |
| 390 | goto err_alloc_queue; |
| 391 | } |
| 392 | pd->q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; |
| 393 | pd->q->io_modes = VB2_READ | VB2_MMAP; |
| 394 | pd->q->ops = &q_ops; |
| 395 | pd->q->mem_ops = &vb2_dma_contig_memops; |
| 396 | pd->q->drv_priv = pd; |
| 397 | pd->curr_buf = NULL; |
| 398 | pd->field_count = 0; |
| 399 | ret = vb2_queue_init(pd->q); |
| 400 | if (ret < 0) |
| 401 | return ret; |
| 402 | INIT_LIST_HEAD(&pd->dmaq); |
| 403 | spin_lock_init(&pd->lock); |
| 404 | /* disable all irqs, clear all irq flags */ |
| 405 | iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, |
| 406 | pd->regs + INT_CSR); |
| 407 | ret = request_irq(pd->pdev->irq, dt3155_irq_handler_even, |
| 408 | IRQF_SHARED, DT3155_NAME, pd); |
| 409 | if (ret) |
| 410 | goto err_request_irq; |
| 411 | } |
| 412 | pd->users++; |
| 413 | return 0; /* success */ |
| 414 | err_request_irq: |
| 415 | kfree(pd->q); |
| 416 | pd->q = NULL; |
| 417 | err_alloc_queue: |
| 418 | mutex_unlock(&pd->mux); |
| 419 | return ret; |
| 420 | } |
| 421 | |
| 422 | static int |
| 423 | dt3155_release(struct file *filp) |
| 424 | { |
| 425 | struct dt3155_priv *pd = video_drvdata(filp); |
| 426 | |
| 427 | mutex_lock(&pd->mux); |
| 428 | pd->users--; |
| 429 | BUG_ON(pd->users < 0); |
| 430 | if (!pd->users) { |
| 431 | vb2_queue_release(pd->q); |
| 432 | free_irq(pd->pdev->irq, pd); |
| 433 | if (pd->q->alloc_ctx[0]) |
| 434 | vb2_dma_contig_cleanup_ctx(pd->q->alloc_ctx[0]); |
| 435 | kfree(pd->q); |
| 436 | pd->q = NULL; |
| 437 | } |
| 438 | mutex_unlock(&pd->mux); |
| 439 | return 0; |
| 440 | } |
| 441 | |
| 442 | static ssize_t |
| 443 | dt3155_read(struct file *filp, char __user *user, size_t size, loff_t *loff) |
| 444 | { |
| 445 | struct dt3155_priv *pd = video_drvdata(filp); |
| 446 | ssize_t res; |
| 447 | |
| 448 | if (mutex_lock_interruptible(&pd->mux)) |
| 449 | return -ERESTARTSYS; |
| 450 | res = vb2_read(pd->q, user, size, loff, filp->f_flags & O_NONBLOCK); |
| 451 | mutex_unlock(&pd->mux); |
| 452 | return res; |
| 453 | } |
| 454 | |
| 455 | static unsigned int |
| 456 | dt3155_poll(struct file *filp, struct poll_table_struct *polltbl) |
| 457 | { |
| 458 | struct dt3155_priv *pd = video_drvdata(filp); |
| 459 | unsigned int res; |
| 460 | |
| 461 | mutex_lock(&pd->mux); |
| 462 | res = vb2_poll(pd->q, filp, polltbl); |
| 463 | mutex_unlock(&pd->mux); |
| 464 | return res; |
| 465 | } |
| 466 | |
| 467 | static int |
| 468 | dt3155_mmap(struct file *filp, struct vm_area_struct *vma) |
| 469 | { |
| 470 | struct dt3155_priv *pd = video_drvdata(filp); |
| 471 | int res; |
| 472 | |
| 473 | if (mutex_lock_interruptible(&pd->mux)) |
| 474 | return -ERESTARTSYS; |
| 475 | res = vb2_mmap(pd->q, vma); |
| 476 | mutex_unlock(&pd->mux); |
| 477 | return res; |
| 478 | } |
| 479 | |
| 480 | static const struct v4l2_file_operations dt3155_fops = { |
| 481 | .owner = THIS_MODULE, |
| 482 | .open = dt3155_open, |
| 483 | .release = dt3155_release, |
| 484 | .read = dt3155_read, |
| 485 | .poll = dt3155_poll, |
| 486 | .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */ |
| 487 | .mmap = dt3155_mmap, |
| 488 | }; |
| 489 | |
| 490 | static int |
| 491 | dt3155_ioc_streamon(struct file *filp, void *p, enum v4l2_buf_type type) |
| 492 | { |
| 493 | struct dt3155_priv *pd = video_drvdata(filp); |
| 494 | |
| 495 | return vb2_streamon(pd->q, type); |
| 496 | } |
| 497 | |
| 498 | static int |
| 499 | dt3155_ioc_streamoff(struct file *filp, void *p, enum v4l2_buf_type type) |
| 500 | { |
| 501 | struct dt3155_priv *pd = video_drvdata(filp); |
| 502 | |
| 503 | return vb2_streamoff(pd->q, type); |
| 504 | } |
| 505 | |
| 506 | static int |
| 507 | dt3155_ioc_querycap(struct file *filp, void *p, struct v4l2_capability *cap) |
| 508 | { |
| 509 | struct dt3155_priv *pd = video_drvdata(filp); |
| 510 | |
| 511 | strcpy(cap->driver, DT3155_NAME); |
| 512 | strcpy(cap->card, DT3155_NAME " frame grabber"); |
| 513 | sprintf(cap->bus_info, "PCI:%s", pci_name(pd->pdev)); |
| 514 | cap->version = |
| 515 | KERNEL_VERSION(DT3155_VER_MAJ, DT3155_VER_MIN, DT3155_VER_EXT); |
| 516 | cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | |
| 517 | DT3155_CAPTURE_METHOD; |
| 518 | return 0; |
| 519 | } |
| 520 | |
| 521 | static int |
| 522 | dt3155_ioc_enum_fmt_vid_cap(struct file *filp, void *p, struct v4l2_fmtdesc *f) |
| 523 | { |
| 524 | if (f->index >= NUM_OF_FORMATS) |
| 525 | return -EINVAL; |
| 526 | *f = frame_std[f->index]; |
| 527 | return 0; |
| 528 | } |
| 529 | |
| 530 | static int |
| 531 | dt3155_ioc_g_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f) |
| 532 | { |
| 533 | if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) |
| 534 | return -EINVAL; |
| 535 | f->fmt.pix.width = img_width; |
| 536 | f->fmt.pix.height = img_height; |
| 537 | f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY; |
| 538 | f->fmt.pix.field = V4L2_FIELD_NONE; |
| 539 | f->fmt.pix.bytesperline = f->fmt.pix.width; |
| 540 | f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height; |
| 541 | f->fmt.pix.colorspace = 0; |
| 542 | f->fmt.pix.priv = 0; |
| 543 | return 0; |
| 544 | } |
| 545 | |
| 546 | static int |
| 547 | dt3155_ioc_try_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f) |
| 548 | { |
| 549 | if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) |
| 550 | return -EINVAL; |
| 551 | if (f->fmt.pix.width == img_width && |
| 552 | f->fmt.pix.height == img_height && |
| 553 | f->fmt.pix.pixelformat == V4L2_PIX_FMT_GREY && |
| 554 | f->fmt.pix.field == V4L2_FIELD_NONE && |
| 555 | f->fmt.pix.bytesperline == f->fmt.pix.width && |
| 556 | f->fmt.pix.sizeimage == f->fmt.pix.width * f->fmt.pix.height) |
| 557 | return 0; |
| 558 | else |
| 559 | return -EINVAL; |
| 560 | } |
| 561 | |
| 562 | static int |
| 563 | dt3155_ioc_s_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f) |
| 564 | { |
| 565 | return dt3155_ioc_g_fmt_vid_cap(filp, p, f); |
| 566 | } |
| 567 | |
| 568 | static int |
| 569 | dt3155_ioc_reqbufs(struct file *filp, void *p, struct v4l2_requestbuffers *b) |
| 570 | { |
| 571 | struct dt3155_priv *pd = video_drvdata(filp); |
| 572 | |
| 573 | return vb2_reqbufs(pd->q, b); |
| 574 | } |
| 575 | |
| 576 | static int |
| 577 | dt3155_ioc_querybuf(struct file *filp, void *p, struct v4l2_buffer *b) |
| 578 | { |
| 579 | struct dt3155_priv *pd = video_drvdata(filp); |
| 580 | |
| 581 | return vb2_querybuf(pd->q, b); |
| 582 | } |
| 583 | |
| 584 | static int |
| 585 | dt3155_ioc_qbuf(struct file *filp, void *p, struct v4l2_buffer *b) |
| 586 | { |
| 587 | struct dt3155_priv *pd = video_drvdata(filp); |
| 588 | |
| 589 | return vb2_qbuf(pd->q, b); |
| 590 | } |
| 591 | |
| 592 | static int |
| 593 | dt3155_ioc_dqbuf(struct file *filp, void *p, struct v4l2_buffer *b) |
| 594 | { |
| 595 | struct dt3155_priv *pd = video_drvdata(filp); |
| 596 | |
| 597 | return vb2_dqbuf(pd->q, b, filp->f_flags & O_NONBLOCK); |
| 598 | } |
| 599 | |
| 600 | static int |
| 601 | dt3155_ioc_querystd(struct file *filp, void *p, v4l2_std_id *norm) |
| 602 | { |
| 603 | *norm = DT3155_CURRENT_NORM; |
| 604 | return 0; |
| 605 | } |
| 606 | |
| 607 | static int |
| 608 | dt3155_ioc_g_std(struct file *filp, void *p, v4l2_std_id *norm) |
| 609 | { |
| 610 | *norm = DT3155_CURRENT_NORM; |
| 611 | return 0; |
| 612 | } |
| 613 | |
| 614 | static int |
| 615 | dt3155_ioc_s_std(struct file *filp, void *p, v4l2_std_id *norm) |
| 616 | { |
| 617 | if (*norm & DT3155_CURRENT_NORM) |
| 618 | return 0; |
| 619 | return -EINVAL; |
| 620 | } |
| 621 | |
| 622 | static int |
| 623 | dt3155_ioc_enum_input(struct file *filp, void *p, struct v4l2_input *input) |
| 624 | { |
| 625 | if (input->index) |
| 626 | return -EINVAL; |
| 627 | strcpy(input->name, "Coax in"); |
| 628 | input->type = V4L2_INPUT_TYPE_CAMERA; |
| 629 | /* |
| 630 | * FIXME: input->std = 0 according to v4l2 API |
| 631 | * VIDIOC_G_STD, VIDIOC_S_STD, VIDIOC_QUERYSTD and VIDIOC_ENUMSTD |
| 632 | * should return -EINVAL |
| 633 | */ |
| 634 | input->std = DT3155_CURRENT_NORM; |
| 635 | input->status = 0;/* FIXME: add sync detection & V4L2_IN_ST_NO_H_LOCK */ |
| 636 | return 0; |
| 637 | } |
| 638 | |
| 639 | static int |
| 640 | dt3155_ioc_g_input(struct file *filp, void *p, unsigned int *i) |
| 641 | { |
| 642 | *i = 0; |
| 643 | return 0; |
| 644 | } |
| 645 | |
| 646 | static int |
| 647 | dt3155_ioc_s_input(struct file *filp, void *p, unsigned int i) |
| 648 | { |
| 649 | if (i) |
| 650 | return -EINVAL; |
| 651 | return 0; |
| 652 | } |
| 653 | |
| 654 | static int |
| 655 | dt3155_ioc_g_parm(struct file *filp, void *p, struct v4l2_streamparm *parms) |
| 656 | { |
| 657 | if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) |
| 658 | return -EINVAL; |
| 659 | parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; |
| 660 | parms->parm.capture.capturemode = 0; |
| 661 | parms->parm.capture.timeperframe.numerator = 1001; |
| 662 | parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000; |
| 663 | parms->parm.capture.extendedmode = 0; |
| 664 | parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */ |
| 665 | return 0; |
| 666 | } |
| 667 | |
| 668 | static int |
| 669 | dt3155_ioc_s_parm(struct file *filp, void *p, struct v4l2_streamparm *parms) |
| 670 | { |
| 671 | if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) |
| 672 | return -EINVAL; |
| 673 | parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; |
| 674 | parms->parm.capture.capturemode = 0; |
| 675 | parms->parm.capture.timeperframe.numerator = 1001; |
| 676 | parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000; |
| 677 | parms->parm.capture.extendedmode = 0; |
| 678 | parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */ |
| 679 | return 0; |
| 680 | } |
| 681 | |
| 682 | static const struct v4l2_ioctl_ops dt3155_ioctl_ops = { |
| 683 | .vidioc_streamon = dt3155_ioc_streamon, |
| 684 | .vidioc_streamoff = dt3155_ioc_streamoff, |
| 685 | .vidioc_querycap = dt3155_ioc_querycap, |
| 686 | /* |
| 687 | .vidioc_g_priority = dt3155_ioc_g_priority, |
| 688 | .vidioc_s_priority = dt3155_ioc_s_priority, |
| 689 | */ |
| 690 | .vidioc_enum_fmt_vid_cap = dt3155_ioc_enum_fmt_vid_cap, |
| 691 | .vidioc_try_fmt_vid_cap = dt3155_ioc_try_fmt_vid_cap, |
| 692 | .vidioc_g_fmt_vid_cap = dt3155_ioc_g_fmt_vid_cap, |
| 693 | .vidioc_s_fmt_vid_cap = dt3155_ioc_s_fmt_vid_cap, |
| 694 | .vidioc_reqbufs = dt3155_ioc_reqbufs, |
| 695 | .vidioc_querybuf = dt3155_ioc_querybuf, |
| 696 | .vidioc_qbuf = dt3155_ioc_qbuf, |
| 697 | .vidioc_dqbuf = dt3155_ioc_dqbuf, |
| 698 | .vidioc_querystd = dt3155_ioc_querystd, |
| 699 | .vidioc_g_std = dt3155_ioc_g_std, |
| 700 | .vidioc_s_std = dt3155_ioc_s_std, |
| 701 | .vidioc_enum_input = dt3155_ioc_enum_input, |
| 702 | .vidioc_g_input = dt3155_ioc_g_input, |
| 703 | .vidioc_s_input = dt3155_ioc_s_input, |
| 704 | /* |
| 705 | .vidioc_queryctrl = dt3155_ioc_queryctrl, |
| 706 | .vidioc_g_ctrl = dt3155_ioc_g_ctrl, |
| 707 | .vidioc_s_ctrl = dt3155_ioc_s_ctrl, |
| 708 | .vidioc_querymenu = dt3155_ioc_querymenu, |
| 709 | .vidioc_g_ext_ctrls = dt3155_ioc_g_ext_ctrls, |
| 710 | .vidioc_s_ext_ctrls = dt3155_ioc_s_ext_ctrls, |
| 711 | */ |
| 712 | .vidioc_g_parm = dt3155_ioc_g_parm, |
| 713 | .vidioc_s_parm = dt3155_ioc_s_parm, |
| 714 | /* |
| 715 | .vidioc_cropcap = dt3155_ioc_cropcap, |
| 716 | .vidioc_g_crop = dt3155_ioc_g_crop, |
| 717 | .vidioc_s_crop = dt3155_ioc_s_crop, |
| 718 | .vidioc_enum_framesizes = dt3155_ioc_enum_framesizes, |
| 719 | .vidioc_enum_frameintervals = dt3155_ioc_enum_frameintervals, |
| 720 | */ |
| 721 | }; |
| 722 | |
| 723 | static int __devinit |
| 724 | dt3155_init_board(struct pci_dev *pdev) |
| 725 | { |
| 726 | struct dt3155_priv *pd = pci_get_drvdata(pdev); |
| 727 | void *buf_cpu; |
| 728 | dma_addr_t buf_dma; |
| 729 | int i; |
| 730 | u8 tmp; |
| 731 | |
| 732 | pci_set_master(pdev); /* dt3155 needs it */ |
| 733 | |
| 734 | /* resetting the adapter */ |
| 735 | iowrite32(FLD_CRPT_ODD | FLD_CRPT_EVEN | FLD_DN_ODD | FLD_DN_EVEN, |
| 736 | pd->regs + CSR1); |
| 737 | mmiowb(); |
| 738 | msleep(20); |
| 739 | |
| 740 | /* initializing adaper registers */ |
| 741 | iowrite32(FIFO_EN | SRST, pd->regs + CSR1); |
| 742 | mmiowb(); |
| 743 | iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT); |
| 744 | iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT); |
| 745 | iowrite32(0x00000020, pd->regs + FIFO_TRIGER); |
| 746 | iowrite32(0x00000103, pd->regs + XFER_MODE); |
| 747 | iowrite32(0, pd->regs + RETRY_WAIT_CNT); |
| 748 | iowrite32(0, pd->regs + INT_CSR); |
| 749 | iowrite32(1, pd->regs + EVEN_FLD_MASK); |
| 750 | iowrite32(1, pd->regs + ODD_FLD_MASK); |
| 751 | iowrite32(0, pd->regs + MASK_LENGTH); |
| 752 | iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT); |
| 753 | iowrite32(0x01010101, pd->regs + IIC_CLK_DUR); |
| 754 | mmiowb(); |
| 755 | |
| 756 | /* verifying that we have a DT3155 board (not just a SAA7116 chip) */ |
| 757 | read_i2c_reg(pd->regs, DT_ID, &tmp); |
| 758 | if (tmp != DT3155_ID) |
| 759 | return -ENODEV; |
| 760 | |
| 761 | /* initialize AD LUT */ |
| 762 | write_i2c_reg(pd->regs, AD_ADDR, 0); |
| 763 | for (i = 0; i < 256; i++) |
| 764 | write_i2c_reg(pd->regs, AD_LUT, i); |
| 765 | |
| 766 | /* initialize ADC references */ |
| 767 | /* FIXME: pos_ref & neg_ref depend on VT_50HZ */ |
| 768 | write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG); |
| 769 | write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3); |
| 770 | write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF); |
| 771 | write_i2c_reg(pd->regs, AD_CMD, 34); |
| 772 | write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF); |
| 773 | write_i2c_reg(pd->regs, AD_CMD, 0); |
| 774 | |
| 775 | /* initialize PM LUT */ |
| 776 | write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM); |
| 777 | for (i = 0; i < 256; i++) { |
| 778 | write_i2c_reg(pd->regs, PM_LUT_ADDR, i); |
| 779 | write_i2c_reg(pd->regs, PM_LUT_DATA, i); |
| 780 | } |
| 781 | write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL); |
| 782 | for (i = 0; i < 256; i++) { |
| 783 | write_i2c_reg(pd->regs, PM_LUT_ADDR, i); |
| 784 | write_i2c_reg(pd->regs, PM_LUT_DATA, i); |
| 785 | } |
| 786 | write_i2c_reg(pd->regs, CONFIG, pd->config); /* ACQ_MODE_EVEN */ |
| 787 | |
| 788 | /* select chanel 1 for input and set sync level */ |
| 789 | write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG); |
| 790 | write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3); |
| 791 | |
| 792 | /* allocate memory, and initialize the DMA machine */ |
| 793 | buf_cpu = dma_alloc_coherent(&pdev->dev, DT3155_BUF_SIZE, &buf_dma, |
| 794 | GFP_KERNEL); |
| 795 | if (!buf_cpu) |
| 796 | return -ENOMEM; |
| 797 | iowrite32(buf_dma, pd->regs + EVEN_DMA_START); |
| 798 | iowrite32(buf_dma, pd->regs + ODD_DMA_START); |
| 799 | iowrite32(0, pd->regs + EVEN_DMA_STRIDE); |
| 800 | iowrite32(0, pd->regs + ODD_DMA_STRIDE); |
| 801 | |
| 802 | /* Perform a pseudo even field acquire */ |
| 803 | iowrite32(FIFO_EN | SRST | CAP_CONT_ODD, pd->regs + CSR1); |
| 804 | write_i2c_reg(pd->regs, CSR2, pd->csr2 | SYNC_SNTL); |
| 805 | write_i2c_reg(pd->regs, CONFIG, pd->config); |
| 806 | write_i2c_reg(pd->regs, EVEN_CSR, CSR_SNGL); |
| 807 | write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | SYNC_SNTL); |
| 808 | msleep(100); |
| 809 | read_i2c_reg(pd->regs, CSR2, &tmp); |
| 810 | write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE); |
| 811 | write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE); |
| 812 | write_i2c_reg(pd->regs, CSR2, pd->csr2); |
| 813 | iowrite32(FIFO_EN | SRST | FLD_DN_EVEN | FLD_DN_ODD, pd->regs + CSR1); |
| 814 | |
| 815 | /* deallocate memory */ |
| 816 | dma_free_coherent(&pdev->dev, DT3155_BUF_SIZE, buf_cpu, buf_dma); |
| 817 | if (tmp & BUSY_EVEN) |
| 818 | return -EIO; |
| 819 | return 0; |
| 820 | } |
| 821 | |
| 822 | static struct video_device dt3155_vdev = { |
| 823 | .name = DT3155_NAME, |
| 824 | .fops = &dt3155_fops, |
| 825 | .ioctl_ops = &dt3155_ioctl_ops, |
| 826 | .minor = -1, |
| 827 | .release = video_device_release, |
| 828 | .tvnorms = DT3155_CURRENT_NORM, |
| 829 | .current_norm = DT3155_CURRENT_NORM, |
| 830 | }; |
| 831 | |
| 832 | /* same as in drivers/base/dma-coherent.c */ |
| 833 | struct dma_coherent_mem { |
| 834 | void *virt_base; |
| 835 | dma_addr_t device_base; |
| 836 | int size; |
| 837 | int flags; |
| 838 | unsigned long *bitmap; |
| 839 | }; |
| 840 | |
| 841 | static int __devinit |
| 842 | dt3155_alloc_coherent(struct device *dev, size_t size, int flags) |
| 843 | { |
| 844 | struct dma_coherent_mem *mem; |
| 845 | dma_addr_t dev_base; |
| 846 | int pages = size >> PAGE_SHIFT; |
| 847 | int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long); |
| 848 | |
| 849 | if ((flags & DMA_MEMORY_MAP) == 0) |
| 850 | goto out; |
| 851 | if (!size) |
| 852 | goto out; |
| 853 | if (dev->dma_mem) |
| 854 | goto out; |
| 855 | |
| 856 | mem = kzalloc(sizeof(*mem), GFP_KERNEL); |
| 857 | if (!mem) |
| 858 | goto out; |
| 859 | mem->virt_base = dma_alloc_coherent(dev, size, &dev_base, |
| 860 | DT3155_COH_FLAGS); |
| 861 | if (!mem->virt_base) |
| 862 | goto err_alloc_coherent; |
| 863 | mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL); |
| 864 | if (!mem->bitmap) |
| 865 | goto err_bitmap; |
| 866 | |
| 867 | /* coherent_dma_mask is already set to 32 bits */ |
| 868 | mem->device_base = dev_base; |
| 869 | mem->size = pages; |
| 870 | mem->flags = flags; |
| 871 | dev->dma_mem = mem; |
| 872 | return DMA_MEMORY_MAP; |
| 873 | |
| 874 | err_bitmap: |
| 875 | dma_free_coherent(dev, size, mem->virt_base, dev_base); |
| 876 | err_alloc_coherent: |
| 877 | kfree(mem); |
| 878 | out: |
| 879 | return 0; |
| 880 | } |
| 881 | |
| 882 | static void __devexit |
| 883 | dt3155_free_coherent(struct device *dev) |
| 884 | { |
| 885 | struct dma_coherent_mem *mem = dev->dma_mem; |
| 886 | |
| 887 | if (!mem) |
| 888 | return; |
| 889 | dev->dma_mem = NULL; |
| 890 | dma_free_coherent(dev, mem->size << PAGE_SHIFT, |
| 891 | mem->virt_base, mem->device_base); |
| 892 | kfree(mem->bitmap); |
| 893 | kfree(mem); |
| 894 | } |
| 895 | |
| 896 | static int __devinit |
| 897 | dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
| 898 | { |
| 899 | int err; |
| 900 | struct dt3155_priv *pd; |
| 901 | |
| 902 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
| 903 | if (err) |
| 904 | return -ENODEV; |
| 905 | err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
| 906 | if (err) |
| 907 | return -ENODEV; |
| 908 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); |
| 909 | if (!pd) |
| 910 | return -ENOMEM; |
| 911 | pd->vdev = video_device_alloc(); |
| 912 | if (!pd->vdev) |
| 913 | goto err_video_device_alloc; |
| 914 | *pd->vdev = dt3155_vdev; |
| 915 | pci_set_drvdata(pdev, pd); /* for use in dt3155_remove() */ |
| 916 | video_set_drvdata(pd->vdev, pd); /* for use in video_fops */ |
| 917 | pd->users = 0; |
| 918 | pd->pdev = pdev; |
| 919 | INIT_LIST_HEAD(&pd->dmaq); |
| 920 | mutex_init(&pd->mux); |
| 921 | pd->vdev->lock = &pd->mux; /* for locking v4l2_file_operations */ |
| 922 | spin_lock_init(&pd->lock); |
| 923 | pd->csr2 = csr2_init; |
| 924 | pd->config = config_init; |
| 925 | err = pci_enable_device(pdev); |
| 926 | if (err) |
| 927 | goto err_enable_dev; |
| 928 | err = pci_request_region(pdev, 0, pci_name(pdev)); |
| 929 | if (err) |
| 930 | goto err_req_region; |
| 931 | pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0)); |
| 932 | if (!pd->regs) { |
| 933 | err = -ENOMEM; |
| 934 | goto err_pci_iomap; |
| 935 | } |
| 936 | err = dt3155_init_board(pdev); |
| 937 | if (err) |
| 938 | goto err_init_board; |
| 939 | err = video_register_device(pd->vdev, VFL_TYPE_GRABBER, -1); |
| 940 | if (err) |
| 941 | goto err_init_board; |
| 942 | if (dt3155_alloc_coherent(&pdev->dev, DT3155_CHUNK_SIZE, |
| 943 | DMA_MEMORY_MAP)) |
| 944 | dev_info(&pdev->dev, "preallocated 8 buffers\n"); |
| 945 | dev_info(&pdev->dev, "/dev/video%i is ready\n", pd->vdev->minor); |
| 946 | return 0; /* success */ |
| 947 | |
| 948 | err_init_board: |
| 949 | pci_iounmap(pdev, pd->regs); |
| 950 | err_pci_iomap: |
| 951 | pci_release_region(pdev, 0); |
| 952 | err_req_region: |
| 953 | pci_disable_device(pdev); |
| 954 | err_enable_dev: |
| 955 | video_device_release(pd->vdev); |
| 956 | err_video_device_alloc: |
| 957 | kfree(pd); |
| 958 | return err; |
| 959 | } |
| 960 | |
| 961 | static void __devexit |
| 962 | dt3155_remove(struct pci_dev *pdev) |
| 963 | { |
| 964 | struct dt3155_priv *pd = pci_get_drvdata(pdev); |
| 965 | |
| 966 | dt3155_free_coherent(&pdev->dev); |
| 967 | video_unregister_device(pd->vdev); |
| 968 | pci_iounmap(pdev, pd->regs); |
| 969 | pci_release_region(pdev, 0); |
| 970 | pci_disable_device(pdev); |
| 971 | /* |
| 972 | * video_device_release() is invoked automatically |
| 973 | * see: struct video_device dt3155_vdev |
| 974 | */ |
| 975 | kfree(pd); |
| 976 | } |
| 977 | |
| 978 | static DEFINE_PCI_DEVICE_TABLE(pci_ids) = { |
| 979 | { PCI_DEVICE(DT3155_VENDOR_ID, DT3155_DEVICE_ID) }, |
| 980 | { 0, /* zero marks the end */ }, |
| 981 | }; |
| 982 | MODULE_DEVICE_TABLE(pci, pci_ids); |
| 983 | |
| 984 | static struct pci_driver pci_driver = { |
| 985 | .name = DT3155_NAME, |
| 986 | .id_table = pci_ids, |
| 987 | .probe = dt3155_probe, |
| 988 | .remove = __devexit_p(dt3155_remove), |
| 989 | }; |
| 990 | |
| 991 | module_pci_driver(pci_driver); |
| 992 | |
| 993 | MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber"); |
| 994 | MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>"); |
| 995 | MODULE_VERSION(DT3155_VERSION); |
| 996 | MODULE_LICENSE("GPL"); |