| 1 | /* |
| 2 | * core_intr.c - DesignWare HS OTG Controller common interrupt handling |
| 3 | * |
| 4 | * Copyright (C) 2004-2013 Synopsys, Inc. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions, and the following disclaimer, |
| 11 | * without modification. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * 3. The names of the above-listed copyright holders may not be used |
| 16 | * to endorse or promote products derived from this software without |
| 17 | * specific prior written permission. |
| 18 | * |
| 19 | * ALTERNATIVELY, this software may be distributed under the terms of the |
| 20 | * GNU General Public License ("GPL") as published by the Free Software |
| 21 | * Foundation; either version 2 of the License, or (at your option) any |
| 22 | * later version. |
| 23 | * |
| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS |
| 25 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
| 26 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 27 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 28 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 29 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 30 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
| 31 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
| 32 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
| 33 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 34 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 35 | */ |
| 36 | |
| 37 | /* |
| 38 | * This file contains the common interrupt handlers |
| 39 | */ |
| 40 | #include <linux/kernel.h> |
| 41 | #include <linux/module.h> |
| 42 | #include <linux/moduleparam.h> |
| 43 | #include <linux/spinlock.h> |
| 44 | #include <linux/interrupt.h> |
| 45 | #include <linux/dma-mapping.h> |
| 46 | #include <linux/io.h> |
| 47 | #include <linux/slab.h> |
| 48 | #include <linux/usb.h> |
| 49 | |
| 50 | #include <linux/usb/hcd.h> |
| 51 | #include <linux/usb/ch11.h> |
| 52 | |
| 53 | #include "core.h" |
| 54 | #include "hcd.h" |
| 55 | |
| 56 | static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg) |
| 57 | { |
| 58 | switch (hsotg->op_state) { |
| 59 | case OTG_STATE_A_HOST: |
| 60 | return "a_host"; |
| 61 | case OTG_STATE_A_SUSPEND: |
| 62 | return "a_suspend"; |
| 63 | case OTG_STATE_A_PERIPHERAL: |
| 64 | return "a_peripheral"; |
| 65 | case OTG_STATE_B_PERIPHERAL: |
| 66 | return "b_peripheral"; |
| 67 | case OTG_STATE_B_HOST: |
| 68 | return "b_host"; |
| 69 | default: |
| 70 | return "unknown"; |
| 71 | } |
| 72 | } |
| 73 | |
| 74 | /** |
| 75 | * dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts. |
| 76 | * When the PRTINT interrupt fires, there are certain status bits in the Host |
| 77 | * Port that needs to get cleared. |
| 78 | * |
| 79 | * @hsotg: Programming view of DWC_otg controller |
| 80 | */ |
| 81 | static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg) |
| 82 | { |
| 83 | u32 hprt0 = readl(hsotg->regs + HPRT0); |
| 84 | |
| 85 | if (hprt0 & HPRT0_ENACHG) { |
| 86 | hprt0 &= ~HPRT0_ENA; |
| 87 | writel(hprt0, hsotg->regs + HPRT0); |
| 88 | } |
| 89 | |
| 90 | /* Clear interrupt */ |
| 91 | writel(GINTSTS_PRTINT, hsotg->regs + GINTSTS); |
| 92 | } |
| 93 | |
| 94 | /** |
| 95 | * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message |
| 96 | * |
| 97 | * @hsotg: Programming view of DWC_otg controller |
| 98 | */ |
| 99 | static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg) |
| 100 | { |
| 101 | dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n", |
| 102 | dwc2_is_host_mode(hsotg) ? "Host" : "Device"); |
| 103 | |
| 104 | /* Clear interrupt */ |
| 105 | writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS); |
| 106 | } |
| 107 | |
| 108 | /** |
| 109 | * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG |
| 110 | * Interrupt Register (GOTGINT) to determine what interrupt has occurred. |
| 111 | * |
| 112 | * @hsotg: Programming view of DWC_otg controller |
| 113 | */ |
| 114 | static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) |
| 115 | { |
| 116 | u32 gotgint; |
| 117 | u32 gotgctl; |
| 118 | u32 gintmsk; |
| 119 | |
| 120 | gotgint = readl(hsotg->regs + GOTGINT); |
| 121 | gotgctl = readl(hsotg->regs + GOTGCTL); |
| 122 | dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint, |
| 123 | dwc2_op_state_str(hsotg)); |
| 124 | |
| 125 | if (gotgint & GOTGINT_SES_END_DET) { |
| 126 | dev_dbg(hsotg->dev, |
| 127 | " ++OTG Interrupt: Session End Detected++ (%s)\n", |
| 128 | dwc2_op_state_str(hsotg)); |
| 129 | gotgctl = readl(hsotg->regs + GOTGCTL); |
| 130 | |
| 131 | if (dwc2_is_device_mode(hsotg)) |
| 132 | s3c_hsotg_disconnect(hsotg); |
| 133 | |
| 134 | if (hsotg->op_state == OTG_STATE_B_HOST) { |
| 135 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
| 136 | } else { |
| 137 | /* |
| 138 | * If not B_HOST and Device HNP still set, HNP did |
| 139 | * not succeed! |
| 140 | */ |
| 141 | if (gotgctl & GOTGCTL_DEVHNPEN) { |
| 142 | dev_dbg(hsotg->dev, "Session End Detected\n"); |
| 143 | dev_err(hsotg->dev, |
| 144 | "Device Not Connected/Responding!\n"); |
| 145 | } |
| 146 | |
| 147 | /* |
| 148 | * If Session End Detected the B-Cable has been |
| 149 | * disconnected |
| 150 | */ |
| 151 | /* Reset to a clean state */ |
| 152 | hsotg->lx_state = DWC2_L0; |
| 153 | } |
| 154 | |
| 155 | gotgctl = readl(hsotg->regs + GOTGCTL); |
| 156 | gotgctl &= ~GOTGCTL_DEVHNPEN; |
| 157 | writel(gotgctl, hsotg->regs + GOTGCTL); |
| 158 | } |
| 159 | |
| 160 | if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) { |
| 161 | dev_dbg(hsotg->dev, |
| 162 | " ++OTG Interrupt: Session Request Success Status Change++\n"); |
| 163 | gotgctl = readl(hsotg->regs + GOTGCTL); |
| 164 | if (gotgctl & GOTGCTL_SESREQSCS) { |
| 165 | if (hsotg->core_params->phy_type == |
| 166 | DWC2_PHY_TYPE_PARAM_FS |
| 167 | && hsotg->core_params->i2c_enable > 0) { |
| 168 | hsotg->srp_success = 1; |
| 169 | } else { |
| 170 | /* Clear Session Request */ |
| 171 | gotgctl = readl(hsotg->regs + GOTGCTL); |
| 172 | gotgctl &= ~GOTGCTL_SESREQ; |
| 173 | writel(gotgctl, hsotg->regs + GOTGCTL); |
| 174 | } |
| 175 | } |
| 176 | } |
| 177 | |
| 178 | if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) { |
| 179 | /* |
| 180 | * Print statements during the HNP interrupt handling |
| 181 | * can cause it to fail |
| 182 | */ |
| 183 | gotgctl = readl(hsotg->regs + GOTGCTL); |
| 184 | /* |
| 185 | * WA for 3.00a- HW is not setting cur_mode, even sometimes |
| 186 | * this does not help |
| 187 | */ |
| 188 | if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) |
| 189 | udelay(100); |
| 190 | if (gotgctl & GOTGCTL_HSTNEGSCS) { |
| 191 | if (dwc2_is_host_mode(hsotg)) { |
| 192 | hsotg->op_state = OTG_STATE_B_HOST; |
| 193 | /* |
| 194 | * Need to disable SOF interrupt immediately. |
| 195 | * When switching from device to host, the PCD |
| 196 | * interrupt handler won't handle the interrupt |
| 197 | * if host mode is already set. The HCD |
| 198 | * interrupt handler won't get called if the |
| 199 | * HCD state is HALT. This means that the |
| 200 | * interrupt does not get handled and Linux |
| 201 | * complains loudly. |
| 202 | */ |
| 203 | gintmsk = readl(hsotg->regs + GINTMSK); |
| 204 | gintmsk &= ~GINTSTS_SOF; |
| 205 | writel(gintmsk, hsotg->regs + GINTMSK); |
| 206 | |
| 207 | /* |
| 208 | * Call callback function with spin lock |
| 209 | * released |
| 210 | */ |
| 211 | spin_unlock(&hsotg->lock); |
| 212 | |
| 213 | /* Initialize the Core for Host mode */ |
| 214 | dwc2_hcd_start(hsotg); |
| 215 | spin_lock(&hsotg->lock); |
| 216 | hsotg->op_state = OTG_STATE_B_HOST; |
| 217 | } |
| 218 | } else { |
| 219 | gotgctl = readl(hsotg->regs + GOTGCTL); |
| 220 | gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN); |
| 221 | writel(gotgctl, hsotg->regs + GOTGCTL); |
| 222 | dev_dbg(hsotg->dev, "HNP Failed\n"); |
| 223 | dev_err(hsotg->dev, |
| 224 | "Device Not Connected/Responding\n"); |
| 225 | } |
| 226 | } |
| 227 | |
| 228 | if (gotgint & GOTGINT_HST_NEG_DET) { |
| 229 | /* |
| 230 | * The disconnect interrupt is set at the same time as |
| 231 | * Host Negotiation Detected. During the mode switch all |
| 232 | * interrupts are cleared so the disconnect interrupt |
| 233 | * handler will not get executed. |
| 234 | */ |
| 235 | dev_dbg(hsotg->dev, |
| 236 | " ++OTG Interrupt: Host Negotiation Detected++ (%s)\n", |
| 237 | (dwc2_is_host_mode(hsotg) ? "Host" : "Device")); |
| 238 | if (dwc2_is_device_mode(hsotg)) { |
| 239 | dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n", |
| 240 | hsotg->op_state); |
| 241 | spin_unlock(&hsotg->lock); |
| 242 | dwc2_hcd_disconnect(hsotg); |
| 243 | spin_lock(&hsotg->lock); |
| 244 | hsotg->op_state = OTG_STATE_A_PERIPHERAL; |
| 245 | } else { |
| 246 | /* Need to disable SOF interrupt immediately */ |
| 247 | gintmsk = readl(hsotg->regs + GINTMSK); |
| 248 | gintmsk &= ~GINTSTS_SOF; |
| 249 | writel(gintmsk, hsotg->regs + GINTMSK); |
| 250 | spin_unlock(&hsotg->lock); |
| 251 | dwc2_hcd_start(hsotg); |
| 252 | spin_lock(&hsotg->lock); |
| 253 | hsotg->op_state = OTG_STATE_A_HOST; |
| 254 | } |
| 255 | } |
| 256 | |
| 257 | if (gotgint & GOTGINT_A_DEV_TOUT_CHG) |
| 258 | dev_dbg(hsotg->dev, |
| 259 | " ++OTG Interrupt: A-Device Timeout Change++\n"); |
| 260 | if (gotgint & GOTGINT_DBNCE_DONE) |
| 261 | dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n"); |
| 262 | |
| 263 | /* Clear GOTGINT */ |
| 264 | writel(gotgint, hsotg->regs + GOTGINT); |
| 265 | } |
| 266 | |
| 267 | /** |
| 268 | * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status |
| 269 | * Change Interrupt |
| 270 | * |
| 271 | * @hsotg: Programming view of DWC_otg controller |
| 272 | * |
| 273 | * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a |
| 274 | * Device to Host Mode transition or a Host to Device Mode transition. This only |
| 275 | * occurs when the cable is connected/removed from the PHY connector. |
| 276 | */ |
| 277 | static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg) |
| 278 | { |
| 279 | u32 gintmsk = readl(hsotg->regs + GINTMSK); |
| 280 | |
| 281 | /* Need to disable SOF interrupt immediately */ |
| 282 | gintmsk &= ~GINTSTS_SOF; |
| 283 | writel(gintmsk, hsotg->regs + GINTMSK); |
| 284 | |
| 285 | dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n", |
| 286 | dwc2_is_host_mode(hsotg) ? "Host" : "Device"); |
| 287 | |
| 288 | /* |
| 289 | * Need to schedule a work, as there are possible DELAY function calls. |
| 290 | * Release lock before scheduling workq as it holds spinlock during |
| 291 | * scheduling. |
| 292 | */ |
| 293 | if (hsotg->wq_otg) { |
| 294 | spin_unlock(&hsotg->lock); |
| 295 | queue_work(hsotg->wq_otg, &hsotg->wf_otg); |
| 296 | spin_lock(&hsotg->lock); |
| 297 | } |
| 298 | |
| 299 | /* Clear interrupt */ |
| 300 | writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS); |
| 301 | } |
| 302 | |
| 303 | /** |
| 304 | * dwc2_handle_session_req_intr() - This interrupt indicates that a device is |
| 305 | * initiating the Session Request Protocol to request the host to turn on bus |
| 306 | * power so a new session can begin |
| 307 | * |
| 308 | * @hsotg: Programming view of DWC_otg controller |
| 309 | * |
| 310 | * This handler responds by turning on bus power. If the DWC_otg controller is |
| 311 | * in low power mode, this handler brings the controller out of low power mode |
| 312 | * before turning on bus power. |
| 313 | */ |
| 314 | static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg) |
| 315 | { |
| 316 | dev_dbg(hsotg->dev, "++Session Request Interrupt++\n"); |
| 317 | |
| 318 | /* Clear interrupt */ |
| 319 | writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS); |
| 320 | |
| 321 | /* |
| 322 | * Report disconnect if there is any previous session established |
| 323 | */ |
| 324 | if (dwc2_is_device_mode(hsotg)) |
| 325 | s3c_hsotg_disconnect(hsotg); |
| 326 | } |
| 327 | |
| 328 | /* |
| 329 | * This interrupt indicates that the DWC_otg controller has detected a |
| 330 | * resume or remote wakeup sequence. If the DWC_otg controller is in |
| 331 | * low power mode, the handler must brings the controller out of low |
| 332 | * power mode. The controller automatically begins resume signaling. |
| 333 | * The handler schedules a time to stop resume signaling. |
| 334 | */ |
| 335 | static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg) |
| 336 | { |
| 337 | dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n"); |
| 338 | dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state); |
| 339 | |
| 340 | if (dwc2_is_device_mode(hsotg)) { |
| 341 | dev_dbg(hsotg->dev, "DSTS=0x%0x\n", readl(hsotg->regs + DSTS)); |
| 342 | if (hsotg->lx_state == DWC2_L2) { |
| 343 | u32 dctl = readl(hsotg->regs + DCTL); |
| 344 | |
| 345 | /* Clear Remote Wakeup Signaling */ |
| 346 | dctl &= ~DCTL_RMTWKUPSIG; |
| 347 | writel(dctl, hsotg->regs + DCTL); |
| 348 | } |
| 349 | /* Change to L0 state */ |
| 350 | hsotg->lx_state = DWC2_L0; |
| 351 | } else { |
| 352 | if (hsotg->lx_state != DWC2_L1) { |
| 353 | u32 pcgcctl = readl(hsotg->regs + PCGCTL); |
| 354 | |
| 355 | /* Restart the Phy Clock */ |
| 356 | pcgcctl &= ~PCGCTL_STOPPCLK; |
| 357 | writel(pcgcctl, hsotg->regs + PCGCTL); |
| 358 | mod_timer(&hsotg->wkp_timer, |
| 359 | jiffies + msecs_to_jiffies(71)); |
| 360 | } else { |
| 361 | /* Change to L0 state */ |
| 362 | hsotg->lx_state = DWC2_L0; |
| 363 | } |
| 364 | } |
| 365 | |
| 366 | /* Clear interrupt */ |
| 367 | writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS); |
| 368 | } |
| 369 | |
| 370 | /* |
| 371 | * This interrupt indicates that a device has been disconnected from the |
| 372 | * root port |
| 373 | */ |
| 374 | static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg) |
| 375 | { |
| 376 | dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n", |
| 377 | dwc2_is_host_mode(hsotg) ? "Host" : "Device", |
| 378 | dwc2_op_state_str(hsotg)); |
| 379 | |
| 380 | if (hsotg->op_state == OTG_STATE_A_HOST) |
| 381 | dwc2_hcd_disconnect(hsotg); |
| 382 | |
| 383 | /* Change to L3 (OFF) state */ |
| 384 | hsotg->lx_state = DWC2_L3; |
| 385 | |
| 386 | writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS); |
| 387 | } |
| 388 | |
| 389 | /* |
| 390 | * This interrupt indicates that SUSPEND state has been detected on the USB. |
| 391 | * |
| 392 | * For HNP the USB Suspend interrupt signals the change from "a_peripheral" |
| 393 | * to "a_host". |
| 394 | * |
| 395 | * When power management is enabled the core will be put in low power mode. |
| 396 | */ |
| 397 | static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg) |
| 398 | { |
| 399 | u32 dsts; |
| 400 | |
| 401 | dev_dbg(hsotg->dev, "USB SUSPEND\n"); |
| 402 | |
| 403 | if (dwc2_is_device_mode(hsotg)) { |
| 404 | /* |
| 405 | * Check the Device status register to determine if the Suspend |
| 406 | * state is active |
| 407 | */ |
| 408 | dsts = readl(hsotg->regs + DSTS); |
| 409 | dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dsts); |
| 410 | dev_dbg(hsotg->dev, |
| 411 | "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d\n", |
| 412 | !!(dsts & DSTS_SUSPSTS), |
| 413 | hsotg->hw_params.power_optimized); |
| 414 | } else { |
| 415 | if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) { |
| 416 | dev_dbg(hsotg->dev, "a_peripheral->a_host\n"); |
| 417 | |
| 418 | /* Clear the a_peripheral flag, back to a_host */ |
| 419 | spin_unlock(&hsotg->lock); |
| 420 | dwc2_hcd_start(hsotg); |
| 421 | spin_lock(&hsotg->lock); |
| 422 | hsotg->op_state = OTG_STATE_A_HOST; |
| 423 | } |
| 424 | } |
| 425 | |
| 426 | /* Change to L2 (suspend) state */ |
| 427 | hsotg->lx_state = DWC2_L2; |
| 428 | |
| 429 | /* Clear interrupt */ |
| 430 | writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS); |
| 431 | } |
| 432 | |
| 433 | #define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \ |
| 434 | GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT | \ |
| 435 | GINTSTS_MODEMIS | GINTSTS_DISCONNINT | \ |
| 436 | GINTSTS_USBSUSP | GINTSTS_PRTINT) |
| 437 | |
| 438 | /* |
| 439 | * This function returns the Core Interrupt register |
| 440 | */ |
| 441 | static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg) |
| 442 | { |
| 443 | u32 gintsts; |
| 444 | u32 gintmsk; |
| 445 | u32 gahbcfg; |
| 446 | u32 gintmsk_common = GINTMSK_COMMON; |
| 447 | |
| 448 | gintsts = readl(hsotg->regs + GINTSTS); |
| 449 | gintmsk = readl(hsotg->regs + GINTMSK); |
| 450 | gahbcfg = readl(hsotg->regs + GAHBCFG); |
| 451 | |
| 452 | /* If any common interrupts set */ |
| 453 | if (gintsts & gintmsk_common) |
| 454 | dev_dbg(hsotg->dev, "gintsts=%08x gintmsk=%08x\n", |
| 455 | gintsts, gintmsk); |
| 456 | |
| 457 | if (gahbcfg & GAHBCFG_GLBL_INTR_EN) |
| 458 | return gintsts & gintmsk & gintmsk_common; |
| 459 | else |
| 460 | return 0; |
| 461 | } |
| 462 | |
| 463 | /* |
| 464 | * Common interrupt handler |
| 465 | * |
| 466 | * The common interrupts are those that occur in both Host and Device mode. |
| 467 | * This handler handles the following interrupts: |
| 468 | * - Mode Mismatch Interrupt |
| 469 | * - OTG Interrupt |
| 470 | * - Connector ID Status Change Interrupt |
| 471 | * - Disconnect Interrupt |
| 472 | * - Session Request Interrupt |
| 473 | * - Resume / Remote Wakeup Detected Interrupt |
| 474 | * - Suspend Interrupt |
| 475 | */ |
| 476 | irqreturn_t dwc2_handle_common_intr(int irq, void *dev) |
| 477 | { |
| 478 | struct dwc2_hsotg *hsotg = dev; |
| 479 | u32 gintsts; |
| 480 | irqreturn_t retval = IRQ_NONE; |
| 481 | |
| 482 | spin_lock(&hsotg->lock); |
| 483 | |
| 484 | if (!dwc2_is_controller_alive(hsotg)) { |
| 485 | dev_warn(hsotg->dev, "Controller is dead\n"); |
| 486 | goto out; |
| 487 | } |
| 488 | |
| 489 | gintsts = dwc2_read_common_intr(hsotg); |
| 490 | if (gintsts & ~GINTSTS_PRTINT) |
| 491 | retval = IRQ_HANDLED; |
| 492 | |
| 493 | if (gintsts & GINTSTS_MODEMIS) |
| 494 | dwc2_handle_mode_mismatch_intr(hsotg); |
| 495 | if (gintsts & GINTSTS_OTGINT) |
| 496 | dwc2_handle_otg_intr(hsotg); |
| 497 | if (gintsts & GINTSTS_CONIDSTSCHNG) |
| 498 | dwc2_handle_conn_id_status_change_intr(hsotg); |
| 499 | if (gintsts & GINTSTS_DISCONNINT) |
| 500 | dwc2_handle_disconnect_intr(hsotg); |
| 501 | if (gintsts & GINTSTS_SESSREQINT) |
| 502 | dwc2_handle_session_req_intr(hsotg); |
| 503 | if (gintsts & GINTSTS_WKUPINT) |
| 504 | dwc2_handle_wakeup_detected_intr(hsotg); |
| 505 | if (gintsts & GINTSTS_USBSUSP) |
| 506 | dwc2_handle_usb_suspend_intr(hsotg); |
| 507 | |
| 508 | if (gintsts & GINTSTS_PRTINT) { |
| 509 | /* |
| 510 | * The port interrupt occurs while in device mode with HPRT0 |
| 511 | * Port Enable/Disable |
| 512 | */ |
| 513 | if (dwc2_is_device_mode(hsotg)) { |
| 514 | dev_dbg(hsotg->dev, |
| 515 | " --Port interrupt received in Device mode--\n"); |
| 516 | dwc2_handle_usb_port_intr(hsotg); |
| 517 | retval = IRQ_HANDLED; |
| 518 | } |
| 519 | } |
| 520 | |
| 521 | out: |
| 522 | spin_unlock(&hsotg->lock); |
| 523 | return retval; |
| 524 | } |
| 525 | EXPORT_SYMBOL_GPL(dwc2_handle_common_intr); |